National Semiconductor MM54HC533, MM74HC533 Service Manual

MM54HC533/MM74HC533
TRI-STATE

Octal D-Type Latch

É

with Inverted Outputs

General Description

These high speed OCTAL D-TYPE LATCHES utilize ad­vanced silicon-gate CMOS technology. They possess the
high noise immunity and low power consumption of stan­dard CMOS integrated circuits, as well as the ability to drive
15 LS-TTL loads. Due to the large output drive capability
and the TRI-STATE feature, these devices are ideally suited
for interfacing with bus lines in a bus organized system.

When the LATCH ENABLE input is high, the data present
on the D inputs will appear inverted at the Q
the LATCH ENABLE goes low, the inverted data will be re­tained at the Q
again. When a high logic level is applied to the OUTPUT
CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.

outputs until LATCH ENABLE returns high

outputs. When

January 1988

The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to V

and ground.

CC

Features

Y

Typical propagation delay: 18 ns

Y

Wide operating voltage range: 2 to 6 volts

Y

Low input current: 1 mA maximum

Y

Low quiescent current: 80 mA, maximum (74HC Series)

Y

Compatible with bus-oriented systems

Y

Output drive capability: 15 LS-TTL loads

MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs

Connection Diagram

Truth Table

Latch

Output Enable

Control G Data Output

LHHL
LHLH
LLXQ
HXXZ

Dual-In-Line Package

Top View

Order Number MM54HC533 or MM74HC533

e

H

high level, Lelow level

e

level of output before steady-state input conditions

Q

0

were established.

e

high impedance

Z

0

TL/F/5339– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/5339

Absolute Maximum Ratings (Notes1&2)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

)

b

0.5 toa7.0V

b

1.5 to V

b

CC

0.5 to V

CC

b

65§Ctoa150§C

a

a

g

g

g

1.5V

0.5V

20 mA

35 mA

70 mA

Supply Voltage (V

CC

)

DC Input Voltage (VIN)

DC Output Voltage (V

OUT

)

Clamp Diode Current (IIK,IOK)

DC Output Current, per pin (I

OUT

)

DC VCCor GND Current, per pin (ICC)

Storage Temperature Range (T

STG

Supply Voltage (V

)26V

CC

DC Input or Output Voltage 0 V

(V

IN,VOUT

)

Operating Temp. Range (TA)

MM74HC
MM54HC

Input Rise or Fall Times

e

V

2.0V(tr,tf) 1000 ns

CC

e

V

4.5V 500 ns

CC

e

V

6.0V 400 ns

CC

Power Dissipation (PD)

(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temp. (T

) (Soldering 10 seconds) 260§C

L

DC Electrical Characteristics

e

T

25§C

Symbol Parameter Conditions V

CC

A

Typ Guaranteed Limits

V

Minimum High Level 2.0V 1.5 1.5 1.5 V

IH

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

V

Maximum Low Level 2.0V 0.5 0.5 0.5 V

IL

Input Voltage** 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

V

Minimum High Level V

OH

Output Voltage

e

VIHor V

l

IN

I

OUT

IL

s

20 mA 2.0V 2.0 1.9 1.9 1.9 V

l

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

e

V

VIHor V

IN

I

l

OUT

I

l

OUT

l

IN

I

OUT

e

V

Maximum Low Level V

OL

Output Voltage

IL

s

6.0 mA 4.5V 4.2 3.98 3.84 3.7 V

l

s

7.8 mA 6.0V 5.7 5.48 5.34 5.2 V

l

VIHor V

IL

s

20 mA 2.0V 0 0.1 0.1 0.1 V

l

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

e

V

VIHor V

IN

I

l

OUT

I

l

OUT

I

I

Maximum Input V

IN

Current

Maximum TRI-STATE V

OZ

Output Leakage V
Current

I

Maximum Quiescent V

CC

Supply Current I

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:

Note 4: For a power supply of 5V

with this supply. Worst case V

) occur for CMOS at the higher voltage and so the 6.0V values should be used.

I

OZ

**V

limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.

IL

g

and VILoccur at V

IH

e

IN

e

IN

OUT

e

IN

OUT

10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing

IL

s

6.0 mA 4.5V 0.2 0.26 0.33 0.4 V

l

s

7.8 mA 6.0V 0.2 0.26 0.33 0.4 V

l

VCCor GND 6.0V

VIHor VIL,OCeVIH6.0V

e

VCCor GND

g

0.1

g

0.5

VCCor GND 6.0V 8.0 80 160 mA

e

0 mA

b

12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.

e

5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and

CC

74HC 54HC

eb

T

40 to 85§CT

A

g

1.0

g

5

Min Max Units

V

§

§

Units

b
b

40
55

eb

A

CC

a

85

a

125

55 to 125§C

g

1.0 mA

g

10 mA

C
C

2

AC Electrical Characteristics V

CC

5V, T

e

A

25§C, t

e

e

t

6ns

r

f

e

Symbol Parameter Conditions Typ Guaranteed Limit Units

t

PHL,tPLH

t

PHL,tPLH

t

PZH,tPZL

t

PHZ,tPLZ

t

S

t

H

t

W

Maximum Propagation Delay, Data to Q C

Maximum Propagation Delay, Enable to Q C

Maximum Output Enable Time R

Maximum Output Disable Time R

Minimum Set Up Time 5 ns

Minimum Hold Time 10 ns

Minimum Pulse Width 16 ns

e

45 pF 18 25 ns

L

e

45 pF 21 30 ns

L

e

1kX 20 28 ns

L

e

45 pF

C

L

e

1kX 18 25 ns

L

e

5pF

C

L

AC Electrical Characteristics V

e

2.0V–6.0V, C

CC

Symbol Parameter Conditions V

t

PHL,tPLH

t

PHL,tPLH

t

PZH,tPZL

t

PHZ,tPLZ

t

S

t

H

t

W

t

THL,tTLH

C

PD

C

IN

C

OUT

Note 5: CPDdetermines the no load dynamic power consumption, P

Maximum Propagation C
Delay, Data to Q

Maximum Propagation C
Delay, Enable to Q C

Maximum Output Enable Time R

Maximum Output Disable Time R

Minimum Set Up Time 2.0V 50 60 75 ns

Minimum Hold Time 2.0V 5 5 5 ns

Minimum Pulse Width 2.0V 30 80 100 120 ns

Maximum Output Rise C
and Fall Time, Clock 4.5V 7 12 15 18 ns

Power Dissipation Capacitance (per latch)
(Note 5) OCeV

Maximum Input Capacitance 5 10 10 10 pF

Maximum Output Capacitance 15 20 20 20 pF

e

50 pF 2.0V 50 150 188 225 ns

L

e

C

150 pF 2.0V 80 200 250 300 ns

L

e

C

50 pF 4.5V 22 30 37 45 ns

L

e

150 pF 4.5V 30 40 50 60 ns

C

L

e

C

50 pF 6.0V 19 26 31 39 ns

L

e

150 pF 6.0V 26 35 44 53 ns

C

L

e

50 pF 2.0V 63 175 220 263 ns

L

e

150 pF 2.0V 110 225 280 338 ns

L

e

C

50 pF 4.5V 25 35 44 52 ns

L

e

150 pF 4.5V 35 45 56 68 ns

C

L

e

C

50 pF 6.0V 21 30 37 45 ns

L

e

150 pF 6.0V 28 39 49 59 ns

C

L

e

1kX

L

e

C

50 pF 2.0V 50 150 188 225 ns

L

e

150 pF 2.0V 80 200 250 300 ns

C

L

e

C

50 pF 4.5V 21 30 37 45 ns

L

e

150 pF 4.5V 30 40 50 60 ns

C

L

e

C

50 pF 6.0V 19 26 31 39 ns

L

e

150 pF 6.0V 26 35 44 53 ns

C

L

e

1kX 2.0V 50 150 188 225 ns

L

e

50 pF 4.5V 21 30 37 45 ns

C

L

e

50 pF 2.0V 25 60 75 90 ns

L

CC

e

Gnd 50 pF

OC

e

D

CC

e

L

e

T

A

50 pF, t

25§C

e

e

t

6 ns (unless otherwise specified)

r

f

74HC 54HC

eb

T

40 to 85§CT

A

A

eb

55 to 125§C

Typ Guaranteed Limits

6.0V 19 26 31 39 ns

4.5V 9 13 15 ns

6.0V 9 11 13 ns

4.5V 5 5 5 ns

6.0V 5 5 5 ns

4.5V 10 16 20 24 ns

6.0V 9 14 18 20 ns

6.0V 6 10 13 15 ns

30 pF

2

CPDV

faICCVCC, and the no load dynamic current consumption, I

CC

e

CPDVCCfaICC.

S

Units

3

Physical Dimensions inches (millimeters)

Order Number MM54HC533J or MM74HC533J

NS Package J20A

Order Number MM74HC533N

LIFE SUPPORT POLICY

NS Package N20A

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs

failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: [e-mail] Ocean Centre, 5 Canton Rd. Fax: [phone]
Tel: [phone] Deutsch Tel: (
Fax: [phone] English Tel: (

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Fran3ais Tel: (
Italiano Tel: (

a

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: [phone]

a

49) 0-180-530 85 85 Tsimshatsui, Kowloon

a

49) 0-180-532 78 32 Hong Kong

a

49) 0-180-532 93 58 Tel: [phone]

a

49) 0-180-534 16 80 Fax: [phone]