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MM54HC30/MM74HC30 8-Input NAND Gate
MM54HC30/MM74HC30 8-Input NAND Gate
January 1988
General Description
This NAND gate utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS integrated circuits. This device has high noise immunity and the
ability to drive 10 LS-TTL loads. The 54HC/74HC logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps to
V
and ground.
CC
Connection and Logic Diagrams
Dual-In-Line Package
Top View
Order Number MM54HC30 or MM74HC30
Features
Y
Typical propagation delay: 20 ns
Y
Wide power supply range: 2– 6V
Y
Low quiescent current: 20 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
TL/F/5133– 1
YeABCDEFGH
TL/F/5133– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5133
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (ICD)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
DC Supply Voltage (V
)2 6 V
CC
DC Input or Output Voltage
(VIN,V
)0V
OUT
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise/Fall Times
e
2.0V(tr,tf) 1000 ns
V
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering, 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level Input 2.0V 1.5 1.5 1.5 V
IH
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level Input 2.0V 0.5 0.5 0.5 V
IL
Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level Output V
OH
Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
Maximum Low Level Output V
OL
Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
V
IH
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
V
IN
IH
s
I
4 mA 4.5V 0.2 0.26 0.33 0.4 V
l
l
OUT
s
I
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
l
OUT
I
IN
I
CC
Maximum Input Current V
Maximum Quiescent Supply V
Current I
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
and VILoccur at V
IH
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V 2.0 20 40 mA
IN
e
0 mA
OUT
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
g
0.1
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
eb
A
a
a
55 to 125§C
g
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
t
PHL,tPLH
Maximum Propagation Delay 20 30 ns
e
A
25§C, C
e
15 pF, t
L
Guaranteed
Limit
r
e
e
t
f
Units
6ns
AC Electrical Characteristics V
CC
Symbol Parameter Conditions V
t
PHL,tPLH
t
TLH,tTHL
Maximum Propagation 2.0V 66 160 190 220 ns
Delay 4.5V 23 35 42 49 ns
Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall 4.5V 8 15 19 22 ns
Time 6.0V 7 13 16 19 ns
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Power Dissipation 34 pF
Capacitance (Note 5)
Maximum Input 5 10 10 10 pF
Capacitance
e
2.0V to 6.0V, C
CC
e
L
e
T
25§C
A
50 pF, t
T
e
e
t
6tns (unless otherwise specified)
r
f
74HC 54HC
eb
40 to 85§CT
A
eb
A
55 to 125§C
Typ Guaranteed Limits
6.0V 18 30 36 42 ns
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
Page 4
Physical Dimensions inches (millimeters)
Order Number MM54HC30J or MM74HC30J
NS Package J14A
MM54HC30/MM74HC30 8-Input NAND Gate
Order Number MM74HC30N
NS Package N14A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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