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MM54HC283/MM74HC283
4-Bit Binary Adder with Fast Carry
MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
January 1988
General Description
This full adder performs the addition of two 4-bit binary numbers utilizing advanced silicon-gate CMOS technology. The
sum (R) outputs are provided for each bit and the resultant
carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. All inputs are protected from damage due to static discharge by
internal diode clamps to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
Features
Y
Full-carry look-ahead across the four bits
Y
Systems achieve partial look-ahead performance
with the economy of ripple carry
Y
Wide supply range: 2V to 6V
Y
Low quiescent power consumption: 8 mAat25§C
Y
Low input current: 1 mA maximum
Top View
Order Number MM54HC283 or MM74HC283
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5332
TL/F/5332– 1
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Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
1.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
IN
I
l
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
V
OL
Maximum Low Level V
Output Voltage
e
IN
I
l
OUT
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
eb
A
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
Maximum Propagation 18 27 ns
Delay From C0 to R1orR2
Maximum Propagation 18 27 ns
Delay From C0 to R3
Maximum Propagation 20 30 ns
Delay From C0 to R4
Maximum Propagation 17 26 ns
Delay From A1 or B1 to R1
Maximum Propagation 22 32 ns
Delay From C0 to C4
Maximum Propagation 22 32 ns
Delay From A1 or B1 to C4
e
A
25§C, C
Guaranteed
Limit
L
e
15 pF, t
e
r
Units
e
t
6ns
f
AC Electrical Characteristics C
e
L
Symbol Parameter Conditions V
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
THL,tTLH
C
IN
C
PD
Note 5: CPDdetermines the no load dynamic power consumption, P
I
S
Maximum Propagation 2.0V 60 150 188 225 ns
Delay From C0 to R1orR2 4.5V 21 30 37 45 ns
Maximum Propagation 2.0V 60 150 188 225 ns
Delay From C0 to R3 4.5V 21 30 37 45 ns
Maximum Propagation 2.0V 65 162 202 243 ns
Delay From C0 to R4 4.5V 24 34 43 51 ns
Maximum Propagation 2.0V 60 150 188 225 ns
Delay From A1 or B1 to R1 4.5V 22 33 41 50 ns
Maximum Propagation 2.0V 70 175 219 263 ns
Delay From C0 to C4 4.5V 26 39 49 59 ns
Maximum Propagation 2.0V 70 175 219 263 ns
Delay From A1 or B1 to C4 4.5V 26 39 49 59 ns
Maximum Output 2.0V 28 75 95 110 ns
Rise and Fall Time 4.5V 8 15 19 22 ns
Maximum Input 6 10 10 10 pF
Capacitance
Power Dissipation 150 pF
Capacitance (Note 5)
e
CPDVCCfaICC.
e
50 pF, t
CC
e
t
6 ns (unless otherwise specified)
r
f
e
T
25§C
A
eb
T
A
74HC 54HC
40 to 85§CT
A
eb
55 to 125§C
Typ Guaranteed Limits
6.0V 18 26 32 39 ns
6.0V 18 26 32 39 ns
6.0V 19 28 35 42 ns
6.0V 18 27 34 41 ns
6.0V 21 32 40 46 ns
6.0V 21 32 40 46 ns
6.0V 7 13 16 19 ns
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption,
CC
Units
3
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Truth Table
Output
Input C0
e
LC0
When When
C2
e
H
e
LC2
e
When When
A1 A3 B1 B3 A2 A4 B2 B4 R1 R3 R 2 R4C2C4R1R3R2R4C2C4
LLLLLLLHLL
HLLLHLLLHL
LHLLH L L LHL
HHLLLHLHHL
LLHLLHLHHL
HLHLHHLL LH
LHHLHHL L LH
HHHL L LHH L H
LLLHLHLHHL
HLLHHHLL LH
LHLHHHL L LH
HHLHLLHHLH
LLHHLLHHLH
HLHHHLHLHH
LHHHH LH L HH
HHHHL HHHHH
e
H
high level, Lelow level
Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R 2 and the value of the
internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs R3, R4, and C4
H
4
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Logic Diagram
’HC283
TL/F/5332– 2
5
Page 6
Physical Dimensions inches (millimeters)
Order Number MM54HC283J or MM74HC283J
NS Package J16A
Order Number MM74HC283N
MM54HC283/MM74HC283 4-Bit Binary Adder with Fast Carry
NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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Tel: 1(800) 272-9959 Deutsch Tel: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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