Page 1
MM54HC259/MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
This device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for
general purpose storage applications in digital systems.
The MM54HC259/MM74HC259 has a single data input (D),
8 latch outputs (Q1 –Q8), 3 address inputs (A, B, and C), a
common enable input (G
operate this device as an addressable latch, data is held on
the D input, and the address of the latch into which the data
is to be entered is held on the A, B, and C inputs. When
ENABLE is taken low the data flows through to the addressed output. The data is stored when ENABLE transitions from low to high. All unaddressed latches will remain
unaffected. With enable in the high state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing.
), and a common CLEAR input. To
If enable is held high and CLEAR is taken low all eight latches are cleared to a low state. If enable is low all latches
except the addressed latch will be cleared. The addressed
latch will instead follow the D input, effectively implementing
a 3-to-8 line decoder.
All inputs are protected from damage due to static discharge by diodes to V
and ground.
CC
Features
Y
Typical propagation delay: 18 ns
Y
Wide supply range: 2– 6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 80 mA maximum (74HC Series)
MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
January 1988
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC259 or MM74HC259
Truth Table
Inputs Outputs of Each
Clear G
HL D Qi0Addressable Latch
HH Q
L L D L 8-Line Decoder
L H L L Clear
Addressed Other
Latch Output
i0
Q
i0
Function
Memory
TL/F/5006– 1
Latch Selection Table
Select Inputs Latch
CBA
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
Hehigh level, Lelow level
e
D
the level at the data input
Q
the level of Qi(ie0,1...7, asappro-
i0
priate) before the indicated steady-state input conditions were established.
Addressed
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/F/5006
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
OZ
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 m A
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
CC
b
b
40
55
eb
A
55 to 125§C
g
a
85
a
125
§
§
Units
1.0 mA
V
C
C
2
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AC Electrical Characteristics (V
CC
e
5.0V, T
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL
t
W
t
W
tr,t
t
s
t
H
AC Electrical Characteristics t
Maximum Propagation Delay 18 32 ns
Data to Output
Maximum Propagation Delay 20 38 ns
Select to Output
Maximum Propagation Delay 20 35 ns
Enable to Output
Maximum Propagation Delay 17 27 ns
Clear to Output
Minimum Enable Pulse Width 10 16 ns
Minimum Clear Pulse Width 10 16 ns
Maximum Input Rise and Fall Time 500 ns
f
Minimum Setup Time Select or 15 20 ns
Data to Enable
Minimum Hold Time Data or
Address to Enable
e
e
t
6 ns, C
r
f
Symbol Parameter Conditions V
t
PHL,tPLH
t
PHL,tPLH
t
PHL,tPLH
t
PHL
t
W
t
s
t
H
t
TLH,tTHL
C
IN
C
PD
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Propagation Delay 2.0V 60 180 225 250 ns
Data to Output 4.5V 19 37 46 52 ns
Maximum Propagation Delay 2.0V 72 220 275 310 ns
Select to Output 4.5V 21 43 54 60 ns
Maximum Propagation Delay 2.0V 65 200 250 280 ns
Enable to Output 4.5V 27 40 50 58 ns
Maximum Propagation Delay 2.0V 50 150 190 210 ns
Clear to Output 4.5V 18 31 39 44 ns
Minimum Pulse Width 2.0V 80 100 120 ns
Clear or Enable 4.5V 16 20 24 ns
Minimum Setup Time Address 2.0V 100 125 150 ns
or Data to Enable 4.5V 20 25 28 ns
Minimum Hold Time Address or 2.0Vb10 0 0 0 ns
Data to Enable 4.5V
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
Input Capacitance 5 10 10 10 pF
Power Dissipation (per package) 80 pF
Capacitance (Note 5)
e
CPDV
D
e
e
A
25§C, t
e
t
r
f
Guaranteed
Limit
b
20 ns
L
CC
e
50 pF, V
T
e
CC
e
25§C
A
e
6 ns, C
15 pF unless otherwise specified.)
L
Units
2.0V–6.0V
74HC 54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
Units
Typ Guaranteed Limits
6.0V 17 32 40 45 ns
6.0V 18 37 46 52 ns
6.0V 23 35 44 50 ns
6.0V 16 26 32 37 ns
6.0V 14 18 20 ns
6.0V 15 19 25 ns
b
20 0 0 ns
b
6.0V
20 0 0 ns
6.0V 7 13 16 19 ns
2
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDsVCCsfaICC.
S
3
Page 4
Logic Diagram
TL/F/5006– 2
4
Page 5
Physical Dimensions inches (millimeters)
Order Number MM54HC259J or MM74HC259J,N
Dual-In-Line Package
NS Package J16A
5
Page 6
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package
Order Number MM74HC259N
NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
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