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MM54HC221A/MM74HC221A
Dual Non-Retriggerable Monostable Multivibrator
General Description
The MM54/74HC221A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power
Schottky TTL circuitry while retaining the low power and
high noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The ’HC221A can be
triggered on the positive transition of the clear while A is
held low and B is held high.
The ’HC221A is a non-retriggerable, and therefore cannot
be retriggered until the output pulse times out.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW
e
(R
)(C
EXT
); where PW
EXT
Connection Diagram
Dual-In-Line Package
is in seconds, R is in ohms, and C is in farads. All inputs are
protected from damage due to static discharge by diodes to
V
and ground.
CC
Features
Y
Typical propagation delay: 40 ns
Y
Wide power supply range: 2V – 6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Y
Simple pulse width formula TeRC
Y
Wide pulse range: 400 ns to%(typ)
Y
Part to part variation:g5% (typ)
Y
Schmitt TriggerA&Binputs enable infinite signal input
rise or fall times
Timing Component
MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
January 1988
Note: Pin 6 and Pin 14 must be hardwired to GND.
TL/F/5325– 2
TL/F/5325– 1
Top View
Order Number MM54HC221A or MM74HC221A
Truth Table
e
H
Inputs Outputs
Clear AB Q Q
LXXLH
XHXLH
XXLLH
HL
H
u
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
v
LHÉß
u
H Éß
TL/F/5325
Éß
High Level
e
L
Low Level
e
Transition from Low to High
u
e
Transition from High to Low
v
e
É
One High Level Pulse
e
ß
One Low Level Pulse
e
X
Irrelevant
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Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5V toa7.0V
1.5V to V
CC
0.5V to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature
(T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
V
V
V
V
I
IN
I
IN
I
CC
I
CC
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
Maximum Low Level 2.0V 0.3 0.3 0.3 V
IL
Input Voltage 4.5V 0.9 0.9 0.9 V
Minimum High Level V
OH
Output Voltage
Maximum Low Level V
OL
Output Voltage
Maximum Input Current V
(Pins 7, 15)
Maximum Input Current V
(all other pins)
Maximum Quiescent Supply V
Current (standby) I
Maximum Active Supply V
Current (per monostable) R/C
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
designing with this supply. Worst-case V
, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
CC
g
10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
IH
e
VIHor V
IN
s
I
l
l
OUT
e
V
VIHor V
IN
s
I
l
l
OUT
s
I
l
l
OUT
e
VIHor V
IN
s
I
l
l
OUT
e
V
VIHor V
IN
s
I
l
l
OUT
s
I
l
l
OUT
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V 8.0 80 160 mA
IN
e
OUT
e
VCCor GND 2.0V 36 80 110 130 mA
IN
EXT
and VILoccur at V
20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
20 mA 2.0V 0 0.1 0.1 0.1 V
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
0 mA
e
0.5VCC4.5V 0.33 1.0 1.3 1.6 mA
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst-case leakage current (IIN,
CC
CC
Typ Guaranteed Limits
6.0V 4.2 4.2 4.2 V
6.0V 1.2 1.2 1.2 V
IL
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
IL
IL
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
IL
6.0V 0.7 2.0 2.6 3.2 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
Operating Conditions
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Maximum Input Rise and Fall
Time (Clear Input)
e
T
25§C
A
e
V
2.0V 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
0.5
g
0.1
g
5.0
g
1.0
Min Max Units
b
40
b
55
eb
55 to 125§C
A
g
g
CC
a
85
a
125
V
§
§
Units
5.0 mA
1.0 mA
C
C
2
Page 3
e
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
Symbol Parameter Conditions Typ
t
PLH
t
PHL
t
PHL
t
PLH
t
W
t
REM
t
WQ(MIN)
t
WQ
Maximum Trigger Propagation 22 36 ns
Delay A, B or Clear to Q
Maximum Trigger Propagation 25 42 ns
Delay A, B or Clear to Q
Maximum Propagation Delay Clear to Q 20 31 ns
Maximum Propagation Delay Clear to Q 22 33 ns
Minimum Pulse Width A, B or Clear 14 26 ns
Minimum Clear Removal Time 0 ns
Minimum Output Pulse Width C
Output Pulse Width C
e
28 pF 400 ns
EXT
e
2kX
R
EXT
e
1000 pF 10 ms
EXT
e
R
10 kX
EXT
e
L
15 pF, t
Guaranteed
e
r
Limit
e
t
6ns
f
Units
AC Electrical Characteristics C
e
L
50 pF, t
e
e
t
r
f
Symbol Parameter Conditions V
t
PLH
t
PHL
t
PHL
t
PLH
t
W
t
REM
t
TLH,tTHL
t
WQ(MIN)
t
WQ
Maximum Trigger Propagation 2.0V 77 169 194 210 ns
Delay A, B or Clear to Q 4.5V 26 42 51 57 ns
Maximum Trigger Propagation 2.0V 88 197 229 250 ns
Delay A, B or Clear to Q
Maximum Propagation 2.0V 54 114 132 143 ns
Delay Clear to Q 4.5V 23 34 41 45 ns
Maximum Propagation 2.0V 56 116 135 147 ns
Delay Clear to Q
Minimum Pulse Width 2.0V 57 123 144 157 ns
A, B, Clear 4.5V 17 30 37 42 ns
Minimum Clear 2.0V 0 0 0 ns
Removal Time 4.5V 0 0 0 ns
Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 8 15 19 22 ns
Minimum Output C
Pulse Width R
Output Pulse Width C
e
28 pF 2.0V 1.5 ms
EXT
e
2kX 4.5V 450 ns
EXT
e
6kX(V
R
EXT
e
0.1 mF Min 5.0V 1 0.9 0.86 0.85 ms
EXT
e
R
10 kX
EXT
e
2V) 6.0V 380 ns
CC
Max 5.0V 1 1.1 1.14 1.15 ms
C
C
C
Power Dissipation 87 pF
PD
Capacitance (Note 5)
Maximum Input 12 20 20 20 pF
IN
Capacitance (Pins7&15)
Maximum Input 6 10 10 10 pF
IN
Capacitance (other inputs)
Note 5: CPDdetermines the no load dynamic power consumption, P
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
6 ns(unless otherwise specified)
74HC 54HC
eb
T
40 to 85§CT
A
A
eb
55 to 125§C
Units
CC
e
T
25§C
A
Typ Guaranteed Limits
6.0V 21 32 39 44 ns
4.5V 29 48 60 67 ns
6.0V 24 38 46 51 ns
6.0V 19 28 33 36 ns
4.5V 25 36 42 46 ns
6.0V 20 29 34 37 ns
6.0V 12 21 27 30 ns
6.0V 0 0 0 ns
6.0V 7 13 16 19 ns
e
CPDVCCfaICC.
S
3
Page 4
Logic Diagram
Theory of Operation
j POSITIVE EDGE TRIGGER m NO RETRIGGERING
k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENING
l POSITIVE EDGE TRIGGER o CLEAR TRIGGER
TL/F/5325– 5
TL/F/5325– 6
FIGURE 1
4
Page 5
TRIGGER OPERATION
Figure 1
As shown in
and the logic diagram before an input
trigger occurs, the monostable is in the quiescent state with
the Q output low, and the timing capacitor C
charged to V
GND (while inputs B and clear are held to V
. When the trigger input A goes from VCCto
CC
ger is recognized, which turns on comparator C1 and Nchannel transistor N1
j. At the same time the output latch
is set. With transistor N1 on, the capacitor C
charges toward GND until V
the output of comparator C1 changes state and transistor
is reached. At this point
REF1
completely
EXT
) a valid trig-
CC
rapidly dis-
EXT
N1 turns off. Comparator C1 then turns off while at the same
time comparator C2 turns on. With transistor N1 off, the capacitor C
R
EXT
V
REF2
latch to reset (Q goes low) while at the same time disabling
begins to charge through the timing resistor,
EXT
, toward VCC. When the voltage across C
, comparator C2 changes state causing the output
EXT
equals
comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
at V
k). The ’HC221 can also be triggered when clear
CC
goes from GND to V
V
o).
CC
(while input A is at GND and input clear is
CC
(while A is at Gnd and B is at
CC
It should be noted that in the quiescent state C
charged to V
be zero. Both comparators are ‘‘off’’ with the total device
causing the current through resistor R
CC
EXT
is fully
EXT
current due only to reverse junction leakages. An added
feature of the ’HC221 is that the output latch is set via the
input trigger without regard to the capacitor voltage. Thus,
propagation delay from trigger to Q is independent of the
value of C
form.
EXT,REXT
, or the duty cycle of the input wave-
The ’HC221 is non-retriggerable and will ignore input transitions on A and B until it has timed out
l and m .
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
the voltage on the capacitor reaches V
will clear and then be ready to accept another pulse. If the
by turning on transistor Q1 n . When
CC
, the reset latch
REF2
clear input is held low, any trigger inputs that occur will be
inhibited and the Q and Q
outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
to
Typical Output Pulse Width
vs. Timing Components
TL/F/5325– 7
Minimum R
Supply Voltage
Note: R and C are not subjected to temperature. The C is polypropylene.
EXT
vs.
Typical Distribution of Output
Pulse Width, Part to Part
TL/F/5325– 10
TL/F/5325– 8
Typical 1ms Pulse Width
Variation vs. Supply
TL/F/5325– 9
Typical 1 ms Pulse Width
Variation vs. Temperature
TL/F/5325– 11
5
Page 6
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC221AJ or MM74HC221AJ
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM74HC221AJN
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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Tel: 1(800) 272-9959 Deutsch Tel: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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