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MM54HC132/MM74HC132 Quad 2-Input NAND Schmitt Trigger
MM54HC132/MM74HC132 Quad 2-Input
NAND Schmitt Trigger
General Description
The MM54HC132/MM74HC132 utilizes advanced silicongate CMOS technology to achieve the low power dissipation
and high noise immunity of standard CMOS, as well as the
capability to drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally and pinout compatible with the standard 54LS/74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Connection and Logic Diagrams
Dual-In-Line Package
Features
Y
Typical propagation delay: 12 ns
Y
Wide power supply range: 2V –6V
Y
Low quiescent current: 20 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Y
Typical hysteresis voltage: 0.9V at V
PRELIMINARY
January 1988
e
4.5V
CC
Top View
Order Number MM54HC132 or MM74HC132
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5309
TL/F/5309– 1
TL/F/5309– 2
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
OUT
IK,IOK
)
)
)
OUT
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
D
STG
)
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (TA)
MM74HC
MM54HC
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
V
Positive Min 2.0V 1.0 1.0 1.0 V
a
T
Going Threshold Voltage 4.5V 2.0 2.0 2.0 V
Max 2.0V 1.5 1.5 1.5 V
V
Negative Going Min 2.0V 0.3 0.3 0.3 V
b
T
Threshold Voltage 4.5V 0.9 0.9 0.9 V
Max 2.0V 1.0 1.0 1.0 V
V
Hysteresis Voltage Min 2.0V 0.2 0.2 0.2 V
H
Max 2.0V 1.0 1.0 1.0 V
V
V
I
IN
I
CC
Minimum High Level V
OH
Output Voltage
Maximum Low Level V
OL
Output Voltage
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
and VILoccur at V
IH
e
VIHor V
I
l
V
I
l
I
l
I
l
V
I
l
I
l
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
e
e
e
e
e
CC
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
VIHor V
IL
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
VIHor V
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
VCCor GND 6.0V 2.0 20 40 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
A
CC
Typ Guaranteed Limits
6.0V 3.0 3.0 3.0 V
4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
6.0V 1.2 1.2 1.2 V
4.5V 2.2 2.2 2.2 V
6.0V 3.0 3.0 3.0 V
4.5V 0.4 0.4 0.4 V
6.0V 0.5 0.5 0.5 V
4.5V 1.4 1.4 1.4 V
6.0V 1.5 1.5 1.5 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
g
2
0.1
)26V
Min Max Units
CC
A
eb
55 to 125§C
g
CC
a
85
a
125
1.0 mA
)
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
b
40
b
55
V
C
§
C
§
Units
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AC Electrical Characteristics V
CC
e
Symbol Parameter Conditions Typ
t
PHL,tPLH
Maximum Propagation 12 20 ns
Delay
5V, T
e
A
25§C, C
Guaranteed
e
L
Limit
15 pF, t
e
r
e
t
f
Units
6ns
AC Electrical Characteristics V
CC
Symbol Parameter Conditions V
t
PHL,tPLH
t
TLH,tTHL
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Propagation 2.0V 63 125 158 186 ns
Delay 4.5V 13 25 32 37 ns
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
Power Dissipation (per gate) 130 pF
Capacitance (Note 5)
Maximum Input 5 10 10 pF
Capacitance
e
2.0V to 6.0V, C
CC
e
L
e
T
25§C
A
50 pF, t
T
e
e
t
6 ns (unless otherwise specified)
r
f
74HC 54HC
eb
40 to 85§CT
A
eb
A
55 to 125§C
Typ Guaranteed Limits
6.0V 11 21 27 32 ns
6.0V 7 13 16 19 ns
2
e
D
CPDV
a
f
ICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
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Physical Dimensions inches (millimeters)
Order Number MM54HC132J or MM74HC132J
Dual-In-Line Package (J)
NS Package J14A
MM54HC132/MM74HC132 Quad 2-Input NAND Schmitt Trigger
Dual-In-Line Package (N)
Order Number MM74HC132N
NS Package N14A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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a
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a
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