National Semiconductor MM54HC125, MM54HC126, MM74HC125, MM74HC126 Service Manual
MM54HC125/MM74HC125
MM54HC126/MM74HC126
TRI-STATE
Quad Buffers
É
MM54HC125/MM74HC125/MM54HC126/MM74HC126 TRI-STATE Quad Buffers
January 1988
General Description
These are general purpose TRI-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable
high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of
CMOS circuitry, yet have speeds comparable to low power
Schottky TTL circuits. Both circuits are capable of driving up
to 15 low power Schottky inputs.
The MM54HC125/MM74HC125 require the TRI-STATE
control input C to be taken high to put the output into the
high impedance condition, whereas the MM54HC126/
MM74HC126 require the control input to be low to put the
output into high impedance.
All inputs are protected from damage due to static discharge by diodes to V
and ground.
CC
Connection Diagrams
Dual-In-Line Package
Features
Y
Typical propagation delay: 13 ns
Y
Wide operating voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 80 mA maximum (74HC)
Y
Fanout of 15 LS-TTL loads
Dual-In-Line Package
Top View
Order Number MM54HC125 or MM74HC125
Truth Tables
Inputs Output
AC
HL H
LL L
XH Z
TRI-STATEÉis a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Y
TL/F/5308
TL/F/5308– 1
Top View
Order Number MM54HC126 or MM74HC126
Inputs Output
AC
HH H
LH L
XL Z
Y
TL/F/5308– 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
)
b
0.5 toa7.0V
b
1.5 to V
b
CC
0.5 to V
CC
b
65§Ctoa150§C
a
a
g
g
g
1.5V
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
OZ
Maximum TRI-STATE V
Output Leakage V
Current C
I
IN
I
CC
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
and VILoccur at V
IH
e
IN
OUT
e
n
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VIHor V
e
VCCor GND
6.0V
IL
g
0.5
Disabled
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
5
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
A
eb
55 to 125§C
g
g
CC
a
85
a
125
10 mA
1.0 mA
C
C
2
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