Page 1
MM54HC125/MM74HC125
MM54HC126/MM74HC126
TRI-STATE
Quad Buffers
É
MM54HC125/MM74HC125/MM54HC126/MM74HC126 TRI-STATE Quad Buffers
January 1988
General Description
These are general purpose TRI-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable
high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of
CMOS circuitry, yet have speeds comparable to low power
Schottky TTL circuits. Both circuits are capable of driving up
to 15 low power Schottky inputs.
The MM54HC125/MM74HC125 require the TRI-STATE
control input C to be taken high to put the output into the
high impedance condition, whereas the MM54HC126/
MM74HC126 require the control input to be low to put the
output into high impedance.
All inputs are protected from damage due to static discharge by diodes to V
and ground.
CC
Connection Diagrams
Dual-In-Line Package
Features
Y
Typical propagation delay: 13 ns
Y
Wide operating voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 80 mA maximum (74HC)
Y
Fanout of 15 LS-TTL loads
Dual-In-Line Package
Top View
Order Number MM54HC125 or MM74HC125
Truth Tables
Inputs Output
AC
HL H
LL L
XH Z
TRI-STATEÉis a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Y
TL/F/5308
TL/F/5308– 1
Top View
Order Number MM54HC126 or MM74HC126
Inputs Output
AC
HH H
LH L
XL Z
Y
TL/F/5308– 2
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
)
b
0.5 toa7.0V
b
1.5 to V
b
CC
0.5 to V
CC
b
65§Ctoa150§C
a
a
g
g
g
1.5V
0.5V
20 mA
35 mA
70 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
Minimum High Level V
OH
Output Voltage
e
VIHor V
l
IN
I
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
IN
I
OUT
e
V
Maximum Low Level V
OL
Output Voltage
IL
s
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
s
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
OZ
Maximum TRI-STATE V
Output Leakage V
Current C
I
IN
I
CC
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
and VILoccur at V
IH
e
IN
OUT
e
n
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VIHor V
e
VCCor GND
6.0V
IL
g
0.5
Disabled
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 8.0 80 160 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
5
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
A
eb
55 to 125§C
g
g
CC
a
85
a
125
10 mA
1.0 mA
C
C
2
Page 3
e
AC Electrical Characteristics V
CC
5V, T
e
A
25§C, C
Symbol Parameter Conditions Typ
t
PHL,tPLH
t
PZH
t
PHZ
t
PZL
t
PLZ
Maximum 13 18 ns
Propagation Delay Time
Maximum R
Output Enable Time to High Level
Maximum R
Output Disable Time from High Level C
Maximum R
Output Enable Time to Low Level
Maximum R
Output Disable Time from Low Level C
e
1kX 13 25 ns
L
e
1kX 17 25 ns
L
e
5pF
L
e
1kX 18 25 ns
L
e
1kX 13 25 ns
L
e
5pF
L
e
L
45 pF, t
e
e
t
6ns
r
f
Guaranteed
Limit
Units
AC Electrical Characteristics V
e
2.0V to 6.0V, C
CC
Symbol Parameter Conditions V
t
PHL,tPLH
t
PLH,tPHL
t
PZH,tPZL
t
PHZ,tPLZ
t
PZL,tPZH
t
TLH,tTHL
C
IN
C
OUT
C
PD
Maximum Propagation 2.0V 40 100 125 150 ns
Delay Time 4.5V 14 20 25 30 ns
Maximum Propagation C
Delay Time 4.5V 14 26 33 39 ns
Maximum Output R
Enable Time 4.5V 14 25 31 38 ns
Maximum Output R
Disable Time 4.5V 14 25 31 38 ns
Maximum Output C
Enable Time R
Maximum Output C
Rise and Fall Time 4.5V 7 12 15 18 ns
e
150 pF 2.0V 35 130 163 195 ns
L
e
1kX 2.0V 25 125 156 188 ns
L
e
1kX 2.0V 25 125 156 188 ns
L
e
150 pF 2.0V 35 140 175 210 ns
L
e
1kX 4.5V 15 28 35 42 ns
L
e
50 pF 2.0V 30 60 75 90 ns
L
Input Capacitance 5 10 10 10 pF
Output Capacitance Outputs 15 20 20 20 pF
Power Dissipation (per gate)
Capacitance (Note 5) Enabled 45 pF
Disabled 6 pF
Note 5: CPDdetermines the no load dynamic power consumption, P
e
CPDV
D
e
L
50 pF, t
e
e
t
6 ns (unless otherwise specified)
r
f
Temperature§C
54HC/74HC 74HC 54HC
CC
e
T
25§C
A
b
40 to 85§Cb55 to 125§C
Units
Typ Guaranteed Limits
6.0V 12 17 21 25 ns
6.0V 12 22 28 33 ns
6.0V 12 21 26 31 ns
6.0V 12 21 26 31 ns
6.0V 13 24 30 36 ns
6.0V 6 10 13 15 ns
2
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
3
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Physical Dimensions inches (millimeters)
Order Number MM54HC125J, MM54HC126J, MM74HC125J, or MM74HC126J
NS Package J14A
Order Number MM74HC125N, or MM74HC126N
LIFE SUPPORT POLICY
NS Package N14A
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
MM54HC125/MM74HC125/MM54HC126/MM74HC126 TRI-STATE Quad Buffers
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
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a
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