Page 1
MM54HC107/MM74HC107
Dual J-K Flip-Flops with Clear
MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear
January 1988
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology to achieve the high noise immunity and low power dissipation of standard CMOS integrated circuits. These
devices can drive 10 LS-TTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and CLEAR
inputs and Q and Q
clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to V
outputs. CLEAR is independent of the
and ground.
CC
Connection Diagram
Dual-In-Line Package
Features
Y
Typical propagation delay: 16 ns
Y
Wide operating voltage range: 2 –6V
Y
Low input current: 1 mA maximum
Y
Low quiescent current: 40 mA (74HC series)
Y
High output drive: 10 LS-TTL loads
Truth Table
Inputs Outputs
CLR CLK J K Q Q
LXXXLH
H
H
H
H
H H X X Q0 Q
L L Q0 Q0
v
HL H L
v
LH L H
v
H H TOGGLE
v
0
TL/F/5304– 1
Order Number MM54HC107 or MM74HC107
Logic Diagram
TL/F/5304– 3
TL/F/5304– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5304
Page 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
e
V
2.0V(tr,tf) 1000 ns
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260§C
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
IH
Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum High Level V
Output Voltage
e
VIHor V
l
I
IN
OUT
IL
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
l
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
l
I
IN
OUT
e
V
OL
Maximum Low Level V
Output Voltage
IL
s
4.0 mA 4.5V 3.98 3.84 3.7 V
l
s
5.2 mA 6.0V 5.48 5.34 5.2 V
l
VIHor V
IL
s
20 mA 2.0V 0 0.1 0.1 0.1 V
l
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
e
V
VIHor V
IN
I
l
OUT
I
l
OUT
I
IN
I
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
I
**V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
g
and VILoccur at V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
OZ
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
IH
e
IN
e
IN
OUT
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
IL
s
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
VCCor GND 6.0V
g
0.1
VCCor GND 6.0V 4.0 40 80 mA
e
0 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
V
§
§
Units
b
b
40
55
eb
A
55 to 125§C
g
CC
a
85
a
125
1.0 mA
C
C
2
Page 3
AC Electrical Characteristics V
CC
e
5V, T
Symbol Parameter Conditions Typ
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REM
t
s
t
H
t
W
Maximum Operating 50 30 MHz
Frequency
Maximum Propagation 16 21 ns
Delay Clock to Q or Q
Maximum Propagation 21 26 ns
Delay Clear to Q or Q
Minimum Removal Time, 10 20 ns
Clear to Clock
Minimum Setup Time, 14 20 ns
J or K to Clock
Minimum Hold Time
J or K from Clock
Minimum Pulse Width, 10 16 ns
Clock or Clear
e
A
b
30 ns
25§C, C
Guaranteed
e
L
Limit
15 pF, t
e
r
e
t
f
Units
6ns
AC Electrical Characteristics C
e
L
Symbol Parameter Conditions V
f
MAX
t
PHL,tPLH
t
PHL,tPLH
t
REM
t
s
t
H
t
W
t
TLH,tTHL
tr,t
f
C
PD
C
IN
Note 5: CPDdetermines the no load dynamic power consumption, P
Maximum Operating 2.0V 9 5 4 3 MHz
Frequency 4.5V 45 27 21 18 MHz
Maximum Propagation 2.0V 70 126 160 185 ns
Delay Clock to Q or Q
Maximum Propagation 2.0V 126 155 194 250 ns
Delay Clear to Q or Q 4.5V 25 31 39 47 ns
Minimum Removal Time 2.0V 55 100 125 150 ns
Clear to Clock 4.5V 11 20 25 30 ns
Minimum Setup Time 2.0V 77 100 125 150 ns
J or K to Clock 4.5V 15 20 25 30 ns
Minimum Hold Time 2.0Vb30 0 0 ns
J or K to Clock 4.5V
Minimum Pulse Width 2.0V 55 80 100 120 ns
Clear or Clock 4.5V 11 16 20 24 ns
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
Power Dissipation (per flip-flop) 80 pF
Capacitance (Note 5)
Maximum Input 5 10 10 10 pF
Capacitance
e
CC
e
t
6 ns (unless otherwise specified)
r
f
e
T
25§C
A
eb
T
A
74HC 54HC
40 to 85§CT
A
eb
55 to 125§C
50 pF, t
Typ Guaranteed Limits
6.0V 53 31 24 20 MHz
4.5V 18 25 32 37 ns
6.0V 16 21 27 32 ns
6.0V 21 26 32 40 ns
6.0V 9 17 21 25 ns
6.0V 13 17 21 25 ns
b
30 0 0 ns
b
6.0V
30 0 0 ns
6.0V 10 14 18 21 ns
6.0V 7 13 16 19 ns
6.0V 400 400 400 ns
2
e
CPDV
D
faICCVCC, and the no load dynamic current consumption, I
CC
e
CPDVCCfaICC.
S
Units
3
Page 4
Typical Applications
N Bit Binary Ripple Counter with Enable and Reset
TL/F/5304– 4
N Bit Shift Register with Clear
TL/F/5304– 5
4
Page 5
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HC107J or MM74HC107J
NS Package Number J14A
5
Page 6
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM74HC107N
NS Package Number N14A
MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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Tel: 1(800) 272-9959 Deutsch Tel: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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