National Semiconductor MM54HC05, MM74HC05 Service Manual
MM54HC05/MM74HC05
Hex Inverter (Open Drain)
MM54HC05/MM74HC05 Hex Inverter (Open Drain)
January 1988
General Description
The MM54HC05/MM74HC05 are logic functions fabricated
by using advanced silicon-gate CMOS technology, which
provides the inherent benefits of CMOSÐlow quiescent
power and wide power supply range. These devices are
also functionally and pin-out compatible with standard
DM54LS/DM74LS logic families. The MM54HC05/
MM74HC05 open drain Hex Inverter requires the addition of
an external resistor to perform a wire-NOR function.
All inputs are protected from static discharge damage by
internal diodes to V
and ground.
CC
Connection Diagram
Dual-In-Line Package
Top View
Order Number MM54HC05 or MM74HC05
Features
Y
Open drain for wire-NOR function
Y
Fanout of 10 LS-TTL loads
Y
Typical propagation delays:
t
(with 1 kX resistor) 8 ns
PZL
t
(with 1 kX resistor) 13 ns
PLZ
Y
Low input current: 1 mA maximum
TL/F/9388– 1
Logic Diagram
TL/F/9388– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/9388
Typical Application
TL/F/9388– 3
Note: Can be extended to more than 2 inputs.
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Clamp Diode Current (IIK,IOK)
DC Output Current, per pin (I
OUT
)
DC VCCor GND Current, per pin (ICC)
Storage Temperature Range (T
STG
b
b
)
b
0.5V toa7.0V
1.5V to V
CC
0.5V to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage 0 V
(V
IN,VOUT
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
(t
r,tf)VCC
V
CC
V
CC
)26V
CC
)
e
2.0V 1000 ns
e
4.5V 500 ns
e
6.0V 400 ns
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
)
L
C
§
DC Electrical Characteristics (Note 4)
e
T
25§C
Symbol Parameter Conditions V
CC
A
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
I
I
I
Maximum Low Level V
OL
Output Voltage
Maximum High Level V
LKG
Output Leakage Current V
Maximum Input V
IN
Current
Maximum Quiescent V
CC
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
designing with this supply. Worst case V
, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
(I
IN,ICC
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
e
V
IN
IH
s
I
20 mA 2.0V 0 0.1 0.1 0.1 V
l
l
OUT
e %
R
L
e
V
V
IN
IH
s
I
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
l
OUT
s
I
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
l
OUT
e
VIHor VIL6.0V
IN
e
V
OUT
CC
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V
IN
e
0 mA
OUT
g
10% the worst case output voltages (VOHand VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
and VILoccur at V
IH
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
0.5 5 10 mA
g
0.1
2.0 20 40 mA
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current
CC
74HC 54HC
eb
T
40§Ctoa85§CT
A
g
1.0
Min Max Units
)
A
A
b
b
eb
a
40
a
55
55§Ctoa125§C
g
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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