National Semiconductor MM54HC03, MM74HC03 Service Manual
MM54HC03/MM74HC03 Quad 2-Input
Open Drain NAND Gate
MM54HC03/MM74HC03 Quad 2-Input Open Drain NAND Gate
January 1988
General Description
These NAND gates utilize advanced silicon-gate CMOS
technology to achieve operating speeds similar to LS-TTL
gates with the low power consumption of standard CMOS
integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10
LS-TTL loads. The 54HC/74HC logic family is functionally
as well as pin-out compatible with the standard 54LS/74LS
logic family. All inputs are protected from damage due to
static discharge by internal diode clamps to V
ground.
As with standard 54HC/74HC push-pull outputs there are
diodes to both V
not be pulled above V
diode voltage above V
electrostatic protection.
and ground. Therefore the output should
CC
as it would be clamped to one
CC
. This diode is added to enhance
CC
CC
and
Connection and Logic Diagrams
Dual-In-Line Package
Features
Y
Typical propagation delay: 12 ns
Y
Wide power supply range: 2–6V
Y
Low quiescent current: 20 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Top View
Order Number MM54HC03 or MM74HC03
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5295
TL/F/5295– 1
TL/F/5295– 2
Absolute Maximum Ratings (Notes1&2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC)
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
CC
IN
)
)
OUT
D
IK,IOK
)
)
)
)
OUT
STG
b
b
)
b
0.5 toa7.0V
1.5 to V
CC
0.5 to V
CC
g
g
b
g
65§Ctoa150§C
a
1.5V
a
0.5V
20 mA
25 mA
50 mA
S.O. Package only 500 mW
Lead Temp. (T
) (Soldering 10 seconds) 260§C
L
Supply Voltage (V
)26V
CC
DC Input or Output Voltage 0 V
(V
IN,VOUT
)
Operating Temp. Range (T
MM74HC
MM54HC
Input Rise or Fall Times
e
2.0V(tr,tf) 1000 ns
V
CC
e
V
4.5V 500 ns
CC
e
V
6.0V 400 ns
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions V
CC
A
e
T
25§C
Typ Guaranteed Limits
V
Minimum High Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
Maximum Low Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
I
LKG
I
IN
I
CC
Minimum Low Level V
OL
Output Voltage
Maximum High Level V
Output Leakage Current V
Maximum Input V
Current
Maximum Quiescent V
Supply Current I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package:
Note 4: For a power supply of 5V
with this supply. Worst case V
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V
limits are currently tested at 20% of VCC. The above VILspecification (30% of VCC) will be implemented no later than Q1, CY’89.
IL
g
10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
and VILoccur at V
IH
e
V
IN
IH
s
I
20 mA 2.0V 0 0.1 0.1 0.1 V
l
l
OUT
e %
R
L
e
V
V
IN
IH
s
I
4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
l
OUT
s
I
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
l
l
OUT
e
VIHor V
IN
e
V
OUT
CC
e
VCCor GND 6.0V
IN
e
VCCor GND 6.0V 2.0 20 40 mA
IN
e
0 mA
OUT
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst case leakage current (IIN,ICC, and
CC
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
6.0V 0.5 5 10 mA
IL
g
0.1
b
12 mW/§C from 65§Cto85§C; ceramic ‘‘J’’ package:b12 mW/§C from 100§Cto125§C.
74HC 54HC
eb
T
40 to 85§CT
A
g
1.0
Min Max Units
)
A
b
b
40
55
A
eb
55 to 125§C
g
a
a
1.0 mA
CC
85
125
V
C
§
C
§
Units
2
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