National Semiconductor MM54C74, MM74C74 Technical data
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MM54C74/MM74C74 Dual D Flip-Flop
General Description
The MM54C74/MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. Each flipflop has independent data, preset, clear and clock inputs
and Q and Q
input is transferred to the output during the positive going
transition of the clock pulse. Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input.
Features
Y
Supply voltage range 3V to 15V
Y
Tenth power TTL compatible Drive 2 LPT2L loads
Y
High noise immunity 0.45 VCC(typ.)
Logic Diagram
outputs. The logic level present at the data
February 1988
Y
Low power 50 nW (typ.)
Y
Medium speed operation 10 MHz (typ.)
with 10V supply
Applications
Y
Automotive
Y
Data terminals
Y
Instrumentation
Y
Medical electronics
Y
Alarm system
Y
Industrial electronics
Y
Remote metering
Y
Computers
MM54C74/MM74C74 Dual D Flip-Flop
TL/F/5885– 1
Truth Table
Preset Clear Q
Q
n
n
Connection Diagram
Dual-In-Line Package
0000
0110
1001
11*Q
*No change in output from previous state.
*Q
n
n
Order Number MM54C74 or MM74C74
Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.
A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5885
Top View
TL/F/5885– 2
Absolute Maximum Ratings (Note 1)
b
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C74
MM74C74
b
0.3V to V
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (Soldering, 10 seconds) 260
Operating V
Range 3V to 15V
CC
VCC(Max) 18V
65§Ctoa150§C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Output Source Current V
Output Source Current V
Output Sink Current V
Output Sink Current V
e
5V 3.5 V
CC
e
V
10V 80 V
CC
e
5V 1.5 V
CC
e
V
10V 2.0 V
CC
e
5V 4.5 V
CC
e
V
10V 9.0 V
CC
e
5V 0.5 V
CC
e
V
10V 1.0 V
CC
e
15V 1.0 m A
CC
e
15V
CC
e
15V 0.05 60 mA
CC
e
4.5V
CC
CC
A
CC
A
CC
A
CC
A
e
e
e
e
e
e
e
e
e
CC
e
CC
e
CC
e
CC
e
CC
e
CC
e
CC
5V, V
25§C, V
10V, V
25§C, V
5V, V
25§C, V
10V, V
25§C, V
4.75V
4.75V
4.75V
4.5V, I
4.75V, I
4.5V, I
4.75V, I
IN(0)
OUT
IN(0)
OUT
IN(1)
OUT
IN(1)
OUT
eb
360 mA
D
eb
360 mA
D
e
360 mA
D
e
360 mA
D
e
0V
e
0V
e
0V
e
0V
e
5V
e
V
CC
e
10V
e
V
CC
74C, V
74C, V
74C, V
74C, V
T
T
T
T
b
1.0 mA
b
1.5
V
CC
2.4 V
b
1.75 mA
b
8.0 mA
1.75 mA
8.0 mA
0.8 V
0.4 V
C
§
2
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