National Semiconductor MM54C74, MM74C74 Technical data

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MM54C74/MM74C74 Dual D Flip-Flop

General Description

The MM54C74/MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. Each flip­flop has independent data, preset, clear and clock inputs
and Q and Q
input is transferred to the output during the positive going
transition of the clock pulse. Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input.

Features

Y

Supply voltage range 3V to 15V

Y

Tenth power TTL compatible Drive 2 LPT2L loads

Y

High noise immunity 0.45 VCC(typ.)

Logic Diagram

outputs. The logic level present at the data

February 1988

Y

Low power 50 nW (typ.)

Y

Medium speed operation 10 MHz (typ.)

with 10V supply

Applications

Y

Automotive

Y

Data terminals

Y

Instrumentation

Y

Medical electronics

Y

Alarm system

Y

Industrial electronics

Y

Remote metering

Y

Computers

MM54C74/MM74C74 Dual D Flip-Flop

TL/F/5885– 1

Truth Table

Preset Clear Q

Q

n

n

Connection Diagram

Dual-In-Line Package

0000
0110
1001
11*Q

*No change in output from previous state.

*Q

n

n

Order Number MM54C74 or MM74C74

Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.

A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/5885

Top View

TL/F/5885– 2

Absolute Maximum Ratings (Note 1)

b

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at Any Pin (Note 1)

Operating Temperature Range

MM54C74
MM74C74

b

0.3V to V

b

b

a

0.3V

CC

55§Ctoa125§C

40§Ctoa85§C

Storage Temperature Range

Power Dissipation

Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature (Soldering, 10 seconds) 260

Operating V

Range 3V to 15V

CC

VCC(Max) 18V

65§Ctoa150§C

DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

V

IN(0)

V

OUT(1)

V

OUT(0)

I

IN(1)

I

IN(0)

I

CC

Logical ‘‘1’’ Input Voltage V

Logical ‘‘0’’ Input Voltage V

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

Supply Current V

CMOS/LPTTL INTERFACE

V

IN(1)

V

IN(0)

V

OUT(1)

V

OUT(0)

Logical ‘‘1’’ Input Voltage 54C, V

Logical ‘‘0’’ Input Voltage 54C, V

Logical ‘‘1’’ Output Voltage 54C, V

Logical ‘‘0’’ Output Voltage 54C, V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)

I

SOURCE

I

SOURCE

I

SINK

I

SINK

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.

Output Source Current V

Output Source Current V

Output Sink Current V

Output Sink Current V

e

5V 3.5 V

CC

e

V

10V 80 V

CC

e

5V 1.5 V

CC

e

V

10V 2.0 V

CC

e

5V 4.5 V

CC

e

V

10V 9.0 V

CC

e

5V 0.5 V

CC

e

V

10V 1.0 V

CC

e

15V 1.0 m A

CC

e

15V

CC

e

15V 0.05 60 mA

CC

e

4.5V

CC

CC
A

CC
A

CC
A

CC
A

e

e

e

e

e

e

e

e

e

CC

e

CC

e

CC

e

CC

e

CC

e

CC

e

CC

5V, V

25§C, V

10V, V

25§C, V

5V, V

25§C, V

10V, V

25§C, V

4.75V

4.75V

4.75V

4.5V, I

4.75V, I

4.5V, I

4.75V, I

IN(0)

OUT

IN(0)

OUT

IN(1)

OUT

IN(1)

OUT

eb

360 mA

D

eb

360 mA

D

e

360 mA

D

e

360 mA

D

e

0V

e

0V

e

0V

e

0V

e

5V

e

V

CC

e

10V

e

V

CC

74C, V

74C, V

74C, V

74C, V

T

T

T

T

b

1.0 mA

b

1.5

V

CC

2.4 V

b

1.75 mA

b

8.0 mA

1.75 mA

8.0 mA

0.8 V

0.4 V

C

§

2

AC Electrical Characteristics* T

e

A

25§C, C

e

50 pF, unless otherwise noted

L

Symbol Parameter Conditions Min Typ Max Units

C

IN

t

pd

t

pd

t

pd

tS0,t

S1

tH0,t

H1

t

PW1

t

PW2

tr,t

f

f

MAX

C

PD

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.

Note 2: Capacitance is guaranteed by periodic testing.

Note 3: C

NoteÐAN-90.

Input Capacitance Any Input (Note 2) 5.0 pF

Propagation Delay Time to a V
Logical ‘‘0’’ t
t

from Clock to Q or Q

pd1

or Logical ‘‘1’’ V

pd0

Propagation Delay Time to a V
Logical ‘‘0’’ from Preset or Clear V

Propagation Delay Time to a V
Logical ‘‘1’’ from Preset or Clear V

Time Prior to Clock Pulse that V
Data Must be Present t

SETUP

Time after Clock Pulse that V
Data Must be Held V

Minimum Clock Pulse V
Width (t

e

tWH)V

WL

Minimum Preset and V
Clear Pulse Width V

Maximum Clock Rise V
and Fall Time V

Maximum Clock Frequency V

e

5V 180 300 ns

CC

e

10V 70 110 ns

CC

e

5V 180 300 ns

CC

e

10V 70 110 ns

CC

e

5V 250 400 ns

CC

e

10V 100 150 ns

CC

e

5V 100 50 ns

CC

e

V

10V 40 20 ns

CC

e

5V

CC

e

10V

CC

e

5V 100 250 ns

CC

e

10V 40 100 ns

CC

e

5V 100 160 ns

CC

e

10V 40 70 ns

CC

e

5V 15.0 ms

CC

e

10V 5.0 ms

CC

e

5V 2.0 3.5 MHz

CC

e

V

10V 5.0 8.0 MHz

CC

b

20 0 ns

b

8.0 0 ns

Power Dissipation Capacitance (Note 3) 40 pF

determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application

PD

Switching Time Waveform

CMOS to CMOS

e

e

t

t

20 ns

r

f

3

TL/F/5885– 3

AC Test Circuit

Typical Applications

74C Compatibility

Ripple Counter (Divide by 2n)

Shift Register

TL/F/5885– 4

TL/F/5885– 5

TL/F/5885– 6

Guaranteed Noise Margin
as a Function of V

CC

TL/F/5885– 7

TL/F/5885– 8

4

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number MM54C74J or MM74C74J

NS Package Number J14A

5

Physical Dimensions inches (millimeters) (Continued)

MM54C74/MM74C74 Dual D Flip-Flop

Order Number MM54C74N or MM74C74N

NS Package Number N14A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

Ceramic Dual-In-Line Package (J)

National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (
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Tel: [phone] Deutsch Tel: (
Fax: [phone] English Tel: (

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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a

49) 0-180-530 85 86 13th Floor, Straight Block, Tel: [phone]

a

49) 0-180-530 85 85 Tsimshatsui, Kowloon

a

49) 0-180-532 78 32 Hong Kong

a

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a

49) 0-180-534 16 80 Fax: [phone]