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MM54C373/MM74C373 TRI-STATEÉOctal D-Type Latch
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop
General Description
The MM54C373/MM74C373, MM54C374/MM74C374 are
integrated, complementary MOS (CMOS), 8-bit storage elements with TRI-STATE outputs. These outputs have been
specially designed to drive high capacitive loads, such as
one might find when driving a bus, and to have a fan out of 1
when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The MM54C373/MM74C373 is an 8-bit latch. When LATCH
ENABLE is high, the Q outputs will follow the D inputs.
When LATCH
which meets the set-up and hold time requirements, will be
retained at the outputs until LATCH
again.
The MM54C374/MM74C374 is an 8-bit, D-type, positiveedge triggered flip-flop. Data at the D inputs, meeting the
set-up and hold time requirements, is transferred to the Q
outputs on positive-going transitions of the CLOCK input.
ENABLE goes low, data at the D inputs,
ENABLE returns high
March 1988
Both the MM54C373/MM74C373 and the MM54C374/
MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300
pin centers.
×
Features
Y
Wide supply voltage range 3V to 15V
Y
High noise immunity 0.45 VCC(typ.)
Y
Low power consumption
Y
TTL compatibility Fan out of 1
Y
Bus driving capability
Y
TRI-STATE outputs
Y
Eight storage elements in one package
Y
Single CLOCK/LATCH ENABLE and OUTPUT
DISABLE control inputs
Y
20-pin dual-in-line package with 0.300×centers takes
half the board space of a 24-pin package
driving standard TTL
MM54C373/MM74C373 TRI-STATE Octal D-Type Latch
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop
Connection Diagrams
MM54C373/MM74C373
Dual-In-Line Package
Top View
Order Number MM54C373 or MM74C373
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5906
TL/F/5906– 1
MM54C374/MM74C374
Dual-In-Line Package
TL/F/5906– 2
Top View
Order Number MM54C374 or MM74C374
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range (TA)
MM54C373
MM74C373
Storage Temperature Range (TS)
b
0.3V to V
b
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
65§Ctoa150§C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
Absolute Maximum V
Lead Temperature (T
(Soldering, 10 seconds) 260
Range 3V to 15V
CC
CC
)
L
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
OZ
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
TRI-STATE Leakage Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C V
Logical ‘‘0’’ Input Voltage 54C V
Logical ‘‘1’’ Output Voltage 54C V
Logical ‘‘0’’ Output Voltage 54C V
OUTPUT DRIVE (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Output Source Current V
Output Source Current V
Output Sink Current V
(N-Channel) T
Output Sink Current V
(N-Channel) T
e
5V 3.5 V
CC
e
V
10V 8.0 V
CC
e
5V 1.5 V
CC
e
V
10V 2.0 V
CC
e
eb
5V, I
CC
e
V
10V, I
CC
e
5V, I
CC
e
V
10V, I
CC
e
15V, V
CC
e
15V, V
CC
e
15V, V
CC
e
V
15V, V
CC
e
15V 0.05 300 mA
CC
74C V
54C V
74C V
54C V
74C V
74C V
e
5V, V
CC
e
25§C (Note 4)
T
A
e
10V, V
CC
e
25§C (Note 4)
T
A
e
5V, V
CC
e
25§C (Note 4)
A
e
10V, V
CC
e
25§C (Note 4)
A
10 mA 4.5 V
O
eb
10 mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
e
15V 0.005 1.0 mA
IN
e
0V
IN
e
15V 0.005 1.0 mA
O
e
0V
O
e
4.5V V
CC
e
4.75V V
CC
e
4.5V 0.8 V
CC
e
4.75V 0.8 V
CC
CC
CC
CC
CC
CC
CC
e
e
e
e
e
e
OUT
OUT
OUT
OUT
4.5V, I
4.75V, I
4.5V, I
4.75V, I
4.5V, I
4.75V, I
e
0V
e
e
V
e
eb
360 mAV
O
eb
360 mAV
O
eb
1.6 mA 2.4 V
O
eb
1.6 mA 2.4 V
O
e
1.6 mA 0.4 V
O
e
1.6 mA 0.4 V
O
0V
CC
V
CC
CC
CC
CC
CC
b
1.0
b
1.0
b
b
b
b
b
12
b
24
b
0.005 mA
b
0.005 mA
1.5 V
1.5 V
0.4 V
0.4 V
b
24 mA
b
48 mA
612 mA
24 48 mA
18V
C
§
2
AC Electrical Characteristics*
MM54C373/MM74C373, T
e
A
25§C, C
L
e
50 pF, t
e
e
t
r
20 ns, unless otherwise noted
f
Symbol Parameter Conditions Min Typ Max Units
t
pd0,tpd1
t
pd0,tpd1
t
SET-UP
f
MAX
t
PWH
tr,t
f
t1H,t
0H
Propagation Delay, V
LATCH
ENABLE to Output V
Propagation Delay Data LATCH ENABLEeV
In to Output V
Minimum Set-Up Time Data In t
to CLOCK/LATCH
ENABLE V
Maximum LATCH ENABLE
Frequency V
Minimum LATCH ENABLE VCC5V 75 150 ns
Pulse Width V
Maximum LATCH ENABLE V
Rise and Fall Time V
Propagation Delay OUTPUT R
DISABLE to High Impedance V
State (from a Logic Level) V
tH1,t
H0
Propagation Delay OUTPUT R
DISABLE to Logic Level V
(from High Impedance State) V
t
THL,tTLH
C
LE
C
OD
C
IN
C
OUT
C
PD
*AC Parameters are guaranteed by DC correlated testing.
Transition Time V
Input Capacitance LE Input (Note 2) 7.5 10 pF
Input Capacitance OUTPUT DISABLE
Input Capacitance Any Other Input (Note 2) 5 7.5 pF
Output Capacitance High Impedance
Power Dissipation Capacitance Per Package (Note 3) 200 pF
e
CC
e
CC
e
V
CC
e
V
CC
e
CC
e
V
CC
e
V
CC
e
V
CC
HOLD
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
e
CC
e
CC
e
L
e
CC
e
CC
e
L
e
CC
e
CC
e
CC
e
V
CC
e
V
CC
e
V
CC
Input (Note 2)
State (Note 2)
e
5V, C
10V, C
5V, C
10V, C
5V, C
10V, C
5V, C
10V, C
e
50 pF 165 330 ns
L
e
50 pF 70 140 ns
L
e
150 pF 195 390 ns
L
e
150 pF 85 170 ns
L
CC
e
50 pF 155 310 ns
L
e
50 pF 70 140 ns
L
e
150 pF 185 370 ns
L
e
150 pF 85 170 ns
L
0ns
5V 70 140 ns
10V 35 70 ns
5V 3.5 6.7 MHz
10V 4.5 9.0 MHz
10V 55 110 ns
5V NA ms
10V NA ms
e
10k, C
5pF
L
5V 105 210 ns
10V 60 120 ns
e
10k, C
50 pF
L
5V 105 210 ns
10V 45 90 ns
e
5V, C
10V, C
5V, C
10V, C
50 pF 65 130 ns
L
e
50 pF 35 70 ns
L
e
150 pF 110 220 ns
L
e
150 pF 70 140 ns
L
7.5 10 pF
10 15 pF
3
AC Electrical Characteristics* (Continued)
MM54C374/MM74C374, T
e
A
25§C, C
L
e
50 pF, t
e
e
t
r
20 ns, unless otherwise noted
f
Symbol Parameter Conditions Min Typ Max Units
t
pd0,tpd1
t
SET-UP
t
PWH,tPWL
f
MAX
t1H,t
0H
Propagation Delay, V
CLOCK to Output V
Minimum Set-Up Time Data In t
to CLOCK/LATCH ENABLE V
Minimum CLOCK Pulse Width V
Maximum CLOCK Frequency V
Propagation Delay OUTPUT R
DISABLE to High Impedance V
State (from a Logic Level) V
tH1,t
H0
Propagation Delay OUTPUT R
DISABLE to Logic Level V
(from High Impedance State) V
t
THL,tTLH
tr,t
f
C
CLK
C
OD
C
IN
C
OUT
C
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
PD
AN-90.
Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA max.
Transition Time V
Maximum CLOCK Rise V
and Fall Time V
Input Capacitance CLOCK Input (Note 2) 7.5 10 pF
Input Capacitance OUTPUT DISABLE
Input Capacitance Any Other Input (Note 2) 5 7.5 pF
Output Capacitance High Impedance
Power Dissipation Capacitance Per Package (Note 3) 250 pF
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note
e
CC
e
CC
e
V
CC
e
V
CC
HOLD
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
e
V
CC
e
L
e
CC
e
CC
e
L
e
CC
e
CC
e
CC
e
V
CC
e
V
CC
e
V
CC
e
CC
e
CC
Input (Note 2)
State (Note 2)
e
5V, C
10V, C
5V, C
10V, C
e
50 pF 150 300 ns
L
e
50 pF 65 130 ns
L
e
150 pF 180 360 ns
L
e
150 pF 80 160 ns
L
0ns
5V 70 140 ns
10V 35 70 ns
5V 70 140 ns
10V 50 100 ns
5V 3.5 7.0 MHz
10V 5 10 MHz
e
10k, C
50 pF
L
5V 105 210 ns
10V 60 120 ns
e
10k, C
50 pF
L
5V 105 210 ns
10V 45 90 ns
e
5V, C
10V, C
5V, C
10V, C
5V 15
10V 5
50 pF 65 130 ns
L
e
50 pF 35 70 ns
L
e
150 pF 110 220 ns
L
e
150 pF 70 140 ns
L
l
2000 ms
l
2000 ms
7.5 10 pF
10 15 pF
4
Typical Performance Characteristics T
e
25§C
A
MM54C373/MM74C373
Propagation Delay, LATCH
to Output vs Load
ENABLE
Capacitance
MM54C373/MM74C373,
MM54C374/MM74C374
Change in Propagation Delay per
pF of Load Capacitance (Dt
vs Power Supply Voltage
PD
/pF)
MM54C373/MM74C373
Propagation Delay,
Data In to Output
vs Load Capacitance
MM54C373/MM74C373,
MM54C374/MM74C374
Output Sink Current vs V
OUT
MM54C374/MM74C374
Propagation Delay,
CLOCK to Output
vs Load Capacitance
TL/F/5906– 3
MM54C373/MM74C373,
MM54C374/MM74C374 Output
Source Current vs V
CC
b
V
OUT
Truth Table
MM54C373/MM74C373
Output LATCH
Disable ENABLE
LHHH
LHLL
LLXQ
H X X Hi-Z
DQ
MM54C374/MM74C374
Output
Disable
Clock D Q
L L HH
L LLL
LLXQ
LHXQ
H X X Hi-Z
5
LeLow logic level
e
H
High logic level
e
X
Irrelevant
e
L
Low to high logic level transition
e
Q
Preexisting output level
e
Hi-Z
High impedance output state
TL/F/5906– 4
Typical Applications
Data Bus Interfacing Element
TL/F/5906– 5
Logic Diagrams
Simple, Latching, Octal, LED Indicator
Driver with Blanking for Use as Data Display,
Bus Monitor, mP Front Panel Display, Etc.
TL/F/5906– 6
MM54C373/MM74C373 (1 of 8 Latches)
MM54C374/MM74C374 (1 of 8 Flip-Flops)
6
TL/F/5906– 7
TL/F/5906– 8
TRI-STATE Test Circuits and Switching Time Waveforms
t1H,t
H1
TL/F/5906– 9
t0H,t
H0
TL/F/5906– 11
Switching Time Waveforms
e
t1H,C
t0H,C
5pF tH1,C
L
e
5pF tH0,C
L
MM54C373/MM74C373
e
50 pF
L
TL/F/5906– 10
e
50 pF
L
TL/F/5906– 12
MM54C374/MM74C374
7
Output DisableeGND
TL/F/5906– 13
Output DisableeGND
TL/F/5906– 14
Physical Dimensions inches (millimeters)
Order Number MM54C373J, MM54C374J, MM74C373J or MM74C374J
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
MM54C373/MM74C373 TRI-STATE Octal D-Type Latch
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop
Order Number MM54C373N, MM54C374N, MM74C373N or MM74C374N
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
Molded Dual-In-Line Package (N)
NS Package Number N20A
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