These up/down counters are monolithic complementary
MOS (CMOS) integrated circuits. The MM54C192 and
MM74C192 are BCD counters, while the MM54C193 and
MM74C193 are binary counters.
Counting up and counting down is performed by two count
inputs, one being held high while the other is clocked. The
outputs change on the positive-going transition of this clock.
These counters feature preset inputs that are set when load
is a logical ‘‘0’’ and a clear which forces all outputs to ‘‘0’’
when it is at a logical ‘‘1’’. The counters also have carry and
borrow outputs so that they can be cascaded using no external circuitry.
Connection Diagram
Dual-In-Line Package
Features
Y
High noise margin1V guaranteed
Y
Tenth power TTL compatibleDrive 2 LPTTL loads
Y
Wide supply range3V to 15V
Y
Carry and borrow outputs for N-bit cascading
Y
Asynchronous clear
Y
High noise immunity0.45 VCC(typ.)
Top View
Order Number MM54C192, MM74C192,
MM54C193 or MM74C193
C
1995 National Semiconductor CorporationRRD-B30M105/Printed in U. S. A.
TL/F/5901
TL/F/5901– 1
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range (TA)
MM54C154
MM74C154
b
0.3V to V
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range (T
)
S
Maximum VCCVoltage18V
Power Dissipation (PD)
Dual-In-Line700 mW
Small Outline500 mW
Operating V
Range3V to 15V
CC
Lead Temperature (TA)
65§Ctoa150§C
b
(Soldering, 10 sec.)260
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
SymbolParameterConditionsMinTypMaxUnits
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input VoltageV
Logical ‘‘0’’ Input VoltageV
Logical ‘‘1’’ Output VoltageV
Logical ‘‘0’’ Output VoltageV
Logical ‘‘1’’ Input CurrentV
Logical ‘‘0’’ Input CurrentV
Supply CurrentV
CMOS TO LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage54C V
Logical ‘‘0’’ Input Voltage54C V
Logical ‘‘1’’ Output Voltage54C V
Logical ‘‘0’’ Output Voltage54C V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Output Source CurrentV
Output Source CurrentV
Output Sink CurrentV
Output Sink CurrentV
e
5V3.5V
CC
e
V
10V8.0V
CC
e
5V1.5V
CC
e
V
10V2.0V
CC
e
eb
5V, I
CC
e
V
10V, I
CC
e
5V, I
CC
e
V
10V, I
CC
e
15V, V
CC
e
15V, V
CC
e
15V0.05300mA
CC
CC
74C V
CC
CC
74C V
CC
CC
74C V
CC
CC
74C V
CC
e
5V, V
CC
e
25§C, V
T
A
e
10V, V
CC
e
25§C, V
T
A
e
5V, V
CC
e
T
25§C, V
A
e
10V, V
CC
e
T
25§C, V
A
10 mA4.5V
O
eb
10 mA9.0V
O
e
10 mA0.5V
O
e
10 mA1.0V
O
e
15V0.0051.0mA
IN
e
0V
IN
e
4.5VV
e
4.75VV
e
4.5V0.8V
e
4.75V0.8V
e
e
e
e
4.5V, I
4.75V, I
4.5V, I
4.75V, I
IN(0)
OUT
IN(0)
OUT
IN(1)
OUT
IN(1)
OUT
eb
100 mA2.4V
O
eb
100 mA2.4V
O
e
360 mA0.4V
O
e
360 mA0.4V
O
e
0V
e
0V
e
0V
e
0V
e
5V
e
V
CC
e
10V
e
V
CC
b
1.0
b
CC
b
CC
b
1.75mA
b
b
0.005mA
1.5V
1.5V
8mA
1.75mA
8mA
C
§
2
AC Electrical Characteristics* T
e
A
25§C, C
e
50 pF, unless otherwise noted
L
SymbolParameterConditionsMinTypMaxUnits
t
pd
t
pd
t
pd
t
S
t
W
t
W
t
pd0,tpd1
t
W
f
MAX
tr,t
f
C
IN
C
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
PD
AN-90.
Propagation Delay Time to QV
from Count Up or DownV
Propagation Delay Time to QV
Borrow from Count DownV
Propagation Delay Time toV
Carry from Count UpV
Time Prior to Load that DataV
Must be PresentV
Minimum Clear Pulse WidthV
Minimum Load Pulse WidthV
Propagation Delay Time to QV
from LoadV
Minimum Count Pulse WidthV
Maximum Count FrequencyV
Count Rise and Fall TimeV
Input Capacitance(Note 2)5pF
Power Dissipation Capacitance(Note 3)100pF
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note
e
5V250400ns
CC
e
10V100160ns
CC
e
5V120200ns
CC
e
10V5080ns
CC
e
5V120200ns
CC
e
10V5080ns
CC
e
5V100160ns
CC
e
10V3050ns
CC
e
5V300480ns
CC
e
V
10V120190ns
CC
e
5V100160ns
CC
e
V
10V4065ns
CC
e
5V300480ns
CC
e
10V120190ns
CC
e
5V120200ns
CC
e
V
10V3580ns
CC
e
5V2.54MHz
CC
e
V
10V610MHz
CC
e
5V15ms
CC
e
V
10V5ms
CC
Cascading Packages
Guaranteed Noise Margin
as a Function of V
TL/F/5901– 2
CC
TL/F/5901– 3
3
Timing Diagrams
MM54C192/MM74C192
Note 1: Clear ouptuts to zero.
Note 2: Load (preset) to binary thirteen.
Note 3: Count up to fourteen, fifteen, carry, zero, one and two.
Note 4: Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
MM54C193/MM74C193
Note 1: Clear ouptuts to zero.
Note 2: Load (preset) to BCD seven.
Note 3: Count up to eight, nine, carry, zero, one, and two.
Note 4: Count down to one, zero, borrow, nine, eight, and seven.
Note A: Clear overrides load, data, and count inputs.
Note B: When counting up, count down input must be high; when counting down, count-up input must be high.
TL/F/5901– 4
TL/F/5901– 5
4
Schematic Diagrams
MM54C192 Synchronous 4-Bit Up/Down Decade Counter
MM54C193 Synchronous 4-Bit Up/Down Binary Counter
TL/F/5901– 6
TL/F/5901– 7
5
Physical Dimensions inches (millimeters)
Order Number MM54C192J, MM74C192J, MM54C193J or MM74C193J
Ceramic Dual-In-Line Package (J)
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM54C192N, MM74C192N, MM54C193N or MM74C193N
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with instructions for use provided in the labeling, caneffectiveness.
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