National Semiconductor MM5483 Technical data
MM5483
Liquid Crystal Display Driver
MM5483 Liquid Crystal Display Driver
May 2002
General Description
The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode devices. It is available in a 40-pin molded package. The chip
can drive up to 31 segments of LCD and can be cascaded to
increase this number. This chip is capable of driving a 4
digit 7-segment display with minimal interface between the
display and the data source.
The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received.
1
Block and Connection Diagrams
Features
n Serial data input
n Serial data output
n Wide power supply operation
n TTL compatibility
⁄2-
n 31 segment outputs
n Alphanumeric and bar graph capability
n Cascade capability
Applications
n COPS™or microprocessor displays
n Industrial control indicator
n Digital clock, thermometer, counter, voltmeter
n Instrumentation readouts
n Remote displays
00614001
FIGURE 1.
COPS™is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS006140 www.national.com
Block and Connection Diagrams (Continued)
MM5483
Dual-In-Line Package
Top View
Order Number MM5483N
See NS Package Number N40A
Order Number MM5483V
See NS Package Number V44A
00614002
00614007
FIGURE 2.
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MM5483
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin V
Operating Temperature −40˚C to +85˚C
to VSS+10V
SS
Storage Temperature −65˚C to +150˚C
Power Dissipation 300 mW at +85˚C
350 mW at +25˚C
Junction Temperature +150˚C
Lead Temperature
(Soldering, 10 seconds) 300˚C
DC Electrical Characteristics
TAwithin operating range, VDD= 3.0V to 10V, VSS= 0V, unless otherwise specified
Parameter Conditions Min Typ Max Units
Power Supply 3.0 10 V
All Outputs Bits = Open, Data Out = Open,
BP_Out = Open, Clock In = 0V,
Data In = 0V, Data Load = 0V,
Average Supply Current, I
Input Voltage Levels
Logic “0”
Logic “1”
Logic “0”
Logic “1”
Output Current Levels
Segments and Data Out
Sink
Source
BP Out Sink
BP Out Source
DD
Osc In = 0V, BP_In = 32Hz
= 3.0V 1.5 2.5 µA
V
DD
V
= 5.0V 10 µA
DD
V
= 10.0V 40 µA
DD
Load, Clock, Data
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 5.0V
= 5.0V
= 3.0V
= 3.0V
= 3.0V, V
= 3.0V, V
= 3.0V, V
= 3.0V, V
OUT
OUT
OUT
OUT
= 0.3V
= 2.7V
= 0.3V
= 2.7V
2.4
2.0
20
20
320
320
0.9
0.4
V
V
V
V
µA
µA
µA
µA
AC Electrical Characteristics
VDD≥ 4.7V, VSS= 0V unless otherwise specified
Symbol Parameter Min Typ Max Units
f
C
t
CH
t
CL
t
DS
t
DH
t
LW
t
LTC
t
CDO
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: AC input waveform specification for test purpose: t
Note 3: Clock input rise and fall times must not excced 300 ms.
Note 4: Output offset voltage is
Functional Description
A block diagram for the MM5483 is shown in Figure 1 and a
package pinout is shown in Figure 2. Figure 3 shows a
possible 3-wire connection system with a typical signal format for Figure 3. Shown in Figure 4, the load input is an
asynchronous input and lets data through from the shift
register to the output buffers any time it is high. The load
input can be connected to V
Clock Frequency, VDD= 3V 500 kHz
Clock Period High (Notes 2, 3) 500 ns
Clock Period Low 500 ns
Data Set-Up before Clock 300 ns
Data Hold Time after Clock 100 ns
Minimum Load Pulse Width 500 ns
Load to Clock 400 ns
Clock to Data Valid 400 750 ns
≤ 20 ns, tf≤ 20 ns, f = 500 kHz, 50%±10% duty cycle.
r
±
50 mV with C
= 250 pF, CBP= 8750 pF.
SEGMENT
Figure 5. In the 2-wire control mode, 31 bits (or less depending on the number of segments used) of data are clocked
into the MM5483 in a short time frame (with less than 0.1
second there probably will be no noticeable flicker) with no
more clocks until new information is to be displayed. If data
was slowly clocked in, it can be seen to “walk” across the
display in the 2-wire mode. An AC timing diagram can be
for 2-wire control as shown in
DD
seen in Figure 6. It should be noted that data out is not a
TTL-compatible output.
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