National Semiconductor LM1262 Technical data

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LM1262
200 MHz I

2

C Compatible RGB Video Amplifier System

with OSD and DACs

General Description

The LM1262 pre-amp is an integrated CMOS CRT pre-amp.
The IC is I
rameters necessary to directlysetupand adjust the gain and
contrast in the CRT display. Brightness and bias can be
controlled through the DAC outputs, and is well matched to
the LM2479 and LM2480 integrated bias clamp IC.

The LM1262 pre-amp is designed to work in cooperation
with the LM246X high gain driver family.

Black level clamping of the signal is carried out directly on
the AC coupled input signal into the high impedance pream­plifier input, thus eliminating the need for additional black
level clamp capacitors.

The IC is packaged in an industry standard 24-lead DIP
molded plastic package.

Features

n I2C compatible interface

2

C compatible, and allows control of all the pa-

March 2002

n 4 external 8-bit DACs for bus controlled Bias and

Brightness

n Vertical blank from sandcastle or input at pin 13 OR’ed

with horz. blank signal, option selected by I

n Contrast and brightness updates synchronous with

vertical blank, enabled by I

n Video set to black level through I
n Suitable for use with discrete or integrated clamp, with

software configurable Brightness mixer

n Power Save (Green) Mode, 80% power reduction
n Matched to 11-lead LM246X driver

2

C

2

C

2

C

Applications

n High end 19” and 21” bus controlled monitors with OSD
n 1600 X 1200, 85 Hz or higher applications
n Low cost and high performance system with LM246X

driver

LM1262 200 MHz I

2

C Compatible RGB Video Amplifier System with OSD and DACs

Block and Connection Diagram

FIGURE 1. Order Number LM1262NA

See NS Package Number N24D

DS200404-1

© 2002 National Semiconductor Corporation DS200404 www.national.com

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required,

LM1262

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage, Pin 9 6.0V
Peak Video Output Source Current

(Any One Amp)
Pins 18, 19, or 20 28 mA

Voltage at Any

Input Pin (V

)

IN

Power Dissipation (P

V

CC

V

IN

)

D

>

+0.5

−0.5V

>

(Above 25˚C Derate based on

and TJ) 2.4W

θ

JA

Thermal Resistance to Ambient (θ

) 51˚C/W

JA

Active Video Signal Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

Symbol Parameter Conditions

I

S

Maximum Supply Current Test Setting 1, RL=∞(Note

8)

I

S-PS

Maximum Supply Current,
Power Save Mode

Test Setting 1, RL=∞,Bit1of
Reg. 9 = 1 (Note 8)

LE Linearity Error Test Setting 4, Triangular

signal input source (Note 9)

V

O Blk Typ

V

O Blk Step

Typical Video Black Level
Output

Test Setting 4, No AC Input
Signal

Video Black Level Step Size Test Setting 4, No AC Input

Signal

V

O White-Max

White Level Video Output

Test Setting 3, Video in = 0.7V

Voltage

V

Blank

t

r

Blanked Output Level Test Setting 4, AC Input Signal 0 0.05 0.2 V
Rise Time 10% to 90%, Test Setting 4,

AC Input Signal (Note 10)

OS

R

Overshoot (Rising Edge) Test Setting 4, AC Input Signal

(Note 10)

t

f

Fall Time 90% to 10%, Test Setting 4,

AC Input Signal (Note 10)

OS

F

Overshoot (Falling Edge) Test Setting 4, AC Input Signal

(Note 10)

f(−3 dB) Video Amplifier Bandwidth

Test Setting 4, V

(Note 13)

V

10kHz Video Amplifier 10 kHz

sep

Test Setting 8 (Note 14)

Isolation

V

10MHz Video Amplifier 10 MHz

sep

Test Setting 8 (Note 14)

Isolation

A

V Max

A

V 1/2

A

V Min

A

V Gain 1/2

A

V Gain Min

A

V Match

A

V Track

Maximum Voltage Gain Test Setting 8, AC Input Signal 3.90 4.15 4.40 V/V
Contrast@50% Level Test Setting 5, AC Input Signal −10 dB
Maximum Contrast Attenuation Test Setting 2, AC Input Signal −20 dB
Gain@50% Level Test Setting 6, AC Input Signal −5 dB
Maximum Gain Attenuation Test Setting 7, AC Input Signal −10 dB
Absolute Gain Match@A
Gain Change between

Amplifiers

V Max

Test Setting 3, AC Input Signal
Tracking when changing from

Test Setting 8 to Test Setting 5
(Note 11)

ABL=VCC,CL

Thermal Resistance to Case (θ
Junction Temperature (T

) 150˚C

J

) 32˚C/W

JC

ESD Susceptibility (Note 4) 3.5 kV
ESD Machine Model (Note 5) 350V
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 10 sec.) 265˚C

Operating Ratings (Note 2)

Temperature Range 0˚C to 70˚C
Supply Voltage (V

) 4.75V<V

CC

Video Inputs 0.0V

= 5 pF, Video Signal Output = 2V

Min

(Note 7)

Typ

(Note 6)

(Note 7)

170 230 mA

45 mA

5%

0.9 1.1 1.3 VDC

80 110 140 mV

4.0 4.3 V

1.9 ns

6%

2.0 ns

8%

=2V

O

P-P

200 MHz

−70 dB

−50 dB

±

0.5 dB

±

0.5 dB

P-P

Max

<

5.25V

CC

<

<

V

1.0V

IN

p-p

.

Units

www.national.com 2

Active Video Signal Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

ABL=VCC,CL

Symbol Parameter Conditions

V

ABL TH

ABL Control Upper Limit Test Setting 4, AC Input Signal

(Note 12)

V

ABL Range

∆A

ABL

ABL Active Range Control
Voltage

Test Setting 4, AC Input Signal
(Note 12)

ABL Control Range Test Setting 4, AC Input Signal

(Note 12)

I

ABL Active

I

ABL Max

V

Vert Bnk Off

ABL Input Bias Current during
ABL

ABL Input Current Clamp Sink
Capability

Vertical Blank Gate Low
Input Voltage at pin 13

Test Setting 4, AC Input
Signal, V

ABL

Test Setting 4, AC Input Signal
(Note 12)

Vertical Blank Comparators Off
Register B set to 0x02 (Note

18)

V

Vert Bnk On

Vertical Blank Gate High
Input Voltage at pin 13

Vertical Blank Comparators On
Register B set to 0x02 (Note

18)

I

Vert Bnk Low

I

Vert Bnk High

Vertical Blank Gate Low
Input Current at pin 13

Vertical Blank Gate High
Input Current at pin 13

V13= 0V, Register B set to
0x02 (Note 18)

V13=VCC, Register B set to
0x02 (Note 18)
(internal 50k resistor to ground)

V

Vert Bnk Off

V

Vert Bnk On

V

Clamp Min

Vertical Blank Gate Low

Input Voltage at pin 23

Vertical Blank Gate High

Input Voltage at pin 23

Horizontal Clamp Gate High

Vertical Blank Comparators Off

Register B set to 0x06

Vertical Blank Comparators On

Register B set to 0x06 (Note

Horizontal Clamp Comparators

Input Voltage

I

Clamp

Clamp Gate Input Current V23=0VtoVCC− 1V,

Register B set to 0x06

t

PW Clamp

t

Clamp-Video

Back Porch Clamp Pulse Width (Note 15) 200 ns
End of Clamp Pulse to Start of

Limit is guaranteed by design

Active Video

t

PW SandClamp

Sandcastle Clamp Pulse Width Horizontal Clamp Comparators

On Register B set to 0x06
(Note 16)

R

In-Video

V

Out V

Ref

Input Resistance Test Setting (4) 20 MΩ

Output Voltage 10 kΩ, 1% Resistor; Pin 10 to

Ref

GND

V

Spot

Spot Killer Voltage VCCAdjusted to Activate 3.4 4.0 4.25 V

= 2V (Note 12)

16)

On

= 5 pF, Video Signal Output = 2V

.

P-P

Min

(Note 7)

Typ

(Note 6)

Max

(Note 7)

5V

2.7 V

-6 −8 dB

010µA

1mA

1.0 V

2.6 V

-4.0 µA

100 µA

0.7 V

1.2 3.2 V

3.8 V

−5 0.1 10 µA

200 ns

0.20 1.20 µsec

1.25 1.40 1.55 V

LM1262

Units

OSD Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V
ting 8.

Symbol Parameter Conditions

V

OSD-L

OSD Input Low Input

OSD Inputs are Selected

Operating Range

V

OSD-H

OSD Input High Input

OSD Inputs are Selected

Operating Range

I

OSD

OSD Input Current V

OSD

ABL=VCC,CL

=0VtoVCC− 1V −5 0.1 10 µA

= 5 pF, Video Signal Output = 2V

Min

(Note 7)

Typ

(Note 6)

(Note 7)

2.5 V

, Test Set-

P-P

Max

Units

1.2 V

www.national.com3

OSD Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

LM1262

ting 8.

Symbol Parameter Conditions

V

OSD-Sel-L

V

OSD-Sel-H

I

OSD-Sel

∆V

O-OSD(Blk)

V

O-OSD(Blk)

V

OSD-out

∆V

OSD-out

V

OSD-out

(Match)

V

OSD-out

(Track)

∆t

OSD/OSD S

V

10 kHz Video Feedthrough into OSD OSD Inputs = 0V −70 dB

feed

V

10 MHz Video Feedthrough into OSD OSD Inputs = 0V −60 dB

feed

OSD Select Low Input
Operating Range

OSD Select High Input
Operating Range

OSD Select Input Current V
OSD ∆Black Level Output

Voltage, Difference from Video
Output

Range of OSD Black Level
Output Voltage between the 3
Channels

OSD Output Voltage, Percent
of Maximum Video Out

OSD Output V

Attenuation Register 08 = 08 52 57 62 %

P-P

Output Match between
Channels

Output Variation between
Channels

Output Skew Time between
OSD and OSD Select

Video Inputs are Selected

OSD Inputs are Selected

OSD-Sel

Register 08 = 18, Minimum
Video Black Level

Register 08 = 18, Minimum
Video Black Level −100 0 +100 mV

Register 08 = 18, Minimum
Video Black Level

Register 08 = 18

Register 08 Changed from 18
to 08

Measured from 50% Point on
all Waveforms

ABL=VCC,CL

= 5 pF, Video Signal Output = 2V

Min

(Note 7)

Typ

(Note 6)

, Test Set-

P-P

Max

(Note 7)

Units

1.2 V

3.5 V

=0VtoVCC− 1V −5 0.1 10 µA

±

45

±

150 mV

85 95 105 %

±

5.0 %

±

3.0

±

2.0 ns

±

5.0 %

External DAC Signals Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

ABL=VCC,CL

ing apply for all four external DACs.

Symbol Parameter Conditions

V

Min DAC

V

Max DAC

Mode 00
V

Max DAC

Mode 11
∆V

Max DAC

(Temp)

∆V

Max DAC

(VCC)

Min DAC Output Voltage Value = 00h 0.5 0.75 V
Max DAC Output Voltage Value = FFh, DCF[1:0] = 00h

(no load)

Max Output Voltage of DACs
1–3 in DCF Mode 11

Variation of any DAC output

Value = FFh, DCF[1:0] = 11h,
DAC4 Value = 00h

<T<

0˚C

70˚C ambient

voltage with temperature
Variation of any DAC output

voltage with V

CC

4.75V<V

<

5.25V

CC

Linearity Linearity of DAC Over its

Range

Monotonicity Monotonicity of the DAC Excluding dead zones at limits

of DAC

= 5 pF, Video Signal Output = 2V

Min

(Note 7)

Typ

(Note 6)

(Note 7)

3.6 4.2 V

2.05 2.40 2.75 V

±

0.5 mV/deg

±

50 mV/V

5%

±

0.5 LSB

. The follow-

P-P

Max

External Interface Signals Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

ABL=VCC,CL

Symbol Parameter Conditions

V

(I2C) I2C Low Input Voltage SDA or SCL Inputs 1.5 V

l

V

(I2C) I2C High Input Voltage SDA or SCL Inputs 3.0 V

h

= 5 pF, Video Output = 2V

Min

(Note 7)

Typ

(Note 6)

P-P

.

Max

(Note 7)

Units

Units

www.national.com 4

External Interface Signals Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5V, VIN= 0.7V, V

ABL=VCC,CL

Symbol Parameter Conditions

t

H-Blank on

t

H-Blank off

I

In Threshold

H-Blank Time Delay from Zero
Crossing Point of H Flyback

H-Blank Time Delay from Zero
Crossing Point of H Flyback

IInH-Blank Detection

Rising Edge of the Flyback
Signal

Falling Edge of the Flyback
Signal

Threshold

I

In-Operating

Minimum—Insure Normal
Operation
Maximum—Should Not

Lowest Operating Horizontal
Frequency in Given Application
(Note 17)

Exceed in Normal Operation

I

In Flyback

Peak Current during Flyback
Period, Recommended Design
Range

Operating Range for all
Horizontal Scan Frequencies,
Maximum Current Should Not
Exceed 2 mA (Note 17)

Note 1: Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur.
Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specified voltage, then discharged directly into the

IC with no external series resistor (resistance of discharge path must be under 50Ω).

Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: The supply current specified is the quiescent current for V

the supply current is used by the pre-amp.
Note 9: Linearity Error is the variation in step height of a 16 step staircase input signal waveform with 0.7 V

with each step approximately 100 ns in width.

±

0.2 dB.

<

1 ns. Scope and generator response used for testing: tr= 1.1 ns, tf= 0.9 ns. Using the RSS technique the scope and

r,tf

∆A

= A(V

ABL

max reference level) to the −3 dB corner frequency (f

V

= 10 MHz for V

IN

Note 10: Input from signal generator: t
generator response have been removed from the output rise and fall times.

Note 11: ∆A
gain change between any two amplifiers with the contrast set to A
gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A

10.0 dB with a tracking change of
Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to –6 dB

Beyond –6 dB the gain characteristics, linearity, pulse response, and/or behavior may depart from normal values.

Note 13: Adjust input frequency from 10 MHz (A
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier

inputs to simulate generator loading. Repeat test at f
Note 15: A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer

clamp pulse may be required.
Note 16: The internal circuit detects the vertical blank only when this signal is present in the sandcastle input. There is typically an 800 nsec delay in detecting the

vertical blank signal. If only the horizontal clamp is present the vertical blank will not be activated. Rise and fall times of the sandcastle input signal should be 10 nsec
or faster.

Note 17: Limits met by matching the external resistor going to pin 24 to the H Flyback voltage.
Note 18: A 4.7 kΩ resistor must be in series with pin 13 when this pin is the input for vertical blanking. When the LM1262 is first turned on the default condition for

pin 13 is for the DAC4 output. Under this condition pin 13 will be damaged by the vertical blanking input if a series resistor is not used.

track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in

V

with RL=∞. Load resistors are not required and are not used in the test circuit, therefore all

CC

and measured relative to the AVmax condition. For example, at AVmax the three amplifiers’

V 1/2

ABL=VABL Max Gain

sep 10 MHz

) - A(V

.

= 5 pF, Video Output = 2V

Min

(Note 7)

−30 −300 µA

0.5 1.5 2.0 mA

level at the input, subdivided into 16 equal steps,

P-P

ABL=VABL Min Gain

−3 dB

)

).

.

P-P

Typ

(Note 6)

Max

(Note 7)

50 ns

50 ns

−20 µA

. This yields a typical gain change of

V 1/2

LM1262

Units

www.national.com5

Typical Performance Characteristics V

LM1262

Gain Attenuation

=5V,TA= 25˚C unless otherwise specified.

CC

Contrast Attenuation

ABL Attenuation

Contrast vs Frequency

DS200404-2

DS200404-4

DS200404-3

Rise and Fall

DS200404-5

Gain vs Frequency

DS200404-6

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DS200404-7