National Semiconductor LM12454, LM12458, LM12H458 Technical data
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with
Self-Calibration
February 2006
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with Self-Calibration
General Description
The LM12458, and LM12H458 are highly integrated Data
Acquisition Systems. Operating on just 5V, they combine a
fully-differential self-calibrating (correcting linearity and zero
errors) 13-bit (12-bit + sign) analog-to-digital converter
(ADC) and sample-and-hold (S/H) with extensive analog
functions and digital functionality. Up to 32 consecutive conversions, using two’s complement format, can be stored in
an internal 32-word (16-bit wide) FIFO data buffer. An internal 8-word RAM can store the conversion sequence for up to
eight acquisitions through the LM12(H)458’s eight-input multiplexer. The obsolete LM12454 has a four-channel multiplexer, a differential multiplexer output, and a differential S/H
input. The LM12(H)458 can also operate with 8-bit + sign
resolution and in a supervisory “watchdog” mode that compares an input signal against two programmable limits.
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the
internal 2.5V bandgap reference.
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit data bus. The LM12(H)458 includes a direct
memory access (DMA) interface for high-speed conversion
data transfer.
Additional applications information can be found in applications notes AN-906, AN-947 and AN-949.
Key Specifications
(f
= 5 MHz; 8 MHz, H)
CLK
j
Resolution 12-bit + sign or 8-bit + sign
j
13-bit conversion time 8.8 µs, 5.5 µs (H) (max)
j
9-bit conversion time 4.2 µs, 2.6 µs (H) (max)
j
13-bit Through-put rate 88k samples/s (min),
140k samples/s (H) (min)
j
Comparison time
(“watchdog” mode)
j
ILE
j
VINrange GND to V
j
Power Consumption 30 mW, 34 mW (H) (max)
j
Stand-by mode 50 µW (typ)
j
Single supply 3V to 5.5V
2.2 µs (max),
1.4 µs (H) (max)
±
1 LSB (max)
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
n Single-ended or differential inputs
n Built-in Sample-and-Hold and 2.5V bandgap reference
n Instruction RAM and event sequencer
n 8-channel multiplexer
n 32-word conversion FIFO
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide data bus microprocessor or DSP
interface
+
A
Applications
n Data Logging
n Instrumentation
n Process Control
n Energy Management
n Inertial Guidance
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
®
AT
is a registered trademark of International Business Machines Corporation.
© 2006 National Semiconductor Corporation DS011264 www.national.com
Ordering Information
Guaranteed Clock Freq
(min)
8 MHz
5 MHz
LM12454/LM12458/LM12H458
* These products are obsolete and shown for reference only.
Connection Diagrams
Order Part Number NS Package
LM12H458CIV
LM12H458CIVX
LM12H458CIVF
LM12454CIV *
LM12458CIV
LM12458CIVX
LM12458CIVF *
V44A (PLCC) (Tape and Reel)
V44A (PLCC) (Tape and Reel)
V44A (PLCC)
VGZ44A (PQFP)
V44A (PLCC)
V44A (PLCC)
VGZ44A (PQFP)
* Pin names in ( ) apply to the obsolete LM12454 and LM12H454.
Order Number LM12454CIV,
LM12458CIV or LM12H458CIV
See NS Package Number V44A
01126402
Order Number LM12458CIVF or LM12H458CIVF
01126434
NS Package Number VGZ44A
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Functional Diagrams
LM12454/LM12458/LM12H458
LM12454
The LM12(H)454 is obsolete
LM12(H)458
01126401
01126421
www.national.com3
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+ and VD+) 6.0V
A
Voltage at Input and Output Pins,
except analog inputs −0.3V to (V
Voltage at Analog Inputs − 5V to (V
|V
+−VD+| 300 mV
LM12454/LM12458/LM12H458
A
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation, PQFP
= 25˚C) (Note 4) 875 mW
(T
A
Storage Temperature −65˚C to +150˚C
Lead Temperature
PQFP, Infrared, 15 sec. +300˚C
PLCC, Solder, 10 sec. +250˚C
ESD Susceptibility (Note 5) 1.5 kV
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Package Thermal Resistances
Package θ
44-Lead PQFP 47˚C / W
44-Lead PLCC 50˚C / W
JA
+
+ 0.3V)
+
±
±
20 mA
+ 5V)
5mA
Operating Ratings (Notes 1, 2)
Temperature Range
(T
min
≤ TA≤ T
) −40˚C ≤ TA≤ 85˚C
max
Supply Voltage
+, VD+ 3.0V to 5.5V
V
A
|V
+−VD+| ≤100 mV
A
V
Input Range GND ≤ V
IN+
V
Input Range GND ≤ V
IN−
V
Input Voltage 1V ≤ V
REF+
V
Input Voltage 0V ≤ V
REF−
V
REF+−VREF−
V
Common Mode
REF
Range (Note 16) 0.1 V
+
A
REF−
≤ V
1V ≤ V
REFCM
≤ V
IN+
IN−
REF+
REF+
REF
≤ 0.6 V
≤ VA+
≤ VA+
≤ VA+
−1V
≤ VA+
TJ(MAX) 150˚C
Reliability Information Transistor Count
Device Type Nmber
P-Chan MOS Transistor 12,232
N-Chan MOS Transistor 15,457
Parasitic Vertical Bipolar Junction Transistor 4
Parasitic Lateral Bipolar Junction Transistor 2
TOTAL Transistors 27,695
+
A
Converter Characteristics (Notes 6, 7, 8, 9)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, V
12-bit + sign conversion mode, f
V
REF+
and V
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
otherwise specified. Boldface limits apply for T
= 8.0 MHz (LM12H458) or f
CLK
A=TJ=TMIN
Symbol Parameter Conditions
ILE Integral Linearity Error (Notes 12, 17) After Auto-Cal
TUE Total Unadjusted Error(Note 12) After Auto-Cal
Resolution with No Missing Codes
(Note 12)
After Auto-Cal 13 Bits (max)
DNL Differential Non-Linearity After Auto-Cal
Zero Error (Notes 13, 17)
After Auto-Cal
LM12H458
Positive Full-Scale Error (Notes 12, 17) After Auto-Cal
Negative Full-Scale Error (Notes 12,
17)
After Auto-Cal
DC Common Mode Error (Note 14)
ILE
TUE
8-Bit + Sign and “Watchdog” Mode
Integral Linearity Error (Note 12)
8-Bit + Sign and “Watchdog” Mode
Total Unadjusted Error
After Auto-Zero
8-Bit + Sign and “Watchdog” Mode
Resolution
with No Missing Codes
= 5.0 MHz (LM12454/8), RS=25Ω, source impedance for
CLK
to T
; all other limits TA=TJ= 25˚C.
MAX
Typical
(Note 10)
±
1/2
±
±
1/2
±
1/2
±
1/2
±
±
1/2
= 5V, V
REF+
Limits
(Note 11)
±
1 LSB (max)
REF−
= 0V,
Units
1 LSB
3
±
⁄
4
LSB (max)
±
1
±
1.5 LSB (max)
±
2 LSB (max)
±
2 LSB (max)
2
±
3.5 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
9 Bits (max)
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Converter Characteristics (Notes 6, 7, 8, 9) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, V
12-bit + sign conversion mode, f
V
REF+
and V
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
otherwise specified. Boldface limits apply for T
= 8.0 MHz (LM12H458) or f
CLK
A=TJ=TMIN
Symbol Parameter Conditions
DNL
8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
8-Bit + Sign and “Watchdog” Mode
Zero Error
After Auto-Zero
8-Bit + Sign and “Watchdog” Full-Scale
Error
8-Bit + Sign and “Watchdog” Mode
DC Common Mode Error
Multiplexer Channel-to-Channel
Matching
V
IN+
V
IN−
V
IN+−VIN−
Non-Inverting Input Range
Inverting Input Range
Differential Input Voltage Range
Common Mode Input Voltage Range
+=VD+=5V±10%
A
REF+
PSS
C
REF
C
IN
Power Supply
Sensitivity (Note
15)
V
REF+/VREF−
Zero Error V
Full-Scale Error V
Linearity Error
Input Capacitance 85 pF
Selected Multiplexer Channel Input
Capacitance
= 5.0 MHz (LM12454/8), RS=25Ω, source impedance for
CLK
to T
; all other limits TA=TJ= 25˚C.
MAX
Typical
(Note 10)
±
1/8 LSB
±
0.05 LSB
±
0.2
= 4.5V, V
REF−
= GND
±
0.4
±
0.2 LSB
75 pF
= 5V, V
REF+
Limits
(Note 11)
±
3/4 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
GND
+
V
A
GND
+
V
A
+
−V
A
VA+
GND
+
V
A
±
1.75 LSB (max)
±
2 LSB (max)
REF−
LM12454/LM12458/LM12H458
= 0V,
Units
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
Converter AC Characteristics (Notes 6, 7, 8, 9)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, V
12-bit + sign conversion mode, f
V
REF+
and V
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
otherwise specified. Boldface limits apply for T
= 8.0 MHz (LM12H458) or f
CLK
A=TJ=TMIN
Symbol Parameter Conditions
Clock Duty Cycle 50 40
13-Bit Resolution, Sequencer
t
C
Conversion Time
State S5 (Figure 15)
9-Bit Resolution, Sequencer State
S5 (Figure 15)
Sequencer State S7 (Figure 15)
t
A
Acquisition Time
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
t
t
Z
CAL
Auto-Zero Time Sequencer State S2 (Figure 15)76(t
Full Calibration Time Sequencer State S2 (Figure 15) 4944 (t
Throughput Rate (Note 18)
LM12H458 142 140 kHz (min)
= 5.0 MHz (LM12454/8), RS=25Ω, source impedance for
CLK
to T
; all other limits TA=TJ= 25˚C.
MAX
Typical
(Note 10)
44 (t
CLK
21 (t
CLK
9(t
CLK
2(t
CLK
CLK
CLK
Limits (Note 11) Units
) 44 (t
) 21 (t
) 9(t
) 2(t
) 76 (t
) 4944 (t
89 88 kHz (min)
= 5V, V
REF+
REF−
60
)+50ns (max)
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
= 0V,
%
% (min)
% (max)
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Converter AC Characteristics (Notes 6, 7, 8, 9) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, V
12-bit + sign conversion mode, f
V
REF+
and V
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
otherwise specified. Boldface limits apply for T
= 8.0 MHz (LM12H458) or f
CLK
A=TJ=TMIN
Symbol Parameter Conditions
t
WD
LM12454/LM12458/LM12H458
DSNR
SESNR
DSINAD
SESINAD
DTHD
SETHD
DENOB
SEENOB
DSFDR
“Watchdog” Mode
Comparison Time
Differential Signal-to-Noise
Ratio
Single-Ended Signal-to-Noise
Ratio
Differential Signal-to-Noise +
Distortion Ratio
Single-Ended Signal-to-Noise
+ Distortion Ratio
Differential Total Harmonic
Distortion
Single-Ended Total Harmonic
Distortion
Differential Effective Number
of Bits
Single-Ended Effective
Number of Bits
Differential Spurious Free
Dynamic Range
Multiplexer
Channel-to-Channel
Crosstalk
t
PU
t
WU
Power-Up Time 10 ms
Wake-Up Time 10 ms
Sequencer States S6, S4, and S5
(Figure 15)
=±5V
V
IN
f
= 1 kHz 77.5 dB
IN
f
= 20 kHz 75.2 dB
IN
f
= 40 kHz 74.7 dB
IN
=5V
V
IN
p-p
fIN= 1 kHz 69.8 dB
f
= 20 kHz 69.2 dB
IN
f
= 40 kHz 66.6 dB
IN
=±5V
V
IN
f
= 1 kHz 76.9 dB
IN
f
= 20 kHz 73.9 dB
IN
f
= 40 kHz 70.7 dB
IN
=5V
V
IN
p-p
fIN= 1 kHz 69.4 dB
f
= 20 kHz 68.3 dB
IN
f
= 40 kHz 65.7 dB
IN
=±5V
V
IN
f
= 1 kHz −85.8 dB
IN
f
= 20 kHz −79.9 dB
IN
f
= 40 kHz −72.9 dB
IN
=5V
V
IN
p-p
fIN= 1 kHz −80.3 dB
f
= 20 kHz −75.6 dB
IN
f
= 40 kHz −72.8 dB
IN
=±5V
V
IN
f
= 1 kHz 12.6 Bits
IN
f
= 20 kHz 12.2 Bits
IN
f
= 40 kHz 12.1 Bits
IN
=5V
V
IN
p-p
fIN= 1 kHz 11.3 Bits
f
= 20 kHz 11.2 Bits
IN
f
= 40 kHz 10.8 Bits
IN
=±5V
V
IN
f
= 1 kHz 87.2 dB
IN
f
= 20 kHz 78.9 dB
IN
f
= 40 kHz 72.8 dB
IN
V
=5V
IN
P-P,fIN
LM12454 MUXOUT Only
=5V
V
IN
P-P,fIN
LM12(H)458 MUX plus Converter
= 40 kHz,
= 40 kHz,
= 5.0 MHz (LM12454/8), RS=25Ω, source impedance for
CLK
to T
; all other limits TA=TJ= 25˚C.
MAX
Typical
(Note 10)
) 11 (t
11 (t
CLK
−76 dB
−78 dB
REF+
= 5V, V
REF−
= 0V,
Limits (Note 11) Units
)+50ns (max)
CLK
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DC Characteristics (Notes 6, 7, 8)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, V
= 8.0 MHz (LM12H454/8) or f
f
CLK
face limits apply for T
A=TJ=TMIN
Symbol Parameter Conditions
+V
I
D
+V
I
A
I
ST
+ Supply Current
D
+ Supply Current
A
Stand-By Supply Current (ID+)+(IA+)
[Power-Down Mode Selected]
Multiplexer ON-Channel Leakage Current
Multiplexer OFF-Channel Leakage Current
R
ON
Multiplexer ON-Resistance
Multiplexer Channel-to-Channel
matching
R
ON
= 5.0 MHz (LM12458), and minimum acquisition time unless otherwise specified. Bold-
CLK
to T
; all other limits TA=TJ= 25˚C.
MAX
Typical
(Note 10)
CS = “1”
LM12454/8
LM12H458
0.55
0.55
CS = “1”
LM12454/8
LM12H458
Clock Stopped
8 MHz Clock
3.1
3.1
10
40
VA+ = 5.5V
ON-Channel = 5.5V,
0.1 0.3 µA (max)
OFF-Channel = 0V
ON-Channel = 0V
OFF-Channel = 5.5V
+ = 5.5V
V
A
ON-Channel = 5.5V
0.1 0.3 µA (max)
0.1 0.3 µA (max)
OFF-Channel = 0V
ON-Channel = 0V
OFF-Channel = 5.5V
0.1
LM12454
= 5V 800 1500 Ω(max)
V
IN
V
= 2.5V 850 1500 Ω(max)
IN
V
= 0V 760 1500 Ω(max)
IN
LM12454
V
V
V
IN
IN
IN
=5V
= 2.5V
=0V
±
±
±
1.0%
1.0%
1.0%
= 5V, V
REF+
Limits
(Note 11)
1.0
1.2
5.0
5.5
0.3
±
3.0% (max)
±
3.0% (max)
±
3.0% (max)
REF−
mA (max)
mA (max)
mA (max)
mA (max)
µA (max)
µA (max)
µA (max)
LM12454/LM12458/LM12H458
= 0V,
Units
Internal Reference Characteristics (Notes 6, 7)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V unless otherwise specified.
to T
Boldface limits apply for T
A=TJ=TMIN
Symbol Parameter Conditions
V
REFOUT
∆V
∆
REF
∆V
I
SC
∆V
t
SU
REF
REF
REF
Internal Reference Output Voltage 2.5 2.5±4% V (max)
/∆T Internal Reference Temperature Coefficient 40 ppm/˚C
/∆ILInternal Reference Load Regulation
Line Regulation 4.5V ≤ VA+ ≤ 5.5V 3 20 mV (max)
Internal Reference Short Circuit Current V
/∆t Long Term Stability 200 ppm/kHr
Internal Reference Start-Up Time
; all other limits TA=TJ= 25˚C.
MAX
<
Sourcing (0
Sinking (−1 ≤ I
REFOUT
V
+=VD+=0V
A
5V, C
L
IL≤ +4 mA) 0.2 %/mA (max)
<
IL
=0V 13 25 mA (max)
→
= 100 µF
Typical
(Note 10)
Limits
(Note 11)
Units
0 mA) 1.2 %/mA (max)
10 ms
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Digital Characteristics (Notes 6, 7)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, unless otherwise specified.
Boldface limits apply for T
A=TJ=TMIN
to T
Symbol Parameter Conditions
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
C
IN
LM12454/LM12458/LM12H458
V
OUT(1)
V
OUT(0)
I
OUT
Logical “1” Input Voltage VA+=VD+ = 5.5V 2.0 V (min)
Logical “0” Input Voltage VA+=VD+ = 4.5V 0.8 V (max)
Logical “1” Input Current VIN= 5V 0.005 1.0 µA (max)
Logical “0” Input Current VIN= 0V −0.005 −1.0 µA (max)
D0–D15 Input Capacitance 6 pF
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE®Output Leakage Current
; all other limits TA=TJ= 25˚C.
MAX
+=VD+ = 4.5V
V
A
I
= −360 µA 2.4 V (min)
OUT
I
= −10 µA 4.25 V (min)
OUT
V
+=VD+ = 4.5V
A
= 1.6 mA
I
OUT
= 0V −0.01 −3.0 µA (max)
V
OUT
V
= 5V 0.01 3.0 µA (max)
OUT
Typical
(Note 10)
Limits
(Note 11)
0.4 V (max)
Digital Timing Characteristics (Notes 6, 7, 8)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+ = 5V, tr=tf= 3 ns, and CL= 100
pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
limits TA=TJ= 25˚C.
Symbol (See Figures
8, 9, 10)
1, 3
2, 4
Parameter Conditions
CS or Address Valid to ALE Low Set-Up
Time
CS or Address Valid to ALE Low Hold
Time
Typical
(Note 10)
5 ALE Pulse Width 45 ns (min)
6 RD High to Next ALE High
7 ALE Low to RD Low
8 RD Pulse Width
9 RD High to Next RD or WR Low
10 ALE Low to WR Low
11 WR Pulse Width
12 WR High to Next ALE High
13 WR High to Next RD or WR Low
14 Data Valid to WR High Set-Up Time
15 Data Valid to WR High Hold Time
16 RD Low to Data Bus Out of TRI-STATE
17 RD High to TRI-STATE
18 RD Low to Data Valid (Access Time)
RL=1kΩ 30
40
30
20 Address Valid or CS Low to RD Low
21 Address Valid or CS Low to WR Low
19 Address Invalid from RD or WR High
22 INT High from RD Low
23 DMARQ Low from RD Low
30
30
A=TJ=TMIN
to T
Limits
(Note 11)
40 ns (min)
20 ns (min)
35 ns (min)
20 ns (min)
100 ns (min)
100 ns (min)
20 ns (min)
60 ns (min)
75 ns (min)
140 ns (min)
40 ns (min)
30 ns (min)
10 ns (min)
70 ns (max)
10 ns (min)
110 ns (max)
10 ns (min)
80 ns (max)
20 ns (min)
20 ns (min)
10 ns (min)
10 ns (min)
60 ns (max)
10 ns (min)
60 ns (max)
MAX
Units
; all other
Units
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Digital Timing Characteristics (Notes 6, 7, 8) (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply
) at any pin exceeds the power supply rails (V
IN
IN
<
GND or V
voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
to ambient thermal resistance), and T
(ambient temperature).
A
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V
will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an
example, if V
+ is 4.5 VDC, full-scale input voltage must be ≤4.6 VDCto ensure accurate conversions.
A
Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+pin to assure
conversion/comparison accuracy.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typical figures are at T
REF(VREF+−VREF−
= 25˚C and represent most likely parametric norm.
A
= 5 MHz for the LM12454/8 and f
CLK
) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figure 6 Figure 7).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 8).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting
output value when the inputs are driven with a 2.5V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V
Note 16: V
(Reference Voltage Common Mode Range) is defined as (V
REFCM
REF++VREF−
Note 17: The LM12(H)454/8’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result
in a repeatability uncertainty of
±
0.10 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per
conversion. The Throughput Rate is f
(MHz)/N, where N is the number of clock cycles/conversion.
CLK
>
(VA+orVD+)), the current at that pin should be limited to 5 mA.
IN
(maximum junction temperature), θJA(package junction
Jmax
01126403
= 8 MHz for the LM12H458.
CLK
+ and VD+ at the specified extremes.
A
)/2.
+ or 5V below GND
A
LM12454/LM12458/LM12H458
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LM12454/LM12458/LM12H458
V
REF=VREF+−VREF−
VIN=V
IN+−VIN−
GND ≤ V
GND ≤ V
IN+≤VA
IN−≤VA
+
+
01126422
FIGURE 1. The General Case of Output Digital Code vs. the Operating Input Voltage Range
V
REF+−VREF−
V
IN=VIN+−VIN−
GND ≤ V
GND ≤ V
IN+≤VA
IN−≤VA
= 4.096V
+
+
FIGURE 2. Specific Case of Output Digital Code vs. the Operating Input Voltage Range for V
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01126423
REF
= 4.096V
LM12454/LM12458/LM12H458
V
REF=VREF+−VREF−
FIGURE 3. The General Case of the V
Operating Range
REF
01126424
V
REF=VREF+−VREF−
VA+=5V
FIGURE 4. The Specific Case of the V
01126425
Operating Range for VA+=5V
REF
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