National Semiconductor DS90LV028A Technical data

DS90LV028A
3V LVDS Dual CMOS Differential Line Receiver

DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver

January 2003

General Description

The DS90LV028A is a dual CMOS differential line receiver
designed for applications requiring ultra low power dissipa­tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.

The DS90LV028A accepts low voltage (350 mV typical) dif­ferential input signals and translates them to 3V CMOS
output levels. The receiver also supports open, shorted and
terminated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV028A has a
flow-through design for easy PCB layout.

The DS90LV028A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.

Connection Diagrams

SOIC

Features

n>400 Mbps (200 MHz) switching rates
n 50 ps differential skew (typical)
n 0.1 ns channel-to-channel skew (typical)
n 2.5 ns maximum propagation delay
n 3.3V power supply design
n Flow-through pinout
n Power down high impedance on LVDS inputs
n Low Power design (18mW
n Interoperable with existing 5V LVDS networks
n Accepts small swing (350 mV typical) differential signal

levels

n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range

(−40˚C to +85˚C)

n Available in SOIC and space saving LLP package

@

3.3V static)

Functional Diagram

Order Number DS90LV028ATM

10007701

See NS Package Number M08A

LLP (Top View)

10007725

Order Number DS90LV028ATLD

See NS Package Number LDC08A

Truth Table

[R

IN

VID≥ 0.1V H

V

Full Fail-safe

OPEN/SHORT

or Terminated

INPUTS OUTPUT

+]−[RIN−] R

≤ −0.1V L

ID

OUT

H

10007702

© 2003 National Semiconductor Corporation DS100077 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

DS90LV028A

Supply Voltage (V

Input Voltage (R

Output Voltage (R

Maximum Package Power Dissipation

M Package 1025 mW

Derate M Package 8.2 mW/˚C above +25˚C

LD Package 3.3W

Derate LD Package 25.6 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C

) −0.3V to +4V

CC

+, RIN−) −0.3V to +3.9V

IN

) −0.3V to VCC+ 0.3V

OUT

@

+25˚C

Lead Temperature Range Soldering

(4 sec.) +260˚C

Maximum Junction Temperature +150˚C

ESD Rating (Note 4)

(HBM 1.5 kΩ, 100 pF) ≥ 7kV

(EIAJ 0Ω, 200 pF) ≥ 500 V

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (V

) +3.0 +3.3 +3.6 V

CC

Receiver Input Voltage GND 3.0 V

Operating Free Air

Temperature (T

) −40 25 +85 ˚C

A

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

V

TH

V

TL

I

IN

V

OH

V

OL

I

OS

V

CL

I

CC

Differential Input High Threshold VCM= +1.2V, 0V, 3V (Note 12) RIN+, +100 mV

Differential Input Low Threshold RIN− −100 mV

Input Current VIN= +2.8V VCC= 3.6V or 0V −10

V

= 0V −10

IN

V

= +3.6V VCC= 0V -20 +20 µA

IN

Output High Voltage IOH= −0.4 mA, VID= +200 mV R

I

= −0.4 mA, Inputs terminated 2.7 3.1 V

OH

I

= −0.4 mA, Inputs shorted 2.7 3.1 V

OH

2.7 3.1 V

OUT

±

1 +10 µA

±

1 +10 µA

Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V

Output Short Circuit Current V

= 0V (Note 5) −15 −50 −100 mA

OUT

Input Clamp Voltage ICL= −18 mA −1.5 −0.8 V

No Load Supply Current Inputs Open V

CC

5.4 9 mA

Switching Characteristics

VCC= +3.3V±10%, TA= −40˚C to +85˚C (Notes 6, 7)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD1

t

SKD2

t

SKD3

t

SKD4

t

TLH

t

THL

f

MAX

www.national.com 2

Differential Propagation Delay High to Low CL= 15 pF 1.0 1.6 2.5 ns

Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 2.5 ns

Differential Pulse Skew |t

PHLD−tPLHD

| (Note 8) (Figure 1 and Figure 2) 0 50 400 ps

Differential Channel-to-Channel Skew-same device (Note 9) 0 0.1 0.5 ns

Differential Part to Part Skew (Note 10) 0 1.0 ns

Differential Part to Part Skew (Note 11) 0 1.5 ns

Rise Time 325 800 ps

Fall Time 225 800 ps

Maximum Operating Frequency (Note 13) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified (such as V

Note 3: All typicals are given for: V

Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7kV

EIAJ (0Ω, 200 pF) ≥ 500V

Note 5: Output short circuit current (I
exceed maximum junction temperature specification.

Note 6: C

L

).

ID

includes probe and jig capacitance.

= +3.3V and TA= +25˚C.

CC

) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

OS

Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, ZO=50Ω,trand tf(0% to 100%) ≤ 3 ns for RIN.

Note 8: t

Note 9: t

integrated circuit.

Note 10: t
and within 5˚C of each other within the operating temperature range.

Note 11: t
recommended operating temperature and voltage ranges, and across process distribution. t

Note 12: V
than 100 mV when V

Note 13: f
V

OL

is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

SKD1

is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the

SKD2

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V

SKD3

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the

SKD4

is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VIDis not allowed to be greater

CC

MAX

(max 0.4V), VOH(min 2.7V), load = 15 pF (stray plus probes).

=0Vor3V.

CM

generator input conditions: tr=t

<

1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,

f

is defined as |Max − Min| differential propagation delay.

SKD4

Parameter Measurement Information

10007703

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

DS90LV028A

CC

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

Typical Application

Balanced System

FIGURE 3. Point-to-Point Application

Applications Information

General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-002), AN-808,
AN-977, AN-971, AN-916, AN-805, AN-903.

LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling

10007704

10007705

environment for the fast edge rates of the drivers. The re­ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termina­tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the driver output (current
mode) into a voltage that is detected by the receiver. Other

www.national.com3