National Semiconductor DS90CR287, DS90CR288A Technical data
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DS90CR287/DS90CR288A
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-85 MHZ
DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ
October 1999
General Description
The DS90CR287 transmitter converts 28 bits of CMOS/TTL
data intofour LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR288A receiver converts the four
LVDS data streams back into 28 bits of CMOS/TTL data. At
a transmit clock frequency of 85 MHZ, 28 bits of TTLdataare
transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHZ clock, the data throughput is 2.38 Gbit/s
(297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
DS90CR287
Features
n 20 to 85 MHZ shift clock support
n 50%duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on TxINPUTs
n Low power consumption
±
n
1V common mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
DS90CR288A
DS101087-1
Order Number DS90CR287MTD
See NS Package Number MTD56
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101087 www.national.com
Order Number DS90CR288AMTD
See NS Package Number MTD56
DS101087-27
Pin Diagrams
DS90CR287
DS90CR287/DS90CR288A
Typical Application
DS101087-21
DS90CR288A
DS101087-22
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DS101087-23
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CMOS/TTL Input Voltage −0.5V to (V
CMOS/TTL Output Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Maximum Package Power Dissipation
) −0.3V to +4V
CC
@
+25˚C
CC
0.3V)
CC
0.3V)
CC
0.3V)
CC
0.3V)
+
+
+
+
DS90CR288A 1.61 W
Package Derating:
DS90CR287 12.5 mW/˚C above
DS90CR288A 12.4 mW/˚C above
ESD Rating
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
Latch Up Tolerance
@
+25˚C
>
>
±
300mA
Recommended Operating
Conditions
Supply Voltage (V
) 3.0 3.3 3.6 V
CC
Operating Free Air
Temperature (T
) −10 +25 +70 ˚C
A
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
Min Nom Max Units
) 100 mV
CC
+25˚C
+25˚C
>
7kV
700V
PP
MTD56 (TSSOP) Package:
DS90CR287 1.63 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
LVDS DRIVER DC SPECIFICATIONS
V
OD
∆V
V
OS
∆V
I
OS
I
OZ
LVDS RECEIVER DC SPECIFICATIONS
V
TH
V
TL
I
IN
High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Output Voltage IOH= −0.4 mA 2.7 3.3 V
Low Level Output Voltage IOL= 2 mA 0.06 0.3 V
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
Input Current VIN= 0.4V, 2.5V or V
V
= GND −10 0 µA
Output Short Circuit Current V
IN
= 0V −60 −120 mA
OUT
CC
+1.8 +15 µA
Differential Output Voltage RL= 100Ω 250 290 450 mV
Change in VODbetween
OD
Complimentary Output States
Offset Voltage (Note 4) 1.125 1.25 1.375 V
Change in VOSbetween
OS
Complimentary Output States
Output Short Circuit Current V
Output TRI-STATE®Current PWR DWN = 0V,
= 0V, RL= 100Ω −3.5 −5 mA
OUT
V
OUT
=0VorV
CC
±
1
Differential Input High Threshold VCM= +1.2V +100 mV
Differential Input Low Threshold −100 mV
Input Current VIN= +2.4V, VCC= 3.6V
V
= 0V, VCC= 3.6V
IN
CC
35 mV
35 mV
±
10 µA
±
10 µA
±
10 µA
DS90CR287/DS90CR288A
V
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current
Worst Case (with Loads)
DS90CR287/DS90CR288A
I
CCTZ
Transmitter Supply Current
Power Down
RL= 100Ω,
= 5 pF,
C
L
Worst Case
Pattern
Figures 1, 2
(
)
PWR DWN = Low
Driver Outputs in TRI-STATE
f = 33 MHz 31 45 mA
f = 40 MHz 32 50 mA
f = 66 MHz 37 55 mA
f = 85 MHz 42 60 mA
10 55 µA
under Powerdown Mode
RECEIVER SUPPLY CURRENT
I
CCRW
I
CCRZ
Receiver Supply Current Worst
Case
Receiver Supply Current Power
Down
CL= 8 pF,
Worst Case
Pattern
Figures 1, 3
(
)
PWR DWN = Low
Receiver Outputs Stay Low during
f = 33 MHz 49 70 mA
f = 40 MHz 53 75 mA
f = 66 MHz 81 114 mA
f = 85 MHz 96 135 mA
140 400 µA
Powerdown Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
Note 4: V
and ∆VOD).
OD
previously referred as VCM.
OS
= 3.3V and TA= +25˚C.
CC
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
Figure 2
LLHT LVDS Low-to-High Transition Time (
LHLT LVDS High-to-Low Transition Time (
TCIT TxCLK IN Transition Time (
Figure 4
TPPos0 Transmitter Output Pulse Position for Bit0 (
TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1 . 68 1.88 ns
TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3 . 36 3.56 ns
TPPos3 Transmitter Output Pulse Position for Bit3 4.51 5 . 04 5.24 ns
TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6 . 72 6.92 ns
TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8 . 40 8.60 ns
TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10 .0810.28 ns
) 0.75 1.5 ns
Figure 2
) 0.75 1.5 ns
) 1.0 6.0 ns
Figure 15
) f = 85 MHz −0.20 0 0.20 ns
TCIP TxCLK IN Period
TCIH TxCLK IN High Time (
TCIL TxCLK IN Low Time (
TSTC TxIN Setup to TxCLK IN (
THTC TxIN Hold to TxCLK IN (
TCCD TxCLK IN to TxCLK OUT Delay
TPLLS Transmitter Phase Lock Loop Set (
TPDD Transmitter Powerdown Delay (
(Figure 6 )
Figure 6
Figure 6
Figure 6
Figure 6
11.76 T 50 ns
) 0.35T 0.5T 0.65T ns
) 0.35T 0.5T 0.65T ns
) f = 85 MHz 2.5 ns
)0ns
@
25˚C,VCC=3.3V (
Figure 10
Figure 13
) 100 ns
Figure 8
) 3.8 6.3 ns
)10ms
TJIT TxCLK IN Cycle-toCycle Jitter (Figure TBD) 2 ns
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
Figure 3
CLHT CMOS/TTL Low-to-High Transition Time (
CHLT CMOS/TTL High-to-Low Transition Time (
RSPos0 Receiver Input Strobe Position for Bit 0 (
RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns
RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns
RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns
RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns
RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns
RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns
RSKM RxIN Skew Margin (Note 5) (
RCOP RxCLK OUT Period (
RCOH RxCLK OUT High Time (
RCOL RxCLK OUT Low Time (
RSRC RxOUT Setup to RxCLK OUT (
RHRC RxOUT Hold to RxCLK OUT (
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set (
RPDD Receiver Powerdown Delay (
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Totallatency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2
Figure 17
Figure 7
Figure 7
Figure 7
) f = 85 MHz 290 ps
) 11.76 T 50 ns
) f = 85 MHz 4 5 6.5 ns
) 3.5 5 6 ns
Figure 7
) 3.5 ns
Figure 7
) 3.5 ns
@
25˚C, VCC= 3.3V (Note 6)(
Figure 11
Figure 14
)1µs
) 2 3.5 ns
Figure 3
) 1.8 3.5 ns
Figure 16
) f = 85 MHz 0.49 0.84 1.19 ns
Figure 9
) 5.5 7 9.5 ns
)10ms
*
T + RCCD), where T=Clock period.
DS90CR287/DS90CR288A
AC Timing Diagrams
DS101087-3
FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times
DS101087-2
FIGURE 1. “Worst Case” Test Pattern
DS101087-4
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