The DS90CF383 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifthLVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at arate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagram
DS90CF383
Features
n 20 to 65 MHz shift clock support
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption
n Power-down mode (
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Falling edge data strobe Transmitter
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating
n Operating Temperature: −40˚C to +85˚C
>
7kV
<
0.5 mW total)
<
250 mW (typ)
DS100033-1
Order Number DS90CF383MTD
See NS Package Number MTD56
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,
please contact the National SemiconductorSales Office/
Distributors for availability and specifications.
DS90CF383
Supply Voltage (V
CMOS/TTL Input Voltage−0.3V to (V
LVDS Driver Output Voltage−0.3V to (V
LVDS Output Short Circuit
DurationContinuous
Junction Temperature+150˚C
Storage Temperature−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)+260˚C
Maximum Package Power Dissipation Capacity
MTD56 (TSSOP) Package:
DS90CF3831.63 W
)−0.3V to +4V
CC
CC
CC
@
+ 0.3V)
+ 0.3V)
25˚C
Package Derating:
DS90CF38312.5 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
Recommended Operating
Conditions
Supply Voltage (V
)3.03.33.6V
CC
Operating Free Air
Temperature (T
)−40 +25 +85˚C
A
Receiver Input Range02.4V
Supply Noise Voltage (V
Min Nom MaxUnits
)100 mV
CC
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
SymbolParameterConditionsMinTypMaxUnits
CMOS/TTL DC SPECIFICATIONS
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
LVDS DC SPECIFICATIONS
V
OD
∆V
V
OS
∆V
I
OS
I
OZ
V
TH
V
TL
I
IN
TRANSMITTER SUPPLY CURRENT
ICCTWTransmitter Supply Current
ICCTGTransmitter Supply Current
ICCTZTransmitter Supply Current
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
High Level Input Voltage2.0V
Low Level Input VoltageGND0.8V
High Level Output VoltageIOH= −0.4 mA2.73.3V
Low Level Output VoltageIOL= 2 mA0.10.3V
Input Clamp VoltageICL= −18 mA−0.79−1.5V
Input CurrentVIN=VCC, GND, 2.5V or 0.4V
Output Short Circuit CurrentV
= 0V−60−120mA
OUT
±
5.1±10µA
Differential Output VoltageRL= 100Ω250345450mV
Change in VODbetween
OD
complimentary output states
Offset Voltage (Note 4)1.1251.251.375V
Change in VOSbetween
OS
complimentary output states
Output Short Circuit CurrentV
Output TRI-STATE®CurrentPower Down = 0V,
Power Down = Low
Driver Outputs in TRI-STATE®under
f = 32.5 MHz3145mA
f = 37.5 MHz3250mA
f = 65 MHz4255mA
f = 32.5 MHz2335mA
f = 37.5 MHz2840mA
f = 65 MHz3145mA
1055µA
Power Down Mode
CC
35mV
35mV
±
10µA
±
10µA
±
10µA
>
7kV
PP
V
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Electrical Characteristics (Continued)
Note 2: Typical values are given for VCC= 3.3V and TA= +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwisespeci-
fied (except V
Note 4: V
and ∆VOD).
OD
previously referred as VCM.
OS
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
SymbolParameterMinTypMax Units
(Figure 4 )
(Figure 3 )
(Figure 3 )
(Figure 5 )
(Figure 12 )
f = 65 MHz−0.400.3ps
LLHTLVDS Low-to-High Transition Time
LHLTLVDS High-to-Low Transition Time
TCITTxCLK IN Transition Time
TCCSTxOUT Channel-to-Channel Skew
TPPos0Transmitter Output Pulse Position for Bit 0
TPPos1Transmitter Output Pulse Position for Bit 11.82.22.5ns
TPPos2Transmitter Output Pulse Position for Bit 24.04.44.7ns
TPPos3Transmitter Output Pulse Position for Bit 36.26.66.9ns
TPPos4Transmitter Output Pulse Position for Bit 48.48.89.1ns
TPPos5Transmitter Output Pulse Position for Bit 510.611.011.3ns
TPPos6Transmitter Output Pulse Position for Bit 612.813.213.5ns
TCIPTxCLK IN Period
TCIHTxCLK IN High Time
TCILTxCLK IN Low Time
TSTCTxIN Setup to TxCLK IN
THTCTxIN Hold to TxCLK IN
TCCDTxCLK IN to TxCLK OUT Delay 25˚C, V
TPLLSTransmitter Phase Lock Loop Set
TPDDTransmitter Power Down Delay
Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7:
Figures 1, 2
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
show a falling edge data strobe (TxCLK IN/RxCLK OUT).
DS100033-6
FIGURE 3. DS90CF383 (Transmitter) LVDS Output Load and Transition Times
DS100033-8
FIGURE 4. DS90CF383 (Transmitter) Input Clock Transition Time
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AC Timing Diagrams (Continued)
DS90CF383
Measurements at V
TCCS measured between earliest and latest LVDS edges
TxCLK Differential Low→High Edge
FIGURE 6. DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
FIGURE 7. DS90CF383 (Transmitter) Clock In to Clock Out Delay
DS100033-9
DS100033-10
DS100033-12
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AC Timing Diagrams (Continued)
DS90CF383
FIGURE 8. DS90CF383 (Transmitter) Phase Lock Loop Set Time
DS100033-14
DS100033-16
FIGURE 9. Seven Bits of LVDS in Once Clock Cycle
FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
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DS100033-17
AC Timing Diagrams (Continued)
FIGURE 11. Transmitter Power Down Delay
DS90CF383
DS100033-18
DS100033-26
FIGURE 12. Transmitter LVDS Output Pulse Position Measurement
DS90CF383 Pin Description—FPD Link Transmitter
Pin NameI/O No.Description
TxINI28TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
TxOUT+O4Positive LVDS differentiaI data output.
TxOUT−O4Negative LVDS differential data output.
FPSHIFT INI1TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+O1Positive LVDS differential clock output.
TxCLK OUT−O1Negative LVDS differential clock output.
PWR DOWN
V
CC
I1TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
I4Power supply pins for TTL inputs.
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
power down.
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DS90CF383 Pin Description—FPD Link Transmitter (Continued)
Pin NameI/O No.Description
GNDI4Ground pins for TTL inputs.
DS90CF383
PLL V
CC
I1Power supply pin for PLL.
PLL GNDI2Ground pins for PLL.
LVDS V
CC
I1Power supply pin for LVDS outputs.
LVDS GNDI3Ground pins for LVDS outputs.
Applications Information
The DS90CF383 and DS90CF384 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CF583 and DS90CF584). To upgrade from a 5V to a
3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V
, LVDS VCCand PLLVCCof both the transmitter
CC
and receiver devices. This change may enable the removal of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90CF383 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CF383MTD
NS Package Number MTD56
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.