National Semiconductor DS90C387A, DS90CF388A Technical data

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DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link

General Description

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a ’dual pixel’ configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It pro-

vides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet.

Features

n Supports SVGA through QXGA panel resolutions n 32.5 to 112/170MHz clock support n Drives long, low cost cables n Up to 5.7 Gbps bandwidth n Pre-emphasis reduces cable loading effects n Dual pixel architecture supports interface to GUI and

timing controller; optional single pixel transmitter inputs support single pixel GUI interface

n Transmitter rejects cycle-to-cycle jitter n 5V tolerant on data and control input pins n Programmable transmitter data and control strobe select

(rising or falling edge strobe)

n Backward compatible with FPD-Link n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link

October 2002

Generalized Transmitter Block Diagram

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

10132002

Generalized Receiver Block Diagram

DS90C387A/DS90CF388A

Generalized Block Diagrams

10132003

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10132001

DS90C387A/DS90CF388A

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

CMOS/TTL Input Voltage −0.3V to +5.5V

CMOS/TTL Output Voltage −0.3V to (V

LVDS Receiver Input Voltage −0.3V to +3.6V

LVDS Driver Output Voltage −0.3V to +3.6V

LVDS Output Short Circuit Duration Continuous

Junction Temperature +150˚C

Storage Temperature −65˚C to +150˚C

Lead Temperature

(Soldering, 4 sec.) +260˚C

Maximum Package Power Dissipation Capacity

100 TQFP Package:

DS90C387A 2.8W

DS90CF388A 2.8W

) −0.3V to +4V

+ 0.3V)

25˚C

Package Derating:

DS90C387 A 18.2mW/˚C above +25˚C

DS90CF388 A 18.2mW/˚C above +25˚C

ESD Rating:

DS90C387A

(HBM, 1.5kΩ, 100pF)

(EIAJ, 0Ω, 200pF)

300 V

DS90CF388A

(HBM, 1.5kΩ, 100pF)

(EIAJ, 0Ω, 200pF)

200 V

Recommended Operating Conditions

Min Nom Max Units

Supply Voltage (V

Operating Free Air

Temperature (T

Receiver Input Range 0 2.4 V

Supply Noise Voltage (V

) 3.0 3.3 3.6 V

−10 +25 +70 ˚C

) 100 mV

6kV

2kV

p-p

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS (Tx inputs, Rx outputs, control inputs and outputs)

LVDS DRIVER DC SPECIFICATIONS

∆V

LVDS RECEIVER DC SPECIFICATIONS

High Level Input Voltage 2.0 V

Low Level Input Voltage GND 0.8 V

High Level Output Voltage IOH= −0.4 mA 2.7 2.9 V

= −2 mA 2.7 2.85 V

Low Level Output Voltage IOL= 2 mA 0.1 0.3 V

Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V

Input Current VIN= 0.4V, 2.5V or V

= GND −15 0 µA

Output Short Circuit Current V

= 0V −120 mA

OUT

+1.8 +15 µA

Differential Output Voltage RL= 100Ω 250 345 450 mV

Change in VODbetween

35 mV

Complimentary Output States

Offset Voltage 1.125 1.25 1.375 V

Change in VOSbetween

35 mV

Complimentary Output States

Output Short Circuit Current V

Output TRI-STATE®Current PD = 0V, V

= 0V, RL= 100Ω −3.5 −10 mA

OUT

=0VorV

10 µA

Differential Input High Threshold VCM= +1.2V +100 mV

Differential Input Low Threshold −100 mV

Input Current VIN= +2.4V, VCC= 3.6V

= 0V, VCC= 3.6V

10 µA

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply Current

Worst Case

DS90C387A/DS90CF388A

Transmitter Supply Current 16 Grayscale

ICCTZ Transmitter Supply Current

Power Down

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current

Worst Case

ICCRG Receiver Support Current

16 Grayscale

ICCRZ Receiver Supply Current

Power Down

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

specified (except V

and ∆VOD).

= 3.3V and TA= +25˚C.

= 100Ω,CL=5

f = 32.5 MHz 115 160 mA pF, Worst Case Pattern (Figures 1, 3), DUAL=High

f = 65 MHz 145 200 mA

f = 85 MHz 165 230 mA

f = 112 MHz 210 260 mA (48-bit RGB)

100Ω,C

= 5 pF,

16 Grayscale Pattern (Figures 2, 3), DUAL=High (48-bit RGB)

f = 32.5 MHz 92 140 mA

f = 65 MHz 100 150 mA

f = 85 MHz 110 170 mA

f = 112 MHz 130 190 mA

PD = Low

Driver Outputs in TRI-STATE under Powerdown Mode

= 8 pF,

Worst Case Pattern (Figures 1, 4), DUAL = High (48-bit RGB)

= 8 pF,

16 Grayscale Pattern (Figures 2, 4), DUAL = High (48-bit RGB)

f = 32.5 MHz 100 140 mA

f = 65 MHz 150 200 mA

f = 85 MHz 170 220 mA

f = 112 MHz 185 240 mA

f = 32.5 MHz 45 80 mA

f = 65 MHz 60 110 mA

f = 85 MHz 85 130 mA

f = 112 MHz 110 160 mA

PD = Low Receiver Outputs stay low during Powerdown mode.

4.8 50 µA

255 300 µA

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DS90C387A/DS90CF388A

Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

TCIT TxCLK IN Transition Time (Figure 5) DUAL=Gnd or Vcc 1.0 2.0 3.0 ns

DUAL=1/2Vcc 1.0 1.5 1.7 ns

TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc 8.928 T 30.77 ns

DUAL=1/2Vcc 5.88 15.38 ns

TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T ns

TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns

TXIT TxIN Transition Time 1.5 6.0 ns

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V

(disabled)

LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.6 ns

LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V

(disabled)

LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.7 ns

TBIT Transmitter Output Bit Width DUAL=Gnd or Vcc 1/7 TCIP ns

DUAL=1/2Vcc 2/7 TCIP ns

TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz −250 0 +250 ps

f = 70 to 112 MHz −200 0 +200 ps

TCCS TxOUT Channel to Channel Skew 100 ps

TSTC TxIN Setup to TxCLK IN (Figure 6) 2.7 ns

THTC TxIN Hold to TxCLK IN (Figure 6)0ns

TJCC Transmitter Jitter Cycle-to-cycle (Figures

13, 14) (Note 5), DUAL=Vcc

TPLLS Transmitter Phase Lock Loop Set (Figure 8)10ms

TPDD Transmitter Powerdown Delay (Figure 10) 100 ns

f = 112 MHz 85 100 ps

f = 85 MHz 60 75 ps

f = 65 MHz 70 80 ps

f = 56 MHz 100 120 ps

f = 32.5 MHz 75 110 ps

0.14 0.7 ns

0.16 0.8 ns

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Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out 1.52 2.0 ns

CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out 0.5 1.0 ns

CHLT CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out 1.7 2.0 ns

CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out 0.5 1.0 ns

RCOP RxCLK OUT Period (Figure 7) 8.928 T 30.77 ns

DS90C387A/DS90CF388A

RCOH RxCLK OUT High Time (Figure 7)(Note 4) f = 112 MHz 3.5 ns

f = 85 MHz 4.5 ns

RCOL RxCLK OUT Low Time (Figure 7)(Note 4) f = 112 MHz 3.5 ns

f = 85 MHz 4.5 ns

RSRC RxOUT Setup to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz 2.4 ns

f = 85 MHz 3.0 ns

RHRC RxOUT Hold to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz 3.4 ns

f = 85 MHz 4.75 ns

RPLLS Receiver Phase Lock Loop Set (Figure 9)10ms

RPDD Receiver Powerdown Delay (Figure 11)1µs

RSKM Receiver Skew Margin (Figure 12) (Notes 4, 6), f = 112 MHz 170 ps

f = 100 MHz 170 240 ps

f = 85MHz 300 350 ps

f = 66MHz 300 350 ps

Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify functional performance.

Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.

Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable) and clock jitter.

RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).

3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16).A jitter event of 3ns, represents worse case jump

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