The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTLdata into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/
LVTTLdata.At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient
interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver
(DS90CF384) without any translation logic. Both devices are
also offered in a 64 ball, 0.8mm fine pitch ball grid array
(FBGA) package which provides a 44 % reduction in PCB
footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
Features
n 20 to 65 MHz shift clock support
n Programmable transmitter (DS90C383) strobe select
(Rising or Falling edge strobe)
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption
7kV
<
0.5 mW total)
n Power-down mode (
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package.
n Also available in a 64 ball, 0.8mm fine pitch ball grid
array (FBGA) package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating
n Operating Temperature: −40˚C to +85˚C
>
<
250 mW (typ)
Typical Application
DS012887-2
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CMOS/TTL Input Voltage−0.3V to (V
CMOS/TTL Output Voltage−0.3V to (V
LVDS Receiver Input Voltage−0.3V to (V
LVDS Driver Output Voltage−0.3V to (V
LVDS Output Short Circuit
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Note 4: V
OS
and ∆VOD).
OD
previously referred as VCM.
= 3.3V and TA= +25C.
CC
,TA=
,TA=
,TA=
,TA=
f = 65 MHz4255mA
f = 32.5 MHz2335mA
f = 65 MHz3145mA
1055µA
®
under
f = 65 MHz78105mA
f = 65 MHz4360mA
1055µA
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
SymbolParameterMinTypMaxUnits
LLHTLVDS Low-to-High Transition Time
LHLTLVDS High-to-Low Transition Time
TCITTxCLK IN Transition Time
(Figure 5 )
TCCSTxOUT Channel-to-Channel Skew
TPPos0Transmitter Output Pulse Position for Bit 0
TPPos1Transmitter Output Pulse Position for Bit 11.82.22.5ns
TPPos2Transmitter Output Pulse Position for Bit 24.04.44.7ns
TPPos3Transmitter Output Pulse Position for Bit 36.26.66.9ns
TPPos4Transmitter Output Pulse Position for Bit 48.48.89.1ns
TPPos5Transmitter Output Pulse Position for Bit 510.61111.3ns
TPPos6Transmitter Output Pulse Position for Bit 612.813.213.5ns
TCIPTxCLK IN Period
TCIHTxCLK IN High Time
TCILTxCLK IN Low Time
TSTCTxIN Setup to TxCLK IN
THTCTxIN Hold to TxCLK IN
(Figure 7)
(Figure 7)
(Figure 7)
(Figure 7 )
(Figure 7 )
TCCDTxCLK IN to TxCLK OUT Delay 25˚C, V
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(Figure 3 )
(Figure 3 )
(Figure 6 )
(Figure 17 )
CC
= 3.3V
(Figure 9 )
0.751.5ns
0.751.5ns
5ns
250ps
f = 65 MHz−0.400.3ns
15T50ns
0.35T0.5T0.65Tns
0.35T0.5T0.65Tns
f = 65 MHz2.5ns
0ns
3.03.75.5ns
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
SymbolParameterMinTypMaxUnits
TPLLSTransmitter Phase Lock Loop Set
TPDDTransmitter Power Down Delay
(Figure 11 )
(Figure 15 )
10ms
100ns
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
SymbolParameterMinTypMaxUnits
CLHTCMOS/TTL Low-to-High Transition Time
CHLTCMOS/TTL High-to-Low Transition Time
RSPos0Receiver Input Strobe Position for Bit 0
RSPos1Receiver Input Strobe Position for Bit 12.93.33.6ns
RSPos2Receiver Input Strobe Position for Bit 25.15.55.8ns
RSPos3Receiver Input Strobe Position for Bit 37.37.78.0ns
RSPos4Receiver Input Strobe Position for Bit 49.59.910.2ns
RSPos5Receiver Input Strobe Position for Bit 511.712.112.4ns
RSPos6Receiver Input Strobe Position for Bit 613.914.314.6ns
RSKMRxIN Skew Margin (Note 5)
RCOPRxCLK OUT Period
RCOHRxCLK OUT High Time
RCOLRxCLK OUT Low Time
RSRCRxOUT Setup to RxCLK OUT
RHRCRxOUT Hold to RxCLK OUT
RCCDRxCLK IN to RxCLK OUT Delay 25˚C, V
RPLLSReceiver Phase Lock Loop Set
RPDDReceiver Power Down Delay
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 8:
Figures 1, 2
Note 9: Recommended pin to signal mapping. Customer may choose to define differently.
show a falling edge data strobe (TxCLK IN/RxCLK OUT).
DS012887-5
FIGURE 3. DS90C383 (Transmitter) LVDS Output Load and Transition Times
DS012887-6
FIGURE 4. DS90CF384 (Receiver) CMOS/TTL Output Load and Transition Times
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AC Timing Diagrams (Continued)
FIGURE 5. DS90C383 (Transmitter) Input Clock Transition Time
DS90C383/DS90CF384
DS012887-7
Measurements at V
TCCS measured between earliest and latest LVDS edges.
TxCLK Differential Low V High Edge
FIGURE 7. DS90C383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS012887-8
DS012887-9
DS012887-10
FIGURE 8. DS90CF384 (Receiver) Setup/Hold and High/Low Times
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AC Timing Diagrams (Continued)
DS90C383/DS90CF384
FIGURE 9. DS90C383 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
DS012887-11
DS012887-12
FIGURE 10. DS90CF384 (Receiver) Clock In to Clock Out Delay
FIGURE 11. DS90C383 (Transmitter) Phase Lock Loop Set Time
FIGURE 12. DS90CF384 (Receiver) Phase Lock Loop Set Time
DS012887-13
DS012887-14
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AC Timing Diagrams (Continued)
FIGURE 13. Seven Bits of LVDS in Once Clock Cycle
DS90C383/DS90CF384
DS012887-15
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
DS012887-17
FIGURE 15. Transmitter Power Down Delay
DS012887-16
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AC Timing Diagrams (Continued)
DS90C383/DS90CF384
DS012887-18
FIGURE 16. Receiver Power Down Delay
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
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DS012887-26
AC Timing Diagrams (Continued)
DS90C383/DS90CF384
FIGURE 18. Receiver LVDS Input Strobe Position
DS012887-25
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AC Timing Diagrams (Continued)
DS90C383/DS90CF384
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHZ
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 19. Receiver LVDS Input Skew Margin
Applications Information
The DS90C383 and DS90CF384 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CR583, DS90CR584, DS90CF583 and DS90CF584).
To upgrade from a 5V to a 3.3V system the following must be
addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V
, LVDS VCCand PLL VCCof both the transmitter
CC
and receiver devices. This change may enable the removal of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90C383 (transmitter) incorporates a rise/fall
strobe select pin. This select function is on pin 17,
formerly a V
rise/fall strobe select pin is connected to V
configured with a rising edge strobe. In a system currently using a 5V rising edge strobe transmitter
(DS90CR583), no layout changes are required to accommodate the new rise/fall select pin on the 3.3V
transmitter. The V
the device will be configured with a rising edge strobe.
When converting from a 5V falling edge transmitter
(DS90CF583) to the 3V transmitter a minimal board
layout change is necessary. The 3.3V transmitter will
not be configured with a falling edge strobe if V
mains connected to the select pin. To guarantee the
3.3V transmitter functions with a falling edge strobe pin
17 should be connected to ground OR left unconnected.
When not connected (left open) and internal pull-down
resistor ties pin 17 to ground, thus configuring the transmitter with a falling edge strobe.
3. The DS90C383 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
connection on the 5V products. When the
CC
signal may remain at pin 17, and
CC
, the part is
CC
re-
CC
DS012887-21
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DS90C383 TSSOP Package Pin Description — FPD Link Transmitter
Pin NameI/ONo.Description
TxINI28TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+O4Positive LVDS differentiaI data output.
TxOUT−O4Negative LVDS differential data output.
FPSHIFT INI1TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FBI1Programmable strobe select.
RTxCLK OUT+O1Positive LVDS differential clock output.
TxCLK OUT−O1Negative LVDS differential clock output.
PWR DOWN
V
CC
GNDI4Ground pins for TTL inputs.
PLL V
CC
PLL GNDI2Ground pins for PLL.
LVDS V
LVDS GNDI3Ground pins for LVDS outputs.
CC
I1TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
I3Power supply pins for TTL inputs.
I1Power supply pin for PLL.
I1Power supply pin for LVDS outputs.
DS90C383SLC SLC64A (FBGA) Package Pin Summary — FPD Link
Transmitter
DS90C383/DS90CF384
Pin NameI/ONo.Description
TxINI28TTL level input.
TxOUT+O4Positive LVDS differential data output.
TxOUT−O4Negative LVDS differential data output.
TxCLKINI1TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+O1Positive LVDS differential clock output.
TxCLK OUT−O1Negative LVDS differential clock output.
PWR DWN
R_FBI1Programmable strobe select. HIGH = rising edge, LOW = falling edge.
V
CC
GNDI5Ground pins for TTL inputs.
PLL V
CC
PLL GNDI2Ground pins for PLL.
LVDS V
LVDS GNDI4Ground pins for LVDS outputs.
NC6Pins not connected.
CC
I1TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
I3Power supply pins for TTL inputs.
I1Power supply pin for PLL.
I2Power supply pin for LVDS outputs.
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter
G : Ground
I : Input
O : Output
P : Power
NC : No Connect
(Continued)
By PinBy Pin Type
DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver
Pin NameI/ONo.Description
RxIN+I4Positive LVDS differentiaI data inputs.
RxIN−I4Negative LVDS differential data inputs.
RxOUTO28TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+I1Positive LVDS differential clock input.
RxCLK IN−I1Negative LVDS differential clock input.
FPSHIFT OUTO1TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
V
CC
GNDI5Ground pins for TTL outputs.
PLL V
CC
PLL GNDI2Ground pin for PLL.
LVDS V
CC
LVDS GNDI3Ground pins for LVDS inputs.
I1TTL level input. When asserted (low input) the receiver outputs are low.
I4Power supply pins for TTL outputs.
RxIN+I4Positive LVDS differentiaI data inputs.
RxIN−I4Negative LVDS differential data inputs.
RxOUTO28TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+I1Positive LVDS differential clock input.
RxCLK IN−I1Negative LVDS differential clock input.
FPSHIFT OUTO1TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN
V
CC
GNDI5Ground pins for TTL outputs.
PLL V
CC
PLL GNDI2Ground pin for PLL.
LVDS V
CC
I1TTL level input. When asserted (low input) the receiver outputs are low.
I4Power supply pins for TTL outputs.
64 ball, 0.8mm fine pitch ball grid array (FBGA) Package
Dimensions show in millimeters only
Order Number DS90CF384SLC or DS90C383SLC
NS Package Number SLC64A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
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