![](/html/00/0023/002339f51c0be3567039cf9dea0053b0b52c3648ce39cdbe5abdd8c678b6967c/bg1.png)
查询DS40MB200供应商
DS40MB200
Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and
Output Pre-Emphasis
DS40MB200 Dual 4 Gb/s 1:2 Mux/Buffer with Input Equalization and Output Pre-Emphasis
August 2005
General Description
The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane
redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data communication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer
to reduce ISI distortion from board traces. All output drivers
have 4 selectable steps of pre-emphasis to compensate for
transmission losses from long FR4 backplanes and reduce
deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers.
The internal loopback paths from switch-side input to switchside output enable at-speed system testing. All receiver
inputs and driver outputs are internally terminated with 100Ω
differential terminating resistors
Functional Block Diagram
Features
n Dual 2:1 multiplexer and 1:2 buffer
n 1– 4 Gbps fully differential data paths
n Fixed input equalization
n Programmable output pre-emphasis
n Independent switch and line side pre-emphasis controls
n Programmable switch-side loopback mode
n On-chip terminations
n +3.3V supply
n Low power, 1W max
n Lead-less LLP-48 package (7mmx7mmx0.8mm, 0.5mm
pitch)
n 0˚C to +85˚C operating temperature range
20021733
© 2005 National Semiconductor Corporation DS200217 www.national.com
![](/html/00/0023/002339f51c0be3567039cf9dea0053b0b52c3648ce39cdbe5abdd8c678b6967c/bg3.png)
Connection Diagram
DS40MB200
Order number DS40MB200SQ
See NS Package Number SQA48D
20021732
www.national.com3
![](/html/00/0023/002339f51c0be3567039cf9dea0053b0b52c3648ce39cdbe5abdd8c678b6967c/bg4.png)
Pin Descriptions
Pin Name
DS40MB200
LINE SIDE HIGH SPEED DIFFERENTIAL IO’s
LI_0+
LI_0−
LO_0+
LO_0−
LI_1+
LI_1−
LO_1+
LO_1−
Pin
Number
6
7
33
34
30
31
9
10
I/O Description
I Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0−
have an internal 50Ω connected to an internal reference voltage.
O Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0−
have an internal 50Ω connected to V
.
CC
I Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1−
have an internal 50Ω connected to an internal reference voltage.
O Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1−
have an internal 50Ω connected to V
.
CC
SWITCH SIDE HIGH SPEED DIFFERENTIAL IO’s
SOA_0+
SOA_0−
SOB_0+
SOB_0−
SIA_0+
SIA_0−
SIB_0+
SIB_0−
SOA_1+
SOA_1−
SOB_1+
SOB_1−
SIA_1+
SIA_1−
SIB_1+
SIB_1−
46
45
40
39
43
42
22
21
28
27
16
15
19
18
O Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and
SOA_0− have an internal 50Ω connected to V
4
3
O Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and
SOB_0− have an internal 50Ω connected to VCC.
.
CC
I Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+
and SIA_0− have an internal 50Ω connected to an internal reference voltage.
I Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+
and SIB_0− have an internal 50Ω connected to an internal reference voltage.
O Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and
SOA_1− have an internal 50Ω connected to V
.
CC
O Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and
SOB_1− have an internal 50Ω connected to V
.
CC
I Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+
and SIA_1− have an internal 50Ω connected to an internal reference voltage.
I Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+
and SIB_1− have an internal 50Ω connected to an internal reference voltage.
CONTROL (3.3V LVCMOS)
MUX_S0 37 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high.
Default state for mux_0 is switch A.
MUX_S1 13 A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high.
Default state for mux_1 is switch A.
PREL_0
PREL_1
12
I PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0
±
1
). PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side
LO_1
pre-emphasis levels.
PRES_0
PRES_1
36
25
I PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0
±
SOB_0
, SOA_1±and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See
Table 4 for switch side pre-emphasis levels.
LB0A 47 I A logic low at LB0A enables the internal loopback path from SIA_0±to SOA_0±. LB0A is
internally pulled high.
±
LB0B 48 I A logic low at LB0B enables the internal loopback path from SIB_0
to SOB_0±. LB0B is
internally pulled high.
±
LB1A 23 I A logic low at LB1A enables the internal loopback path from SIA_1
to SOA_1±. LB1A is
internally pulled high.
LB1B 24 I A logic low at LB1B enables the internal loopback path from SIB_1±to SOB_1±. LB1B is
internally pulled high.
RSV 26 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to
GND through an external pull-down resistor.
±
and
±
,
www.national.com 4
![](/html/00/0023/002339f51c0be3567039cf9dea0053b0b52c3648ce39cdbe5abdd8c678b6967c/bg5.png)
Pin Descriptions (Continued)
DS40MB200
Pin Name
POWER
V
CC
GND 5, 11, 17,
GND DAP P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the
Note: I = Input, O = Output, P = Power
Pin
Number
2, 8, 14,
20, 29, 35,
38, 44
32, 41
I/O Description
PV
P Ground reference. Each ground pin should be connected to the ground plane through a low
= 3.3V±5%.
CC
Each V
typically with a via located as close as possible to the landing pad of the V
It is recommended to have a 0.01 µF or 0.1 µF, X7R, size-0402 bypass capacitor from
each V
inductance path, typically with a via located as close as possible to the landing pad of the
GND pin.
LLP-48 package. It should be connected to the GND plane with at least 4 via to lower the
ground impedance and improve the thermal performance of the package.
pin should be connected to the VCCplane through a low inductance path,
CC
CC
pin to ground plane.
CC
pin.
Functional Descriptions
The DS40MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 4 Gb/s. Each
input stage has a fixed equalizer that provides equalization to compensate about 5 dB of transmission loss from a short backplane
trace (about 10 inches backplane). The output driver has pre-emphasis (driver-side equalization) to compensate the transmission
loss of the backplane that it is driving. The driver conditions the output signal such that the lower frequency and higher frequency
pulses reach approximately the same amplitude at the end of the backplane, and minimize the deterministic jitter caused by the
amplitude disparity. The DS40MB200 provides 4 steps of user-selectable pre-emphasis ranging from 0, -3, -6 and –9 dB to handle
different lengths of backplane. Figure 1 shows a driver pre-emphasis waveform. The pre-emphasis duration is 200ps nominal,
corresponds to 0.75 bit-width at 4 Gb/s. The pre-emphasis levels of switch-side and line-side can be individually programmed.
The high speed inputs are self-biased to about 1.5V and are designed for AC coupling. The inputs are compatible to most AC
coupling differential signals such as LVDS, LVPECL and CML.
TABLE 1. LOGIC TABLE FOR MULTIPLEX CONTROLS
MUX_S0 Mux Function
0 MUX_0 select switch_B input, SIB_0
1 (default) MUX_0 select switch_A input, SIA_0
MUX_S1 Mux Function
0 MUX_1 select switch_B input, SIB_1
1 (default) MUX_1 select switch_A input, SIA_0
TABLE 2. LOGIC TABLE FOR LOOPBACK Controls
LB0A Loopback Function
0 Enable loopback from SIA_0
1 (default) Normal mode. Loopback disabled.
LB0B Loopback Function
0 Enable loopback from SIB_0
1 (default) Normal mode. Loopback disabled.
LB1A Loopback Function
0 Enable loopback from SIA_1
1 (default) Normal mode. Loopback disabled.
LB1B Loopback Function
0 Enable loopback from SIB_1
1 (default) Normal mode. Loopback disabled.
±
to SOA_0±.
±
to SOB_0±.
±
to SOA_1±.
±
to SOB_1±.
±
.
±
.
±
.
±
.
www.national.com5