National Semiconductor DS32EV400 Technical data

DS32EV400
Programmable Quad Equalizer

DS32EV400 Programmable Quad Equalizer

April 18, 2008

General Description

The DS32EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS32EV400 is optimized for operation up to

3.2 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro­grammed by three control pins, or individually through a Serial
Management Bus (SMBus) interface.

The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal­anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs. The
DS32EV400 is available in a 7 mm x 7 mm 48-pin leadless
LLP package. Power is supplied from either a 2.5V or 3.3V
supply.

Simplified Application Diagram

Features

Equalizes up to 14 dB loss at 3.2 Gbps

■

8 levels of programmable equalization

■

Settable through control pins or SMBus interface

■

Operates up to 3.2 Gbps with 40” FR4 traces

■

0.12 UI residual deterministic jitter at 3.2 Gbps with 40”

■

FR4 traces
Single 2.5V or 3.3V power supply

■

Signal Detect for individual channels

■

Standby mode for individual channels

■

Supports AC or DC-Coupling with wide input common-

■

mode
Low power consumption: 375 mW Typ at 2.5V

■

Small 7 mm x 7 mm 48-pin LLP package

■

9 kV HBM ESD Rating

■

-40 to 85°C operating temperature range

■

30031924

© 2008 National Semiconductor Corporation 300319 www.national.com

Pin Descriptions

Pin Name Pin # I/O, Type Description

HIGH SPEED DIFFERENTIAL I/O

DS32EV400

IN_0+
IN_0–

IN_1+
IN_1–

IN_2+
IN_2–

IN_3+
IN_3–

OUT_0+
OUT_0–

OUT_1+
OUT_1–

OUT_2+
OUT_2–

OUT_3+
OUT_3–

EQUALIZATION CONTROL

BST_2
BST_1
BST_0

DEVICE CONTROL

EN0 44 I, LVCMOS Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held

EN1 42 I, LVCMOS Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held

EN2 40 I, LVCMOS Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held

EN3 38 I, LVCMOS Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held

FEB 21 I, LVCMOS Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]

SD0 45 O, LVCMOS Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.

SD1 43 O, LVCMOS Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.

SD2 41 O, LVCMOS Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.

SD3 39 O, LVCMOS Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.

POWER

V

DD

GND 22, 24,

DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to

1
2

4
5

8
9

11
12

36
35

33
32

29
28

26
25

37
14
23

3, 6, 7,
10, 13,

15, 46

27, 30,

31, 34

I, CML

I, CML

I, CML

I, CML

O, CML

O, CML

O, CML

O, CML

I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is

Power VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance

Power Ground reference. GND should be tied to a solid ground plane through a low impedance

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD.

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD.

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD.

Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD.

internally pulled high. BST_1 and BST_0 are internally pulled low.

Low, standby mode is selected. EN is internally pulled High.

Low, standby mode is selected. EN is internally pulled High.

Low, standby mode is selected. EN is internally pulled High.

Low, standby mode is selected. EN is internally pulled High.

pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.

path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.

path.

ground plane of the board.

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Pin Name Pin # I/O, Type Description

SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS

SDA
SDC
CS

Other

Reserv 19, 20

Note: I = Input O = Output

18
17
16

47,48

I/O, LVCMOS

I, LVCMOS
I, LVCMOS

Reserved. Do not connect.

Data input/output (bi-directional). Internally pulled high.
Clock input. Internally pulled high.
Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus
configuration Registers” section for detail information.

Connection Diagram

DS32EV400

30031926

Ordering Information

NSID Package Type, Qty Size Package ID

DS32EV400SQ 48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250 SQA48D

DS32EV400SQX 48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500 SQA48D

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

DS32EV400

Supply Voltage (VDD)

CMOS Input Voltage -0.5V + 4.0V
CMOS Output Voltage -0.5V to 4.0V
CML Input/Output Voltage -0.5V to 4.0V

Junction temperature +150°C
Storage temperature -65°C to +150°C
Lead temperature (Soldering, 4

Seconds)

-0.5V to +4.0V

+260°C

ESD rating

HBM, 1.5 kΩ, 100 pF

EIAJ, 0Ω, 200pF

Thermal Resistance

 θJA, no airflow

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (Note 9)
V

to GND 2.375 2.5 2.625 V

DD2.5

V

to GND 3.0 3.3 3.6 V

DD3.3

Ambient Temperature -40 25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless other specified.

Symbol Parameter Conditions Min

POWER

P Power Supply Consumption Device Output Enabled

(EN [0–3] = High), V

DD3.3

Device Output Disable
(EN [0–3] = Low), V

DD3.3

P Power Supply Consumption Device Output Enabled

(EN [0–3] = High), V

DD2.5

Device Output Disable
(EN [0–3] = Low), V

DD2.5

N Supply Noise Tolerance (Note 4) 50 Hz — 100 Hz

100 Hz — 10 MHz
10 MHz — 1.6 GHz

LVCMOS DC SPECIFICATIONS

V

IH

V

IL

V

OH

V

OL

I

IN

High Level Input Voltage V

V

DD3.3

DD2.5

Low Level Input Voltage -0.3 0.8 V

High Level Output Voltage IOH = -3mA, V

IOH = -3mA, V

DD3.3

DD2.5

Low Level Output Voltage IOL = 3mA 0.4 V

Input Leakage Current VIN = V

DD

VIN = GND -15

I

IN-P

Input Leakage Current with
Internal Pull-Down/Up Resistors

VIN = VDD, with internal pull-down
resistors

VIN = GND, with internal pull-up
resistors

SIGNAL DETECT

SDH Signal Detect ON Threshold Level Default input signal level to assert

SD pin, 3.2 Gbps

SDI Signal Detect OFF Threshold

Level

Default input signal level to de­assert SD, 3.2Gbps

2.0

1.6

2.4 V

2.0

+15

+120

-20

70 mV

40 mV

Typ

(note 2)

490 700 mW

360 490 mW

100

> 9 kV

> 250 V

30°C/W

Max Units

100 mW

30

mV

40
10

V

V

DD3.3

DD2.5

mV
mV

P-P

P-P

P-P

V

V

μA

μA

μA

μA

p-p

p-p

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DS32EV400

Symbol Parameter Conditions Min

Typ

(note 2)

Max Units

CML RECEIVER INPUTS (IN_n+, IN_n-)

V

TX

Source Transmit Launch Signal
Level (IN diff)

AC-Coupled or DC-Coupled
Requirement, Differential
measurement at point A.

400 1600

mV

P-P

Figure 1

V

INTRE

V

DDTX

V

ICMDC

R

LI

R

IN

Input Threshold Voltage Differential measurement at

point B. Figure 1

Supply Voltage of Transmitter toEQDC-Coupled Requirement

(Note 10)

Input Common Mode Voltage DC-Coupled Requirement,

Differential measurement at point
A. Figure 1, (Note 7)

Differential Input Return Loss 100MHz – 1.6GHz, with fixture’s

effect de-embedded

Input Resistance Differential across IN+ and IN-,

Figure 6.

120

V

V

DD

DDTX

0.2

–

1.6

V

–

DDTX

0.8

10 dB

85 100 115

mV

P-P

V

V

Ω

CML OUTPUTS (OUT_n+, OUT_n-)

V

OD

Output Differential Voltage Level
(OUT diff)

Differential measurement with
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled

500 620 725

mV

P-P

Figure 2

V

OCM

Output Common Mode Voltage Single-ended measurement DC-

Coupled with 50Ω terminations

VDD– 0.2

VDD– 0.1

V

(Note 7)

tR, t

F

Transition Time 20% to 80% of differential output

voltage, measured within 1” from

20 60 ps

output pins. Figure 2, (Note 7)

R

O

R

LO

Output Resistance Single ended to V

DD

Differential Output Return Loss 100 MHz – 1.6 GHz, with fixture’s

effect de-embedded. IN+ = static

42 50 58

10 dB

Ω

high.

t

PLHD

t

PHLD

t

CCSK

t

PPSK

Differential Low to High
Propagation Delay

Differential High to Low
Propagation Delay

Inter Pair Channel to Channel
Skew

Propagation delay measurement
at 50% VO between input to
output, 100 Mbps. Figure 3,
(Note 7)

Difference in 50% crossing
between channels

Part to Part Output Skew Difference in 50% crossing

between outputs

240 ps

240 ps

7 ps

20 ps

EQUALIZATION

DJ1 Residual Deterministic Jitter

at 3.2 Gbps

40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)

0.12 0.20

UI

P-P

pattern. (Note 5, 6)

DJ2 Residual Deterministic Jitter

at 2.5 Gbps

40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)

0.1 0.16

UI

P-P

pattern. (Note 5, 6)

DJ3 Residual Deterministic Jitter

at 1 Gbps

40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)

0.05

UI

P-P

pattern. (Note 5, 6)

RJ Random Jitter (Note 7, 8) 0.5 psrms

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Symbol Parameter Conditions Min

Typ

(note 2)

Max Units

SIGNAL DETECT and ENABLE TIMING

t

DS32EV400

ZISD

t

IZSD

Input OFF to ON detect — SD
Output High Response Time

Input ON to OFF detect — SD
Output Low Response Time

Response time measurement at
VIN to SD output, VIN = 800 mV
100 Mbps, 40” of 6 mil microstrip
FR4

P-P

35 ns

,

400 ns

(Figure 1, 4), (Note 7)

t

OZOED

t

ZOED

EN High to Output ON Response
Time

EN Low to Output OFF Response
Time

Response time measurement at
EN input to VO, VIN = 800 mV

P-P

100 Mbps, 40” of 6 mil microstrip
FR4

,

150 ns

5 ns

(Figure 1, 5), (Note 7)

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.

Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.

Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 4: Allowed supply noise (mV

Note 5: Specification is guaranteed by characterization and is not tested in production.

Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).

Random jitter is removed through the use of averaging or similar means.

Note 7: Measured with clock like {11111 00000} pattern.

Note 8: Random jitter contributed by the equalizer is defined as sqrt (J

Figure 1; JIN is the random jitter at the input of the equalizer in ps-rms, see Figure 1.

Note 9: The V

is VDD = 2.5V ± 5% and V

DD2.5

sine wave) under typical conditions.

P-P

is VDD = 3.3V ± 10%.

DD3.3

OUT

2

− J

2

). J

is the random jitter at the equalizer outputs in ps-rms, see point C of

IN

OUT

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