National Semiconductor DS16EV5110 Technical data

DS16EV5110 Video Equalizer (3D+C) for DVI, HDMI Sink-Side Applications

July 17, 2008

General Description

The DS16EV5110 is a multi-channel equalizer optimized for video cable extension sink-side applications. It operates between 250Mbps and 2.25Gbps with common applications at

1.65Gbps and 2.25Gbps (per data channel). It contains three Transition-Minimized Differential Signaling (TMDS) data channels and one clock channel as commonly found in DVI and HDMI cables. It provides compensation for skin-effect and dielectric losses, a common phenomenon when transmitting video on commercially available high definition video cables.

The inputs conform to DVI and HDMI requirements and features programmable levels of input equalization. The programmable levels of equalization provide optimal signal boost and reduces inter-symbol interference. Eight levels of boost are selectable via a pin interface or by the optional System Management Bus.

The clock channel is optimized for clock rates of up to 225 MHz and features a signal detect circuit. To maximize noise immunity, the DS16EV5110 features a signal detector with programmable thresholds. The threshold is adjustable through a System Management Bus (SMBus) interface.

The DS16EV5110 also provides support for system power management via output enable controls. Additional controls are provided via the SMBus enabling customization and optimization for specific applications requirements. These controls include programmable features such as output amplitude and boost controls as well as system level diagnostics.

Features

8 levels of equalization settable by 3 pins or through the

■

SMBus interface

DC-Coupled inputs and outputs

■

Optimized for operation from 250 Mbps to 2.25 Gbps in

■

support of UXGA, 480 I/P, 720 I/P, 1080 I, and 1080 P with 8, 10, and 12–bit Color Depth Resolutions

Two DS16EV5110 devices support DVI/HDMI Dual Link

■

DVI 1.0, and HDMI 1.3a Compatible TMDS Interface

■

Clock channel signal detect (LOS)

■

Enable for power savings standby mode

■

System Management Bus (SMBus) provides control of

■

boost, output amplitude, enable, and clock channel signal detect threshold

Low power consumption: 475mW (Typical)

■

0.13 UI total jitter at 1.65 Gbps including cable

■

Single 3.3V power supply

■

Small 7mm x 7mm, 48-pin leadless LLP package

■

-40°C to +85°C operating temperature range

■

Extends TMDS cable reach over:

■

1.

> 40 meters 24 AWG DVI Cable (1.65Gbps)

2.

> 20 meters 28 AWG DVI Cable (1.65Gbps)

3.

> 20 meters Cat5/Cat5e/Cat6 cables (1.65Gbps)

4.

> 20 meters 28 AWG HDMI cables (2.25Gbps)

Applications

Sink–side Video Applications:

■

Projectors

■

High Definition Displays

■

Typical Application

20216251

Pin Descriptions

Pin Name Pin Number I/O, Type Description

HIGH SPEED DIFFERENTIAL I/O

DS16EV5110

C_IN−

C_IN+

D_IN0−

D_IN0+

D_IN1−

D_IN1+

D_IN2−

D_IN2+

C_OUT-

C_OUT+

D_OUT0−

D_OUT0+

D_OUT1–

D_OUT1+

D_OUT2−

D_OUT2+

Equalization Control

BST_0

BST_1

BST_2

Device Control

EN 44 I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,

FEB 21 I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the BST_

SD 45 O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.

POWER

V

DD

GND 22, 24,

Exposed

Pad

System Management Bus (SMBus) Interface Control Pins

SDA 18 IO,

SDC 17 I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.

CS 16 I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held

Other

Reserv 19, 20, 38,

Note: I = Input, O = Output, IO =Input/Output,

1

2

4

5

8

9

11

12

36

35

33

32

29

28

26

25

23

14

37

3, 6, 7,

10, 13,

15, 46

27, 30,

31, 34

DAP GND The exposed pad at the center of the package must be connected to the ground plane.

39, 40,41,

42, 43, 47,

48

I, CML

O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.

I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0,

Power VDD pins should be tied to the VDD plane through a low inductance path. A 0.1µF bypass

GND Ground reference. GND should be tied to a solid ground plane through a low impedance

LVCMOS

Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating

resistor connects C_IN+ to VDD and C_IN- to VDD.

Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

resistor connects D_IN0+ to VDD and D_IN0- to VDD.

Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

resistor connects D_IN1+ to VDD and D_IN1- to VDD.

Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating

resistor connects D_IN2+ to VDD and D_IN2- to VDD.

BST_1, and BST_2 are internally pulled Low. See Table 2.

standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock

channels.

[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus (see Table 1) control pins. FEB is internally pulled High.

capacitor should be connected between each VDD pin to the GND planes.

path.

SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.

Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally

gated with SDC.

Reserved. Do not connect.

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Connection Diagram

DS16EV5110

TOP VIEW — Not to Scale

Ordering Information

NSID Tape & Reel Quantity Package

DS16EV5110SQ 250 SQA48D

DS16EV5110SQX 2,500 SQA48D

20216252

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

DS16EV5110

Supply Voltage (VDD)

LVCMOS Input Voltage -0.5V + 4.0V

LVCMOS Output Voltage -0.5V to 4.0V

CML Input/Output Voltage -0.5V to 4.0V

Junction Temperature +150°C

Storage Temperature -65°C to +150°C

Lead Temp. (Soldering, 5 sec.) +260°C

-0.5V to +4.0V

ESD Rating

HBM, 1.5 kΩ, 100 pF

CML Inputs >10 kV

Thermal Resistance

θJA, No Airflow

Recommended Operating Conditions (Notes 2, 3)

Min Typ Max Units

Supply Voltage

(VDD to GND)

Ambient Temperature -40 25 +85 °C

3.0 3.3 3.6 V

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC SPECIFICATIONS

I

IH-PU

I

IH-PD

I

IL-PU

I

IL-PD

V

IH

V

IL

V

OH

V

OL

POWER

PD Power Dissipation EN = High, Device Enabled 475 700 mW

N Supply Noise Tolerance (Note 4) DC to 50MHz

CML INPUTS

V

TX

V

ICMDC

V

IN

R

LI

R

IN

CML OUTPUTS

V

O

V

OCM

tR, t

F

t

CCSK

High Level Input Leakage Current LVCMOS pins with internal pull-up

resistors

High Level Input Leakage Current LVCMOS pins with internal pull-

down resistors

Low Level Input Leakage Current LVCMOS pins with internal pull-up

resistors

Low Level Input Leakage Current LVCMOS pins with internal pull-

down resistors

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage SD Pin, IOH = -3mA

Low Level Output Voltage SD Pin, IOL = 3mA

-10 +10

80 105

-20 -10

-10 +10

2.0 VDD V

0 0.8 V

2.4 V

0.4 V

EN = Low, Power Down Mode 70 mW

Input Voltage Swing (Launch

Amplitude)

Input Common-Mode Voltage DC-Coupled Requirement

Input Voltage Swing Measured differentially at TPB

Differential Input Return Loss 100 MHz– 825 MHz, with fixture's

Input Resistance IN+ to VDD and IN− to VDD

Measured differentially at TPA (Figure 2)

Measured at TPA (Figure 2)

(Figure 2)

effect de-embedded

800 1200

VDD-0.3

120

10 dB

45 50 55

Output Voltage Swing Measured differentially with OUT+

and OUT− terminated by 50Ω to

800 1200

VDD

Output common-mode Voltage Measured Single-ended VDD-0.3

Transition Time 20% to 80% of differential output

voltage, measured within 1" from

75 240 ps

output pins.

Inter Pair Channel-to-Channel

Skew (all 4 Channels)

Difference in 50% crossing

between shortest and longest

25 ps

channels

100

mV

VDD-0.2

>8 kV

30°C/W

μA

mV

V

mV

Ω

mV

V

P-P

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Symbol Parameter Conditions Min Typ Max

Electrical Characteristics — System Management Bus Interface (Notes 2, 3)

Over recommended operating supply and temperature ranges unless other specified.

Symbol Parameter Conditions Min Typ Max Units

DS16EV5110

System Bus Interface — DC Specifications

V

IL

V

IH

I

PULLUP

V

DD

I

LEAK-Bus

I

LEAK-Pin

C

I

R

TERM

System Bus Interface Timing Specification

FSMB Bus Operating Frequency (Note 12) 10 100 kHz

TBUF Bus Free Time Between Stop and

THD:STA Hold Time After (Repeated) Start

TSU:STA Repeated Start Condition Setup

TSU:STO Stop Condition Setup Time 4.0 µs

THD:DAT Data Hold Time 300 ns

TSU:DAT Data Setup Time 250 ns

T

TIMEOUT

T

LOW

T

HIGH

T

:SEXT Cumulative Clock Low Extend

LOW

t

F

t

R

t

POR

Data, Clock Input Low Voltage

Data, Clock Input High Voltage 2.8

Current through pull-up resistor or

VOL = 0.4V

current source

Nominal Bus Voltage 3.0

Input Leakage per bus segment (Note 9)

—200

Input Leakage per device pin

Capacitance for SDA and SDC (Notes 9, 10)

Termination Resistance V

Start Condition

Condition. First CLK generated

, (Notes 9, 10, 11)

DD3.3

At I

PULLUP

, Max

4.7

4.0 µs

after this period.

Time

Detect Clock Low Timeout (Note 12)

Clock Low Period

Clock High Period (Note 12)

4.7 µs

25 35 ms

4.7 µs

4.0 50 µs

(Note 12)

Time (Slave Device)

Clock/Data Fall Time (Note 12)

Clock/Data Rise Time (Note 12)

Time in which a device must be

(Note 12)

operational after power-on reset

10

0.8

V

DD

3.6

+200

—15

10 pF

1000

2 ms

300 ns

1000 ns

500 ms

V

mA

V

µA

Ω

µs

Note 9: Recommended value. Parameter not tested in production.

Note 10: Recommended maximum capacitance load per bus segment is 400pF.

Note 11: Maximum termination voltage should be identical to the device supply voltage.

Note 12: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common

AC specifications for details.

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