The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
) monitors
Typical Application
Features
DC - 1.5 Gbps low jitter, low skew, low power operation
■
Pin and SMBus configurable, fully differential, non-
■
blocking architecture
Wide input common mode range enables DC coupled
■
interface to CML or LVPECL drivers
circuitry detects open inputs fault condition
LOS
■
On-chip 100 Ω input and output termination minimizes
■
insertion and return losses, reduces component count and
minimizes board space
8 kV ESD on LVDS I/O pins protects adjoining
■
components
Small 6 mm x 6 mm LLP-40 space saving package
EN_smb17I, LVCMOSSystem Management Bus (SMBus) mode enable pin. The pin has
S00/SCL,
S01/SDA
S10/ADDR0,
S11/ADDR1
S20/ADDR2,
S21/ADDR3
S30, S3113, 14I, LVCMOSFor EN_smb = [0], these pins select which LVDS input is routed
PWDN38I, LVCMOSFor EN_smb = [0], this is the power down pin. When the PWDN is
NC11, 12,
VDD3, 8,
GND16, DAP PowerGround pin and pad (DAP - die attach pad).
Number
1, 2,
4, 5,
6, 7,
9, 10
29, 28,
27, 26,
24, 23,
22, 21
37,
36
35,
34
33,
32
18, 19,
20, 31,
39, 40
15,25, 30
I/O, TypePin Description
I, LVDSInverting and non-inverting high speed LVDS input pins.
O, LVDSInverting and non-inverting high speed LVDS output pins.
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
I/O, LVCMOSFor EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
I/O, LVCMOSFor EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
I/O, LVCMOSFor EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic [0] or [1].
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
No connect pins. May be left floating.
PowerPower supply pins.
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DS10CP154A
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage−0.3V to +4V
LVCMOS Input Voltage−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage−0.3V to (VCC + 0.3V)
LVDS Input Voltage−0.3V to +4V
LVDS Differential Input Voltage0V to 1.0V
LVDS Output Voltage−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage0V to 1.0V
LVDS Output Short Circuit Current
Duration
Junction Temperature+150°C
Storage Temperature Range−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)+260°C
Maximum Package Power Dissipation at 25°C
SQA Package4.65W
Derate SQA Package37.2 mW/°C above +25°C
5 ms
Package Thermal Resistance
θ
θ
JA
JC
+26.9°C/W
+3.8°C/W
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Output Short Circuit Current (Note 8)OUT to GND-25-55mA
OUT to V
CC
Output CapacitanceAny LVDS Output Pin to GND
Output Termination ResistorBetween OUT+ and OUT-
755mA
1.2pF
100
SUPPLY CURRENT
I
I
CC1
CC2
Supply CurrentPWDN = 04050mA
Supply CurrentPWDN = 1
103125mA
Broadcast Mode (1:4)
I
CC3
Supply CurrentPWDN = 1
115140mA
Quad Buffer Mode (4:4)
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD andΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Ω
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