DS10CP154A
1.5 Gbps 4x4 LVDS Crosspoint Switch
DS10CP154A 1.5 Gbps 4x4 LVDS Crosspoint Switch
August 12, 2008
General Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
) monitors
Typical Application
Features
DC - 1.5 Gbps low jitter, low skew, low power operation
■
Pin and SMBus configurable, fully differential, non-
■
blocking architecture
Wide input common mode range enables DC coupled
■
interface to CML or LVPECL drivers
circuitry detects open inputs fault condition
LOS
■
On-chip 100 Ω input and output termination minimizes
■
insertion and return losses, reduces component count and
minimizes board space
8 kV ESD on LVDS I/O pins protects adjoining
■
components
Small 6 mm x 6 mm LLP-40 space saving package
■
Applications
High-speed channel select applications
■
Clock and data buffering and muxing
■
SD / HD SDI Routers
■
30073703
© 2008 National Semiconductor Corporation 300737 www.national.com
Ordering Code
NSID Function
DS10CP154ATSQ Crosspoint Switch
DS10CP154A
Block Diagram
30073701
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Connection Diagram
DS10CP154A
DS10CP154A Pin Diagram
30073702
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Pin Descriptions
Pin Name Pin
DS10CP154A
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
EN_smb 17 I, LVCMOS System Management Bus (SMBus) mode enable pin. The pin has
S00/SCL,
S01/SDA
S10/ADDR0,
S11/ADDR1
S20/ADDR2,
S21/ADDR3
S30, S31 13, 14 I, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
PWDN 38 I, LVCMOS For EN_smb = [0], this is the power down pin. When the PWDN is
NC 11, 12,
VDD 3, 8,
GND 16, DAP Power Ground pin and pad (DAP - die attach pad).
Number
1, 2,
4, 5,
6, 7,
9, 10
29, 28,
27, 26,
24, 23,
22, 21
37,
36
35,
34
33,
32
18, 19,
20, 31,
39, 40
15,25, 30
I/O, Type Pin Description
I, LVDS Inverting and non-inverting high speed LVDS input pins.
O, LVDS Inverting and non-inverting high speed LVDS output pins.
an internal 20k pull down. When the pin is set to a [1], the device
is in the SMBus mode. All SMBus registers are reset when the pin
is toggled.
I/O, LVCMOS For EN_smb = [1], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are the
SMBus clock input and data I/O pins respectively.
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
I/O, LVCMOS For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are nonfunctional and should be tied to either logic [0] or [1].
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
No connect pins. May be left floating.
Power Power supply pins.
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DS10CP154A
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVCMOS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
LVDS Differential Input Voltage 0V to 1.0V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1.0V
LVDS Output Short Circuit Current
Duration
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
SQA Package 4.65W
Derate SQA Package 37.2 mW/°C above +25°C
5 ms
Package Thermal Resistance
θ
θ
JA
JC
+26.9°C/W
+3.8°C/W
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
≥8 kV
≥250V
≥1250V
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
SMBus (SDA, SCL) 3.6 V
0 1.0 V
−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
V
IH
V
IL
I
IH
I
IL
V
CL
V
OL
LVDS INPUT DC SPECIFICATIONS
V
ID
V
TH
V
TL
V
CMR
I
IN
C
IN
R
IN
High Level Input Voltage 2.0 V
DD
Low Level Input Voltage GND 0.8 V
High Level Input Current VIN = 3.6V
VCC = 3.6V
Low Level Input Current VIN = GND
0 ±10
EN_smb pin 40 175 250
0 ±10
VCC = 3.6V
Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V
Low Level Output Voltage IOL= 4 mA SDA pin 0.4 V
Input Differential Voltage 0 1 V
Differential Input High Threshold
Differential Input Low Threshold
VCM = +0.05V or VCC-0.05V
0 +100 mV
−100 0 mV
Common Mode Voltage Range VID = 100 mV 0.05 VCC -
0.05
Input Current
VIN = 3.6V or 0V
VCC = 3.6V or 0V
Input Capacitance Any LVDS Input Pin to GND
Input Termination Resistor Between IN+ and IN-
±1 ±10
1.7 pF
100
V
μA
μA
μA
V
μA
Ω
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Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT DC SPECIFICATIONS
V
OD
ΔV
DS10CP154A
V
OS
ΔV
I
OS
C
OUT
R
OUT
Differential Output Voltage
Change in Magnitude of VOD for Complimentary
OD
Output States
Offset Voltage
Change in Magnitude of VOS for Complimentary
OS
Output States
RL = 100Ω
RL = 100Ω
250 350 450 mV
-35 35 mV
1.05 1.2 1.375 V
-35 35 mV
Output Short Circuit Current (Note 8) OUT to GND -25 -55 mA
OUT to V
CC
Output Capacitance Any LVDS Output Pin to GND
Output Termination Resistor Between OUT+ and OUT-
7 55 mA
1.2 pF
100
SUPPLY CURRENT
I
I
CC1
CC2
Supply Current PWDN = 0 40 50 mA
Supply Current PWDN = 1
103 125 mA
Broadcast Mode (1:4)
I
CC3
Supply Current PWDN = 1
115 140 mA
Quad Buffer Mode (4:4)
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Ω
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (Note 11)
t
PLHD
t
PHLD
t
SKD1
t
SKD2
t
SKD3
t
LHT
t
HLT
t
ON
t
OFF
t
SEL
JITTER PERFORMANCE (Note 11)
t
RJ1
t
RJ2
t
RJ3
t
RJ4
t
DJ1
t
DJ2
t
DJ3
t
DJ4
t
TJ1
t
TJ2
t
TJ3
t
TJ4
Differential Propagation Delay Low to
High
Differential Propagation Delay High to
RL = 100Ω
500 675 ps
460 675 ps
Low
Pulse Skew |t
PLHD
− t
| , (Note 12) 40 100 ps
PHLD
Channel to Channel Skew , (Note 13) 40 125 ps
Part to Part Skew , (Note 14) 50 225 ps
Rise Time
Fall Time 145 350 ps
Power Up Time
RL = 100Ω
Time from PWDN = LH to OUTn active
Power Down Time Time from PWDN = HL to OUTn
145 350 ps
7 20
6 25 ns
inactive
Select Time Time from Sn = LH or HL to new signal
8 12 ns
at OUTn
Random Jitter
(RMS Value)
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz 1 2.0 ps
311 MHz 0.5 1.2 ps
503 MHz 0.5 1.0 ps
750 MHz 0.5 1.0 ps
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
270 Mbps 7 30 ps
622 Mbps 12 26 ps
1.06 Gbps 9 24 ps
1.5 Gbps 12 28 ps
Total Jitter
(Peak to Peak Value)
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
270 mbps 0.008 0.036
622 Mbps 0.007 0.043
1.06Gbps 0.008 0.064
1.5 Gbps 0.007 0.072
UI
UI
UI
UI
DS10CP154A
μs
P-P
P-P
P-P
P-P
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Symbol Parameter Conditions Min Typ Max Units
SMBus AC SPECIFICATIONS
f
SMB
t
BUF
DS10CP154A
t
HD:SDA
SMBus Operating Frequency 10 100 kHz
Bus free time between Stop and Start
Conditions
4.7
Hold time after (Repeated) Start
Condition. After this period, the first clock
4.0
is generated.
t
SU:SDA
t
SU:SDO
t
HD:DAT
t
SU:DAT
t
TIMEOUT
t
LOW
t
HIGH
t
POR
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: t
going edge of the same channel.
Note 13: t
all outputs).
Note 14: t
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Repeated Start Condition setup time. 4.7
Stop Condition setup time 4.0
Data hold time 300 ns
Data setup time 250 ns
Detect clock low timeout 25 35 ms
Clock low period 4.7
Clock high period 4.0 50
Time in which a device must be
operational after power-on reset
, |t
− t
SKD1
PLHD
, Channel to Channel Skew, is the difference in propagation delay (t
SKD2
, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
SKD3
|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
PHLD
500 ms
or t
PLHD
) among all output channels in Broadcast mode (any one input to
PHLD
μs
μs
μs
μs
μs
μs
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DC Test Circuits
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
DS10CP154A
30073720
FIGURE 2. Differential Driver AC Test Circuit
30073722
FIGURE 3. Propagation Delay Timing Diagram
FIGURE 4. LVDS Output Transition Times
30073721
30073723
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Functional Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables. The DS10CP154A operates in two modes: Pin
DS10CP154A
Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).
When in the Pin Mode, the switch is fully configurable with
external pins. This is possible with two input select pins per
output (e.g. S00 and S01 pins for OUT0).
In the Pin Mode, feedback from the LOS (Loss Of Signal)
monitor circuitry is not available (there is not an LOS output
pin).
When in the SMBus Mode, the full switch configuration and
SoftPWDN can be programmed via the SMBus interface. In
addition, by using the SMBus interface, a user can obtain the
feedback from the built-in LOS circuitry which detects an open
inputs fault condition.
In the SMBus Mode, the S00 and S01 pins become SMBus
clock (SCL) input and data (SDA) input pins respectively; the
S10, S11, S21 and S21 pins become the User-Set SMBus
Slave Address input pins (ADDR0, 1, 2 and 3) while the S30
Switch Configuration Truth Tables
TABLE 1. Input Select Pins Configuration for the Output OUT0
S01 S00 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
and S31 pins become non-functional (tieing these two pins to
either H or L is recommended if the device will function only
in the SMBus mode).
In the SMBus Mode, the PWDN pin remains functional. How
this pin functions in each mode is detailed in the following
sections.
DS10CP154A OPERATION IN THE PIN MODE
Power Up
In the Pin Mode, when the power is applied to the device
power suppy pins, the DS10CP154A enters the Power Up
mode when the PWDN pin is set to logic H. When in the Power
Down mode (PWDN pin is set to logic L), all circuitry is shut
down except the minimum required circuitry for the LOS and
SMBus Slave operation.
Switch Configuration
In the Pin Mode, the DS10CP154A operates as a fully pinconfigurable crosspoint switch. The following truth tables illustrate how the swich can be configured with external pins.
TABLE 2. Input Select Pins Configuration for the Output OUT1
S11 S10 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
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TABLE 3. Input Select Pins Configuration for the Output OUT2
S21 S20 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31 S30 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
DS10CP154A
DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Management Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has
a 7-bit slave address. The three most significant bits of the
TABLE 5. DS10CP154A Slave Address
1 0 1 ADDR3 ADDR2 ADDR1 ADDR0
MSB LSB
This slave address configuration allows up to sixteen
DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A
SMBus into the START condition, then a byte (8 bits) is transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been received.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
slave address are hard wired inside the DS10CP154A and
are “101”. The four least significant bits of the address are
assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
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REGISTER DESCRIPTIONS
There are three data registers in the DS10CP154A accessible via the SMBus interface.
TABLE 6. DS10CP154A SMBus Data Registers
DS10CP154A
Address
(hex)
Name Access Description
0 Switch Configuration R/W Switch Configuration Register
3 Control R/W Powerdown, LOS Enable and Pin Control Register
4 LOS RO Loss Of Signal (LOS) Reporting Register
30073710
FIGURE 5. DS10CP154A Registers Block Diagram
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Switch Configuration Register
The Switch Configuration register is utilized to configure the switch. The following two tables show the Switch Configuration Register
mapping and associated truth table.
Bit Default Bit Name Access Description
D[1:0] 00 Input Select 0 R/W Selects which input is routed to the OUT0.
D[3:2] 00 Input Select 1 R/W Selects which input is routed to the OUT1.
D[5:4] 00 Input Select 2 R/W Selects which input is routed to the OUT2.
D[7:6] 00 Input Select 3 R/W Selects which input is routed to the OUT3.
TABLE 7. Switch Configuration Register Truth Table
D1 D0 Input Routed to the OUT0
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
The truth tables for the OUT1, OUT2, and OUT3 outputs are identical to this table.
The switch configuration logic has a SmartPWDN circuitry which automatically optimizes the device's power consumption based
on the switch configuration (i.e. It places unused I/O blocks and other unused circuitry in the power down state).
DS10CP154A
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Control Register
The Control register enables SoftPWDN
via the SMBus. The following table shows the register mapping.
Bit Default Bit Name Access Description
DS10CP154A
D[3:0] 1111 PWDNn R/W Writing a [0] to the bit D[n] will power down the output OUTn
D[4] x n/a R/W Undefined.
D[5] x n/a R/W Undefined.
D[6] 0 EN_LOS R/W Writing a [1] to the bit D[6] will enable the LOS circuitry and
D[7] 0 SoftPWDN R/W Writing a [0] to the bit D[7] will place the device into the power
PWDN SoftPWDN PWDNn DS25CP104 Power Mode
0 0 x Power Down Mode. In this mode, all circuitry is shut down except the
0
1
1
1
0
1
control, individual output power down (PWDNn) control and LOS Circuitry Enable control
when either the PWDN pin OR the Control Register bit D[7]
(SoftPWDN) is set to a high [1].
receivers on all four inputs. The SmartPWDN circuitry will not
disable any of the inputs nor any supporting LOS circuitry
depending on the switch configuration.
down mode. This pin is ORed together with the PWDN pin.
TABLE 8. DS10CP154A Power Modes Truth Table
minimum required circuitry for the LOS and SMBus Slave operation. The
SMBus circuitry allows enabling the LOS circuitry and receivers on all inputs
in this mode by setting the EN_LOS bit to a [1].
x
x
x
Power Up Mode. In this mode, the SmartPWDN circuitry will automatically
power down any unused I/O and logic blocks and other supporting circuitry
depending on the switch configuration.
An output will be enabled only when the SmartPWDN circuitry indicates that
that particular output is needed for the particular switch configuration and
the respective PWDNn bit has logic high [1].
An input will be enabled when the SmartPWDN circuitry indicates that that
particular input is needed for the particular switch configuration or the
EN_LOS bit is set to a [1].
LOS Register
The LOS register reports an open inputs fault condition for each of the inputs. The following table shows the register mapping.
Bit Default Bit Name Access Description
D[0] 0 LOS0 RO Reading a [0] from the bit D[0] indicates an open inputs fault condition on
the IN0. A [1] indicates presence of a valid signal.
D[1] 0 LOS1 RO Reading a [0] from the bit D[1] indicates an open inputs fault condition on
the IN1. A [1] indicates presence of a valid signal.
D[2] 0 LOS2 RO Reading a [0] from the bit D[2] indicates an open inputs fault condition on
the IN2. A [1] indicates presence of a valid signal.
D[3] 0 LOS3 RO Reading a [0] from the bit D[3] indicates an open inputs fault condition on
the IN3. A [1] indicates presence of a valid signal.
D[7:4] 0000 Reserved RO Reserved for future use. Returns undefined value when read.
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DS10CP154A
INPUT INTERFACING
The DS10CP154A accepts differential signals and allows
simple AC or DC coupling. With a wide common mode range,
the DS10CP154A can be DC-coupled with all common dif-
Typical LVDS Driver DC-Coupled Interface to DS10CP154A Input
ferential drivers (i.e. LVPECL, LVDS, CML). The following
three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10CP154A inputs
are internally terminated with a 100Ω resistor.
30073731
Typical CML Driver DC-Coupled Interface to DS10CP154A Input
Typical LVPECL Driver DC-Coupled Interface to DS10CP154A Input
30073732
30073733
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OUTPUT INTERFACING
The DS10CP154A outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
DS10CP154A
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Typical DS10CP154A Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
30073734
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Physical Dimensions inches (millimeters) unless otherwise noted
DS10CP154A
Order Number DS10CP154ATSQ
(See AN-1187 for PCB Design and Assembly Recommendations)
NS Package Number SQA40A
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Notes
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