National Semiconductor DM54161, DM74161, DM74163 Technical data

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DM54161/DM74161/DM74163
Synchronous 4-Bit Counters

General Description

These synchronous, presettable counters feature an inter­nal carry look-ahead for application in high-speed counting
designs. The 161 and 163 are 4-bit binary counters. The
carry output is decoded by means of a NOR gate, thus pre­venting spikes during the normal counting mode of opera­tion. Synchronous operation is provided by having all flip­flops clocked simultaneously so that the outputs change co­incident with each other when so instructed by the count­enable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.

These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the 161 is asynchronous; and a
low level at the clear input sets all four of the flip-flop out­puts low, regardless of the levels of clock, load, or enable
inputs. The clear function for the 163 is synchronous; and a
low level at the clear input sets all four of the flip-flop out­puts low after the next clock pulse, regardless of the levels
of the enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maxi­mum count desired can be accomplished with one

October 1992

external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter to all low out­puts. Low-to-high transitions at the clear input of the 163 are
also permissible, regardless of the logic levels on the clock,
enable, or load inputs.

The carry look-ahead circuitry provides for cascading coun­ters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both count­enable inputs (P and T) must be high to count, and input T is
fed forward to enable the ripple carry output. The ripple car­ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the Q
can be used to enable successive cascaded stages. High­to-low-level transitions at the enable P or T inputs of the 161
through 163 may occur, regardless of the logic level on the
clock.

output. This high-level overflow ripple carry pulse

A

Features

Y

Synchronously programmable

Y

Internal look-ahead for fast counting

Y

Carry output for n-bit cascading

Y

Synchronous counting

Y

Load control line

Y

Diode-clamped inputs

DM54161/DM74161/DM74163 Synchronous 4-Bit Counters

Connection Diagram

Dual-In-Line Package

Order Number DM54161J, DM54161W,

See NS Package Number J16A, N16E or W16A

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/6551

DM74161N or DM74163N

TL/F/6551– 1

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

DM54
DM74 0

Storage Temperature Range

b

55§Ctoa125§C

Ctoa70§C

§

b

65§Ctoa150§C

Recommended Operating Conditions

Symbol Parameter

V

V

V

I

OH

I

OL

f

CLK

t

W

t

SU

t

H

T

CC

IH

IL

A

Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

High Level Input Voltage 2 2 V

Low Level Input Voltage 0.8 0.8 V

High Level Output Current

Low Level Output Current 16 16 mA

Clock Frequency (Note 6) 0 25 0 25 MHz

Pulse Width Clock 25 25
(Note 6)

Setup Time Data 20 20
(Note 6)

Hold Time (Note 6) 0 0 ns

Free Air Operating Temperature

Clear 20 20

Enable P 34 34

Load 25 25

Clear (Note 5) 20 20

Min Nom Max Min Nom Max

b

55 125 0 70

The ‘‘Absolute Maximum Ratings’’ are those values

Note:

beyond which the safety of the device cannot be guaran­teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.

DM54161 DM74161 and 163

b

0.8

b

0.8 mA

Units

ns

ns

C

§

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min

e

V

I

V

OH

V

OL

I

I

I

IH

I

IL

Input Clamp Voltage V

High Level Output V
Voltage V

Low Level Output V
Voltage V

Input Current@Max V
Input Voltage

High Level Input V
Current

Low Level Input V
Current

CC

CC

e

IL

CC

e

IH

CC

CC

e

V

I

CC

e

V

I

eb

Min, I

e

Min, I

Max, V

e

Min, I

Min, V

e

Max, V

e

Max Enable T 80

I

OH

OL

IL

12 mA

e

Max

e

Min

IH

e

Max

e

Max

e

5.5V

I

2.4 3.4 V

2.4V Clock 80 mA

Others 40

e

Max Enable T

0.4V Clock

Others

2

Typ

(Note 1)

Max Units

b

1.5 V

0.2 0.4 V

1mA

b

3.2

b

3.2 mA

b

1.6

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted) (Continued)

L

e

400X,C

Typ

(Note 1)

L

e

Symbol Parameter Conditions Min

I

OS

I

CCH

I

CCL

Note 1: All typicals are at V

Note 2: Not more than one output should be shorted at a time.

Note 3: I

CCH

Note 4: I

CCL

Note 5: Applies to 163 which has synchronous clear inputs.

Note 6: T

A

Short Circuit V
Output Current (Note 2)

Supply Current V
with Outputs High (Note 3)

Supply Current V
with Outputs Low (Note 4)

e

e

5V, T

5V.

25§C.

A

CC

is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open.

is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open.

e

25§C and V

e

CC

Switching Characteristics at V

Symbol Parameter

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

Note 7: Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163.

Maximum Clock
Frequency

Propagation Delay Time Clock to
Low to High Level Output Ripple Carry

Propagation Delay Time Clock to
High to Low Level Output Ripple Carry

Propagation Delay Time Clock
Low to High Level Output (Load High) to Q

Propagation Delay Time Clock
High to Low Level Output (Load High) to Q

Propagation Delay Time Clock
Low to High Level Output (Load Low) to Q

Propagation Delay Time Clock
High to Low Level Output (Load Low) to Q

Propagation Delay Time Enable T to
Low to High Level Output Ripple Carry

Propagation Delay Time Enable T to
High to Low Level Output Ripple Carry

Propagation Delay Time Clear (Note 7)
High to Low Level Output to Q

e

Max DM54

CC

DM74

e

Max DM54 85

CC

DM74 59 94

e

Max DM54 91

CC

DM74 63 101

CC

e

5V and T

e

25§C (See Section 1 for Test Waveforms and Output Load)

A

From (Input)

To (Output)

b

20

b

20

R

Min Max

25 MHz

Max Units

b

57

b

57

15 pF

35 ns

35 ns

20 ns

23 ns

25 ns

29 ns

16 ns

16 ns

38 ns

mA

mA

mA

Units

3