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TL/F/6638
DM54L95 4-Bit Parallel Access Shift Registers
June 1989
DM54L95 4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs, parallel output, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction Q
A
toward QD)
Shift left (the direction Q
D
toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock 2 when the
mode control is high by connecting the output of each flipflop to the parallel input of the previous flip-flop (Q
D
to input
C, etc.) and serial data is entered at input D. The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source.
Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensure that register contents are protected.
Features
Y
Typical maximum clock frequency 14 MHz
Y
Typical power dissipation mW
Connection Diagram
Dual-In-Line Package
TL/F/6638– 1
Order Number DM54L95J
or DM54L95W
See NS Package Number
J14A or W14B
Function Table
Inputs Outputs
Mode
Clocks
Serial
Parallel
Q
AQBQCQD
Control
2 (L) 1 (R) A B C D
HHXXXXXXQAOQBOQCOQ
DO
H
v
XXabcdabcd
H
v
XXQ
B
²
Q
C
²
Q
D
²
dQBnQCnQ
Dn
d
LLHXXXXXQ
AOQBOQCOQDO
LX
v
HXXXXHQAnQBnQ
Cn
LX
v
LXXXXLQAnQBnQ
Cn
u
LL XXXXXQAOQBnQCOQ
DO
v
LL XXXXXQAOQBOQCOQ
DO
v
LH X XXXXQAOQBOQCOQ
DO
u
HL X XXXXQAOQBOQCOQ
DO
u
HH X XXXXQAOQBOQCOQ
DO
²
Shifting left requires external connection of QBto A, QCto B, QDto C. Serial data is entered at input D.
H
e
High Level (Steady State), LeLow Level (Steady State), XeDon’t Care (Any input, including transitions).
v
e
Transition from high to low level.
u
e
Transition from low to high level.
a, b, c, d,
e
The level of steady state input at inputs A, B, C, or D, respectively.
Q
AO,QBO,QCO,QDO
e
The level of QA,QB,QC,orQD, respectively, before the indicated steady state input conditions were established.
Q
An,QBn,QCn,QDn
e
The level of QA,QB,QC,orQD, respectively, before the most recentvtransition of the clock.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Page 2
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 8V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54L
b
55§Ctoa125§C
Storage Temperature Range
b
65§Ctoa150§C
Note:
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol Parameter
DM54L95
Units
Min Nom Max
V
CC
Supply Voltage 4.5 5 5.5 V
V
IH
High Level Input Voltage 2 V
V
IL
Low Level Input Voltage 0.7 V
I
OH
High Level Output Current
b
0.2 mA
I
OL
Low Level Output Current 2 mA
f
CLK
Clock Frequency (Note 1) 0 6 MHz
t
W(CLK)
Pulse Width of Clock (Note 1) 90 ns
t
SU
Data Setup Time (Note 1) 50 ns
t
EN
Time to Enable Clock 1 120 ns
Clock (Note 1)
Clock 2 100 ns
t
H
Data Hold Time (Note 1) 0 ns
t
IN
Time to Inhibit Clock 1 or Clock 2 (Note 1) 0 ns
T
A
Free Air Operating Temperature
b
55 125
§
C
Note 1: T
A
e
25§C and V
CC
e
5V.
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Conditions Min
Typ
Max Units
(Note 1)
V
OH
High Level Output V
CC
e
Min, I
OH
e
Max
2.4 3.1 V
Voltage V
IL
e
Max, V
IH
e
Min
V
OL
Low Level Output V
CC
e
Min, I
OL
e
Max
0.13 0.3
V
Voltage V
IL
e
Max, V
IH
e
Min
I
I
Input Current@Max V
CC
e
Max Mode 0.2
mA
Input Voltage V
I
e
5.5V
Others 0.1
I
IH
High Level Input V
CC
e
Max Mode 20
mA
Current V
I
e
2.4V
Others 10
I
IL
Low Level Input V
CC
e
Max Mode
b
0.36
mA
Current V
I
e
0.3V
Others
b
0.18
I
OS
Short Circuit V
CC
e
Max
b
3
b
15 mA
Output Current (Note 2)
I
CC
Supply Current V
CC
e
Max (Note 3) 4.8 8 mA
Note 1: All typicals are at V
CC
e
5V, TA25§C
Note 2: Not more than one output should be shorted at a time.
Note 3: I
CC
is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5V; and a momentary 3V, then ground, applied to
both clock inputs.
2
Page 3
Switching Characteristics at V
CC
e
5V and TA25§C (See Section 1 for Test Waveforms and Output Load)
Symbol Parameter
From (Input)
R
L
e
4X,C
L
e
50 pF
Units
To (Output)
Min Max
f
MAX
Maximum Clock Frequency 6 MHz
t
PLH
Propagation Delay Time Clock to
90 ns
Low to High Level Output Output
t
PHL
Propagation Delay Time Clock to
90 ns
High to Low Level Output Output
Logic Diagram
TL/F/6638– 2
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54L95J
NS Package Number J14A
3
Page 4
DM54L95 4-Bit Parallel Access Shift Registers
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)
Order Number DM54L95W
NS Package Number W14B
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