National Semiconductor CP3BT26 User Manual

PRELIMINARY

MAY 2004

CP3BT26 Reprogrammable Connectivity Processor with
Bluetooth®, USB, and CAN Interfaces

1.0 General Description

The CP3BT26 connectivity processor combines high perfor­mance with the massive integration needed for embedded
Bluetooth applications. A powerful RISC core with on-chip
SRAM and Flash memory provides high computing band­width, hardware communications peripherals provide high­I/O bandwidth, and an external bus provides system ex­pandability.

On-chip communications peripherals include: Bluetooth
Lower Link Controller, Universal Serial Bus (USB) 1.1 node,
CAN, Microwire/Plus, SPI, ACCESS.bus, quad UART, 12-bit
A/D converter, and Advanced Audio Interface (AAI). Addi­tional on-chip peripherals include Random Number Gener­ator (RNG), DMA controller, CVSD/PCM conversion
module, Timing and Watchdog Unit, Versatile Timer Unit,
Multi-Function Timer, and Multi-Input Wake-Up (MIWU)
unit.

Bluetooth hand-held devices can be both smaller and lower
in cost for maximum consumer appeal. The low voltage and

advanced power-saving modes achieve new design points
in the trade-off between battery size and operating time for
handheld and portable applications.

In addition to providing the features needed for the next gen­eration of embedded Bluetooth products, the CP3BT26 is
backed up by the software resources designers need for
rapid time-to-market, including an operating system, Blue­tooth protocol stack implementation, peripheral drivers, ref­erence designs, and an integrated development
environment. Combined with a Bluetooth radio transceiver
such as National’s LMX5252, the CP3BT26 provides a com­plete Bluetooth system solution.

National Semiconductor offers a complete and industry­proven application development environment for CP3BT26
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Applica­tion Software.

CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces

Block Diagram

Clock Generator

12 MHz and 32 kHz

Oscillator

CR16C

CPU Core

Bus

Interface

Unit

GPIO

PLL and Clock

256K Bytes

Flash
Program
Memory

DMA

Controller

Audio

Interface

Generator

8K Bytes

Flash

Data

Peripheral

Bus

Controller

Microwiire/

SPI

Power-on-Reset

32K Bytes

Static
RAM

Interrupt

Control

Unit

Quad UART

CAN 2.0B
Controller

CPU Core Bus

CVSD/PCM

Peripheral Bus

ACCESS

.bus

Converter

Timer Unit

Versatile

RF Interface

Protocol

Core

Powe r

Manage-

ment

Muti-Func-

tion Timer

Bluetooth Lower

Link Controller

1K Byte

Sequencer RAM

4.5K Bytes
Data RAM

Timing and

Watchdog

Unit

Multi-Input

Wake-Up

Serial

Debug

Interface

Random

Number

Generator

8-Channel

12-bit ADC

USB

Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
TRI-STATE is a registered trademark of National Semiconductor Corporation.

©2004 National Semiconductor Corporation www.national.com

DS202

1.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

CP3BT26

3.1 CR16C CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.4 Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.5 Interrupt Control Unit (ICU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.6 Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.7 Bluetooth LLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.8 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.9 CAN Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.10 Quad UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.11 Advanced Audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.12 CVSD/PCM Conversion Module. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.13 12-bit Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.14 Random Number Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.15 Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.16 ACCESS.bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.17 Multi-Function Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.18 Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.19 Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.20 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.21 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.22 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.23 Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.24 Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.0 CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Dedicated Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Processor Status Register (PSR). . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 Configuration Register (CFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.7 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Operating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.2 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4 BIU Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.5 Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.0 System Configuration Registers . . . . . . . . . . . . . . . 29

7.1 Module Configuration Register (MCFG) . . . . . . . . . . . . . . . . . . . . 29

7.2 Module Status Register (MSTAT). . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3 Software Reset Register (SWRESET) . . . . . . . . . . . . . . . . . . . . . 30

8.0 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.2 Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.3 Flash Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.4 Information Block Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.5 Flash Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . 35

9.0 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.1 Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.2 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.4 Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.5 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.6 DMA Controller Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.4 Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.5 Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.0 Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 51

11.1 External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.2 Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.3 Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.4 PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.5 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.6 Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.7 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.8 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.9 Clock and Reset Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.0 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . 56

12.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

12.2 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

12.3 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.5 Hardware Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.6 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.7 Switching Between Power Modes . . . . . . . . . . . . . . . . . . . . . . . . 59

13.0 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 61

13.1 Multi-Input Wake-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

13.2 Programming Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

14.0 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14.1 Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

14.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

15.0 Bluetooth Controller . . . . . . . . . . . . . . . . . . . . . . . . . 72

15.1 RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

15.2 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

15.3 LMX5251 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 76

15.4 LMX5252 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 76

15.5 Bluetooth Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

15.6 Bluetooth Global Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

15.7 Bluetooth Sequencer RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

15.8 Bluetooth Shared Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

16.0 12-Bit Analog to Digital Converter . . . . . . . . . . . . . . 79

16.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

16.2 Touchscreen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table of Contents

16.3 ADC Operation in Power-Saving Modes . . . . . . . . . . . . . . . . . . . 83

16.4 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

16.5 ADC Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

17.0 Random Number Generator (RNG). . . . . . . . . . . . . . 88

17.1 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

17.2 Random Number Generator Register Set . . . . . . . . . . . . . . . . . . 89

18.0 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

18.1 Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

18.2 Endpoint Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

18.3 USB Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

18.4 Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

19.0 CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

19.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

19.2 Basic CAN Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

19.3 Message Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

19.4 Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

19.5 Receive Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

19.6 Transmit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

19.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

19.8 Time Stamp Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

19.9 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

19.10 CAN Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

19.11 System Start-Up and Multi-Input Wake-Up. . . . . . . . . . . . . . . . . 140

19.12 Usage Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

20.0 Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . 143

20.1 Audio Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

20.2 Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

20.3 Bit Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

20.4 Frame Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

20.5 Audio Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

20.6 Communication Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

20.7 Audio Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

21.0 CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 158

21.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

21.2 PCM Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

21.3 CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

21.4 PCM to CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

21.5 CVSD to PCM Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

21.6 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

21.7 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

21.8 Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

21.9 CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . . . . . . . . 160

22.0 UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

22.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

22.2 UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

22.3 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

22.4 Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

23.0 Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 175

23.1 Microwire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

23.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

23.3 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

23.4 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

23.5 Microwire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

24.0 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 181

24.1 ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

24.2 ACB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

24.3 ACCESS.bus Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . 185

24.4 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

25.0 Timing and Watchdog Module . . . . . . . . . . . . . . . . 192

25.1 TWM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

25.2 Timer T0 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

25.3 Watchdog Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

25.4 TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

25.5 Watchdog Programming Procedure . . . . . . . . . . . . . . . . . . . . . . 195

26.0 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 196

26.1 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

26.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

26.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

26.4 Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

26.5 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

27.0 Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 206

27.1 VTU Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

27.2 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

28.0 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

29.0 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 230

30.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 243

30.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

30.2 DC Electrical Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

30.3 USB Transceiver Electrical Characteristics . . . . . . . . . . . . . . . . 245

30.4 ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 245

30.5 Flash Memory On-Chip Programming . . . . . . . . . . . . . . . . . . . . 246

30.6 Output Signal Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

30.7 Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

30.8 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

30.9 I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

30.10 Advanced Audio Interface (AAI) Timing . . . . . . . . . . . . . . . . . . . 251

30.11 Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

30.12 ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

30.13 USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

30.14 Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . . . . . . . . 261

30.15 Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . . . . . . . . 262

30.16 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

31.0 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

31.1 LQFP-128 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

31.2 LQFP-144 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

32.0 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

33.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 277

www.national.com 2

2.0 Features

CPU Features

 Fully static RISC processor core, capable of operating

from 0 to 24 MHz with zero wait/hold states

 Minimum 41.7 ns instruction cycle time with a 24-MHz in-

ternal clock frequency, based on a 12-MHz external input

 47 independently vectored peripheral interrupts

On-Chip Memory

 256K bytes reprogrammable Flash program memory
 8K bytes Flash data memory
 32K bytes of static RAM data memory
 Addresses up to 12M bytes of external memory

Broad Range of Hardware Communications Peripherals

 Bluetooth Lower Link Controller (LLC) including a shared

4.5K byte Bluetooth RAM and 1K byte Bluetooth Se­quencer RAM

 Universal Serial Bus (USB) 1.1 full-speed node
 ACCESS.bus serial bus (compatible with Philips I
 CAN interface with 15 message buffers conforming to

CAN specification 2.0B active

 8/16-bit SPI, Microwire/Plus serial interface
 Four-channel Universal Asynchronous Receiver/Trans-

mitter (UART), one channel has USART capability

 Advanced Audio Interface (AAI) to connect to external 8/

13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)

 CVSD/PCM converter supporting one bidirectional audio

connection

General-Purpose Hardware Peripherals

 12-bit A/D Converter (ADC)
 Dual 16-bit Multi-Function Timer (MFT)
 Versatile Timer Unit with four subsystems (VTU)
 Four-channel DMA controller
 Timing and Watchdog Unit
 Random Number Generator peripheral

Extensive Power and Clock Management Support

 On-chip Phase Locked Loop
 Support for multiple clock options
 Dual clock and reset

2

C bus)

CP3BT26

 Power-down modes

Flexible I/O

 Up to 54 general-purpose I/O pins (shared with on-chip

peripheral I/O)

 Programmable I/O pin characteristics: TRI-STATE out-

put, push-pull output, weak pull-up input, high-imped­ance input

 Schmitt triggers on general-purpose inputs
 Multi-Input Wake-Up (MIWU) capability

Power Supply

 I/O port operation at 2.5V to 3.3V
 Core logic operation at 2.5V
 On-chip power-on reset

Temperature Range

 -40°C to +85°C (Industrial)

Packages

 LQFP-128, LQFP-144

Complete Development Environment

 Pre-integrated hardware and software support for rapid

prototyping and production

 Integrated environment
 Project manager
 Multi-file C source editor
 High-level C source debugger
 Comprehensive, integrated, one-stop technical support

Bluetooth Protocol Stack

 Applications can interface to the high-level protocols or

directly to the low-level Host Controller Interface (HCI)

 Transport layer support allows HCI command-based in-

terface over UART port

 Baseband (Link Controller) hardware minimizes the

bandwidth demand on the CPU

 Link Manager (LM)
 Logical Link Control and Adaptation Protocol (L2CAP)
 Service Discovery Protocol (SDP)
 RFCOMM Serial Port Emulation Protocol
 All packet types, piconet, and scatternet functionality

supported

CP3BT26 Connectivity Processor Selection Guide

NSID

CP3BT26G18NEP 24 -40° to +85°C 256 8 32 0 54 LQFP-128

CP3BT26G18NEPNOPB 24 -40° to +85°C 256 8 32 0 54 LQFP-128

CP3BT26G18NEPX 24 -40° to +85°C 256 8 32 0 54 LQFP-128

CP3BT26G18NEPXNOPB 24 -40° to +85°C 256 8 32 0 54 LQFP-128

CP3BT26Y98NEP 24 -40° to +85°C 256 8 32 23 48 LQFP-144

CP3BT26Y98NEPNOPB 24 -40° to +85°C 256 8 32 23 48 LQFP-144

CP3BT26Y98NEPX 24 -40° to +85°C 256 8 32 23 48 LQFP-144

CP3BT26Y98NEPXNOPB 24 -40° to +85°C 256 8 32 23 48 LQFP-144

NEP - Erased part (Bluetooth device address in Information Block 1); X - Tape and reel; NOPB - No lead solder

Speed

(MHz)

Temp. Range

Program

Flash

(Kbytes)

Data

Flash

(Kbytes)

SRAM

(Kbytes)

External
Address

Lines

I/Os

Package

Type

3 www.national.com

3.0 Device Overview

The CP3BT26 connectivity processor is a complete micro­computer with all system timing, interrupt logic, program

CP3BT26

memory, data memory, and I/O ports included on-chip, mak­ing it well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip com­ponents of the CP3BT26 devices.

3.1 CR16C CPU CORE

The CP3BT26 device implements the CR16C CPU core
module. The high performance of the CPU core results from
the implementation of a pipelined architecture with a two­bytes-per-cycle pipelined system bus. As a result, the CPU
can support a peak execution rate of one instruction per
clock cycle.

For more information, please refer to the CR16C Program­mer’s Reference Manual (document number 424521772­101, which may be downloaded from National’s web site at
http://www.national.com).

3.2 MEMORY

The CP3BT26 devices support a uniform linear address
space of up to 16 megabytes. Three types of on-chip mem­ory occupy specific regions within this address space, along
with any external memory:

 256K bytes of Flash program memory
 8K bytes of Flash data memory
 32K bytes of static RAM
 Up to 12M bytes of external memory (144-pin devices)

The 256K bytes of Flash program memory are used to store
the application program, Bluetooth protocol stack, and real­time operating system. The Flash memory has security fea­tures to prevent unintentional programming and to prevent
unauthorized access to the program code. This memory
can be programmed with an external programming unit or
with the device installed in the application system (in-sys­tem programming).

The 8K bytes of Flash data memory are used for non-vola­tile storage of data entered by the end-user, such as config­uration settings.

The 32K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, de­pending on the instruction executed by the CPU.

Up to 12M bytes of external memory can be added on an
external bus. The external bus is only available on devices
in 144-pin packages.

For Flash program and data memory, the device internally
generates the necessary voltages for programming. No ad­ditional power supply is required.

3.3 INPUT/OUTPUT PORTS

The device has up to 54 software-configurable I/O pins, or­ganized into seven ports called Port B, Port C, Port E, Port
G, Port H, Port I, and Port J. Each pin can be configured to
operate as a general-purpose input or general-purpose out­put. In addition, many I/O pins can be configured to operate
as inputs or outputs for on-chip peripheral modules such as
the UART, timers, or Microwire/SPI interface.

The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push­pull output, weak pull-up input, or high-impedance input.

3.4 BUS INTERFACE UNIT

The Bus Interface Unit (BIU) controls access to internal/ex­ternal memory and I/O. It determines the configured param­eters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.

The BIU uses a set of control registers to determine how
many wait states and hold states are used when accessing
Flash program memory and the I/O area. At start-up, the
configuration registers are set for slowest possible memory
access. To achieve fastest possible program execution, ap­propriate values must be programmed. These settings vary
with the clock frequency and the type of off-chip device be­ing accessed.

3.5 INTERRUPT CONTROL UNIT (ICU)

The ICU receives interrupt requests from internal and exter­nal sources and generates interrupts to the CPU. An inter­rupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execu­tion continues with the next instruction in the program fol­lowing the point of interruption.

Interrupts from the timers, UARTs, Microwire/SPI interface,
and Multi-Input Wake-Up, are all maskable interrupts; they
can be enabled or disabled by software. There are 47
maskable interrupts, assigned to 47 linear priority levels.

The highest-priority interrupt is the Non-Maskable Interrupt

), which is generated by a signal received on the NMI

(NMI
input pin.

3.6 MULTI-INPUT WAKE-UP

The two Multi-Input Wake-Up (MIWU) modules can be used
for two purposes: to provide inputs for waking up (exiting)
from the Halt, Idle, or Power Save mode, and to provide gen­eral-purpose edge-triggered maskable interrupts to the lev­el-sensitive interrupt control unit (ICU) inputs. Each 16­channel module generates four programmable interrupts to
the ICU, for a total of 8 ICU inputs generated from 32 MIWU
inputs. Channels can be individually enabled or disabled,
and programmed to respond to positive or negative edges.

www.national.com 4

3.7 BLUETOOTH LLC

The integrated hardware Bluetooth Lower Link Controller
(LLC) complies to the Bluetooth Specification Version 1.1
and integrates the following functions:

 4.5K-byte dedicated Bluetooth Data RAM
 1K-byte dedicated Bluetooth Sequencer RAM
 Support of all Bluetooth 1.1 packet types
 Support for fast frequency hopping of 1600 hops/s
 Access code correlation and slot timing recovery circuit
 Power Management Control Logic
 BlueRF-compatible interface (mode 2/3) to connect with

National’s LMX5252 and other RF transceiver chips

3.8 USB

The CR16 USB node is a Universal Serial Bus (USB) Node
controller compatible with USB Specification 1.1. It inte­grates the required USB transceiver, the Serial Interface En­gine (SIE), and USB endpoint FIFOs. A total of seven
endpoint pipes are supported: one bidirectional pipe for the
mandatory control EP0 and an additional six pipes for unidi­rectional endpoints to support USB interrupt, bulk, and iso­chronous data transfers.

3.9 CAN INTERFACE

The CAN module contains a Full CAN 2.0B class, CAN se­rial bus interface for applications that require a high-speed
(up to 1 Mbits per second) or a low-speed interface with
CAN bus master capability. The data transfer between CAN
and the CPU is established by 15 memory-mapped mes­sage buffers, which can be individually configured as re­ceive or transmit buffers. An incoming message is filtered by
two masks, one for the first 14 message buffers and another
one for the 15th message buffer to provide a basic CAN
path. A priority decoder allows any buffer to have the high­est or lowest transmit priority. Remote transmission re­quests can be processed automatically by automatic
reconfiguration to a receiver after transmission or by auto­mated transmit scheduling upon reception. In addition, a
time stamp counter (16-bits wide) is provided to support
real-time applications.

The CAN module is a fast core bus peripheral, which allows
single-cycle byte or word read/write access. A set of diag­nostic features (such as loopback, listen only, and error
identification) support the development with the CAN mod­ule and provide a sophisticated error management tool.

The CAN receiver can trigger a wake-up condition out of the
low-power modes through the Multi-Input Wake-Up module.

3.10 QUAD UART

Four UART modules support a wide range of programmable
baud rates and data formats, parity generation, and several
error detection schemes. The baud rate is generated on­chip, under software control. One UART channel supports
hardware flow control, DMA, and USART capability (syn­chronous mode).

The UARTs offer a wake-up condition from the low-power
modes using the Multi-Input Wake-Up module.

CP3BT26

3.11 ADVANCED AUDIO INTERFACE

The audio interface provides a serial synchronous, full-du­plex interface to CODECs and similar serial devices. Trans­mit and receive paths operate asynchronously with respect
to each other. Each path uses three signals for communica­tion: shift clock, frame synchronization, and data.

When the receiver and transmitter use separate shift clocks
and frame sync signals, the interface operates in its asyn­chronous mode. Alternatively, the transmit and receive path
can share the same shift clock and frame sync signals for
synchronous mode operation.

3.12 CVSD/PCM CONVERSION MODULE

The CVSD/PCM module performs conversion between
CVSD data and PCM data, in which the CVSD encoding is
as defined in the Bluetooth specification and the PCM data
can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.

3.13 12-BIT ANALOG TO DIGITAL
CONVERTER

This device contains an 8-channel, multiplexed input, suc­cessive approximation, 12-bit Analog-to-Digital Converter. It
supports both Single Ended and Differential modes of oper­ation.

The integrated 12-bit ADC provides the following features:

 8-channel, multiplexed input
 4 differential channels
 Single-ended and differential external filtering capability
 12-bit resolution; 11-bit accuracy
 15-microsecond conversion time
 Support for 4-wire touchscreen applications
 External start trigger
 Programmable start delay after start trigger
 Poll or interrupt on done

The ADC is compatible with 4-wire resistive touchscreen
applications and is intended to provide the resolution neces­sary to support handwriting recognition. Low-ohmic touch­screen drivers are provided internally on the ADC[3:0] pins.
Pendown detection is also provided.

The ADC provides several options for the voltage reference
source. The positive reference can be ADVCC (internal),
VREFP, ADC0, or ADC3. The negative reference can be
ADVCC (internal), ADC1, or ADC2.

Two specific analog channel selection modes are support­ed. These are as follows:

 Allow any specific channel to be selected at one time.

The A/D Converter performs the specific conversion re­quested and stops.

 Allow any differential channel pair to be selected at one

time. The A/D Converter performs the specific differential
conversion requested and stops.

In both Single-Ended and Differential modes, there is the
capability to connect the analog multiplexer output and A/D
converter input to external pins. This provides the ability to
externally connect a common filter/signal conditioning cir­cuit for the A/D Converter.

5 www.national.com

3.14 RANDOM NUMBER GENERATOR

RNG peripheral for use in Trusted Computer Peripheral Ap­plications (TCPA) to improve the authenticity, integrity, and
privacy of Internet-based communication and commerce.

CP3BT26

3.15 MICROWIRE/SPI

The Microwire/SPI (MWSPI) interface module supports syn­chronous serial communications with other devices that
conform to Microwire or Serial Peripheral Interface (SPI)
specifications. It supports 8-bit and 16-bit data transfers.

The Microwire interface allows several devices to communi­cate over a single system consisting of four wires: serial in,
serial out, shift clock, and slave enable. At any given time,
the Microwire interface operates as the master or a slave.
The Microwire interface supports the full set of slave select
for multi-slave implementation.

In master mode, the shift clock is generated on-chip under
software control. In slave mode, a wake-up out of a low­power mode may be triggered using the Multi-Input Wake­Up module.

3.16 ACCESS.BUS INTERFACE

The ACCESS.bus interface module (ACB) is a two-wire se­rial interface compatible with the ACCESS.bus physical lay­er. It is also compatible with Intel’s System Management
Bus (SMBus) and Philips’ I
configured as a bus master or slave, and it can maintain bi­directional communications with both multiple master and
slave devices.

The ACCESS.bus receiver can trigger a wake-up condition
out of the low-power modes through the Multi-Input Wake­Up module.

2

C bus. The ACB module can be

3.17 MULTI-FUNCTION TIMER

The Multi-Function Timer (MFT) module contains a pair of
16-bit timer/counter registers. Each timer/counter unit can
be configured to operate in any of the following modes:

— Processor-Independent Pulse Width Modulation

(PWM) mode: Generates pulses of a specified width
and duty cycle and provides a general-purpose timer/
counter.

— Dual Input Capture mode: Measures the elapsed time

between occurrences of external event and provides
a general-purpose timer/counter.

— Dual Independent Timer mode: Generates system

timing signals or counts occurrences of external
events.

— Single Input Capture and Single Timer mode: Pro-

vides one external event counter and one system tim­er.

3.18 TIMING AND WATCHDOG MODULE

The Timing and Watchdog Module (TWM) contains a Real­Time timer and a Watchdog unit. The Real-Time Clock Tim­ing function can be used to generate periodic real-time
based system interrupts. The timer output is one of 16 in­puts to the Multi-Input Wake-Up module which can be used
to exit from a power-saving mode. The Watchdog unit is de­signed to detect the application program getting stuck in an
infinite loop resulting in loss of program control or “runaway”
programs. When the watchdog triggers, it resets the device.
The TWM is clocked by the low-speed System Clock.

3.19 VERSATILE TIMER UNIT

The Versatile Timer Unit (VTU) module contains four inde­pendent timer subsystems, each operating in either dual 8­bit PWM configuration, as a single 16-bit PWM timer, or a
16-bit counter with two input capture channels. Each of the
four timer subsystems offer an 8-bit clock prescaler to ac­commodate a wide range of frequencies.

3.20 TRIPLE CLOCK AND RESET

The Triple Clock and Reset module generates a high-speed
main System Clock from an external crystal network. It also
provides the main system reset signal and a power-on reset
function.

This module generates a slow System Clock (32.768 kHz)
from an optional external crystal network. The Slow Clock is
used for operating the device in a low-power mode. The

32.768 kHz external crystal network is optional, because

the low speed System Clock can be derived from the high­speed clock by a prescaler. Also, two independent clocks di­vided down from the high speed clock are available on out­put pins.

The Triple Clock and Reset module provides the clock sig­nals required for the operation of the various CP3BT26 on­chip modules. From external crystal networks, it generates
the Main Clock, which can be scaled up to 24 MHz from an
external 12 MHz input clock, and a 32.768 kHz secondary
System Clock. The 12 MHz external clock is primarily used
as the reference frequency for the on-chip PLL. The clock
for modules which require a fixed clock rate (e.g. the Blue­tooth LLC and the CVSD/PCM transcoder) is also generat­ed through prescalers from the 12 MHz clock. The PLL may
be used to drive the high-speed System Clock through a
prescaler. Alternatively, the high speed System Clock can
be derived directly from the 12 MHz Main Clock.

In addition, this module generates the device reset by using
reset input signals coming from an external reset and vari­ous on-chip modules.

www.national.com 6

3.21 POWER MANAGEMENT

The Power Management Module (PMM) improves the effi­ciency of the device by changing the operating mode and
power consumption to match the required level of activity.

The device can operate in any of four power modes:

— Active: The device operates at full speed using the

high-frequency clock. All device functions are fully op­erational.

— Power Save: The device operates at reduced speed

using the Slow Clock. The CPU and some modules
can continue to operate at this low speed.

— Idle: The device is inactive except for the Power Man-

agement Module and Timing and Watchdog Module,
which continue to operate using the Slow Clock.

— Halt: The device is inactive but still retains its internal

state (RAM and register contents).

3.22 DMA CONTROLLER

The Direct Memory Access Controller (DMAC) can speed
up data transfer between memory and I/O devices or be­tween two memories, relative to data transfers performed di­rectly by the CPU. A method called cycle-stealing allows the
CPU and the DMAC to share the CPU bus efficiently. The
DMAC implements four independent DMA channels. DMA
requests from a primary and a secondary source are recog­nized for each DMA channel, as well as a software DMA re­quest issued directly by the CPU. Table 1 shows the DMA
channel assignment on the CP3BT26 architecture. The fol­lowing on-chip modules can assert a DMA request to the
DMAC:

• CR16C (Software DMA request)

•USB

• USART

• Advanced Audio Interface

• CVSD/PCM Converter

Table 1 shows how the four DMA channels are assigned
to the modules listed above.

CP3BT26

In the normal mode of operation, the interface only transfers
one word at a periodic rate. In the network mode, the inter­face transfers multiple words at a periodic rate. The periodic
rate is also called a data frame and each word within one
frame is called a slot. The beginning of each new data frame
is marked by the frame sync signal.

3.23 SERIAL DEBUG INTERFACE

The Serial Debug Interface module (SDI module) provides
a JTAG-based serial link to an external debugger, for exam­ple running on a PC. In addition, the SDI module integrates
an on-chip debug module, which allows the user to set up to
eight hardware breakpoints on instruction execution and
data transfer. The SDI module can act as a CPU bus master
to access all memory mapped resources, such as RAM and
peripherals. Therefore it also allows for fast program code
download into the on-chip Flash program memory using the
JTAG interface.

3.24 DEVELOPMENT SUPPORT

In addition to providing the features needed for the next gen­eration of embedded Bluetooth products, the CP3BT26 de­vices are backed up by the software resources designers
need for rapid product development, including an operating
system, Bluetooth protocol stack implementation, peripher­al drivers, reference designs, and an integrated develop­ment environment. Combined with National’s LMX5251
Bluetooth radio transceiver, the CP3BT26 devices provide a
total Bluetooth system solution.

National Semiconductor offers a complete and industry­proven application development environment for CP3BT26
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth Protocol Stack, and Applica­tion Software. See your National Semiconductor sales rep­resentative for current information on availability and
features of emulation equipment and evaluation boards.

Table 1 DMA Channel Assignment

Channel

0

1

2

3

The interface can handle data words of either 8- or 16-bit
length and data frames can consist of up to four slots.

Primary/

Secondary

Primary USB Read/Write

Secondary UART0 Read

Primary UART0 Write

Secondary Unused N/A

Primary AAI Read

Secondary CVSD/PCM Read

Primary AAI Write

Secondary CVSD/PCM Write

Peripheral Transaction

7 www.national.com

4.0 Signal Descriptions

U

U

U

C

12 MHz Crystal

or Ext. Clock

CP3BT26

32.768 kHz
Crystal

Supply

Chip Reset

JTAG I/F to

Debugger/

Programmer

Selection

RF/MFT

Touchscreen

ACCESS.bus

AN Bus/MIWU

CAN Bus

Powe r

Mode

ADC/

USB

X1CKI/BBCLK
X1CKO

X2CKI
X2CKO

AVC C

1

AGND

1

ADVCC

1

ADGND

1

VCC

6

GND

6

IOVCC

15

IOGND

14

RESET

TMS
TDI
TDO

TCK
RDY

ENV0
ENV1
ENV2

PG7/BTSEQ3/TA

ADC0/TSX+
ADC1/TSY+
ADC2/TSX­ADC3/TSY­ADC4/MUXOUT0
ADC5/MUXOUT1
ADC6
ADC7/ADCIN
PJ7/ASYNC/

WUI9

VREFP

SDA
SCL

PH6/CANRX/
WUI17

PH7/CANTX

D+
D­UVCC
UGND

CP3BT26

(LQFP-128)

PGO/RFSYNC

PE4/CKX/TB

PH0/RXD1/WUI11

PH1/TXD1/WUI12

PH2/RXD1/WUI13

PH3/TXD1/WUI14

PH4/RXD1/WUI15

PH5/TXD1/WUI16

PF0/MSK/TIO1

PF1/MDIDO/TIO2

PF2/MDODO/TIO3

PF3/MWCS/TIO4

PF4/SCK/TIO5

PF5/SFS/TIO6
PF6/STD/TIO7

PF7/SRD/TIO8

PE5/SRFS/NMI

PG2/BTSEQ1/SRCLK

PG6/BTSEQ2/WUI10

PB[7:0]
PC[7:0]

RFDATA

PG1/RFCE
PG3/SCLK

PG4/SDAT

PG5/SLE

PE0/RXD0
PE1/TXD0

PE2/RTS
PE3/CTS

PJ0/WUI18
PJ1/WUI19
PJ2/WUI20
PJ3/WUI21
PJ4/WUI22
PJ5/WUI23
PJ6/WUI24

8

8

12 MHz Crystal

GPIO

or Ext. Clock

32.768 kHz

RF Interface

Chip Reset

JTAG I/F to

Debugger/

Programmer

UART0

UART0/MFT

Selection

UART1/MIWU

UART2/MIWU

UART3/MIWU

Touchscreen

Microwire/
SPI/
VTU

AAI/
VTU

ACCESS.bus

AAI/NMI

CAN Bus/MIWU

RF/AAI

MIWU

RF/MIWU

Crystal

Powe r

Supply

Mode

RF/MFT

ADC/

CAN Bus

USB

1

1

1

1

6

6

10

11

X1CKI/BBCLK
X1CKO

X2CKI
X2CKO

AVCC
AGND
ADVCC
ADGND

CP3BT26

VCC

(LQFP-144)

GND
IOVCC

IOGND

RESET

TMS
TDI
TDO

TCK
RDY

ENV0
ENV1
ENV2

PG7/BTSEQ3/TA

ADC0/TSX+
ADC1/TSY+
ADC2/TSX­ADC3/TSY­ADC4/MUXOUT0
ADC5/MUXOUT1
ADC6
ADC7/ADCIN
PJ7/ASYNC/

WUI9
VREFP

SDA
SCL

PH6/CANRX/
WUI17

PH7/CANTX

D+
D­UVCC
UGND

PG2/BTSEQ1/SRCLK

PB[7:0]
PC[7:0]
A[22:0]

SEL0
SEL1
SEL2

SELIO

WR0
WR1

RD

RFDATA

PGO/RFSYNC

PG1/RFCE
PG3/SCLK

PG4/SDAT

PG5/SLE

PE0/RXD0

PE1/TXD0

PE2/RTS
PE3/CTS

PE4/CKX/TB

PH0/RXD1/WUI11
PH1/TXD1/WUI12

PH2/RXD1/WUI13
PH3/TXD1/WUI14

PH4/RXD1/WUI15

PH5/TXD1/WUI16

PF0/MSK/TIO1

PF1/MDIDO/TIO2

PF2/MDODO/TIO3

PF3/MWCS/TIO4

PF4/SCK/TIO5

PF5/SFS/TIO6
PF6/STD/TIO7

PF7/SRD/TIO8

PE5/SRFS/NMI

PJ0/WUI18

PG6/BTSEQ2/WUI10

8

8

23

External
Bus
Interface

RF Interface

UART0

UART0/MFT

UART1/MIW

UART2/MIW

UART3/MIW

Microwire/
SPI/
VTU

AAI/
VTU

AAI/NMI

RF/AAI

MIWU

RF/MIWU

DS208

Some pins may be enabled as general-purpose I/O-port
pins or as alternate functions associated with specific pe­ripherals or interfaces. These pins may be individually con­figured as port pins, even when the associated peripheral or
interface is enabled. Table 2 describes the device signals for
the LQFP-128 package. Table 3 describes the device sig­nals for the LQFP-144 package.

www.national.com 8

Figure 1. CP3BT26 Device SIgnals

Table 2 CP3BT26 LQFP-128 Signal Descriptions

CP3BT26

Name Pins I/O Primary Function

X1CKI 1

X1CKO 1

X2CKI 1

X2CKO 1

RESET 1

ENV0 1

ENV1 1

ENV2 1

TMS 1

TCK 1

TDI 1

TDO 1

Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface

Output 12 MHz Oscillator Output None None

Input 32 kHz Oscillator Input None None

Output 32 kHz Oscillator Output None None

Input Chip general reset None None

I/O

I/O

I/O

Input

Input

Input

Output JTAG Test Data Output None None

Special mode select input with
internal pull-up during reset

Special mode select input with
internal pull-up during reset

Special mode select input with
internal pull-up during reset

JTAG Test Mode Select
(with internal weak pull-up)

JTAG Test Clock Input
(with internal weak pull-up)

JTAG Test Data Input
(with internal weak pull-up)

Alternate

Name

PLLCLK PLL Clock Output

CPUCLK CPU Clock Output

SLOWCLK Slow Clock Output

None None

None None

None None

Alternate Function

RDY

VCC 6

GND 6

IOVCC 15

IOGND 14

AVC C 1

AGND

ADVCC 1

ADGND

RFDATA

SCL

SDA

D- 1

D+ 1

UVCC 1

UGND

Output NEXUS Ready Output None None

1

Input

Input Core Ground None None

Input 2.5

Input I/O Ground None None

Input PLL Analog Power Supply None None

1 Input PLL Analog Ground None None

Input ADC Analog Power Supply None None

1 Input ADC Analog Ground None None

1 I/O Bluetooth RX/TX Data Pin None None

1 I/O ACCESS.bus Clock None None

1 I/O ACCESS.bus Serial Data None None

I/O USB D- Upstream Port None None

I/O USB D+ Upstream Port None None

Input 3.3V USB Transceiver Supply None None

1 Input USB Transceiver Ground None None

2.5V Core Logic
Power Supply

None None

–3.3V I/O Power Supply None None

ADC0

ADC1

ADC2

1 I/O ADC Input Channel 0 TSX+ Touchscreen X+ contact

1 I/O ADC Input Channel 1 TSY+ Touchscreen Y+ contact

1 I/O ADC Input Channel 2 TSX- Touchscreen X- contact

9 www.national.com

Name Pins I/O Primary Function

Alternate

Name

Alternate Function

CP3BT26

ADC3

ADC4

ADC5

ADC6

ADC7

VREFP

PB[7:0]

PC[7:0]

PE0

PE1

PE2

PE3

PE4

PE5

PF0

PF1

PF2

1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact

1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0

1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1

1 Input ADC Input Channel 6 None None

1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode)

1 Input ADC Positive Voltage Reference None None

8 I/O Generic I/O None None

8 I/O Generic I/O None None

1 I/O Generic I/O RXD0 UART Channel 0 Receive Data Input

1 I/O Generic I/O TXD0 UART Channel 0 Transmit Data Output

1 I/O Generic I/O RTS

1 I/O Generic I/O CTS UART Channel 0 Clear-To-Send Input

CKX UART Channel 0 Clock Input

1 I/O Generic I/O

TB Multi Function Timer Port B

SRFS AAI Receive Frame Sync

1 I/O Generic I/O

NMI

MSK SPI Shift Clock

1 I/O Generic I/O

TIO1 Versatile Timer Channel 1

MDIDO SPI Master In Slave Out

1 I/O Generic I/O

TIO2 Versatile Timer Channel 2

MDODI SPI Master Out Slave In

1 I/O Generic I/O

TIO3 Versatile Timer Channel 3

UART Channel 0 Ready-To-Send Output

Non-Maskable Interrupt Input

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

www.national.com 10

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O RFSYNC BT AC Correlation/TX Enable Output

1 I/O Generic I/O RFCE BT RF Chip Enable Output

1 I/O Generic I/O

1 I/O Generic I/O SCLK BT Serial I/F Shift Clock Output

MWCS

TIO4 Versatile Timer Channel 4

SCK AAI Clock

TIO5 Versatile Timer Channel 5

SFS AAI Frame Synchronization

TIO6 Versatile Timer Channel 6

STD AAI Transmit Data Output

TIO7 Versatile Timer Channel 7

SRD AAI Receive Data Input

TIO8 Versatile Timer Channel 8

BTSEQ1 Bluetooth Sequencer Status

SRCLK AAI Receive Clock

SPI Slave Select Input

CP3BT26

Name Pins I/O Primary Function

PG4

PG5

PG6

PG7

PH0

PH1

PH2

PH3

PH4

PH5

1 I/O Generic I/O SDAT BT Serial I/F Data

1 I/O Generic I/O SLE BT Serial I/F Load Enable Output

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

Alternate

Name

WUI10 Multi-Input Wake-Up Channel 10

BTSEQ2 Bluetooth Sequencer Status

TA Multi Function Timer Port A

BTSEQ3 Bluetooth Sequencer Status

RXD1 UART Channel 1 Receive Data Input

WUI11 Multi-Input Wake-Up Channel 11

TXD1 UART Channel 1 Transmit Data Output

WUI12 Multi-Input Wake-Up Channel 12

RXD2 UART Channel 2 Receive Data Input

WUI13 Multi-Input Wake-Up Channel 13

TXD2 UART Channel 2 Transmit Data Output

WUI14 Multi-Input Wake-Up Channel 14

RXD3 UART Channel 3 Receive Data Input

WUI15 Multi-Input Wake-Up Channel 15

TXD3 UART Channel 3 Transmit Data Output

WUI16 Multi-Input Wake-Up Channel 16

Alternate Function

PH6

PH7

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

1 I/O Generic I/O

CANRX CAN Receive Input

WUI17 Multi-Input Wake-Up Channel 17

1 I/O Generic I/O CANTX CAN Transmit Output

1 I/O Generic I/O WUI18 Multi-Input Wake-Up Channel 18

1 I/O Generic I/O WUI19 Multi-Input Wake-Up Channel 19

1 I/O Generic I/O WUI20 Multi-Input Wake-Up Channel 20

1 I/O Generic I/O WUI21 Multi-Input Wake-Up Channel 21

1 I/O Generic I/O WUI22 Multi-Input Wake-Up Channel 22

1 I/O Generic I/O WUI23 Multi-Input Wake-Up Channel 23

1 I/O Generic I/O WUI24 Multi-Input Wake-Up Channel 24

ASYNC Start convert signal to ADC

1 I/O Generic I/O

WUI9 Multi-Input Wake-Up Channel 9

11 www.national.com

Table 3 CP3BT26 LQFP-144 Signal Descriptions

Name Pins I/O Primary Function

CP3BT26

X1CKI 1

X1CKO 1

X2CKI 1

X2CKO 1

RESET 1

ENV0 1

ENV1 1

ENV2 1

TMS 1

TCK 1

TDI 1

TDO 1

Alternate

Name

Input 12 MHz Oscillator Input BBCLK BB reference clock for the RF Interface

Output 12 MHz Oscillator Output None None

Input 32 kHz Oscillator Input None None

Output 32 kHz Oscillator Output None None

Input Chip general reset None None

I/O

I/O

I/O

Input

Input

Input

Output JTAG Test Data Output None None

Special mode select input with
internal pull-up during reset

Special mode select input with
internal pull-up during reset

Special mode select input with
internal pull-up during reset

JTAG Test Mode Select
(with internal weak pull-up)

JTAG Test Clock Input
(with internal weak pull-up)

JTAG Test Data Input
(with internal weak pull-up)

PLLCLK PLL Clock Output

CPUCLK CPU Clock Output

SLOWCLK Slow Clock Output

None None

None None

None None

Alternate Function

RDY

VCC 6

GND 6

IOVCC 10

IOGND 11

AVC C 1

AGND

ADVCC 1

ADGND

RFDATA

SCL

SDA

D- 1

D+ 1

UVCC 1

UGND

Output NEXUS Ready Output None None

1

Input

Input Core Ground None None

Input 2.5

Input I/O Ground None None

Input PLL Analog Power Supply None None

1 Input PLL Analog Ground None None

Input ADC Analog Power Supply None None

1 Input ADC Analog Ground None None

1 I/O Bluetooth RX/TX Data Pin None None

1 I/O ACCESS.bus Clock None None

1 I/O ACCESS.bus Serial Data None None

I/O USB D- Upstream Port None None

I/O USB D+ Upstream Port None None

Input 3.3V USB Transceiver Supply None None

1 Input USB Transceiver Ground None None

2.5V Core Logic
Power Supply

None None

–3.3V I/O Power Supply None None

ADC0

ADC1

ADC2

www.national.com 12

1 I/O ADC Input Channel 0 TSX+ Touchscreen X+ contact

1 I/O ADC Input Channel 1 TSY+ Touchscreen Y+ contact

1 I/O ADC Input Channel 2 TSX- Touchscreen X- contact

CP3BT26

Name Pins I/O Primary Function

ADC3

ADC4

ADC5

ADC6

ADC7

VREFP

PB[7:0]

PC[7:0]

A[22:0]

SEL0

SEL1

SEL2

SELIO

WR0

WR1

1 I/O ADC Input Channel 3 TSY- Touchscreen Y- contact

1 I/O ADC Input Channel 4 MUXOUT0 Analog Multiplexer Output 0

1 I/O ADC Input Channel 5 MUXOUT1 Analog Multiplexer Output 1

1 Input ADC Input Channel 6 None None

1 Input ADC Input Channel 7 ADCIN ADC Input (in MUX mode)

1 Input ADC Positive Voltage Reference None None

8 I/O Generic I/O D[7:0] External Data Bus Bits 0 to 7

8 I/O Generic I/O D[8:15] External Data Bus Bits 8 to 15

23 Output External Address Bus Bits 0 to 22 None None

1 Output Chip Select for Zone 0 None None

1 Output Chip Select for Zone 1 None None

1 Output Chip Select for Zone 2 None None

1 Output Chip Select for I/O Zone None None

1 Output External Memory Write Low Byte None None

1 Output External Memory Write High Byte None None

Alternate

Name

Alternate Function

RD

PE0

PE1

PE2

PE3

PE4

PE5

PF0

PF1

PF2

PF3

1 Output External Memory Read None None

1 I/O Generic I/O RXD0 UART0 Receive Data Input

1 I/O Generic I/O TXD0 UART0 Transmit Data Output

1 I/O Generic I/O RTS UART0 Ready-To-Send Output

1 I/O Generic I/O CTS UART0 Clear-To-Send Input

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

CKX UART0 Clock Input

TB Multi Function Timer Port B

SRFS AAI Receive Frame Sync

NMI

MSK SPI Shift Clock

TIO1 Versatile Timer Channel 1

MDIDO SPI Master In Slave Out

TIO2 Versatile Timer Channel 2

MDODI SPI Master Out Slave In

TIO3 Versatile Timer Channel 3

MWCS

TIO4 Versatile Timer Channel 4

Non-Maskable Interrupt Input

SPI Slave Select Input

PF4

PF5

1 I/O Generic I/O

1 I/O Generic I/O

SCK AAI Clock

TIO5 Versatile Timer Channel 5

SFS AAI Frame Synchronization

TIO6 Versatile Timer Channel 6

13 www.national.com

Name Pins I/O Primary Function

Alternate

Name

Alternate Function

CP3BT26

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PH0

PH1

PH2

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O RFSYNC BT AC Correlation/TX Enable Output

1 I/O Generic I/O RFCE BT RF Chip Enable Output

1 I/O Generic I/O

1 I/O Generic I/O SCLK BT Serial I/F Shift Clock Output

1 I/O Generic I/O SDAT BT Serial I/F Data

1 I/O Generic I/O SLE

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

1 I/O Generic I/O

STD AAI Transmit Data Output

TIO7 Versatile Timer Channel 7

SRD AAI Receive Data Input

TIO8 Versatile Timer Channel 8

BTSEQ1 Bluetooth Sequencer Status

SRCLK AAI Receive Clock

BT Serial I/F Load Enable Output

WUI10 Multi-Input Wake-Up Channel 10

BTSEQ2 Bluetooth Sequencer Status

TA Multi Function Timer Port A

BTSEQ3 Bluetooth Sequencer Status

RXD1 UART Channel 1 Receive Data Input

WUI11 Multi-Input Wake-Up Channel 11

TXD1 UART Channel 1 Transmit Data Output

WUI12 Multi-Input Wake-Up Channel 12

RXD2 UART Channel 2 Receive Data Input

WUI13 Multi-Input Wake-Up Channel 13

PH3

PH4

PH5

PH6

PH7

PJ0

PJ7

1 I/O Generic I/O

TXD2 UART Channel 2 Transmit Data Output

WUI14 Multi-Input Wake-Up Channel 14

RXD3 UART Channel 3 Receive Data Input

1 I/O Generic I/O

WUI15 Multi-Input Wake-Up Channel 15

TXD3 UART Channel 3 Transmit Data Output

1 I/O Generic I/O

WUI16 Multi-Input Wake-Up Channel 16

CANRX CAN Receive Input

1 I/O Generic I/O

WUI17 Multi-Input Wake-Up Channel 17

1 I/O Generic I/O CANTX CAN Transmit Output

1 I/O Generic I/O WUI18 Multi-Input Wake-Up Channel 18

ASYNC Start Convert Signal to ADC

1 I/O Generic I/O

WUI9 Multi-Input Wake-Up Channel 9

www.national.com 14

5.0 CPU Architecture

The CP3BT26 uses the CR16C third-generation 16-bit
CompactRISC processor core. The CPU implements a Re­duced Instruction Set Computer (RISC) architecture that al­lows an effective execution rate of up to one instruction per
clock cycle. For a detailed description of the CPU16C archi­tecture, see the CompactRISC CR16C Programmer’s Ref-
erence Manual which is available on the National
Semiconductor web site (http://www.nsc.com).

The CR16C CPU core includes these internal registers:

 General-purpose registers (R0-R13, RA, and SP)
 Dedicated address registers (PC, ISP, USP, and INT-

BASE)

 Processor Status Register (PSR)
 Configuration Register (CFG)

The R0-R11, PSR, and CFG registers are 16 bits wide. The
R12, R13, RA, SP, ISP and USP registers are 32 bits wide.
The PC register is 24 bits wide. Figure 2 shows the CPU
registers.

Dedicated Address Registers

31

ISPH

USPH

INTBASEH

15

23

PC

ISPL

USPL

INTBASEL

Processor Status Register

15

PSR

Configuration Register

15

CFG

0

0

0

31

Figure 2. CPU Registers

Some register bits are designated as “reserved.” Software
must write a zero to these bit locations when it writes to the
register. Read operations from reserved bit locations return
undefined values.

5.1 GENERAL-PURPOSE REGISTERS

The CompactRISC CPU features 16 general-purpose regis­ters. These registers are used individually as 16-bit oper­ands or as register pairs for operations on addresses
greater than 16 bits.

 General-purpose registers are defined as R0 through

R13, RA, and SP.

 Registers are grouped into pairs based on the setting of

the Short Register bit in the Configuration Register
(CFG.SR). When the CFG.SR bit is set, the grouping of
register pairs is upward-compatible with the architecture
of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ...
(R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L,
R13_L) and SP. (R14_L, R13_L) is the same as
(RA,ERA).

General-Purpose Registers

15 0

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

RA

SP

DS004

CP3BT26

 When the CFG.SR bit is clear, register pairs are grouped

in the manner used by native CR16C software: (R1,R0),
(R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP.
R12, R13, RA, and SP are 32-bit registers for holding ad­dresses greater than 16 bits.

With the recommended calling convention for the architec­ture, some of these registers are assigned special hardware
and software functions. Registers R0 to R13 are for general­purpose use, such as holding variables, addresses, or index
values. The SP register holds a pointer to the program run­time stack. The RA register holds a subroutine return ad­dress. The R12 and R13 registers are available to hold base
addresses used in the index addressing mode.

If a general-purpose register is specified by an operation
that is 8 bits long, only the lower byte of the register is used;
the upper part is not referenced or modified. Similarly, for
word operations on register pairs, only the lower word is
used. The upper word is not referenced or modified.

5.2 DEDICATED ADDRESS REGISTERS

The CR16C has four dedicated address registers to imple­ment specific functions: the PC, ISP, USP, and INTBASE
registers.

5.2.1 Program Counter (PC) Register

The 24-bit value in the PC register points to the first byte of
the instruction currently being executed. CR16C instruc­tions are aligned to even addresses, therefore the least sig­nificant bit of the PC is always 0. At reset, the PC is
initialized to 0 or an optional predetermined value. When a
warm reset occurs, value of the PC prior to reset is saved in
the (R1,R0) general-purpose register pair.

5.2.2 Interrupt Stack Pointer (ISP)

The 32-bit ISP register points to the top of the interrupt
stack. This stack is used by hardware to service exceptions
(interrupts and traps). The stack pointer may be accessed
as the ISP register for initialization. The interrupt stack can
be located anywhere in the CPU address space. The ISP
cannot be used for any purpose other than the interrupt
stack, which is used for automatic storage of the CPU reg­isters when an exception occurs and restoration of these
registers when the exception handler returns. The interrupt
stack grows downward in memory. The least significant bit
and the 8 most significant bits of the ISP register are always

0.

5.2.3 User Stack Pointer (USP)

The USP register points to the top of the user-mode pro­gram stack. Separate stacks are available for user and su­pervisor modes, to support protection mechanisms for
multitasking software. The processor mode is controlled by
the U bit in the PSR register (which is called PSR.U in the
shorthand convention). Stack grow downward in memory. If
the USP register points to an illegal address (any address
greater than 0x00FF_FFFF) and the USP is used for stack
access, an IAD trap is taken.

15 www.national.com

5.2.4 Interrupt Base Register (INTBASE)

The INTBASE register holds the address of the dispatch ta­ble for exceptions. The dispatch table can be located any­where in the CPU address space. When loading the

CP3BT26

INTBASE register, bits 31 to 24 and bit 0 must written with 0.

5.3 PROCESSOR STATUS REGISTER (PSR)

The PSR provides state information and controls operating
modes for the CPU. The format of the PSR is shown below.

15 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved I P E 0 N Z F 0 U L T C

C The Carry bit indicates whether a carry or bor-

row occurred after addition or subtraction.
0 – No carry or borrow occurred.
1 – Carry or borrow occurred.

T The Trace bit enables execution tracing, in

which a Trace trap (TRC) is taken after every
instruction. Tracing is automatically disabled
during the execution of an exception handler.

– Tracing disabled.

0
1 – Tracing enabled.

L The Low bit indicates the result of the last

comparison operation, with the operands in­terpreted as unsigned integers.

– Second operand greater than or equal to

0

first operand.

1 – Second operand less than first operand.

U The User Mode bit controls whether the CPU

is in user or supervisor mode. In supervisor
mode, the SP register is used for stack opera­tions. In user mode, the USP register is used
instead. User mode is entered by executing
the Jump USR instruction. When an exception
is taken, the exception handler automatically
begins execution in supervisor mode. The
USP register is accessible using the Load
Processor Register (LPR/LPRD) instruction in
supervisor mode. In user mode, an attempt to
access the USP register generates a UND
trap.

– CPU is executing in supervisor mode.

0

– CPU is executing in user mode.

1

F The Flag bit is a general condition flag for sig-

nalling exception conditions or distinguishing
the results of an instruction, among other
thing uses. For example, integer arithmetic in­structions use the F bit to indicate an overflow
condition after an addition or subtraction oper­ation.

Z The Zero bit is used by comparison opera-

tions. In a comparison of integers, the Z bit is
set if the two operands are equal. If the oper­ands are unequal, the Z bit is cleared.

– Source and destination operands un-

0

equal.

1 – Source and destination operands equal.

N The Negative bit indicates the result of the last

comparison operation, with the operands in­terpreted as signed integers.

– Second operand greater than or equal to

0

first operand.

1 – Second operand less than first operand.

E The Local Maskable Interrupt Enable bit en-

ables or disables maskable interrupts. If this
bit and the Global Maskable Interrupt Enable
(I) bit are both set, all interrupts are enabled.
If either of these bits is clear, only the non­maskable interrupt is enabled. The E bit is set
by the Enable Interrupts (EI) instruction and
cleared by the Disable Interrupts (DI) instruc­tion.

– Maskable interrupts disabled.

0
1 – Maskable interrupts enabled.

P The Trace Trap Pending bit is used together

with the Trace (T) bit to prevent a Trace (TRC)
trap from occurring more than once for one in­struction. At the beginning of the execution of
an instruction, the state of the T bit is copied
into the P bit. If the P bit remains set at the end
of the instruction execution, the TRC trap is
taken.

– No trace trap pending.

0

– Trace trap pending.

1

I The Global Maskable Interrupt Enable bit is

used to enable or disable maskable interrupts.
If this bit and the Local Maskable Interrupt En­able (E) bit are both set, all maskable inter­rupts are taken. If either bit is clear, only the
non-maskable interrupt is taken. Unlike the E
bit, the I bit is automatically cleared when an
interrupt occurs and automatically set upon
completion of an interrupt handler.

– Maskable interrupts disabled.

0
1 – Maskable interrupts enabled.

Bits Z, C, L, N, and F of the PSR are referenced from as­sembly language by the condition code in conditional
branch instructions. A conditional branch instruction may
cause a branch in program execution, based on the value of
one or more of these PSR bits. For example, one of the
Bcond instructions, BEQ (Branch EQual), causes a branch
if the PSR.Z bit is set.

On reset, bits 0 through 11 of the PSR are cleared, except
for the PSR.E bit, which is set. On warm reset, the values of
each bit before reset are copied into the R2 general-pur­pose register. Bits 4 and 8 of the PSR have a constant value
of 0. Bits 12 through 15 are reserved. In general, status bits
are modified only by specific instructions. Otherwise, status
bits maintain their values throughout instructions which do
not implicitly affect them.

www.national.com 16

5.4 CONFIGURATION REGISTER (CFG)

The CFG register is used to enable or disable various oper­ating modes and to control optional on-chip caches. Be­cause the CP3BT26 does not have cache memory, the
cache control bits in the CFG register are reserved. All CFG
bits are cleared on reset.

15 10 9 8 7 6 5 2 1 0

Reserved SR ED 0 0 Reserved 0 0

ED The Extended Dispatch bit selects whether

the size of an entry in the interrupt dispatch ta­ble (IDT) is 16 or 32 bits. Each entry holds the
address of the appropriate exception handler.
When the IDT has 16-bit entries, and all ex­ception handlers must reside in the first 128K
of the address space. The location of the IDT
is held in the INTBASE register, which is not
affected by the state of the ED bit.

– Interrupt dispatch table has 16-bit entries.

0
1 – Interrupt dispatch table has 32-bit entries.

SR The Short Register bit enables a compatibility

mode for the CR16B large model. In the
CR16C core, registers R12, R13, and RA are
extended to 32 bits. In the CR16B large mod­el, only the lower 16 bits of these registers are
used, and these “short registers” are paired
together for 32-bit operations. In this mode,
the (RA, R13) register pair is used as the ex­tended RA register, and address displace­ments relative to a single register are
supported with offsets of 0 and 14 bits in place
of the index addressing with these displace­ments.

– 32-bit registers are used.

0
1 – 16-bit registers are used (CR16B mode).

CP3BT26

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5.5 ADDRESSING MODES

The CR16C CPU core implements a load/store architec­ture, in which arithmetic and logical instructions operate on
register operands. Memory operands are made accessible

CP3BT26

in registers using load and store instructions. For efficient
implementation of I/O-intensive embedded applications, the
architecture also provides a set of bit operations that oper­ate on memory operands.

The load and store instructions support these addressing
modes: register/pair, immediate, relative, absolute, and in­dex addressing. When register pairs are used, the lower bits
are in the lower index register and the upper bits are in the
higher index register. When the CFG.SR bit is clear, the 32­bit registers R12, R13, RA, and SP are also treated as reg­ister pairs.

References to register pairs in assembly language use pa­rentheses. With a register pair, the lower numbered register
pair must be on the right. For example,

jump (r5, r4)

load $4(r4,r3), (r6,r5)

load $5(r12), (r13)

The instruction set supports the following addressing
modes:

Register/Pair
Mode

Immediate
Mode

Relative Mode In relative mode, the operand is ad-

In register/pair mode, the operand is held
in a general-purpose register, or in a gen­eral-purpose register pair. For example,
the following instruction adds the con­tents of the low byte of register r1 to the
contents of the low byte of r2, and places
the result in the low byte register r2. The
high byte of register r2 is not modified.

ADDB R1, R2
In immediate mode, the operand is a con-

stant value which is encoded in the in­struction. For example, the following
instruction multiplies the value of r4 by 4
and places the result in r4.

MULW $4, R4

dressed using a relative value (displace­ment) encoded in the instruction. This
displacement is relative to the current
Program Counter (PC), a general-pur­pose register, or a register pair.

In branch instructions, the displacement
is always relative to the current value of
the PC Register. For example, the follow­ing instruction causes an unconditional
branch to an address 10 ahead of the
current PC.

BR *+10

In another example, the operand resides
in memory. Its address is obtained by
adding a displacement encoded in the in­struction to the contents of register r5.
The address calculation does not modify
the contents of register r5.

LOADW 12(R5), R6
The following example calculates the ad-

dress of a source operand by adding a
displacement of 4 to the contents of a
register pair (r5, r4) and loads this oper­and into the register pair (r7, r6). r7 re­ceives the high word of the operand, and
r6 receives the low word.

LOADD 4(r5, r4), (r7, r6)

Index Mode In index mode, the operand address is

calculated with a base address held in ei­ther R12 or R13. The CFG.SR bit must
be clear to use this mode.

 For relative mode operands, the mem-

ory address is calculated by adding
the value of a register pair and a dis­placement to the base address. The
displacement can be a 14 or 20-bit un­signed value, which is encoded in the
instruction.

 For absolute mode operands, the

memory address is calculated by add­ing a 20-bit absolute address encoded
in the instruction to the base address.

In the following example, the operand ad­dress is the sum of the displacement 4,
the contents of the register pair (r5,r4),
and the base address held in register r12.
The word at this address is loaded into
register r6.

LOADW [r12]4(r5, r4), r6

Absolute Mode In absolute mode, the operand is located

in memory, and its address is encoded in
the instruction (normally 20 or 24 bits).
For example, the following instruction
loads the byte at address 4000 into the
lower 8 bits of register r6.

LOADB 4000, r6

For additional information on the addressing modes, see the
CompactRISC CR16C Programmer's Reference Manual.

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5.6 STACKS

A stack is a last-in, first-out data structure for dynamic stor­age of data and addresses. A stack consists of a block of
memory used to hold the data and a pointer to the top of the
stack. As more data is pushed onto a stack, the stack grows
downward in memory. The CR16C supports two types of
stacks: the interrupt stack and program stacks.

5.6.1 Interrupt Stack

The processor uses the interrupt stack to save and restore
the program state during the exception handling. Hardware
automatically pushes this data onto the interrupt stack be­fore entering an exception handler. When the exception
handler returns, hardware restores the processor state with
data popped from the interrupt stack. The interrupt stack
pointer is held in the ISP register.

5.6.2 Program Stack

The program stack is normally used by software to save and
restore register values on subroutine entry and exit, hold lo­cal and temporary variables, and hold parameters passed
between the calling routine and the subroutine. The only
hardware mechanisms which operate on the program stack
are the PUSH, POP, and POPRET instructions.

5.6.3 User and Supervisor Stack Pointers

To support multitasking operating systems, support is pro­vided for two program stack pointers: a user stack pointer
and a supervisor stack pointer. When the PSR.U bit is clear,
the SP register is used for all program stack operations. This
is the default mode when the user/supervisor protection
mechanism is not used, and it is the supervisor mode when
protection is used.

When the PSR.U bit is set, the processor is in user mode,
and the USP register is used as the program stack pointer.
User mode can only be entered using the JUSR instruction,
which performs a jump and sets the PSR.U bit. User mode
is exited when an exception is taken and re-entered when
the exception handler returns. In user mode, the LPRD in­struction cannot be used to change the state of processor
registers (such as the PSR).

5.7 INSTRUCTION SET

Table 4 lists the operand specifiers for the instruction set,
and Table 5 is a summary of all instructions. For each in­struction, the table shows the mnemonic and a brief de­scription of the operation performed.

In the mnemonic column, the lower-case letter “i” is used to
indicate the type of integer that the instruction operates on,
either “B” for byte or “W” for word. For example, the notation
ADDi for the “add” instruction means that there are two
forms of this instruction, ADDB and ADDW, which operate
on bytes and words, respectively.

Similarly, the lower-case string “cond” is used to indicate the
type of condition tested by the instruction. For example, the
notation Jcond represents a class of conditional jump in­structions: JEQ for Jump on Equal, JNE for Jump on Not
Equal, etc. For detailed information on all instructions, see
the CompactRISC CR16C Programmer's Reference Manu-
al.

Table 4 Key to Operand Specifiers

Operand Specifier Description

abs Absolute address

disp

imm

Iposition Bit position in memory

Rbase Base register (relative mode)

Rdest Destination register

Rindex Index register

RPbase, RPbasex Base register pair (relative mode)

RPdest Destination register pair

RPlink Link register pair

Rposition Bit position in register

Displacement (numeric suffix

indicates number of bits)

Immediate operand (numeric suf-

fix indicates number of bits)

CP3BT26

Rproc 16-bit processor register

Rprocd 32-bit processor register

RPsrc Source register pair

RPtarget Target register pair

Rsrc, Rsrc1, Rsrc2 Source register

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Table 5 Instruction Set Summary

CP3BT26

Mnemonic Operands Description

MOVi Rsrc/imm, Rdest Move

MOVXB Rsrc, Rdest Move with sign extension

MOVZB Rsrc, Rdest Move with zero extension

MOVXW Rsrc, RPdest Move with sign extension

MOVZW Rsrc, RPdest Move with zero extension

MOVD imm, RPdest Move immediate to register-pair

RPsrc, RPdest Move between register-pairs

ADD[U]i Rsrc/imm, Rdest Add

ADDCi Rsrc/imm, Rdest Add with carry

ADDD RPsrc/imm, RPdest Add with RP or immediate.

MACQWa Rsrc1, Rsrc2, RPdest Multiply signed Q15:

RPdest := RPdest + (Rsrc1 × Rsrc2)

MACSWa Rsrc1, Rsrc2, RPdest Multiply signed and add result:

RPdest := RPdest + (Rsrc1 × Rsrc2)

MACUWa Rsrc1, Rsrc2, RPdest Multiply unsigned and add result:

RPdest := RPdest + (Rsrc1 × Rsrc2)

MULi Rsrc/imm, Rdest Multiply: Rdest(8) := Rdest(8) × Rsrc(8)/imm

Rdest(16) := Rdest(16) × Rsrc(16)/imm

MULSB Rsrc, Rdest Multiply: Rdest(16) := Rdest(8) × Rsrc(8)

MULSW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16)

MULUW Rsrc, RPdest Multiply: RPdest := RPdest(16) × Rsrc(16);

SUBi Rsrc/imm, Rdest Subtract: (Rdest := Rdest - Rsrc/imm)

SUBD RPsrc/imm, RPdest Subtract: (RPdest := RPdest - RPsrc/imm)

SUBCi Rsrc/imm, Rdest Subtract with carry: (Rdest := Rdest - Rsrc/imm)

CMPi Rsrc/imm, Rdest Compare Rdest - Rsrc/imm

CMPD RPsrc/imm, RPdest Compare RPdest - RPsrc/imm

BEQ0i Rsrc, disp Compare Rsrc to 0 and branch if EQUAL

BNE0i Rsrc, disp Compare Rsrc to 0 and branch if NOT EQUAL

ANDi Rsrc/imm, Rdest Logical AND: Rdest := Rdest & Rsrc/imm

ANDD RPsrc/imm, RPdest Logical AND: RPdest := RPsrc & RPsrc/imm

ORi Rsrc/imm, Rdest Logical OR: Rdest := Rdest | Rsrc/imm

ORD RPsrc/imm, RPdest Logical OR: Rdest := RPdest | RPsrc/imm

Scond Rdest Save condition code as boolean

XORi Rsrc/imm, Rdest Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm

XORD RPsrc/imm, RPdest Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm

ASHUi Rsrc/imm, Rdest Arithmetic left/right shift

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Table 5 Instruction Set Summary

Mnemonic Operands Description

ASHUD Rsrc/imm, RPdest Arithmetic left/right shift

LSHi Rsrc/imm, Rdest Logical left/right shift

LSHD Rsrc/imm, RPdest Logical left/right shift

SBITi Iposition, disp(Rbase) Set a bit in memory

Iposition, disp(RPbase)

Iposition, (Rindex)disp(RPbasex)

Iposition, abs

Iposition, (Rindex)abs

CBITi Iposition, disp(Rbase) Clear a bit in memory

Iposition, disp(RPbase)

Iposition, (Rindex)disp(RPbasex)

Iposition, abs

Iposition, (Rindex)abs

(Because this instruction treats the destination as a read­modify-write operand, it not be used to set bits in write­only registers.)

CP3BT26

TBIT
TBITi

LPR Rsrc, Rproc Load processor register

LPRD RPsrc, Rprocd Load double processor register

SPR Rproc, Rdest Store processor register

SPRD Rprocd, RPdest Store 32-bit processor register

Bcond disp9 Conditional branch

BAL RPlink, disp24 Branch and link

BR disp9 Branch

Rposition/imm, Rsrc Test a bit in a register

Iposition, disp(Rbase)

Iposition, disp(RPbase)

Iposition, (Rindex)disp(RPbasex)

Iposition, abs

Iposition, (Rindex)abs

disp17

disp24

disp17

disp24

Test a bit in memory

EXCP vector Trap (vector)

Jcond RPtarget Conditional Jump to a large address

JAL RA, RPtarget, Jump and link to a large address

RPlink, RPtarget

JUMP RPtarget Jump

JUSR RPtarget Jump and set PSR.U

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Table 5 Instruction Set Summary

Mnemonic Operands Description

CP3BT26

RETX Return from exception

PUSH imm, Rsrc, RA Push “imm” number of registers on user stack, starting

with Rsrc and possibly including RA

POP imm, Rdest, RA Restore “imm” number of registers from user stack,

starting with Rdest and possibly including RA

POPRET imm, Rdest, RA Restore registers (similar to POP) and JUMP RA

LOADi disp(Rbase), Rdest Load (register relative)

abs, Rdest Load (absolute)

(Rindex)abs, Rdest Load (absolute index relative)

(Rindex)disp(RPbasex), Rdest Load (register relative index)

disp(RPbase), Rdest Load (register pair relative)

LOADD disp(Rbase), Rdest Load (register relative)

abs, Rdest Load (absolute)

(Rindex)abs, Rdest Load (absolute index relative)

(Rindex)disp(RPbasex), Rdest Load (register pair relative index)

disp(RPbase), Rdest Load (register pair relative)

STORi Rsrc, disp(Rbase) Store (register relative)

Rsrc, disp(RPbase) Store (register pair relative)

Rsrc, abs Store (absolute)

Rsrc, (Rindex)disp(RPbasex) Store (register pair relative index)

Rsrc, (Rindex)abs Store (absolute index)

STORD RPsrc, disp(Rbase) Store (register relative)

RPsrc, disp(RPbase) Store (register pair relative)

RPsrc, abs Store (absolute)

RPsrc, (Rindex)disp(RPbasex) Store (register pair index relative)

RPsrc, (Rindex)abs Store (absolute index relative)

STOR IMM imm4, disp(Rbase) Store unsigned 4-bit immediate value extended to operand

imm4, disp(RPbase)

imm4, (Rindex)disp(RPbasex)

imm4, abs

imm4, (Rindex)abs

LOADM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory

length in memory

starting at (R0)

LOADMP imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory

STORM STORM imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting

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starting at (R1, R0)

at (R2)

Table 5 Instruction Set Summary

Mnemonic Operands Description

STORMP imm3 Store 1 to 8 registers (R2-R5, R8-R11) to memory starting

at (R7,R6)

DI Disable maskable interrupts

EI Enable maskable interrupts

EIWAIT Enable maskable interrupts and wait for interrupt

NOP No operation

WAIT Wait for interrupt

CP3BT26

23 www.national.com

6.0 Memory

The CP3BT26 supports a uniform 16M-byte linear address
space. Table 6 lists the types of memory and peripherals

CP3BT26

that occupy this memory space. Unlisted address ranges

Table 6 CP3BT26 Memory Map

are reserved and must not be read or written. The BIU
zones are regions of the address space that share the same
control bits in the Bus Interface Unit (BIU).

Start

Address

00 0000h 03 FFFFh 256K

04 0000h 0C FFFFh 576K Reserved

0D 0000h 0D 1FFFh 8K On-chip Flash Data Memory

0D 2000h 0D FFFFh 56K Reserved

0E 0000h 0E 7FFFh 32K System RAM N/A

0E 8000h 0E 91FFh 4.5K Bluetooth Data RAM

0E 9200h 0E E7FFh 21.5K Reserved

0E E800h 0E EBFFh 1K Bluetooth Lower Link Controller Sequencer RAM

0E EC00h 0E EFFFh 1K Reserved

0E F000h 0E F13Fh 320 CAN Buffers and Registers

0E F140h 0E F17Fh 64 Reserved

0E F180h 0E F1FFh 128 Bluetooth Lower Link Controller Registers

0E F200h 0F FFFFh 67K Reserved

10 0000h 3F FFFFh 3072K Reserved

End

Address

Size in

Bytes

Description BIU Zone

On-chip Flash Program Memory, including Boot
Memory

Static Zone 0
(mapped internally
in IRE and ERE
mode; mapped to
the external bus in
DEV mode)

40 0000h 7F FFFFh 4096K External Memory Zone 1 Static Zone 1

80 0000h FE FFFFh 8128K External Memory Zone 2 Static Zone 2

FF 0000h FF F1FFh 61952 Reserved

FF F200h FF F5FFh 1K Peripherals and Other I/O Ports N/A

FF F600h FF FAFFh 1280 BIU, DMA, Flash interfaces IN/A

FF FB00h FF FBFFh 256 I/O Expansion I/O Zone

FF FC00h FF FFFFh 1K Peripherals and Other I/O Ports N/A

6.1 OPERATING ENVIRONMENT

The operating environment controls whether external mem­ory is supported and whether the reset vector jumps to a
code space intended to support In-System Programming
(ISP). Up to 12M of external memory space is available.

The operating mode of the device is controlled by the states
on the ENV[2:0] pins at reset and the states of the EMPTY
bits in the Protection Word, as shown in Table 7. Internal
pullups on the ENV[2:0] pins select IRE mode or ISP mode
if these pins are allowed to float.

When ENV[2:0] = 111b, IRE mode is selected unless the
EMPTY bits in the Protection word indicate that the program
flash memory is empty (unprogrammed), in which case ISP
mode is selected. When ENV[2:0] = 011b, ERE mode is se­lected unless the EMPTY bits indicate that the program

flash memory is empty, in which case ISP mode is selected.
When ENV[2:0] = 110b, ISP mode is selected without re­gard to the states of the EMPTY bits. See Section 8.4.2 for
more details.

In the DEV environment, the on-chip flash memory is dis­abled, and the corresponding region of the address space
is mapped to external memory. DEVINT mode is equivalent
to DEV mode but maps static memory zone 0 to the on-chip
memory.

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Table 7 Operating Environment Selection

ENV[2:0] EMPTY Operating Environment

111 No Internal ROM enabled (IRE) mode

011 No External ROM enabled (ERE) mode

000 N/A Development (DEV) mode

001 N/A

110 N/A In-System-Programming (ISP) mode

111 Yes In-System-Programming (ISP) mode

011 Yes In-System-Programming (ISP) mode

Development (DEVINT) mode with
internal memory

6.2 BUS INTERFACE UNIT (BIU)

The BIU controls the interface between the CPU core bus
and those on-chip modules which are mapped into BIU
zones. These on-chip modules are the flash program mem­ory and the I/O zone. The BIU controls the configured pa­rameters for bus access (such as the number of wait states
for memory access) and issues the appropriate bus signals
for the requested access.

6.3 BUS CYCLES

There are four types of data transfer bus cycles:

 Normal read
 Fast read
 Early write
 Late write

The type of data cycle used in a particular transaction de­pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write
or normal/fast read).

For read operations, a basic normal read takes two clock cy­cles, and a fast-read bus cycle takes one clock cycle. Nor­mal read bus cycles are enabled by default after reset.

For write operations, a basic late-write bus cycle takes two
clock cycles, and a basic early-write bus cycle takes three
clock cycles. Early-write bus cycles are enabled by default
after reset. However, late-write bus cycles are needed for
ordinary write operations, so this configuration must be
changed by software (see Section 6.4.1).

In certain cases, one or more additional clock cycles are
added to a bus access cycle. There are two types of addi­tional clock cycles for ordinary memory accesses, called in­ternal wait cycles (TIW) and hold (T

A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request.

A hold cycle is inserted at the end of a bus cycle. This holds
the data on the data bus for an extended number of clock cy­cles.

hold

) cycles.

6.4 BIU CONTROL REGISTERS

The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access­ing memory. During initialization of the system, these regis­ters should be programmed with appropriate values so that
the minimum allowable number of cycles is used. This num­ber varies with the clock frequency.

There are five BIU control registers, as listed in Table 8.
These registers control the bus cycle configuration used for
accessing the various on-chip memory types.

Table 8 Bus Control Registers

Name Address Description

BCFG FF F900h BIU Configuration Register

IOCFG FF F902h

SZCFG0 FF F904h

SZCFG1 FF F906h

SZCFG2 FF F908h

6.4.1 BIU Configuration Register (BCFG)

The BCFG register is a byte-wide, read/write register that
selects early-write or late-write bus cycles. At reset, the reg­ister is initialized to 07h. The register format is shown below.

7 3 2 1 0

Reserved 1 1 EWR

EWR The Early Write bit controls write cycle timing.

– Late-write operation (2 clock cycles to

0

write).

– Early-write operation.

1

At reset, the BCFG register is initialized to 07h, which se­lects early-write operation. However, late-write operation is
required for normal device operation, so software must
change the register value to 06h. Bits 1 and 2 of this register
must always be set when writing to this register.

I/O Zone Configuration

Register

Static Zone 0

Configuration Register

Static Zone 1

Configuration Register

Static Zone 2

Configuration Register

CP3BT26

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6.4.2 I/O Zone Configuration Register (IOCFG)

The IOCFG register is a word-wide, read/write register that
controls the timing and bus characteristics of accesses to
the 256-byte I/O Zone memory space (FF FB00h to FF

CP3BT26

FBFFh). The registers associated with Port B and Port C re­side in the I/O memory array. At reset, the register is initial­ized to 069Fh. The register format is shown below.

7 6 5 4 3 2 0

BW Reserved HOLD WAIT

15 10 9 8

Reserved IPST Res.

WAIT The Memory Wait Cycles field specifies the

number of TIW (internal wait state) clock cy­cles added for each memory access, ranging
from 000 binary for no additional TIW wait cy­cles to 111 binary for seven additional TIW
wait cycles.

HOLD The Memory Hold Cycles field specifies the

number of T
memory access, ranging from 00b for no
T

cycles to 11b for three T

hold

cles.

BW The Bus Width bit defines the bus width of the

IO Zone.

– 8-bit bus width.

0
1 – 16-bit bus width (default)

IPST The Post Idle bit controls whether an idle cycle

follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.

– No idle cycle (recommended).

0
1 – Idle cycle.

clock cycles used for each

hold

hold

clock cy-

6.4.3 Static Zone 0 Configuration Register (SZCFG0)

The SZCFG0 register is a word-wide, read/write register
that controls the timing and bus characteristics of Zone 0
memory accesses. Zone 0 is used for the on-chip flash
memory (including the boot area, program memory, and
data memory).

At reset, the register is initialized to 069Fh. The register for­mat is shown below.

7 6 5 4 3 2 0

BW WBR RBE HOLD WAIT

15 12 11 10 9 8

Reserved FRE IPRE IPST Res.

WAIT The Memory Wait field specifies the number

of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG0.FRE bit is set.

HOLD The Memory Hold field specifies the number

of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG0.FRE bit is set.

RBE The Read Burst Enable enables burst cycles

on 16-bit reads from 8-bit bus width regions of
the address space. Because the flash pro­gram memory is required to be 16-bit bus
width, the RBE bit is a don’t care bit. This bit
is ignored when the SZCFG0.FRE bit is set.
0
1 – Burst read enabled.

WBR The Wait on Burst Read bit controls if a wait

state is added on burst read transaction. This
bit is ignored, when SZCFG0.FRE bit is set or
when SZCFG0.RBE is clear.
0
1 – One TBW on burst read cycles.

BW The Bus Width bit controls the bus width of the

zone. The flash program memory must be
configured for 16-bit bus width.
0
1

FRE The Fast Read Enable bit controls whether

fast read bus cycles are used. A fast read op­eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1

IPST The Post Idle bit controls whether an idle cycle

follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1

clock cycles used for each memory

hold

clock cycles. These bits

hold

– Burst read disabled.

– No TBW on burst read cycles.

– 8-bit bus width.
– 16-bit bus width (required).

– Normal read cycles.
– Fast read cycles.

– No idle cycle (recommended).
– Idle cycle inserted.

hold

cycles

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IPRE The Preliminary Idle bit controls whether an

idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif­ferent zone. No idle cycles are required for on­chip accesses.

– No idle cycle (recommended).

0

– Idle cycle inserted.

1

6.4.4 Static Zone 1 Configuration Register (SZCFG1)

The SZCFG1 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL1

At reset, the register is initialized to 069Fh. The register for­mat is shown below.

7 6 5 4 3 2 0

BW WBR RBE HOLD WAIT

output signal.

IPST The Post Idle bit controls whether an idle cycle

follows the current bus cycle, when the next
bus cycle accesses a different zone.

– No idle cycle.

0
1 – Idle cycle inserted.

IPRE The Preliminary Idle bit controls whether an

idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif­ferent zone.

– No idle cycle.

0
1

– Idle cycle inserted.

6.4.5 Static Zone 2 Configuration Register (SZCFG2)

The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL2 output signal.

At reset, the register is initialized to 069Fh. The register for­mat is shown below.

CP3BT26

15 12 11 10 9 8

Reserved FRE IPRE IPST Res.

WAIT The Memory Wait field specifies the number

of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG1.FRE bit is set.

HOLD The Memory Hold field specifies the number

of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG1.FRE bit is set.

RBE The Read Burst Enable enables burst cycles

on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG1.FRE bit is set or the
SZCFG1.BW is clear.
0
1

WBR The Wait on Burst Read bit controls if a wait

state is added on burst read transaction. This
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0
1

BW The Bus Width bit controls the bus width of the

zone.
0
1

FRE The Fast Read Enable bit controls whether

fast read bus cycles are used. A fast read op­eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1

clock cycles used for each memory

hold

clock cycles. These bits

hold

– Burst read disabled.
– Burst read enabled.

– No TBW on burst read cycles.
– One TBW on burst read cycles.

– 8-bit bus width.
– 16-bit bus width.

– Normal read cycles.
– Fast read cycles.

hold

cycles

7 6 5 4 3 2 0

BW WBR RBE HOLD WAIT

15 12 11 10 9 8

Reserved FRE IPRE IPST Res.

WAIT The Memory Wait field specifies the number

of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.

HOLD The Memory Hold field specifies the number

of T
access, ranging from 00b for no T
to 11b for three T
are ignored if the SZCFG2.FRE bit is set.

RBE The Read Burst Enable enables burst cycles

on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG2.FRE bit is set or the
SZCFG2.BW is clear.
0
1

WBR The Wait on Burst Read bit controls if a wait

state is added on burst read transaction. This
bit is ignored, when SZCFG2.FRE bit is set or
when SZCFG2.RBE is clear.
0
1

BW The Bus Width bit controls the bus width of the

zone.
0
1

clock cycles used for each memory

hold

clock cycles. These bits

hold

– Burst read disabled.
– Burst read enabled.

– No TBW on burst read cycles.
– One TBW on burst read cycles.

– 8-bit bus width.
– 16-bit bus width.

hold

cycles

27 www.national.com

FRE The Fast Read Enable bit controls whether

fast read bus cycles are used. A fast read op­eration takes one clock cycle. A normal read

CP3BT26

IPST The Post Idle bit controls whether an idle cycle

IPRE The Preliminary Idle bit controls whether an

operation takes at least two clock cycles.

– Normal read cycles.

0
1 – Fast read cycles.

follows the current bus cycle, when the next
bus cycle accesses a different zone.

– No idle cycle.

0
1

– Idle cycle inserted.

idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif­ferent zone.

– No idle cycle.

0
1 – Idle cycle inserted.

6.5 WAIT AND HOLD STATES

The number of wait cycles and hold cycles inserted into a
bus cycle depends on whether it is a read or write operation,
the type of memory or I/O being accessed, and the control
register settings.

6.5.1 Flash Program/Data Memory

When the CPU accesses the Flash program and data mem­ory (address ranges 000000h
0E1FFFh), the number of added wait and hold cycles de­pends on the type of access and the BIU register settings.

In fast-read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operat­ing frequency to 24 MHz.

For a read operation in normal-read mode
(SZCFG0.FRE=0), the number of inserted wait cycles is
specified in the SZCFG0.WAIT field. The total number of
wait cycles is the value in the WAIT field plus 1, so it can
range from 1 to 8. The number of inserted hold cycles is
specified in the SCCFG0.HOLD field, which can range from
0 to 3.

For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is 1. No hold cycles are
used.

For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in
the early write mode). The number of inserted hold cycles is
equal to the value written to the SCCFG0.HOLD field, which
can range from 0 to 3.

6.5.2 RAM Memory

Read and write accesses to on-chip RAM is performed with­in a single cycle, without regard to the BIU settings. The
RAM address is in the range of 0E 0000h
8000h–0E 91FFh.

–03FFFFh and 0E0000h–

–0E 7FFFh and 0E

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6.5.3 Access to Peripherals

When the CPU accesses on-chip peripherals in the range of
0E F000h
cycle and one preliminary idle cycle is used. No hold cycles
are used. The IOCFG register determines the access timing
for the address range FF FB00h

–0E F1FFh and FF 0000h–FF FBFFh, one wait

–FF FBFFh.

7.0 System Configuration Registers

The system configuration registers control and provide sta­tus for certain aspects of device setup and operation, such
as indicating the states sampled from the ENV[2:0] inputs.
The system configuration registers are listed in Table 9.

Table 9 System Configuration Registers

Name Address Description

MCFG FF F910h

MSTAT FF F914h

7.1 MODULE CONFIGURATION REGISTER
(MCFG)

The MCFG register is a byte-wide, read/write register that
selects the clock output features of the device.

At reset, the register bits are cleared except for the
USB_ENABLE bit, which is set. Initialization software must
write a specific value to this register to enable the SCLK,
MCLK, output pin function.

The register must be written in active mode only, not in pow­er save, HALT, or IDLE mode. However, the register con­tents are preserved during all power modes.

The MCFG register format is shown below.

Module Configuration

Register

Module Status

Register

USB_ENABLE

MISC_IO_SPEED

MEM_IO_SPEED

The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the Function Word (see Section 8.4.1), and
the USB_ENABLE bit in the MCFG register.
0

1 – Transceiver power mode dependent on

The MISC_IO_SPEED bit controls the slew
rate of the output drivers for the ENV[2:0],
RDY
noise, the slow slew rate is recommended.
0 – Fast slew rate.
1
The MEM_IO_SPEED bit controls the slew
rate of the output drivers for the A[22:0], RD,
SEL[2:0]
PC[7:0] pins. Memory speeds for the
CP3BT26 are characterized with fast slew
rate. Slow slew rate reduces the available
memory access time by 5 ns.
0
1

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– External USB transceiver forced into low-

power mode.

USB controller status and programming
of the Function Word. (This is the state of
the USB_ENABLE bit after reset.)

, RFDATA, and TDO pins. To minimize

– Slow slew rate.

, SELIO, WR[1:0], PB[7:0], and

– Fast slew rate.
– Slow slew rate.

7 6 5 4 3 2 1 0

MEM_IO

Res.

_SPEED

EXIOE The EXIOE bit controls whether the external

PLLCLKOE

MCLKOE The MCLKOE bit controls whether the Main

SCLKOE The SCLKOE bit controls whether the Slow

MISC_IO
_SPEED

bus is enabled in the IRE environment for im­plementing the I/O Zone (FF FB00h
FBFFh).

– External bus disabled.

0
1 – External bus enabled.
The PLLCLKOE bit controls whether the PLL
clock is driven on the ENV0/PLLCLK pin.

– ENV0/PLLCLK pin is high impedance.

0

– PLL clock driven on the ENV0/PLLCLK

1

pin.

Clock is driven on the ENV1/CPUCLK pin.

– ENV1/CPUCLK pin is high impedance.

0

– Main Clock is driven on the ENV1/CPU-

1

CLK pin.

Clock is driven on the ENV2/SLOWCLK pin.

– ENV2/SLOWCLK pin is high impedance.

0

– Slow Clock is driven on the ENV2/SLOW-

1

CLK pin.

USB

_ENABLE

SCLKOEMCLKOEPLLCLKOEEXI

OE

–FF

29 www.national.com

7.2 MODULE STATUS REGISTER (MSTAT)

The MSTAT register is a byte-wide, read-only register that
indicates the general status of the device. The MCFG regis­ter format is shown below.

CP3BT26

7 6 5 4 3 2 0

ISPRST WDRST Res.

OENV2:0 The Operating Environment bits hold the

states sampled from the ENV[2:0] input pins
at reset. These states are controlled by exter­nal hardware at reset and are held constant in
the register until the next reset.

PGMBUSY The Flash Programming Busy bit is automati-

cally set when either the program memory or
the data memory is being programmed or
erased. It is clear when neither of the memo­ries is busy. When this bit is set, software must
not attempt to program or erase either of
these two memories. This bit is a copy of the
FMBUSY bit in the FMSTAT register.

– Flash memory is not busy.

0
1 – Flash memory is busy.

DPGMBUSY

WDRST The Watchdog Reset bit indicates that a

ISPRST The Software ISP Reset bit indicates that a

The Data Flash Programming Busy indicates
that the flash data memory is being erased or
a pipelined programming sequence is current­ly ongoing. Software must not attempt to per­form any write access to the flash program
memory at this time, without also polling the
FSMSTAT.FMFULL bit in the flash memory in­terface. The DPGMBUSY bit is a copy of the
FMBUSY bit in the FSMSTAT register.

– Flash data memory is not busy.

0

– Flash data memory is busy.

1

Watchdog timer reset has occurred. Write a 1
to this bit to clear it. Power-on reset also
clears this bit.

– No Watchdog timer reset has occurred

0

– A Watchdog timer reset has occurred

1

software ISP reset has occurred since the bit
was last cleared. This bit is cleared by a
SWRESET(CLR) sequence or a power-on re­set.

– No software ISP reset has occurred since

0

– A software ISP reset has occurred since

1

DPGMBUSY

since this bit was last cleared.

since this bit was last cleared.

this bit was last cleared.

this bit was last cleared.

PGMBUSY

OENV2:0

7.3 SOFTWARE RESET REGISTER
(SWRESET)

The SWRESET register is a byte-wide, write-only register
which provides a mechanism for software to initiate a reset
into ISP mode without regard to the status of the EMPTY
bits in the flash protection word. This form of reset is only al­lowed when all of the following conditions are true:

 The device is in IRE or ERE mode
 BOOTAREA is defined (has a value other than 1111b) in

the Protection Word (see Section 8.4.2 for more details).

 ISPE is set in the flash protection word, indicating that

there is ISP code in the flash

To initiate a reset under these conditions, it is necessary to
write the value E1h to the SWRESET register, followed with­in 127 clock cycles by the value 3Eh. The reset then follows
immediately. This sequence is called SWRESET(ISP).

Once the device has been reset into ISP mode by SWRE­SET(ISP), any subsequent reset (other than internal or ex­ternal power-on reset) will cause the part to reset into ISP
mode because the EMPTY bits in the Protection Word con­tinue to be ignored.

A second set of special values written to the SWRESET reg­ister will cause a reset out of ISP mode (whether or not the
device is currently in ISP mode). This can be used as a sim­ple software reset. In this case, no conditions are checked.
To initiate reset out of ISP mode, write the value E1h to the
SWRESET register, followed within 127 clock cycles by the
value 0Eh. The reset then follows immediately. This se­quence is called SWRESET(CLR). This reset also cancels
the effect of any previous SWRESET(ISP), so subsequent
resets will check the EMPTY bits to determine whether to
enter ISP mode.

The ISP reset behaves similarly to the Watchdog reset, for
example, if the flash interface is busy when reset is assert­ed, the reset to the clock module is delayed until the flash
operations are completed.

www.national.com 30

8.0 Flash Memory

The flash memory consists of the flash program memory
and the flash data memory. The flash program memory is
further divided into the Boot Area and the Code Area.

A special protection scheme is applied to the lower portion
of the flash program memory, called the Boot Area. The
Boot Area always starts at address 0 and ranges up to a
programmable end address. The maximum boot area ad­dress which can be selected is 00 77FFh. The intended use
of this area is to hold In-System-Programming (ISP) rou­tines or essential application routines. The Boot Area is al­ways protected against CPU write access, to avoid
unintended modifications.

The Code Area is intended to hold the application code and
constant data. The Code Area begins with the next byte af­ter the Boot Area. Table 10 summarizes the properties of
the regions of flash memory mapped into the CPU address
space.

Table 10 Flash Memory Areas

Area Address Range

Boot
Area

Code

Area

Data
Area

–BOOTAREA - 1 Yes No

0

BOOTAREA–03 FFFFh Yes

0E 0000h

–0E 1FFFh Yes

8.1 FLASH MEMORY PROTECTION

The memory protection mechanisms provide both global
and section-level protection. Section-level protection
against CPU writes is applied to individual 8K-byte sections
of the flash program memory and 512-byte sections of the
flash data memory. Section-level protection is controlled
through read/write registers mapped into the CPU address
space. Global write protection is applied at the device level,
to disable flash memory writes by the CPU. Global write pro­tection is controlled by the encoding of bits stored in the
flash memory array.

8.1.1 Section-Level Protection

Each bit in the Flash Memory Write Enable (FM0WER and
FM1WER) registers enables or disables write access to a
corresponding section of flash program memory. Write ac­cess to the flash data memory is controlled by the bits in the
Flash Slave Memory Write Enable (FSM0WER) register. By

Read

Access

Write Access

Write access

only if section

write enable

bit is set and

global write

protection is

disabled.

Write access

only if section

write enable

bit is set and

global write

protection is

disabled.

default (after reset) all bits in the FM0WER, FM1WER, and
FSM0WER registers are cleared, which disables write ac­cess by the CPU to all sections. Write access to a section is
enabled by setting the corresponding write enable bit. After
completing a programming or erase operation, software
should clear all write enable bits to protect the flash program
memory against any unintended writes.

8.1.2 Global Protection

The WRPROT field in the Protection Word controls global
write protection. The Protection Word is located in a special
flash memory outside of the CPU address space. If a major­ity of the bits in the 3-bit WRPROT field are clear, write pro­tection is enabled. Enabling this mode prevents the CPU
from writing to flash memory.

The RDPROT field in the Protection Word controls global
read protection. If a majority of the bits in the 3-bit RDPROT
field are clear, read protection is enabled. Enabling this
mode prevents reading by an external debugger through the
serial debug interface or by an external flash programmer.
CPU read access is not affected by the RDPROT bits.

8.2 FLASH MEMORY ORGANIZATION

Each of the flash memories are divided into main blocks and
information blocks. The main blocks hold the code or data
used by application software. The information blocks hold
factory parameters, protection settings, and other device­specific data. The main blocks are mapped into the CPU ad­dress space. The information blocks are accessed indirectly
through a register-based interface. Separate sets of regis­ters are provided for accessing flash program memory (FM
registers) and flash data memory (FSM registers). The flash
program memory consists of two main blocks and two data
blocks, as shown in Table 11. The flash data memory con­sists of one main block and one information block.

Table 11 Flash Memory Blocks

Name Address Range Function

Main Block 0

Information

Block 0

Main Block 1

Information

Block 1

Main Block 2

Information

Block 2

00 0000h

(CPU address space)

(address register)

02 0000h

(CPU address space)

(address register)

0D 0000h

(CPU address space)

(address register)

000h

080h

000h

–01 FFFFh

–07Fh

–03 FFFFh

–0FFh

–0D 1FFFh

–07Fh

Flash Program

Memory

Function Word,

Factory

Parameters

Flash Program

Memory

Protection Word,

User Data

Flash Data

Memory

User Data

CP3BT26

31 www.national.com

8.2.1 Main Block 0 and 1

Main Block 0 and Main Block 1 hold the 256K-byte program
space, which consists of the Boot Area and Code Area.
Each block consists of sixteen 8K-byte sections. Write ac-

CP3BT26

cess by the CPU to Main Block 0 and Main Block 1 is con­trolled by the corresponding bits in the FM0WER and
FM1WER registers, respectively. The least significant bit in
each register controls the section at the lowest address.

8.2.2 Information Block 0

Information Block 0 contains 128 bytes, of which one 16-bit
word has a dedicated function, called the Function Word.
The Function Word resides at address 07Eh. It controls the
power mode of an external USB transceiver. The remaining
Information Block 0 locations are used to hold factory pa­rameters.

Software only has read access to Information Block 0
through a register-based interface. The Function Word and
the factory parameters are protected against CPU writes.
Table 12 shows the structure of Information Block 0.

Table 12 Information Block 0

Name

Function

Word

Other (Used

for Factory

Parameters)

8.2.3 Information Block 1

Information Block 1 contains 128 bytes, of which one 16-bit
word has a dedicated function, called the Protection Word.
The Protection Word resides at address 0FEh. It controls
the global protection mechanisms and the size of the Boot
Area. The Protection Word can be written by the CPU, how­ever the changes only become valid after the next device re­set. The remaining Information Block 1 locations can be
used to store other user data. Erasing Information Block 1
also erases Main Block 1. Table 13 shows the structure of
the Information Block 1.

Name

Protection

Word

Other

(User Data)

Address

Range

–07Fh

07Eh

–07Dh

000h

Table 13 Information Block 1

Address

Range

–0FFh

0FEh

–0FDh

080h

Read

Access

Ye s N o

Read

Access

Ye s

Write Access

Write Access

Write access only

if section write
enable bit is set
and global write

protection is dis-

abled.

8.2.4 Main Block 2

Main Block 2 holds the 8K-byte data area, which consists of
sixteen 512-byte sections. Write access by the CPU to Main
Block 2 is controlled by the corresponding bits in the
FSM0WER register. The least significant bit in the register
controls the section at the lowest address.

8.2.5 Information Block 2

Information Block 2 contains 128 bytes, which can be used
to store user data. The CPU can always read Information
Block 2. The CPU can write Information Block 2 only when
global write protection is disabled. Erasing Information
Block 2 also erases Main Block 2.

8.3 FLASH MEMORY OPERATIONS

Flash memory programming (erasing and writing) can be
performed on the flash data memory while the CPU is exe­cuting out of flash program memory. Although the CPU can
execute out of flash data memory, it cannot erase or write
the flash program memory while executing from flash data
memory. To erase or write the flash program memory, the
CPU must be executing from the on-chip static RAM or off­chip memory.

An erase operation is required before programming. An
erase operation sets all of the bits in the erased region. A
programming operation clears selected bits.

The programming mechanism is pipelined, so that a new
write request can be loaded while a previous request is in
progress. When the FMFULL bit in the FMSTAT or FSM­STAT register is clear, the pipeline is ready to receive a new
request. New requests may be loaded after checking only
the FMFULL bit.

8.3.1 Main Block Read

Read accesses from flash program memory can only occur
when the flash program memory is not busy from a previous
write or erase operation. Read accesses from the flash data
memory can only occur when both the flash program mem­ory and the flash data memory are not busy. Both byte and
word read operations are supported.

8.3.2 Information Block Read

Information block data is read through the register-based in­terface. Only word read operations are supported and the
read address must be word-aligned (LSB = 0). The following
steps are used to read from an information block:

1. Load the word address in the Flash Memory Informa­tion Block Address (FMIBAR) or Flash Slave Memory
Information Block Address (FSMIBAR) register.

2. Read the data word by reading out the Flash Memory
Information Block Data (FMIBDR) or Flash Slave Mem­ory Information Block Data (FSMIBDR) register.

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8.3.3 Main Block Page Erase

A flash erase operation sets all of the bits in the erased re­gion. Pages of a main block can be individually erased if
their write enable bits are set. This method cannot be used
to erase the boot area, if defined. Each page in Main Block
0 and 1 consists of 1024 bytes (512 words). Each page in
Main Block 2 consists of 512 bytes (256 words). To erase a
page, the following steps are performed:

1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.

2. Prevent accesses to the flash memory while erasing is
in progress.

3. Set the Page Erase (PER) bit in the FMCTRL or FSM­CTRL register.

4. Write to an address within the desired page.

5. Wait until the FMBUSY bit becomes clear again.

6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
page.

7. Repeat steps 4 through 6 to erase additional pages.

8. Clear the PER bit.

8.3.4 Main Block Module Erase

A module erase operation can be used to erase an entire
main block. All sections within the block must be enabled for
writing. If a boot area is defined in the block, it cannot be
erased. The following steps are performed to erase a main
block:

1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.

2. Prevent accesses to the flash memory while erasing is
in progress.

3. Set the Module Erase (MER) bit in the FMCTRL or
FSMCTRL register.

4. Write to any address within the desired main block.

5. Wait until the FMBUSY bit becomes clear again.

6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
block.

7. Clear the MER bit.

8.3.5 Information Block Module Erase

Erasing an information block also erases the corresponding
main block. If a boot area is defined in the main block, nei­ther block can be erased. Page erase is not supported for
information blocks. The following steps are performed to
erase an information block:

1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.

2. Prevent accesses to the flash memory while erasing is
in progress.

3. Set the Module Erase (MER) bit in the FMCTRL or
FSMCTRL register.

4. Load the FMIBAR or FSMIBAR register with any ad­dress within the block, then write any data to the FMIB­DR or FSMIBDR register.

5. Wait until the FMBUSY bit becomes clear again.

6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
block.

7. Clear the MER bit.

CP3BT26

8.3.6 Main Block Write

Writing is only allowed when global write protection is dis­abled. Writing by the CPU is only allowed when the write en­able bit is set for the sector which contains the word to be
written. The CPU cannot write the Boot Area. Only word­wide write access to word-aligned addresses is supported.
The following steps are performed to write a word:

1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.

2. Prevent accesses to the flash memory while the write
is in progress.

3. Set the Program Enable (PE) bit in the FMCTRL or
FSMCTRL register.

4. Write a word to the desired word-aligned address. This
starts a new pipelined programming sequence. The
FMBUSY bit becomes set while the write operation is in
progress. The FMFULL bit in the FMSTAT or FSMSTAT
register becomes set if a previous write operation is still
in progress.

5. Wait until the FMFULL bit becomes clear.

6. Repeat steps 4 and 5 for additional words.

7. Wait until the FMBUSY bit becomes clear again.

8. Check the programming error (PERR) bit in the FM­STAT or FSMSTAT register to confirm successful pro­gramming.

9. Clear the Program Enable (PE) bit.

8.3.7 Information Block Write

Writing is only allowed when global write protection is dis­abled. Writing by the CPU is only allowed when the write en­able bit is set for the sector which contains the word to be
written. The CPU cannot write Information Block 0. Only
word-wide write access to word-aligned addresses is sup­ported. The following steps are performed to write a word:

1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.

2. Prevent accesses to the flash memory while the write
is in progress.

3. Set the Program Enable (PE) bit in the FMCTRL or
FSMCTRL register.

4. Write the desired target address into the FMIBAR or
FSMIBAR register.

5. Write the data word into the FMIBDR or FSMIBDR reg­ister. This starts a new pipelined programming se­quence. The FMBUSY bit becomes set while the write
operation is in progress. The FMFULL bit in the FM­STAT or FSMSTAT register becomes set if a previous
write operation is still in progress.

6. Wait until the FMFULL bit becomes clear.

7. Repeat steps 4 through 6 for additional words.

8. Wait until the FMBUSY bit becomes clear again.

9. Check the programming error (PERR) bit in the FM­STAT or FSMSTAT register to confirm successful pro­gramming.

10. Clear the Program Enable (PE) bit.

33 www.national.com

8.4 INFORMATION BLOCK WORDS

Two words in the information blocks are dedicated to hold
settings that affect the operation of the system: the Function
Word in Information Block 0 and the Protection Word in In-

CP3BT26

formation Block 1.

8.4.1 Function Word

The Function Word resides in the Information Block 0 at ad­dress 07Eh. At reset, the Function Word is copied into the
FMAR0 register.

Table 14 lists all possible boot area encod­ings.

Table 14 Boot Area Encodings

BOOT
AREA

1111 No Boot Area defined 00 0000h

1110 2K bytes 00 0800h

Size of the Boot

Area

Code Area

Start

Address

15 1 0

Reserved USB_ENABLE

USB_ENABLE

8.4.2 Protection Word

The Protection Word resides in Information Block 1 at ad­dress 0FEh. At reset, the Protection Word is copied into the
FMAR1 register.

15 13 12 10 9 7 6 4 3 1 0

WRPROT RDPROT ISPE EMPTY BOOTAREA

BOOTAREA The BOOTAREA field specifies the size of the

The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the MCFG register (see Section 7.1), and
the USB_ENABLE bit in the Function Word.

– External USB transceiver forced into low-

0

power mode.

1 – Transceiver power mode dependent on

USB controller status and programming
of the Function Word.

Boot Area. The Boot Area starts at address 0
and ends at the address specified by this field.
The inverted bits of the BOOTAREA field
count the number of 2048-byte blocks to be
reserved as the Boot Area. The maximum
Boot Area size is 30K bytes (address range 0
to 77FFh). The end of the Boot Area defines
the start of the Code Area. If the device starts
in ISP mode and there is no Boot Area defined
(encoding 1111b), the device is kept in reset.

1101 4K bytes 00 1000h

1100 6K bytes 00 1800h

1011 8K bytes 00 2000h

1010 10K bytes 00 2800h

1001 12K bytes 00 3000h

1000 14K bytes 00 3800h

0111 16K bytes 00 4000h

0110 18K bytes 00 4800h

0101 20K bytes 00 5000h

0100 22K bytes 00 5800h

0011 24K bytes 00 6000h

0010 26K bytes 00 6800h

0001 28K bytes 00 7000h

0000 30K bytes 00 7800h

EMPTY The EMPTY field indicates whether the flash

program memory has been programmed or
should be treated as blank. If a majority of the
three EMPTY bits are clear, the flash program
memory is treated as programmed. If a major­ity of the EMPTY bits are set, the flash pro­gram memory is treated as empty. If the
ENV[1:0] inputs (see Section 6.1) are sam­pled high at reset and the EMPTY bits indicate
the flash program memory is empty, the de­vice will begin execution in ISP mode. The de­vice enters ISP mode without regard to the
EMPTY status if ENV0 is driven low and
ENV1 is driven high.

ISPE The ISPE field indicates whether the Boot

Area is used to hold In-System-Programming
routines or user application routines. If a ma­jority of the three ISPE bits are set, the Boot
Area is intended to store ISP routines. If ma­jority of the ISPE bits are clear, the Boot Area
holds user application routines. Table 15 sum­marizes all possible EMPTY, ISPE, and Boot
Area settings and the corresponding start-up
operation for each combination. In DEV
mode, the EMPTY bit settings are ignored and
the CPU always starts executing from address

0.

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CP3BT26

Table 15 CPU Reset Behavior

EMPTY ISPE Boot Area Start-Up Operation

Device starts in IRE/

Not Empty ISP Defined

Not Empty ISP

Not Empty No ISP Don’t Care

Empty ISP Defined

Empty ISP

Empty No ISP Don’t Care

RDPROT The RDPROT field controls the global read

protection mechanism for the on-chip flash
program memory. If a majority of the three
RDPROT bits are clear, the flash program
memory is protected against read access
from the serial debug interface or an external
flash programmer. CPU read access is not af­fected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.

WRPROT The WRPROT field controls the global write

protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the se­rial debug interface. If a majority of the WR­PROT bits are set, write access is allowed.

Not

Defined

Not

Defined

ERE mode from
Code Area start

address

Device starts in IRE/

ERE mode from
Code Area start

address

Device starts in IRE/

ERE mode from

address 0

Device starts in ISP

mode from Code

Area start address

Device starts in ISP
mode and is kept in

its reset state

8.5 FLASH MEMORY INTERFACE
REGISTERS

There is a separate interface for the program flash and data
flash memories. The same set of registers exist in both in­terfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 16 lists the registers.

Table 16 Flash Memory Interface Registers

Program

Memory

FMIBAR

FF F940h

FMIBDR

FF F942h

FM0WER
FF F944h

FM1WER
FF F946h

FMCTRL

FF F94Ch

FMSTAT

FF F94Eh

FMPSR

FF F950h

FMSTART

FF F952h

FMTRAN

FF F954h

FMPROG
FF F956h

FMPERASE

FF F958h

FMMERASE0

FF F95Ah

FMEND

FF F95Eh

FMMEND
FF F960h

FMRCV

FF F962h

Data

Memory

FSMIBAR
FF F740h

FSMIBDR
FF F742h

FSM0WER

FF F744h

N/A

FSMCTRL

FF F74Ch

FSMSTAT
FF F74Eh

FSMPSR

FF F750h

FSMSTART

FF F752h

FSMTRAN

FF F754h

FSMPROG

FF F756h

FSMPERASE

FF F758h

FSMMERASE0

FF F75Ah

FSMEND

FF F75Eh

FSMMEND

FF F760h

FSMRCV

FF F762h

Description

Flash Memory
Information Block
Address Register

Flash Memory
Information Block
Address Register

Flash Memory 0

Write Enable Register

Flash Memory 1

Write Enable Register

Flash Memory

Control Register

Flash Memory

Status Register

Flash Memory

Prescaler Register

Flash Memory Start

Time Reload Register

Flash Memory

Transition Time

Reload Register

Flash Memory

Programming Time

Reload Register

Flash Memory Page

Erase Time Reload

Register

Flash Memory Module

Erase Time Reload

Register 0

Flash Memory End

Time Reload Register

Flash Memory Module

Erase End Time
Reload Register

Flash Memory

Recovery Time

Reload Register

FMAR0

FF F964h

FMAR1

FF F966h

FMAR2

FF F968h

FSMAR0

FF F764h

FSMAR1

FF F766h

FSMAR2

FF F768h

Flash Memory

Auto-Read Register 0

Flash Memory

Auto-Read Register 1

Flash Memory

Auto-Read Register 2

35 www.national.com

8.5.1 Flash Memory Information Block Address
Register (FMIBAR/FSMIBAR)

The FMIBAR register specifies the 8-bit address for read or
write access to an information block. Because only word ac-

CP3BT26

cess to the information blocks is supported, the least signif­icant bit (LSB) of the FMIBAR must be 0 (word-aligned). The
hardware automatically clears the LSB, without regard to
the value written to the bit. The FMIBAR register is cleared
after device reset. The CPU bus master has read/write ac­cess to this register.

15 8 7 0

Reserved IBA

IBA The Information Block Address field holds the

word-aligned address of an information block
location accessed during a read or write
transaction. The LSB of the IBA field is always
clear.

8.5.2 Flash Memory Information Block Data Register
(FMIBDR/FSMIBDR)

The FMIBDR register holds the 16-bit data for read or write
access to an information block. The FMIBDR register is
cleared after device reset. The CPU bus master has read/
write access to this register.

15 0

IBD

IBD The Information Block Data field holds the

data word for access to an information block.
For write operations the IBD field holds the
data word to be programmed into the informa­tion block location specified by the IBA ad­dress. During a read operation from an
information block, the IBD field receives the
data word read from the location specified by
the IBA address.

8.5.3 Flash Memory 0 Write Enable Register
(FM0WER/FSM0WER)

The FM0WER register controls section-level write protec­tion for the first half of the flash program memory. The
FMS0WER registers controls section-level write protection
for the flash data memory. Each data block is divided into 16
8K-byte sections. Each bit in the FM0WER and FSM0WER
registers controls write protection for one of these sections.
The FM0WER and FSM0WER registers are cleared after
device reset, so the flash memory is write protected after re­set. The CPU bus master has read/write access to this reg­isters.

15 0

FM0WE

FM0WEn The Flash Memory 0 Write Enable n bits con-

trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.

Bit Logical Address Range

0 00 0000h–00 1FFFh

1–14 . . .

15 01 E000h–01 FFFFh

8.5.4 Flash Memory 1 Write Enable Register
(FM1WER)

The FM1WER register controls write protection for the sec­ond half of the program flash memory. The data block is di­vided into 16 8K-byte sections. Each bit in the FM1WER
register controls write protection for one of these sections.
The FM1WER register is cleared after device reset, so the
flash memory is write protected after reset. The CPU bus
master has read/write access to this registers.

15 0

FM1WE

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FM1WEn The Flash Memory 1 Write Enable n bits con-

trol write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.

Bit Logical Address Range

0 02 0000h

1

–14 . . .

15 03 E000h–03 FFFFh

–02 1FFFh

8.5.5 Flash Data Memory 0 Write Enable Register
(FSM0WER)

The FSM0WER register controls write protection for the
flash data memory. The data block is divided into 16 512­byte sections. Each bit in the FSM0WER register controls
write protection for one of these sections. The FSM0WER
register is cleared after device reset, so the flash memory is
write protected after reset. The CPU bus master has read/
write access to this registers.

15 0

FSM0WE

FSM0WEn The Flash Data Memory 0 Write Enable n bits

control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.

Bit Logical Address Range

0 0E 0000h

1–14 . . .

15 0E 1E00h–0E 1FFFh

8.5.6 Flash Memory Control Register (FMCTRL/
FSMCTRL)

This register controls the basic functions of the Flash pro­gram memory. The register is clear after device reset. The
CPU bus master has read/write access to this register.

7 6 5 4 3 2 1 0

MER PER PE IENPROG DISVRF Res. CWD LOWPRW

LOWPRW The Low Power Mode controls whether flash

program memory is operated in low-power
mode, which draws less current when data is
read. This is accomplished be only accessing
the flash program memory during the first half
of the clock period. The low-power mode must
not be used at System Clock frequencies
above 25 MHz, otherwise a read access may
return undefined data. This bit must not be
changed while the flash program memory is
busy being programmed or erased.

– Normal mode.

0

– Low-power mode.

1

CWD The CPU Write Disable bit controls whether

the CPU has write access to flash memory.
This bit must not be changed while FMBUSY
is set.

– The CPU has write access to the flash

0

memory

1 – An external debugging tool is the current

“owner” of the flash memory interface, so
write accesses by the CPU are inhibited.

–0E 01FFh

DISVRF The Disable Verify bit controls the automatic

verification feature. This bit must not be
changed while the flash program memory is
busy being programmed or erased.

– New flash program memory contents are

0

automatically verified after programming.

– Automatic verification is disabled.

1

IENPROG The Interrupt Enable for Program bit is clear

after reset. The flash program and data mem­ories share a single interrupt channel but have
independent interrupt enable control bits.

– No interrupt request is asserted to the

0

ICU when the FMFULL bit is cleared.

1 – An interrupt request is made when the

FMFULL bit is cleared and new data can
be written into the write buffer.

PE The Program Enable bit controls write access

of the CPU to the flash program memory. This
bit must not be altered while the flash program
memory is busy being programmed or erased.
The PER and MER bits must be clear when
this bit is set.

– Programming the flash program memory

0

by the CPU is disabled.

– Programming the flash program memory

1

is enabled.

PER The Page Erase Enable bit controls whether a

a valid write operation triggers an erase oper­ation on a 1024-byte page of flash memory.
Page erase operations are only supported for
the main blocks, not the information blocks. A
page erase operation on an information block
is ignored and does not alter the information
block. When the PER bit is set, the PE and
MER bits must be clear. This bit must not be
changed while the flash program memory is
busy being programmed or erased.

– Page erase mode disabled. Write opera-

0

tions are performed normally.

– A valid write operation to a word location

1

in program memory erases the page that
contains the word.

MER The Module Erase Enable bit controls wheth-

er a valid write operation triggers an erase op­eration on an entire block of flash memory. If
an information block is written in this mode,
both the information block and its correspond­ing main block are erased. When the MER bit
is set, the PE and PER bits must be clear. This
bit must not be changed while the flash pro­gram memory is busy being programmed or
erased.

– Module erase mode disabled. Write oper-

0

ations are performed normally.

– A valid write operation to a word location

1

in a main block erases the block that con­tains the word. A valid write operation to a
word location in an information block
erases the block that contains the word
and its associated main block.

CP3BT26

37 www.national.com

8.5.7 Flash Memory Status Register (FMSTAT/
FSMSTAT)

This register reports the currents status of the on-chip Flash
memory. The FLSR register is clear after device reset. The

CP3BT26

CPU bus master has read/write access to this register.

7 5 4 3 2 1 0

Reserved DERR FMFULL FMBUSY PERR EERR

EERR The Erase Error bit indicates whether an error

has occurred during a page erase or module
(block) erase. After an erase error occurs,
software can clear the EERR bit by writing a 1
to it. Writing a 0 to the EERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being pro­grammed or erased.

– The erase operation was successful.

0
1 – An erase error occurred.

PERR The Program Error bit indicates whether an

error has occurred during programming. After
a programming error occurs, software can
clear the PERR bit by writing a 1 to it. Writing
a 0 to the PERR bit has no effect. Software
must not change this bit while the flash pro­gram memory is busy being programmed or
erased.

– The programming operation was suc-

0

cessful.

– A programming error occurred.

1

FMBUSY The Flash Memory Busy bit indicates whether

the flash memory (either main block or infor­mation block) is busy being programmed or
erased. During that time, software must not
request any further flash memory operations.
If such an attempt is made, the CPU is
stopped as long as the FMBUSY bit is active.
The CPU must not attempt to read from pro­gram memory (including instruction fetches)
while it is busy.

– Flash memory is ready to receive a new

0

erase or programming request.

– Flash memory busy with previous erase

1

or programming operation.

FMFULL The Flash Memory Buffer Full bit indicates

whether the write buffer for programming is
full or not. When the buffer is full, new erase
and write requests may not be made. The
IENPROG bit can be enabled to trigger an in­terrupt when the buffer is ready to receive a
new request.

– Buffer is ready to receive new erase or

0

write requests.

– Buffer is full. No new erase or write re-

1

quests can be accepted.

DERR The Data Loss Error bit indicates that a buffer

overrun has occurred during a programming
sequence. After a data loss error occurs, soft­ware can clear the DERR bit by writing a 1 to
it. Writing a 0 to the DERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being pro­grammed or erased.

– No data loss error occurred.

0

– Data loss error occurred.

1

8.5.8 Flash Memory Prescaler Register (FMPSR/
FSMPSR)

The FMPSR register is a byte-wide read/write register that
selects the prescaler divider ratio. The CPU must not modify
this register while an erase or programming operation is in
progress (FMBUSY is set). At reset, this register is initial­ized to 04h if the flash memory is idle. The CPU bus master
has read/write access to this register.

754 0

Reserved FTDIV

FTDIV The prescaler divisor scales the frequency of

the System Clock by a factor of (FTDIV + 1).

8.5.9 Flash Memory Start Time Reload Register
(FMSTART/FSMSTART)

The FMSTART/FSMSTART register is a byte-wide read/
write register that controls the program/erase start delay
time. Software must not modify this register while a pro­gram/erase operation is in progress (FMBUSY set). At re­set, this register is initialized to 18h if the flash memory is
idle. The CPU bus master has read/write access to this reg­ister.

70

FTSTART

FTSTART The Flash Timing Start Delay Count field gen-

erates a delay of (FTSTART + 1) prescaler
output clocks.

www.national.com 38

8.5.10 Flash Memory Transition Time Reload
Register (FMTRAN/FSMTRAN)

The FMTRAN/FMSTRAN register is a byte-wide read/write
register that controls some program/erase transition times.
Software must not modify this register while program/erase
operation is in progress (FMBUSY set). At reset, this regis­ter is initialized to 30h if the flash memory is idle. The CPU
bus master has read/write access to this register.

70

FTTRAN

FTTRAN The Flash TIming Transition Count field spec-

ifies a delay of (FTTRAN + 1) prescaler output
clocks.

8.5.11 Flash Memory Programming Time Reload
Register (FMPROG/FSMPROG)

The FMPROG/FSMPROG register is a byte-wide read/write
register that controls the programming pulse width. Soft­ware must not modify this register while a program/erase
operation is in progress (FMBUSY set). At reset, this regis­ter is initialized to 16h if the flash memory is idle. The CPU
bus master has read/write access to this register.

70

FTPROG

FTPROG The Flash Timing Programming Pulse Width

field specifies a programming pulse width of
8 × (FTPROG + 1) prescaler output clocks.

8.5.12 Flash Memory Page Erase Time Reload
Register (FMPERASE/FSMPERASE)

The FMPERASE/FSMPERASE register is a byte-wide
read/write register that controls the page erase pulse width.
Software must not modify this register while a program/
erase operation is in progress (FMBUSY set). At reset, this
register is initialized to 04h if the flash memory is idle. The
CPU bus master has read/write access to this register.

70

FTPER

8.5.13 Flash Memory Module Erase Time Reload
Register 0 (FMMERASE0/FSMMERASE0)

The FMMERASE0/FSMMERASE0 register is a byte-wide
read/write register that controls the module erase pulse
width. Software must not modify this register while a pro­gram/erase operation is in progress (FMBUSY set). At re­set, this register is initialized to EAh if the flash memory is
idle. The CPU bus master has read/write access to this reg­ister.

70

FTMER

FTMER The Flash Timing Module Erase Pulse Width

field specifies a module erase pulse width of
4096 × (FTMER + 1) prescaler output clocks.

8.5.14 Flash Memory End Time Reload Register
(FMEND/FSMEND)

The FMEND/FSMEND register is a byte-wide read/write
register that controls the delay time after a program/erase
operation. Software must not modify this register while a
program/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 18h when the flash mem­ory on the chip is idle. The CPU bus master has read/write
access to this register.

70

FTEND

FTEND The Flash Timing End Delay Count field spec-

ifies a delay of (FTEND + 1) prescaler output
clocks.

8.5.15 Flash Memory Module Erase End Time Reload
Register (FMMEND/FSMMEND)

The FMMEND/FSMMEND register is a byte-wide read/write
register that controls the delay time after a module erase op­eration. Software must not modify this register while a pro­gram/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 3Ch if the flash memory is
idle. The CPU bus master has read/write access to this reg­ister.

CP3BT26

FTPER The Flash Timing Page Erase Pulse Width

field specifies a page erase pulse width of
4096 × (FTPER + 1) prescaler output clocks.

70

FTMEND

FTMEND The Flash Timing Module Erase End Delay

Count field specifies a delay of 8 × (FTMEND
+ 1) prescaler output clocks.

39 www.national.com

8.5.16 Flash Memory Recovery Time Reload Register
(FMRCV/FSMRCV)

The FMRCV/FSMRCV register is a byte-wide read/write
register that controls the recovery delay time between two

CP3BT26

flash memory accesses. Software must not modify this reg­ister while a program/erase operation is in progress (FM­BUSY set). At reset, this register is initialized to 04h if the
flash memory is idle. The CPU bus master has read/write
access to this register.

70

FTRCV

FTRCV The Flash Timing Recovery Delay Count field

specifies a delay of (FTRCV + 1) prescaler
output clocks.

8.5.17 Flash Memory Auto-Read Register 0 (FMAR0/
FSMAR0)

The FMAR0/FSMAR0 register contains a copy of the Func­tion Word from Information Block 0. The Function Word is
sampled at reset. The contents of the FMAR0 register are
used to enable or disable special device functions. The CPU
bus master has read-only access to this register. The
FSMAR0 register has the same value as the FMAR0 regis­ter

15 1 0

Reserved USB_ENABLE

USB_ENABLE

The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The USB power mode is dependent on
the USB controller status, the USB_ENABLE
bit in the MCFG register (see Section 7.1),
and the USB_ENABLE bit in the Function
Word.

– External USB transceiver forced into low-

0

power mode.

– Transceiver power mode dependent on

1

USB controller status and programming
of the Function Word.

8.5.18 Flash Memory Auto-Read Register 1 (FMAR1/
FSMAR1)

The FMAR1 register contains a copy of the Protection Word
from Information Block 1. The Protection Word is sampled
at reset. The contents of the FMAR1 register define the cur­rent Flash memory protection settings. The CPU bus mas­ter has read-only access to this register. The FSMAR1
register has the same value as the FMAR1 register. The for­mat is the same as the format of the Protection Word (see
Section 8.4.2).

15 13 12 10 9 7 6 4 3 1 0

WRPROT RDPROT ISPE EMPTY BOOTAREA 1

8.5.19 Flash Memory Auto-Read Register 2 (FMAR2/
FSMAR2)

The FMAR2 register is a word-wide read-only register,
which is loaded during reset. It is used to build the Code
Area start address. At reset, the CPU executes a branch,
using the contents of the FMAR2 register as displacement.
The CPU bus master has read-only access to this register.

The FSMAR2 register has the same value as the FMAR2
register.

CADR10:0 The Code Area Start Address (bits 10:0) con-

CADR14:11 The Code Area Start Address (bits 14:11) are

CADR15 The Code Area Start Address (bits 15) con-

70

CADR7:0

15 14 11 10 8

CADR15

CADR14:11 CADR10:8

tains the lower 11 bits of the Code Area start
address. The CADR10:0 field has a fixed val­ue of 0.

loaded during reset with the inverted value of
BOOTAREA3:0.

tains the upper bit of the Code Area start ad­dress. The CADR15 field has a fixed value of

0.

www.national.com 40

9.0 DMA Controller

5

The DMA Controller (DMAC) has a register-based program­ming interface, as opposed to an interface based on I/O
control blocks. After loading the registers with source and
destination addresses, as well as block size and type of op­eration, a DMAC channel is ready to respond to DMA trans­fer requests. A request can only come from on-chip
peripherals or software, not external peripherals. On receiv­ing a DMA transfer request, if the channel is enabled, the
DMAC performs the following operations:

1. Arbitrates to become master of the CPU bus.

2. Determines priority among the DMAC channels, one
clock cycle before T1 of the DMAC transfer cycle. (T1
is the first clock cycle of the bus cycle.) Priority among
the DMAC channels is fixed in descending order, with
Channel 0 having the highest priority.

3. Executes data transfer bus cycle(s) selected by the val­ues held in the control registers of the channel being
serviced, and according to the accessed memory ad­dress. The DMAC acknowledges the request during the
bus cycle that accesses the requesting device.

4. If the transfer of a block is terminated, the DMAC does
the following:
Updates the termination bits.
Generates an interrupt (if enabled).
Goes to step 6.

5. If DMRQ
ous”, returns to step 3.

6. Returns mastership of the CPU bus to the CPU.

Each DMAC channel can be programmed for direct (flyby)
or indirect (memory-to-memory) data transfers. Once a
DMAC transfer cycle is in progress, the next transfer request
is sampled when the DMAC acknowledge is de-asserted,
then on the rising edge of every clock cycle.

The configuration of either address freeze or address up­date (increment or decrement) is independent of the num­ber of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be config­ured for each channel by programming the appropriate con­trol registers.

Each DMAC channel has eight control registers. DMAC
channels are described hereafter with the suffix n, where n
= 0 to 3, representing the channel number in the register­names.

n is still active, and the Bus Policy is “continu-

Table 17 DMA Channel Assignment

Channel Peripheral

Trans­action

Register

0 (Primary) USB R/W RX/TX FIFO

0 (Secondary) UART0 R RXBUF

1 (Primary) UART0 W TXBUF

1 (Secondary) Reserved N/A N/A

2 (Primary) Audio Interface R ARDR0

2 (Secondary)

CVSD/PCM

Transcoder

RPCMOUT

3 (Primary) Audio Interface W ATDR0

3 (Secondary)

CVSD/PCM

Transcoder

WPCMIN

9.2 TRANSFER TYPES

The DMAC uses two data transfer modes, Direct (Flyby)
and Indirect (Memory-to-Memory). The choice of mode de­pends on the required bus performance and whether direct
mode is available for the transfer. Indirect mode must be
used when the source and destination have differing bus
widths, when both the source and destination are in memo­ry, and when the destination does not support direct mode.

9.2.1 Direct (Flyby) Transfers

In direct mode each data item is transferred using a single
bus cycle, without reading the data into the DMAC. It pro­vides the fastest transfer rate, but it requires identical source
and destination bus widths. The DMAC cannot use Direct
cycles between two memory devices. One of the devices
must be an I/O device that supports the Direct (Flyby) mech­anism, as shown in Figure 3.

Bus State

T1 T1T2 Tidle

CLK

DMRQ[3:0]

CP3BT26

9.1 CHANNEL ASSIGNMENT

Table 17 shows the assignment of the DMA channels to dif­ferent tasks. Four channels can be shared by a primary and
an secondary function. However, only one source at a time
can be enabled. If a channel is used for memory block trans­fers, other resources must be disabled.

ADDR ADCA

MACK[3:0]

DS00

Figure 3. Direct DMA Cycle Followed by a CPU Cycle

41 www.national.com

Direct mode supports two bus policies: intermittent and con­tinuous. In intermittent mode, the DMAC gives bus master­ship back to the CPU after every cycle. In continuous mode,
the DMAC remains bus master until the transfer is complet-

CP3BT26

ed. The maximum bus throughput in intermittent mode is
one transfer for every three System Clock cycles. The max­imum bus throughput in continuous mode is one transfer for
every clock cycle.

The I/O device which made the DMA request is called the
implied I/O device. The other device can be either memory
or another I/O device, and is called the addressed device.

Because only one address is required in direct mode, this
address is taken from the corresponding ADCAn counter.
The DMAC channel generates either a read or a write bus
cycle, as controlled by the DMACNTLn.DIR bit.

When the DMACNTLn.DIR bit is clear, a read bus cycle
from the addressed device is performed, and the data is
written to the implied I/O device. When the DMACNTLn.DIR
bit is set, a write bus cycle to the addressed device is per­formed, and the data is read from the implied I/O device.

The configuration of either address freeze or address up­date (increment or decrement) is independent of the num­ber of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be config­ured for each channel by programming the appropriate con­trol register.

Whether 8 or 16 bits are transferred in each cycle is select­ed by the DMACNTLn.TCS register bit. After the data item
has been transferred, the BLTCn counter is decremented by
one. The ADCAn counter is updated according to the INCA
and ADA fields in the DMACNTLn register.

9.2.2 Indirect (Memory-To-Memory) Transfers

In indirect (memory-to-memory) mode, data transfers use
two consecutive bus cycles. The data is first read into a tem­porary register, and then written to the destination in the fol­lowing cycle. This mode is slower than the direct (flyby)
mode, but it provides support for different source and desti­nation bus widths. Indirect mode must be used for transfers
between memory devices.

If an intermittent bus policy is used, the maximum through­put is one transfer for every five clock cycles. If a continuous
bus policy is used, maximum throughput is one transfer for
every two clock cycles.

When the DMACNTLn.DIR bit is 0, the first bus cycle reads
data from the source using the ADCAn counter, while the
second bus cycle writes the data into the destination using
the ADCBn counter. When the DMACNTLn.DIR bit is set,
the first bus cycle reads data from the source using the AD­CBn counter, while the second bus cycle writes the data into
the destination addressed by the ADCAn counter.

The number of bytes transferred in each cycle is taken from
the DMACNTLn.TCS register bit. After the data item has
been transferred, the BLTCn counter is decremented by
one. The ADCAn and ADCBn counters are updated accord­ing to the INCA, INCB, ADA, and ADB fields in the
DMACNTLn register.

9.3 OPERATION MODES

The DMAC operates in three different block transfer modes:
single transfer, double buffer, and auto-initialize.

9.3.1 Single Transfer Operation

This mode provides the simplest way to accomplish a single
block data transfer.

Initialization

1. Write the block transfer addresses and byte count into
the corresponding ADCAn, ADCBn, and BLTCn
counters.

2. Clear the DMACNTLn.OT bit to select non-auto-initial­ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.

3. Set the DMACNTLn.CHEN bit to activate the channel
and enable it to respond to DMA transfer requests.

Termination

When the BLTCn counter reaches 0:

1. The transfer operation terminates.

2. The DMASTAT.TC and DMASTAT.OVR bits are set, and
the DMASTAT.CHAC bit is cleared.

3. An interrupt is generated if enabled by the
DMACNTLn.ETC or DMACNTLn.EOVR bits.

The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.

9.3.2 Double Buffer Operation

This mode allows software to set up the next block transfer
while the current block transfer proceeds.

Initialization

1. Write the block transfer addresses and byte count into
the ADCAn, ADCBn, and BLTCn counters.

2. Clear the DMACNTLn.OT bit to select non-auto-initial­ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.

3. Set the DMACNTLn.CHEN bit. This activates the chan­nel and enables it to respond to DMA transfer requests.

4. While the current block transfer proceeds, write the ad­dresses and byte count for the next block into the
ADRAn, ADRBn, and BLTRn registers. The BLTRn reg­ister must be written last, because it sets the DMAS­TAT.VLD bit which indicates that all the parameters for
the next transfer have been updated.

Continuation/Termination

When the BLTCn counter reaches 0:

1. The DMASTAT.TC bit is set.

2. An interrupt is generated if enabled by the
DMACNTLn.ETC bit.

3. The DMAC channel checks the value of the VLD bit.

If the DMASTAT.VLD bit is set:

1. The channel copies the ADRAn, ADRBn, and BLTRn
values into the ADCAn, ADCBn, and BLTCn registers.

2. The DMASTAT.VLD bit is cleared.

3. The next block transfer is started.

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If the DMASTAT.VLD bit is clear:

1. The transfer operation terminates.

2. The channel sets the DMASTAT.OVR bit.

3. The DMASTAT.CHAC bit is cleared.

4. An interrupt is generated if enabled by the
DMACNTLn.EOVR bit.

The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.

Note: The ADCBn and ADRBn registers are used only in
indirect (memory-to-memory) transfer. In direct (flyby)
mode, the DMAC does not use them and therefore does not
copy ADRBn into ADCBn.

9.3.3 Auto-Initialize Operation

This mode allows the DMAC to continuously fill the same
memory area without software intervention.

Initialization

1. Write the block addresses and byte count into the AD­CAn, ADCBn, and BLTCn counters, as well as the
ADRAn, ADRBn, and BLTRn registers.

2. Set the DMACNTLn.OT bit to select auto-initialize
mode.

3. Set the DMACNTLn.CHEN bit to activate the channel
and enable it to respond to DMA transfer requests.

Continuation

When the BLTCn counter reaches 0:

1. The contents of the ADRAn, ADRBn, and BLTRn regis­ters are copied to the ADCAn, ADCBn, and BLTCn
counters.

2. The DMAC channel checks the value of the DMAS­TAT.TC bit.

If the DMASTAT.TC bit is set:

1. The DMASTAT.OVR bit is set.

2. A level interrupt is generated if enabled by the
DMACNTLn.EOVR bit.

3. The operation is repeated.

If the DMASTAT.TC bit is clear:

1. The DMASTAT.TC bit is set.

2. A level interrupt is generated if enabled by the
DMACNTLn.ETC bit.

3. The DMAC operation is repeated.

Termination

The DMA transfer is terminated when the
DMACNTLn.CHEN bit is cleared.

9.4 SOFTWARE DMA REQUEST

In addition to the hardware requests from I/O devices, a
DMA transfer request can also be initiated by software. A
software DMA transfer request must be used for block copy­ing between memory devices.

When the DMACNTLn.SWRQ bit is set, the corresponding
DMA channel receives a DMA transfer request. When the
DMACNTLn.SWRQ bit is clear, the software DMA transfer
request of the corresponding channel is inactive.

For each channel, use the software DMA transfer request
only when the corresponding hardware DMA request is in­active and no terminal count interrupt is pending. Software
can poll the DMASTAT.CHAC bit to determine whether the
DMA channel is already active. After verifying the DMAS­TATn.CHAC bit is clear (channel inactive), check the DMAS­TATn.TC (terminal count) bit. If the TC bit is clear, then no
terminal count condition exists and therefore no terminal
count interrupt is pending. If the channel is not active and no
terminal count interrupt is pending, software may request a
DMA transfer.

9.5 DEBUG MODE

When the FREEZE signal is active, all DMA operations are
stopped. They will start again when the FREEZE signal
goes inactive. This allows breakpoints to be used in debug
systems.

9.6 DMA CONTROLLER REGISTER SET

There are four identical sets of DMA controller registers, as
listed in Table 18.

Table 18 DMA Controller Registers

Name Address Description

ADCA0 FF F800h

ADRA0 FF F804h

ADCB0 FF F808h

ADRB0 FF F80Ch

BLTC0 FF F810h

BLTR0 FF F814h Block Length Register

DMACNTL0 FF F81Ch DMA Control Register

DMASTAT0 FF F81Eh DMA Status Register

ADCA1 FF F820h

ADRA1 FF F824h

ADCB1 FF F828h

ADRB1 FF F82Ch

BLTC1 FF F830h

BLTR1 FF F834h Block Length Register

DMACNTL1 FF F83Ch DMA Control Register

DMASTAT1 FF F83Eh DMA Status Register

Device A Address

Counter Register

Device A Address

Register

Device B Address

Counter Register

Device B Address

Register

Block Length

Counter Register

Device A Address

Counter Register

Device A Address

Register

Device B Address

Counter Register

Device B Address

Register

Block Length

Counter Register

CP3BT26

43 www.national.com

Name Address Description

CP3BT26

ADCA2 FF F840h

ADRA2 FF F844h

ADCB2 FF F848h

Table 18 DMA Controller Registers

Device A Address

Counter Register

Device A Address

Register

Device B Address

Counter Register

9.6.2 Device A Address Register (ADRAn)

The Device A Address register is a 32-bit, read/write regis­ter. It holds the 24-bit starting address of either the next
source data block, or the next destination data area, according
to the DIR bit in the DMACNTLn register. The upper 8 bits of
the ADRAn register are reserved and always clear.

31 24 23 0

Reserved Device A Address

ADRB2 FF F84Ch

BLTC2 FF F850h

BLTR2 FF F854h Block Length Register

DMACNTL2 FF F85Ch DMA Control Register

DMASTAT2 FF F85Eh DMA Status Register

ADCA3 FF F860h

ADRA3 FF F864h

ADCB3 FF F868h

ADRB3 FF F86Ch

BLTC3 FF F870h

BLTR3 FF F874h Block Length Register

DMACNTL3 FF F87Ch DMA Control Register

DMASTAT3 FF F87Eh DMA Status Register

Device B Address

Register

Block Length

Counter Register

Device A Address

Counter Register

Device A Address

Register

Device B Address

Counter Register

Device B Address

Register

Block Length

Counter Register

9.6.3 Device B Address Counter Register (ADCBn)

The Device B Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item, or the destination location, according to
the DIR bit in the CNTLn register. The ADCBn register is up­dated after each transfer cycle by INCB field of the
DMACNTLn register according to ADB bit of the
DMACNTLn register. In direct (flyby) mode, this register is
not used.
served and always clear.

9.6.4 Device B Address Register (ADRBn)

The Device B Address register is a 32-bit, read/write regis­ter. It holds the 24-bit starting address of either the next
source data block or the next destination data area, accord­ing to the DIR bit in the CNTLn register. In direct (flyby)
mode, this register is not used.
CRBn register are reserved and always clear.

The upper 8 bits of the ADCBn register are re-

31 24 23 0

Reserved Device B Address Counter

The upper 8 bits of the AD-

31 24 23 0

Reserved Device B Address

9.6.1 Device A Address Counter Register (ADCAn)

The Device A Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item or the destination location, depending on
the state of the DIR bit in the CNTLn register. The ADA bit
of DMACNTLn register controls whether to adjust the point­er in the ADCAn register by the step size specified in the
INCA field of DMACNTLn register. The upper 8 bits of the
ADCAn register are reserved and always clear.

31 24 23 0

Reserved Device A Address Counter

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9.6.5 Block Length Counter Register (BLTCn)

The Block Length Counter register is a 16-bit, read/write
register. It holds the current number of DMA transfers to be
executed in the current block. BLTCn is decremented by one
after each transfer cycle. A DMA transfer may consist of 1 or
2 bytes, as selected by the DMACNTLn.TCS bit.

15 0

Block Length Counter

Note: 0000h is interpreted as 216-1 transfer cycles.

9.6.6 Block Length Register (BLTRn)

The Block Length register is a 16-bit, read/write register. It
holds the number of DMA transfers to be performed for the
next block. Writing this register automatically sets the DM­ASTAT.VLD bit.

15 0

Block Length

16

Note: 0000h is interpreted as 2

9.6.7 DMA Control Register (DMACNTLn)

The DMA Control register n is a word-wide, read/write reg­ister that controls the operation of DMA channel n. This reg­ister is cleared at reset. Reserved bits must be written with

0.

76543210

BPC OT DIR IND TCS EOVR ETC CHEN

15 14 13 12 11 10 9 8

Res. INCB ADB INCA ADA SWRQ

CHEN The Channel Enable bit must be set to enable

any DMA operation on this channel. Writing a
1 to this bit starts a new DMA transfer even if
it is currently a 1. If all DMACNTLn.CHEN bits
are clear, the DMA clock is disabled to reduce
power.

– Channel disabled.

0
1 – Channel enabled.

ETC If the Enable Interrupt on Terminal Count bit is

set, it enables an interrupt when the DMAS­TAT.TC bit is set.

– Interrupt disabled.

0

– Interrupt enabled.

1

EOVR If the Enable Interrupt on OVR bit is set, it en-

ables an interrupt when the DMASTAT.OVR
bit is set.

– Interrupt disabled.

0

– Interrupt enabled.

1

TCS The Transfer Cycle Size bit specifies the num-

ber of bytes transferred in each DMA transfer
cycle. In direct (fly-by) mode, undefined re­sults occur if the TCS bit is not equal to the ad­dressed memory bus width.

– Byte transfers (8 bits per cycle).

0
1

– Word transfers (16 bits per cycle).

IND The Direct/Indirect Transfer bit specifies the

transfer type.

– Direct transfer (flyby).

0

– Indirect transfer (memory-to-memory).

1

-1 transfer cycles.

DIR The Transfer Direction bit specifies the direc-

tion of the transfer relative to Device A.

– Device A (pointed to by the ADCAn regis-

0

ter) is the source. In Fly-By mode a read
transaction is initialized.

– Device A (pointed to by the ADCAn regis-

1

ter) is the destination. In Fly-By mode a
write transaction is initialized.

OT The Operation Type bit specifies the operation

mode of the DMA controller.

– Single-buffer mode or double-buffer mode

0

enabled.

– Auto-Initialize mode enabled.

1

BPC The Bus Policy Control bit specifies the bus

policy applied by the DMA controller. The op­eration mode can be either intermittent (cycle
stealing) or continuous (burst).

– Intermittent operation. The DMAC chan-

0

nel relinquishes the bus after each trans­action, even if the request is still asserted.

– Continuous operation. The DMAC chan-

1

nel n uses the bus continuously as long
as the request is asserted. This mode can
only be used for software DMA requests.
For hardware DMA requests, the BPC bit
must be clear.

SWRQ The Software DMA Request bit is written with

a 1 to initiate a software DMA request. Writing
a 0 to this bit deactivates the software DMA
request. The SWRQ bit must only be written
when the DMRQ signal for this channel is in­active (DMASTAT.CHAC = 0).

– Software DMA request is inactive.

0
1 – Software DMA request is active.

ADA If the Device A Address Control bit is set, it en-

ables updating the Device A address.
0 – ADCAn address unchanged.
1 – ADCAn address incremented or decre-

mented, according to INCA field of
DMACNTLn register.

INCA The Increment/Decrement ADCAn field spec-

ifies the step size for the Device A address in­crement/decrement.
00 – Increment ADCAn register by 1.
01 – Increment ADCAn register by 2.
10 – Decrement ADCAn register by 1.
11 – Decrement ADCAn register by 2.

ADB If the Device B Address Control bit is set, it en-

ables updating the Device B Address.

– ADCBn address unchanged.

0

– ADCBn address incremented or decre-

1

mented, according to INCB field of
DMACNTLn register.

INCB The Increment/Decrement ADCBn field spec-

ifies the step size for the Device B address in­crement/decrement.
00 – Increment ADCBn register by 1.
01 – Increment ADCBn register by 2.
10 – Decrement ADCBn register by 1.
11 – Decrement ADCBn register by 2.

CP3BT26

45 www.national.com

9.6.8 DMA Status Register (DMASTAT)

The DMA status register is a byte-wide, read register that
holds the status information for the DMA channel n. This
register is cleared at reset. The reserved bits always return

CP3BT26

zero when read. The VLD, OVR and TC bits are sticky (once
set by the occurrence of the specific condition, they remain
set until explicitly cleared by software). These bits can be in­dividually cleared by writing 1 to the bit positions in the DM­ASTAT register to be cleared. Writing 0 to these bits has no
effect

7 4 3 2 1 0

Reserved VLD CHAC OVR TC

TC The Terminal Count bit indicates whether the

transfer was completed by a terminal count
condition (BLTCn Register reached 0).

– Terminal count condition did not occur.

0
1 – Terminal count condition occurred.

OVR The behavior of the Channel Overrun bit de-

pends on the operation mode (single buffer,
double buffer, or auto-initialize) of the DMA
channel.

In double-buffered mode (DMACNTLn.OT =

0):

The OVR bit is set when the present transfer
is completed (BLTCn = 0), but the parameters
for the next transfer (address and block
length) are not valid (DMASTAT.VLD = 0).

In auto-initialize mode (DMACNTLn.OT = 1):

The OVR bit is set when the present transfer
is completed (BLTCn = 0), and the DMAS­TAT.TC bit is still set.

In single-buffer mode:

Operates in the same way as double-buffer
mode. In single-buffered mode, the DMAS­TAT.VLD bit should always be clear, so it will
also be set when the DMASTAT.TC bit is set.
Therefore, the OVR bit can be ignored in this
mode.

CHAC The Channel Active bit continuously indicates

the active or inactive status of the channel,
and therefore, it is read only. Data written to
the CHAC bit is ignored.

– Channel inactive.

0
1

– Indicates that the channel is active

(CHEN bit in the CNTLn register is 1 and
BLTCn > 0)

VLD The Transfer Parameters Valid bit specifies

whether the transfer parameters for the next
block to be transferred are valid. Writing the
BLTRn register automatically sets this bit. The
bit is cleared in the following cases:
 The present transfer is completed and the

ADRAn, ADRBn (indirect mode only), and
BLTR registers are copied to the ADCAn,
ADCBn (indirect mode only), and BLTCn
registers.

 Writing 1 to the VLD bit.

www.national.com 46

10.0 Interrupts

The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. Interrupts from the timers, UARTs, Microwire/
SPI interface, and Multi-Input Wake-Up module are all
maskable interrupts. The highest-priority interrupt is the
Non-Maskable Interrupt (NMI), which is triggered by a falling
edge received on the NMI

The priorities of the maskable interrupts are hardwired and
therefore fixed. The implemented interrupts are named
IRQ0 through IRQ47, in which IRQ0 has the lowest priority
and IRQ47 has the highest priority. (IRQ0 is not implement­ed, so IRQ1 is the lowest priority interrupt that normally may
occur.)

10.1 NON-MASKABLE INTERRUPTS

The Interrupt Control Unit (ICU) receives the external NMI
input and generates the NMI signal driven to the CPU. The
NMI input is an asynchronous input with Schmitt trigger
characteristics and an internal synchronization circuit,
therefore no external synchronizing circuit is needed. The

pin triggers an exception on its falling edge.

NMI

10.1.1 Non-Maskable Interrupt Processing

The CPU performs an interrupt acknowledge bus cycle
when beginning to process a non-maskable interrupt.

At reset, NMI interrupts are disabled and must remain dis­abled until software initializes the interrupt table, interrupt
base register (INTBASE), and the interrupt mode. The ex­ternal NMI
LCK bit and will remain enabled until a reset occurs.
Alternatively, the external NMI interrupt can be enabled by
setting the EXNMI.EN bit and will remain enabled until an in­terrupt event or a reset occurs.

interrupt is enabled by setting the EXNMI.EN-

10.2 MASKABLE INTERRUPTS

The ICU receives level-triggered interrupt request signals
from 47 sources and generates a vectored interrupt to the
CPU when required. Priority among the implemented inter­rupt sources (named IRQ1 through IRQ47) is fixed.

The maskable interrupts are globally enabled and disabled
by the E bit in the PSR register. The EI and DI instructions
are used to set (enable) and clear (disable) this bit. The glo­bal maskable interrupt enable bit (I bit in the PSR) must also
be set before any maskable interrupts are taken.

Each interrupt source can be individually enabled or dis­abled under software control through the ICU interrupt en­able registers and also through interrupt enable bits in the
peripherals that request the interrupts. The ICU supports
IRQ0, but in the CP3BT26 it is not connected to any inter­rupt source.

input pin.

10.2.1 Maskable Interrupt Processing

Interrupt vector numbers are always positive, in the range
10h to 3Fh. The IVCT register contains the interrupt vector
of the enabled and pending interrupt with the highest priori­ty. The interrupt vector 10h corresponds to IRQ0 and the
lowest priority, while the vector 3Fh corresponds to IRQ47
and the highest priority. The CPU performs an interrupt ac­knowledge bus cycle on receiving a maskable interrupt re­quest from the ICU. During the interrupt acknowledge cycle,
a byte is read from address FF FE00h (IVCT register). The
byte is used as an index into the Dispatch Table to deter­mine the address of the interrupt handler.

Because IRQ0 is not connected to any interrupt source, it
would seem that the interrupt vector would never return the
value 10h. If it does return a value of 10h, the entry in the
dispatch table should point to a default interrupt handler that
handles this error condition. One possible condition for this
to occur is deassertion of the interrupt before the interrupt
acknowledge cycle.

10.3 INTERRUPT CONTROLLER REGISTERS

Table 19 lists the ICU registers.

Table 19 Interrupt Controller Registers

Name Address Description

IVCT FF FE00h

NMISTAT FF FE02h

EXNMI FF FE04h

ISTAT0 FF FE0Ah

ISTAT1 FF FE0Ch

ISTAT2 FF FE20h

IENAM0 FF FE0Eh

IENAM1 FF FE10h

IENAM2 FF FE22h

Interrupt Vector

Register

Non-Maskable

Interrupt Status

Register

External NMI Trap

Control and Status

Register

Interrupt Status

Register 0

Interrupt Status

Register 1

Interrupt Status

Register 2

Interrupt Enable and

Mask Register 0

Interrupt Enable and

Mask Register 1

Interrupt Enable and

Mask Register 2

CP3BT26

47 www.national.com

10.3.1 Interrupt Vector Register (IVCT)

The IVCT register is a byte-wide read-only register which re­ports the encoded value of the highest priority maskable in­terrupt that is both asserted and enabled. The valid range is

CP3BT26

from 10h to 3Fh. The register is read by the CPU during an
interrupt acknowledge bus cycle, and INTVECT is valid dur­ing that time. It may contain invalid data while INTVECT is
updated.

10.3.3 External NMI Trap Control and Status Register
(EXNMI)

The EXNMI register is a byte-wide read/write register. It in­dicates the current value of the NMI
NMI interrupt trap generation based on a falling edge of the

pin. TST, EN and ENLCK are cleared on reset. When

NMI
writing to this register, all reserved bits must be written with
0 for the device to function properly

pin and controls the

7 6 5 0

0 0 INTVECT

INTVECT The Interrupt Vector field indicates the highest

priority interrupt which is both asserted and
enabled.

10.3.2 Non-Maskable Interrupt Status Register
(NMISTAT)

The NMISTAT register is a byte-wide read-only register. It
holds the status of the current pending Non-Maskable Inter­rupt (NMI) requests. On the CP3BT26, the external NMI
put is the only source of NMI interrupts. The NMISTAT
register is cleared on reset and each time its contents are
read.

710

Reserved EXT

EXT The External NMI request bit indicates wheth-

er an external non-maskable interrupt request
has occurred. Refer to the description of the
EXNMI register below for additional details.

– No external NMI request.

0

– External NMI request has occurred.

1

in-

73210

Reserved ENLCK PIN EN

EN The EXNMI trap enable bit is one of two bits

that can be used to enable NMI interrupts.
The bit is cleared by hardware at reset and
whenever the NMI interrupt occurs (EXN­MI.EXT set). It is intended for applications
where the NMI
nested NMI traps are not desired. For these
applications, the EN bit needs to be re-en­abled before exiting the trap handler. When
used this way, the ENLCK bit should never be
set. The EN bit can be set and cleared by soft­ware (software can set this bit only if EXN­MI.EXT is cleared), and should only be set
after the interrupt base register and the inter­rupt stack pointer have been set up.

– NMI interrupts not enabled by this bit (but

0

may be enabled by the ENLCK bit).

– NMI interrupts enabled.

1

PIN The PIN bit indicates the state (non-inverted)

on the NMI input pin. This bit is read-only, data
written into it is ignored.

– NMI pin not asserted.

0
1 – NMI pin asserted.

ENLCK The EXNMI trap enable lock bit is used to per-

manently enable NMI interrupts. Only a de­vice reset can clear the ENLCK bit. This
allows the external NMI feature to be enabled
after the interrupt base register and the inter­rupt stack pointer have been set up. When the
ENLCK bit is set, the EN bit is ignored.

– NMI interrupts not enabled by this bit (but

0

may be enabled by the EN bit).

– NMI interrupts enabled.

1

input toggles frequently but

www.national.com 48

10.3.4 Interrupt Enable and Mask Register 0 (IENAM0)

The IENAM0 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ1 through IRQ15. The reg­ister is initialized to FFFFh at reset.

CP3BT26

10.3.7 Interrupt Status Register 0 (ISTAT0)

The ISTAT0 register is a word-wide read-only register. It in­dicates which maskable interrupt inputs to the ICU are ac­tive. These bits are not affected by the state of the
corresponding IENA bits.

15 1 0

IENA Res.

IENA Each Interrupt Enable bit enables or disables

the corresponding interrupt request IRQ1
through IRQ15, for example IENA15 controls
IRQ15. Because IRQ0 is not used, IENA0 is
ignored.

– Interrupt is disabled.

0
1 – Interrupt is enabled.

10.3.5 Interrupt Enable and Mask Register 1 (IENAM1)

The IENAM1 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ16 through IRQ31. The reg­ister is initialized to FFFFh at reset.

15 0

IENA

IENA Each Interrupt Enable bit enables or disables

the corresponding interrupt request IRQ16
through IRQ31, for example IENA31 controls
IRQ31.

– Interrupt is disabled.

0
1 – Interrupt is enabled.

10.3.6 Interrupt Enable and Mask Register 2 (IENAM2)

The IENAM2 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ32 through IRQ47. The reg­ister is initialized to FFFFh at reset.

15 1 0

IST Res.

IST The Interrupt Status bits indicate if a

maskable interrupt source is signalling an in­terrupt request. IST15:1 correspond to IRQ15
to IRQ1 respectively. Because the IRQ0 inter­rupt is not used, bit 0 always reads back 0.

– Interrupt is not active.

0
1 – Interrupt is active.

10.3.8 Interrupt Status Register 1 (ISTAT1)

The ISTAT1 register is a word-wide read-only register. It in­dicates which maskable interrupt inputs into the ICU are ac­tive. These bits are not affected by the state of the
corresponding IENA bits.

15 0

IST

IST The Interrupt Status bits indicate if a

maskable interrupt source is signalling an in­terrupt request. IST31:16 correspond to
IRQ31 to IRQ16, respectively.

– Interrupt is not active.

0
1 – Interrupt is active.

10.3.9 Interrupt Status Register 2 (ISTAT2)

The ISTAT2 register is a word-wide read-only register. It in­dicates which maskable interrupt inputs into the ICU are ac­tive. These bits are not affected by the state of the
corresponding IENA bits.

15 0

IENA

IENA Each Interrupt Enable bit enables or disables

the corresponding interrupt request IRQ32
through IRQ47, for example IENA47 controls
IRQ47.

– Interrupt is disabled.

0
1

– Interrupt is enabled.

15 0

IST

IST The Interrupt Status bits indicate if a

maskable interrupt source is signalling an in­terrupt request. IST47:32 correspond to
IRQ47 to IRQ32, respectively.

– Interrupt is not active.

0
1

– Interrupt is active.

49 www.national.com

10.4 MASKABLE INTERRUPT SOURCES

Table 20 shows the interrupts assigned to various on-chip
maskable interrupts. The priority of simultaneous maskable
interrupts is linear, with IRQ47 having the highest priority.

CP3BT26

Table 20 Maskable Interrupts Assignment

IRQ Number Description

IRQ47 TWM (Timer 0)

IRQ46 Bluetooth LLC 0

IRQ45 Bluetooth LLC 1

IRQ44 Bluetooth LLC 2

IRQ43 Bluetooth LLC 3

IRQ42 Bluetooth LLC 4

IRQ41 Bluetooth LLC 5

IRQ40 USB Interface

IRQ39 DMA Channel 0

IRQ38 DMA Channel 1

IRQ37 DMA Channel 2

IRQ36 DMA Channel 3

IRQ35 CAN

IRQ34 Advanced Audio Interface (AAI)

IRQ33 UART0 RX

IRQ32 CVSD/PCM Converter

IRQ31 ACCESS.bus

IRQ30 TA (Timer input A)

IRQ29 TB (Timer input B)

IRQ28 VTUA (VTU Interrupt Request 1)

IRQ27 VTUB (VTU Interrupt Request 2)

IRQ26 VTUC (VTU Interrupt Request 3)

IRQ25 VTUD (VTU Interrupt Request 4)

IRQ Number Description

IRQ14 Reserved

IRQ13 ADC (Done)

IRQ12 MIWU Interrupt 0

IRQ11 MIWU Interrupt 1

IRQ10 MIWU Interrupt 2

IRQ9 MIWU Interrupt 3

IRQ8 MIWU Interrupt 4

IRQ7 MIWU Interrupt 5

IRQ6 MIWU Interrupt 6

IRQ5 MIWU Interrupt 7

IRQ4 Reserved

IRQ3 Random Number Generator (RNG)

IRQ2 Reserved

IRQ1 Flash Program/Data Memory

IRQ0 Reserved

All reserved interrupt vectors should point to default or error
interrupt handlers.

10.5 NESTED INTERRUPTS

Nested NMI interrupts are always enabled. Nested
maskable interrupts are disabled by default, however an in­terrupt handler can allow nested maskable interrupts by set­ting the I bit in the PSR. The LPR instruction is used to set
the I bit.

Nesting of specific maskable interrupts can be allowed by
disabling interrupts from sources for which nesting is not al­lowed, before setting the I bit. Individual maskable interrupt
sources can be disabled using the IENAM0 and IENAM1
registers.

Any number of levels of nested interrupts are allowed, limit­ed only by the available memory for the interrupt stack.

IRQ24 Microwire/SPI RX/TX

IRQ23 UART0 TX

IRQ22 UART0 CTS

IRQ21 Reserved

IRQ20 UART1 RX

IRQ19 UART1 TX

IRQ18 UART2 RX

IRQ17 UART2 TX

IRQ16 UART3 RX

IRQ15 UART3 TX

www.national.com 50

11.0 Triple Clock and Reset

The Triple Clock and Reset module generates a 12 MHz
Main Clock and a 32.768 kHz Slow Clock from external
crystal networks or external clock sources. It provides vari­ous clock signals for the rest of the chip. It also provides the
main system reset signal, a power-on reset function, Main

TWM (Invalid Watchdog Service)

Flash Interface (Program/Erase Busy)

External Reset

Reset

Power-On-Reset

Module (POR)

Clock prescalers to generate two additional low-speed
clocks, and a 32-kHz oscillator start-up delay.

Figure 4 is block diagram of the Triple Clock and Reset mod­ule.

Reset

Module

Device Reset

Stretched
Reset

CP3BT26

X1CKI

X1CKO

Main Clock

X2CKI

X2CKO

High Frequency

Oscillator

Low Frequency

Oscillator

Stop Main Osc.

Preset

Start-Up-Delay

14-Bit Timer

4-Bit Aux1

Prescaler

4-Bit Aux2

Prescaler

Div.

by 2

Slow Clock Prescaler

8-Bit

Prescaler

Start-Up-Delay

8-Bit Timer

Preset

Mux

Time-out

Fast Clock

Prescaler

4-Bit

Prescaler

Mux

Stop Main Osc

Good Main Clock

Auxiliary Clock 1

Auxiliary Clock 2

Slow Clock

Slow Clock
Select

Good Slow Clock

Stop Slow Osc

Bypass
32 kHz Osc

System Clock

PLL

(x3, x4, or x5)

Mux

Stop PLL

Figure 4. Triple Clock and Reset Module

51 www.national.com

Fast Clock
Select

PLL Clock

Bypass PLL

Good PLL Clock

Stop PLL

DS006

11.1 EXTERNAL CRYSTAL NETWORK

An external crystal network is connected to the X1CKI and
X1CKO pins to generate the Main Clock, unless an external
clock signal is driven on the X1CKI pin. A similar external

CP3BT26

crystal network may be used at pins X2CKI and X2CKO for
the Slow Clock. If an external crystal network is not used for
the Slow Clock, the Slow Clock is generated by dividing the
fast Main Clock.

The crystal network you choose may require external com­ponents different from the ones specified in this datasheet.
In this case, consult with National’s engineers for the com­ponent specifications

The crystals and other oscillator components must be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO de­vice input pins to keep the printed trace lengths to an abso­lute minimum.

Figure 5 shows the external crystal network for the X1CKI
and X1CKO pins. Figure 6 shows the external crystal net­work for the X2CKI and X2CKO pins. Table 21 shows the
component specifications for the main crystal network, and
Table 22 shows the component specifications for the 32.768
kHz crystal network.

X1CKI

12 MHz

Crystal

C1

C2

X1CKO

GND

Figure 5. Main Clock External Crystal Network

X2CKI

C1

DS189

32.768 kHz
Crystal

C2

X2CKO

GND

Figure 6. Slow Clock External Crystal Network

Table 21 Component Values of the High Frequency Crystal Circuit

Component Parameters Values Tolerance

Crystal Resonance Frequency

Ty pe
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance

12 MHz ± 20 ppm

AT- Cu t

50 Ω

7 pF

22 pF

N/A

Capacitor C1, C2 Capacitance 22 pF 20%

DS215

www.national.com 52

Table 22 Component Values of the Low Frequency Crystal Circuit

Component Parameters Values Tolerance

CP3BT26

Crystal Resonance Frequency

Ty p e
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Min. Q factor

Capacitor C1, C2 Capacitance 25 pF 20%

Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when com­bined with the parasitic capacitance of the trace, socket, and
package (which can vary from 0 to 8 pF). As a guideline, the
load capacitance is:

C1 C2×

---------------------

CL

C1 C2+

C2 > C1

C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
Q value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.

Cparasitic+=

11.2 MAIN CLOCK

The Main Clock is generated by the 12-MHz high-frequency
oscillator or driven by an external signal (typically the
LMX5252 RF chip). It can be stopped by the Power Man­agement Module to reduce power consumption during peri­ods of reduced activity. When the Main Clock is restarted, a
14-bit timer generates a Good Main Clock signal after a
start-up delay of 32,768 clock cycles. This signal is an indi­cator that the high-frequency oscillator is stable.

The Stop Main Osc signal from the Power Management
Module stops and starts the high-frequency oscillator.
When this signal is asserted, it presets the 14-bit timer to
3FFFh and stops the high-frequency oscillator. When the
signal goes inactive, the high-frequency oscillator starts and
the 14-bit timer counts down from its preset value. When the
timer reaches zero, it stops counting and asserts the Good
Main Clock signal.

11.3 SLOW CLOCK

The Slow Clock is necessary for operating the device in re­duced power modes and to provide a clock source for mod­ules such as the Timing and Watchdog Module.

The Slow Clock operates in a manner similar to the Main
Clock. The Stop Slow Osc signal from the Power Manage­ment Module stops and starts the low-frequency (32.768
kHz) oscillator. When this signal is asserted, it presets a 6­bit timer to 3Fh and disables the low-frequency oscillator.
When the signal goes inactive, the low-frequency oscillator
starts, and the 6-bit timer counts down from its preset value.
When the timer reaches zero, it stops counting and asserts

the Good Slow Clock signal, which indicates that the Slow
Clock is stable.

For systems that do not require a reduced power consump­tion mode, the external crystal network may be omitted for
the Slow Clock. In that case, the Slow Clock can be synthe­sized by dividing the Main Clock by a prescaler factor. The
prescaler circuit consists of a fixed divide-by-2 counter and
a programmable 8-bit prescaler register. This allows a
choice of clock divisors ranging from 2 to 512. The resulting
Slow Clock frequency must not exceed 100 kHz.

A software-programmable multiplexer selects either the
prescaled Main Clock or the 32.768 kHz oscillator as the
Slow Clock. At reset, the prescaled Main Clock is selected,
ensuring that the Slow Clock is always present initially. Se­lection of the 32.768 kHz oscillator as the Slow Clock dis­ables the clock prescaler, which allows the CLK1 oscillator
to be turned off, which reduces power consumption and ra­diated emissions. This can be done only if the module de­tects a toggling low-speed oscillator. If the low-speed
oscillator is not operating, the prescaler remains available
as the Slow Clock source.

11.4 PLL CLOCK

The PLL Clock is generated by the PLL from the 12 MHz
Main Clock by applying a multiplication factor of ×3, ×4, or
×5. The USB interface is clocked directly by the PLL Clock
and requires a 48 MHz clock, so a ×4 scaling factor must be
used if the USB interface is active.

To enable the PLL:

1. Set the PLL multiplication factor in PRFSC.MODE.

2. Clear the PLL power-down bit CRCTRL.PLLPWD.

3. Clear the high-frequency clock select bit CRC­TRL.FCLK.

4. Read CRCTRL.FCLK, and go back to step 3 if not clear.

The CRCTRL.FCLK bit will be clear only after the PLL has
stabilized, so software must repeat step 3 until the bit is
clear. The clock source can be switched back to the Main
Clock by setting the CRCTRL.FCLK bit.

The PRSFC register must not be modified while the System
Clock is derived from the PLL Clock. The System Clock
must be derived from the low-frequency oscillator clock
while the MODE field is modified.

32.768 kHz
Parallel

N-Cut or XY-bar

40 kΩ

2 pF

12.5 pF

40000

N/A

53 www.national.com

11.5 SYSTEM CLOCK

The System Clock drives most of the on-chip modules, in­cluding the CPU. Typically, it is driven by the Main Clock, but
it can also be driven by the PLL. In either case, the clock sig-

CP3BT26

nal is passed through a programmable divider (scale factors
from ÷1 to ÷16).

rise time. The time constant also should exceed the stabili­zation time for the high-frequency oscillator.

11.9 CLOCK AND RESET REGISTERS

Table 23 lists the clock and reset registers.

Table 23 Clock and Reset Registers

11.6 AUXILIARY CLOCKS

Auxiliary Clock 1 and Auxiliary Clock 2 are generated from
Main Clock for use by certain peripherals. Auxiliary Clock 1
is available for the Bluetooth controller and the Advanced
Audio Interface. Auxiliary Clock 2 is available for the CVSD/
PCM transcoder and the 12-bit ADC. The Auxiliary clocks
may be configured to keep these peripherals running when
the System Clock is slowed down or suspended during low­power modes.

11.7 POWER-ON RESET

The Power-On Reset circuit generates a system reset signal
at power-up and holds the signal active for a period of time
to allow the crystal oscillator to stabilize. The circuit detects
a power turn-on condition, which presets a 14-bit timer driv­en by Main Clock to a value of 3FFFh. This preset value is
defined in hardware and not programmable. Once oscilla­tion starts and the clock becomes active, the timer starts
counting down. When the count reaches zero, the 14-bit
timer stops counting and the internal reset signal is deacti­vated (unless the RESET

pin is held low).

The circuit sets a power-on reset bit on detection of a power­on condition. The CPU can read this bit to determine wheth­er a reset was caused by a power-up or by the RESET

input.

Note: The Power-On Reset circuit cannot be used to detect
a drop in the supply voltage.

11.8 EXTERNAL RESET

The active-low RESET input can be used to reset the device
at any time. When the signal goes low, it generates an inter­nal system reset signal that remains active until the RESET
signal goes high again. There is no internal pullup on this in­put, so it must be driven or pulled high externally for proper
device operation.

If the VCC power supply has slow rise-time. it may be nec­essary to use an external reset circuit to insure proper de­vice initialization. Figure 7 shows an example of an external
reset circuit.

IOVCC

IOVCC

R

C

Figure 7. External Reset Circuit

The value of R should be less than 50K ohms. The RC time
constant of the circuit should be 5 times the power supply

CP3BT2x

RESET

GND

DS216

Name Address Description

CRCTRL FF FC40h

PRSFC FF FC42h

PRSSC FF FC44h

PRSAC FF FC46h

Clock and Reset
Control Register

High Frequency Clock

Prescaler Register

Low Frequency Clock

Prescaler Register

Auxiliary Clock

Prescaler Register

11.9.1 Clock and Reset Control Register (CRCTRL)

The CRCTRL register is a byte-wide read/write register that
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as de­scribed below:

7 6 5 4 3 2 1 0

Reserved POR ACE2 ACE1 PLLPWD FCLK SCLK

SCLK The Slow Clock Select bit controls the clock

source used for the Slow Clock.

– Slow Clock driven by prescaled Main

0

Clock.

1 – Slow Clock driven by 32.768 kHz oscilla-

tor.

FCLK The Fast Clock Select bit selects between the

12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.

– The System Clock prescaler is driven by

0

the output of the PLL.

1 – The System Clock prescaler is driven by

the 12-MHz Main Clock. This is the de­fault after reset.

PLLPWD The PLL Power-Down bit controls whether the

PLL is active or powered down (Stop PLL sig­nal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is pow­ered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The

www.national.com 54

FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0 – PLL is active.

– PLL is powered down.

1

ACE1 When the Auxiliary Clock Enable bit is set and

a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Clock 1 is stopped. Auxiliary Clock 1 is used
as the clock input for the Bluetooth LLC and
the Advanced Audio Interface. After reset this
bit is clear.

– Auxiliary Clock 1 is stopped.

0

– Auxiliary Clock 1 is active if the Main

1

Clock is stable.

ACE2 When the Auxiliary Clock Enable 2 bit is set

and a stable Main Clock is provided, the Aux­iliary Clock 2 prescaler is enabled and gener­ates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Aux­iliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder and the A/D converter. After reset
this bit is clear.

– Auxiliary Clock 2 is stopped.

0

– Auxiliary Clock 2 is active if the Main

1

Clock is stable.

POR Power-On-Reset - The Power-On-Reset bit is

set when a power-turn-on condition has been
detected. This bit can only be cleared by soft­ware, not set. Writing a 1 to this bit will be ig­nored, and the previous value of the bit will be
unchanged.

– Software cleared this bit.

0

– Software has not cleared his bit since the

1

last reset.

11.9.2 High Frequency Clock Prescaler Register
(PRSFC)

The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre­quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode

7 6 4 3 0

Res MODE FCDIV

FCDIV The Fast Clock Divisor specifies the divisor

used to obtain the high-frequency System
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).

MODE The PLL MODE field specifies the operation

mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
System Clock is derived from the PLL Clock.
The System Clock must be derived from the

.)

low-frequency oscillator clock while the
MODE field is modified.

Output

MODE2:0

000 Reserved Reserved

001 Reserved Reserved

010 Reserved Reserved

011 36 MHz 3× Mode

100 48 MHz 4× Mode

101 60 MHz 5× Mode

110 Reserved Reserved

111 Reserved Reserved

11.9.3 Low Frequency Clock Prescaler Register
(PRSSC)

The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.

7 0

SCDIV The Slow Clock Divisor field specifies a divi-

sor to be used when generating the Slow
Clock from the Main Clock. The Main Clock is
divided by a value of (2 × (SCDIV + 1)) to ob­tain the Slow Clock. At reset, the SCDIV reg­ister is initialized to B6h, which generates a
Slow Clock rate of 32786.89 Hz. This is about

0.5% faster than a Slow Clock generated from
an external 32768 Hz crystal network.

11.9.4 Auxiliary Clock Prescaler Register (PRSAC)

The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to gener­ate the two auxiliary clocks from the Main Clock. The regis­ter is initialized to FFh at reset.

7 4 3 0

ACDIV2 ACDIV2

ACDIV1 The Auxiliary Clock Divisor 1 field specifies

the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).

ACDIV2 The Auxiliary Clock Divisor 2 field specifies

the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).

Frequency

(from 12 MHz

input clock)

SCDIV

Description

CP3BT26

55 www.national.com

12.0 Power Management

The Power Management Module (PMM) improves the effi­ciency of the CP3BT26 by changing the operating mode

CP3BT26

(and therefore the power consumption) according to the re­quired level of device activity. The device implements four
power modes:

 Active
 Power Save
 Idle
 Halt

Table 24 summarizes the differences between power
modes: the state of the high-frequency oscillator (on or off),
the System Clock source (clock used by most modules),
and the clock source used by the Timing and Watchdog
Module (TWM). The high-frequency oscillator generates the
12-MHz Main Clock, and the low-frequency oscillator gener­ates a 32.768 kHz clock. The Slow Clock can be driven by
the 32.768 kHz clock or a scaled version of the Main Clock.

Table 24 Power Mode Operating Summary

Mode

Active On Main Clock Slow Clock

Power Save On or Off Slow Clock Slow Clock

Idle On or Off None Slow Clock

Halt Off None None

The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the de­vice power supply pins. In Halt mode, however, Slow Clock
does not toggle, and as a result, the TWM timer and Watch­dog Module do not operate. For the Power Save and Idle
modes, the high-frequency oscillator can be turned on or off
under software control, as long as the low-frequency oscil­lator is used to drive Slow Clock.

Table 25 shows the clock sources used by the CP3BT26 de­vice modules and their behavior in each power mode.

Module

CPU On On/Off Off Off System

MIWU On On Active Active System

PMM On On On Active Slow Clock

TWM OnOnOnOffSlow Clock

USB On/Off On/Off On/Off Off PLL Clock

Bluetooth On/Off On/Off On/Off Off Aux 1 Clock

AAI On/Off On/Off On/Off Off Aux 1 Clock

CVSD/PCM On/Off On/Off On/Off Off Aux 2 Clock

ADC On/Off On/Off On/Off Off* Aux 2 Clock

All Others On/Off On/Off Off Off System

High-Frequency

Oscillator

Table 25 Module Activity Summary

Power Mode

Active

Power

Save

System

Clock

Idle Halt

TWM Clock

Clock

Source

* The Analog/Digital Converter (ADC) module is not auto­matically disabled by entering Halt mode, however its clock
is stopped so no conversions may be performed in Halt
mode. For maximum power savings, software must disable
the ADC module before entering Halt mode.

A module shown as On/Off in Table 25 may be enabled or
disabled by software. A module shown as Active continues
to operate even while its clock is suspended, which allows
wake-up events to be processed during Idle and Halt
modes.

The Random Number Generator (RNG) module has two os­cillators which operate independently of the rest of the sys­tem. For maximum power savings, software must disable
these oscillators.

12.1 ACTIVE MODE

In Active mode, the high-frequency oscillator is active and
generates the 12-MHz Main Clock. The 32.768 kHz oscilla­tor is active and may be used to generate the Slow Clock.
The PLL can be active or inactive, as required. Most on-chip
modules are driven by the System Clock. The System Clock
can be the PLL Clock after a programmable divider or the
12-MHz Main Clock. The activity of peripheral modules is
controlled by their enable bits.

Power consumption can be reduced in this mode by selec­tively disabling modules and by executing the WAIT instruc­tion. When the WAIT instruction is executed, the CPU stops
executing new instructions until it receives an interrupt sig­nal. After reset, the CP3BT26 is in Active Mode.

12.2 POWER SAVE MODE

In Power Save mode, Slow Clock is used as the System
Clock which drives the CPU and most on-chip modules. If
Slow Clock is driven by the 32.768 kHz oscillator and no on­chip module currently requires the 12-MHz Main Clock, soft­ware can disable the high-frequency oscillator to further re­duce power consumption. Auxiliary Clocks 1 and 2 can be
turned off under software control before switching to a re­duced power mode, or they may remain active as long as
Main Clock is also active. If the system does not require the
PLL output clock, the PLL can be disabled. Alternatively, the
Main Clock and the PLL can also be controlled by the Hard­ware Clock Control function, if enabled. The clock architec­ture is described in Section 11.0.

The Bluetooth LLC can either be switched to the 32 kHz
clock internally in the module, or it remains running off Aux­iliary clock 1 as long as the Main Clock and Auxiliary Clock
1 are enabled.

In Power Save mode, some modules are disabled or their
operation is restricted. Other modules, including the CPU,
continue to function normally, but operate at a reduced clock
rate. Details of each module’s activity in Power Save mode
are described in each module’s descriptions.

It is recommended to keep CPU activity at a minimum by ex­ecuting the WAIT instruction to guarantee low power con­sumption in the system.

www.national.com 56

12.3 IDLE MODE

In Idle mode, the System Clock is disabled and therefore the
clock is stopped to most modules of the device. The PLL
and the high-frequency oscillator may be disabled as con­trolled by register bits. The low-frequency oscillator remains
active. The Power Management Module (PMM) and the
Timing and Watchdog Module (TWM) continue to operate
off the Slow Clock. Auxiliary Clocks 1 and 2 can be turned
off under software control before switching to a power sav­ing mode, or they remain active as long as Main Clock is
also active. Alternatively, the 12 MHz Main Clock and the
PLL can also be controlled by the Hardware Clock Control
function, if enabled.

The Bluetooth LLC can either be switched to the Slow Clock
internally in the module or it remains running off the Auxilia­ry Clock 1 as long as the Main Clock and Auxiliary Clock 1
are enabled.

12.4 HALT MODE

In Halt mode, all the device clocks, including the System
Clock, Main Clock, and Slow Clock, are disabled. The high­frequency oscillator and PLL are turned off. The low-fre­quency oscillator continues to operate, however its circuitry
is optimized to guarantee lowest possible power consump­tion. This mode allows the device to reach the absolute min­imum power consumption without losing its state (memory,
registers, etc.).

12.5 HARDWARE CLOCK CONTROL

The Hardware Clock Control (HCC) mechanism gives the
Bluetooth Lower Link Controller (LLC) individual control
over the high-frequency oscillator and the PLL. The Blue­tooth LLC can enter a Sleep mode for a specified number of
low-frequency clock cycles. While the Bluetooth LLC is in
Sleep mode and the CP3BT26 is in Power Save or Idle
mode, the HCC mechanism may be used to control whether
the high-frequency oscillator, PLL, or both units are dis­abled.

Altogether, three mechanisms control whether the high-fre­quency oscillator is active, and four mechanisms control
whether the PLL is active:

 HCC Bits: The HCCM and HCCH bits in the PMMCR

register may be used to disable the high-frequency oscil­lator and PLL, respectively, in Power Save and Idle
modes when the Bluetooth LLC is in Sleep mode.

 Disable Bits: The DMC and DHC bits in the PMMCR

register may be used to disable the high-frequency oscil­lator and PLL, respectively, in Power Save and Idle
modes. When used to disable the high-frequency oscilla­tor or PLL, the DMC and DHC bits override the HCC
mechanism.

 Power Management Mode: Halt mode disables the

high-frequency oscillator and PLL. Active Mode enables
them. The DMC and DHC bits and the HCC mechanism
have no effect in Active or Halt mode.

 PLL Power Down Bit: The PLLPWD bit in the CRCTRL

register can be used to disable the PLL in all modes. This
bit does not affect the high-frequency oscillator.

12.6 POWER MANAGEMENT REGISTERS

Table 26 lists the power management registers.

Table 26 Power Management Registers

Name Address Description

PMMCR FF FC60h

PMMSR FF FC62h

12.6.1 Power Management Control Register (PMMCR)

The Power Management Control/Status Register (PMMCR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator in the Power Save
and Idle modes. At reset, the non-reserved bits of this reg­ister are cleared. The format of the register is shown below.

7 6 5 4 3 2 1 0

HCCH HCCM DHC DMC WBPSM HALT IDLE PSM

PSM If the Power Save Mode bit is clear and the

WBPSM bit is clear, writing 1 to the PSM bit
causes the device to start the switch to Power
Save mode. If the WBPSM bit is set when the
PSM bit is written with 1, entry into Power
Save mode is delayed until execution of a
WAIT instruction. The PSM bit becomes set
after the switch to Power Save mode is com­plete. The PSM bit can be cleared by soft­ware, and it can be cleared by hardware when
a hardware wake-up event is detected.

– Device is not in Power Save mode.

0
1 – Device is in Power Save mode.

IDLE The Idle Mode bit indicates whether the de-

vice has entered Idle mode. The WBPSM bit
must be set to enter Idle mode. When the
IDLE bit is written with 1, the device enters
IDLE mode at the execution of the next WAIT
instruction. The IDLE bit can be set and
cleared by software. It is also cleared by the
hardware when a hardware wake-up event is
detected.

– Device is not in Idle mode.

0
1

– Device is in Idle mode.

Power Management

Control Register

Power Management

Status Register

CP3BT26

57 www.national.com

HALT The Halt Mode bit indicates whether the de-

vice is in Halt mode. Before entering Halt
mode, the WBPSM bit must be set. When the

CP3BT26

WBPSM When the Wait Before Power Save Mode bit is

DMC The Disable Main Clock bit may be used to

HALT bit is written with 1, the device enters
the Halt mode at the execution of the next
WAIT instruction. When in HALT mode, the
PMM stops the System Clock and then turns
off the PLL and the high-frequency oscillator.
The HALT bit can be set and cleared by soft­ware. The Halt mode is exited by a hardware
wake-up event. When this signal is set high,
the oscillator is started. After the oscillator has
stabilized, the HALT bit is cleared by the hard­ware.

– Device is not in Halt mode.

0
1 – Device is in Halt mode.

clear, a switch from Active mode to Power
Save mode only requires setting the PSM bit.
When the WBPSM bit is set, a switch from Ac­tive mode to Power Save, Idle, or Halt mode is
performed by setting the PSM, IDLE or HALT
bit, respectively, and then executing a WAIT
instruction. Also, if the DMC or DHC bits are
set, the high-frequency oscillator and PLL
may be disabled only after a WAIT instruction
is executed and the Power Save, Idle, or Halt
mode is entered.

– Mode transitions may occur immediately.

0

– Mode transitions are delayed until the

1

next WAIT instruction is executed.

disable the high-frequency oscillator in Power
Save and Idle modes. In Active mode, the
high-frequency oscillator is enabled without
regard to the DMC value. In Halt mode, the
high-frequency oscillator is disabled without
regard to the DMC value. The DMC bit is
cleared by hardware when a hardware wake­up event is detected.

– High-frequency oscillator is only disabled

0

in Halt mode or when disabled by the
HCC mechanism.

– High-frequency oscillator is also disabled

1

in Power Save and Idle modes.

DHC The Disable High-Frequency (PLL) Clock bit

and the CRCTRL.PLLPWD bit may be used to
disable the PLL in Power Save and Idle
modes. When the DHC bit is clear (and PLL­PWD = 0), the PLL is enabled in these modes.
If the DHC bit is set, the PLL is disabled in
Power Save and Idle mode. In Active mode
with the CRCTRL.PLLPWD bit set, the PLL is
enabled without regard to the DHC value. In
Halt mode, the PLL is disabled without regard
to the DMC value. The DHC bit is cleared by
hardware when a hardware wake-up event is
detected.

– PLL is disabled only by entering Halt

0

mode or setting the CRCTRL.PLLPWD
bit.

– PLL is also disabled in Power Save or Idle

1

mode.

HCCM The Hardware Clock Control for Main Clock

bit may be used in Power Save and Idle
modes to disable the high-frequency oscillator
conditionally, depending on whether the Blue­tooth LLC is in Sleep mode. The DMC bit must
be clear for this mechanism to operate. The
HCCM bit is automatically cleared when the
device enters Active mode.

– High-frequency oscillator is disabled in

0

Power Save or Idle mode only if the DMC
bit is set.

– High-frequency oscillator is also disabled

1

if the Bluetooth LLC is idle.

HCCH The Hardware Clock Control for High-Fre-

quency (PLL) bit may be used in Power Save
and Idle modes to disable the PLL condition­ally, depending on whether the Bluetooth LLC
is in Sleep mode. The DHC bit and the CRC­TRL.PLLPWD bit must be clear for this mech­anism to operate. The HCCH bit is
automatically cleared when the device enters
Active mode.

– PLL is disabled in Power Save or Idle

0

mode only if the DMC bit or the CRC­TRL.PLLPWD bit is set.

– PLL is also disabled if the Bluetooth LLC

1

is idle.

www.national.com 58

12.6.2 Power Management Status Register (PMMSR)

The Management Status Register (PMMR) is a byte-wide,
read/write register that provides status signals for the vari­ous clocks. The reset value of PMSR register bits 0 to 2 de­pend on the status of the clock sources monitored by the
PMM. The upper 5 bits are clear after reset. The format of
the register is shown below.

7 3 2 1 0

Reserved OHC OMC OLC

OLC The Oscillating Low Frequency Clock bit indi-

cates whether the low-frequency oscillator is
producing a stable clock. When the low-fre­quency oscillator is unavailable, the PMM will
not switch to Power Save, Idle, or Halt mode.

– Low-frequency oscillator is unstable, dis-

0

abled, or not oscillating.

– Low-frequency oscillator is available.

1

OMC The Oscillating Main Clock bit indicates

whether the high-frequency oscillator is pro­ducing a stable clock. When the high-frequen­cy oscillator is unavailable, the PMM will not
switch to Active mode.

– High-frequency oscillator is unstable, dis-

0

abled, or not oscillating.

– High-frequency oscillator is available.

1

OHC The Oscillating High Frequency (PLL) Clock

bit indicates whether the PLL is producing a
stable clock. Because the PMM tests the sta­bility of the PLL clock to qualify power mode
state transitions, a stable clock is indicated
when the PLL is disabled. This removes the
stability of the PLL clock from the test when
the PLL is disabled. When the PLL is enabled
but unstable, the PMM will not switch to Active
mode.

– PLL is enabled but unstable.

0

– PLL is stable or disabled (CRCTRL.PLL-

1

PWD = 0).

12.7 SWITCHING BETWEEN POWER MODES

Switching from a higher to a lower power consumption
mode is performed by writing an appropriate value to the
Power Management Control/Status Register (PMMCR).
Switching from a lower power consumption mode to the Ac­tive mode is usually triggered by a hardware interrupt.
Figure 8 shows the four power consumption modes and the
events that trigger a transition from one mode to another.

Reset

WBPSM = 1 &
HALT = 1 &
"WAIT"

WBPSM = 1 &
IDLE = 1 &
"WAIT"

Note:
HW Event = MIWU wake-up or NMI

WBPSM = 0 & PSM = 1
or
WBPSM = 1 & PSM = 1 & "WAIT"

WBPSM = 1 & IDLE = 1 & "WAIT"

IDLE = 1

Figure 8. Power Mode State Diagram

Some of the power-up transitions are based on the occur­rence of a wake-up event. An event of this type can be either
a maskable interrupt or a non-maskable interrupt (NMI). All
of the maskable hardware wake-up events are monitored by
the Multi-Input Wake-Up (MIWU) Module, which is active in
all modes. Once a wake-up event is detected, it is latched
until an interrupt acknowledge cycle occurs or a reset is ap­plied.

A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execu­tion of the program. It is the interrupt handler associated
with the wake-up source (MIWU or NMI) that causes pro­gram execution to resume.

Active Mode

Power Save Mode

Idle Mode

Halt Mode

HW Event

HW Event

HW Event

DS008

CP3BT26

12.7.1 Active Mode to Power Save Mode

A transition from Active mode to Power Save mode is per­formed by writing a 1 to the PMMCR.PSM bit. The transition
to Power Save mode is either initiated immediately or at ex­ecution of the next WAIT instruction, depending on the state
of the PMMCR.WBPSM bit.

For an immediate transition to Power Save mode (PM­MCR.WBPSM = 0), the CPU continues to operate using the
low-frequency clock. The PMMCR.PSM bit becomes set
when the transition to the Power Save mode is completed.

For a transition at the next WAIT instruction (PM­MCR.WBPSM = 1), the CPU continues to operate in Active
mode until it executes a WAIT instruction. At execution of
the WAIT instruction, the device enters the Power Save
mode, and the CPU waits for the next interrupt event. In this
case, the PMMCR.PSM bit becomes set when it is written,
even before the WAIT instruction is executed.

59 www.national.com

12.7.2 Entering Idle Mode

Entry into Idle mode is performed by writing a 1 to the PM­MCR.IDLE bit and then executing a WAIT instruction. The
PMMCR.WBPSM bit must be set before the WAIT instruc-

CP3BT26

tion is executed. Idle mode can be entered only from the Ac­tive or Power Save mode.

12.7.3 Disabling the High-Frequency Clock

When the low-frequency oscillator is used to generate the
Slow Clock, power consumption can be reduced further in
the Power Save or Idle mode by disabling the high-frequen­cy oscillator. This is accomplished by writing a 1 to the PM­MCR.DHC bit before executing the WAIT instruction that
puts the device in the Power Save or Idle mode. The high­frequency clock is turned off only after the device enters the
Power Save or Idle mode.

The CPU operates on the low-frequency clock in Power
Save mode. It can turn off the high-frequency clock at any
time by writing a 1 to the PMMCR.DHC bit. The high-fre­quency oscillator is always enabled in Active mode and al­ways disabled in Halt mode, without regard to the
PMMCR.DHC bit setting.

Immediately after power-up and entry into Active mode,
software must wait for the low-frequency clock to become
stable before it can put the device in Power Save mode. It
should monitor the PMMSR.OLC bit for this purpose. Once
this bit is set, Slow Clock is stable and Power Save mode
can be entered.

12.7.4 Entering Halt Mode

Entry into Halt mode is accomplished by writing a 1 to the
PMMCR.HALT bit and then executing a WAIT instruction.
The PMMCR.WBPSM bit must be set before the WAIT in­struction is executed. Halt mode can be entered only from
Active or Power Save mode.

12.7.5 Software-Controlled Transition to Active Mode

A transition from Power Save mode to Active mode can be
accomplished by either a software command or a hardware
wake-up event. The software method is to write a 0 to the
PMMCR.PSM bit. The value of the register bit changes only
after the transition to the Active mode is completed.

If the high-frequency oscillator is disabled for Power Save
operation, the oscillator must be enabled and allowed to sta­bilize before the transition to Active mode. To enable the
high-frequency oscillator, software writes a 0 to the PM­MCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit,
software must first monitor the PMMSR.OMC bit to deter­mine when the oscillator has stabilized.

12.7.6 Wake-Up Transition to Active Mode

A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to Active mode. Hardware
wake-up events are:

 Non-Maskable Interrupt (NMI)
 Valid wake-up event on a Multi-Input Wake-Up channel

When a wake-up event occurs, the on-chip hardware per­forms the following steps:

1. Clears the PMMCR.DMC bit, which enables the high­frequency clock (if it was disabled).

2. Waits for the PMMSR.OMC bit to become set, which in­dicates that the high-frequency clock is operating and
is stable.

3. Clears the PMMCR.DHC bit, which enables the PLL.

4. Waits for the PMMSR.OHC bit to become set.

5. Switches the device into Active mode.

12.7.7 Power Mode Switching Protection

The Power Management Module has several mechanisms
to protect the device from malfunctions caused by missing
or unstable clock signals.

The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits
indicate the current status of the PLL, high-frequency oscil­lator, and low-frequency oscillator, respectively. Software
can check the appropriate bit before switching to a power
mode that requires the clock. A set status bit indicates an
operating, stable clock. A clear status bit indicates a clock
that is disabled, not available, or not yet stable. (Except in
the case of the PLL, which has a set status bit when dis­abled.)

During a power mode transition, if there is a request to
switch to a mode with a clear status bit, the switch is delayed
until that bit is set by the hardware.

When the system is built without an external crystal network
for the low-frequency clock, Main Clock is divided by a pres­caler factor to produce the low-frequency clock. In this situ­ation, Main Clock is disabled only in the Halt mode, and
cannot be disabled for the Power Save or Idle mode.

Without an external crystal network for the low-frequency
clock, the device comes out of Halt or Idle mode and enters
Active mode with Main Clock driving Slow Clock.

Note: For correct operation in the absence of a low-fre­quency crystal, the X2CKI pin must be tied low (not left float­ing) so that the hardware can detect the absence of the
crystal.

www.national.com 60

13.0 Multi-Input Wake-Up

The Multi-Input Wake-Up (MIWU) unit consists of two iden­tical 16-channel modules. Each module can assert a wake­up signal for exiting from a low-power mode, and each can
assert an interrupt request on any of four Interrupt Control
Unit (ICU) channels assigned to that module. The modules
operate independently, so each may assert an interrupt re­quest to the ICU. Together, these modules provide 32 MIWU
input channels and 8 interrupt request outputs.

Each 16-channel module monitors its inputs for a software­selectable trigger condition. On detection of a trigger condi­tion, the module generates an interrupt request and if en­abled, a wake-up request. A wake-up request can be used
by the power management unit to exit the Halt, Idle, or Pow­er Save mode and return to the Active mode. An interrupt
request generates an interrupt to the CPU, which allows an
interrupt handler to respond to MIWU events.

The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the in­terrupt request asserted by the MIWU that gets the CPU to
start executing code, by jumping to the corresponding inter-

CP3BT26

rupt handler. Therefore, setting up the MIWU interrupt han­dler is essential for any wake-up operation.

Each 16-channel module has four interrupt requests that
can be routed to the ICU as shown in Figure 9. Each of the
16 channels can be programmed to activate one of these
four interrupt requests.

The 32 MIWU channels are named WUI0 through WUI31,
as shown in Table 27.

Each channel can be configured to trigger on rising or falling
edges, as determined by the setting in the WK0EDG or
WK1EDG register. Each trigger event is latched into the
WK0PND or WK1PND register. If a trigger event is enabled
by its respective bit in the WK0ENA or WK1ENA register, an
active wake-up/interrupt signal is generated. Software can
determine which channel has generated the active signal by
reading the WK0PND or WK1PND register.

The MIWU is active at all times, including the Halt mode. All
device clocks are stopped in this mode. Therefore, detecting
an external trigger condition and the subsequent setting of
the pending bit are not synchronous to the System Clock.

WUI0

WUI15

WUI16

WUI31

WK0EDG
WK1EDG

0

15

WK0PND
WK1PND

Peripheral Bus

15

15

. . . . . . . . . . .

WK0IENA
WK1IENA

WK0ENA
WK1ENA

. . . . . . . . . . .

0

0

WK0ICTL1/WK0ICTL2
WK1ICTL1/WK1ICTL2

Encoder

4

MIWU Interrupt 3:0
MIWU Interrupt 7:4

Wake-Up Signal
To Power Mgt

DS218

Figure 9. Multi-Input Wake-Up Module Block Diagram

61 www.national.com

Table 27 MIWU Sources

13.1 MULTI-INPUT WAKE-UP REGISTERS

Table 28 lists the MIWU registers.

CP3BT26

MIWU Channel Source

WUI0 TWM T0OUT

WUI1 ACCESS.bus

WUI2 CANRX

WUI3 MWCS

WUI4 UART0 CTS

WUI5 UART0 RXD

WUI6 Bluetooth LLC

WUI7 AAI SFS

WUI8 USB Wake-Up

WUI9 PJ7

WUI10 PG6

WUI11 PH0

WUI12 PH1

WUI13 PH2

WUI14 PH3

Table 28 Multi-Input Wake-Up Registers

Name Address Description

Wake-Up Edge

WK0EDG FF FC80h

WK1EDG FF FCA0h

WK0ENA FF FC82h

WK1ENA FF FCA2h

WK0ICTL1 FF FC84h

WK1ICTL1 FF FCA4h

Detection Register

Module 0

Wake-Up Edge

Detection Register

Module 1

Wake-Up Enable

Register

Module 0

Wake-Up Enable

Register

Module 1

Wake-Up Interrupt

Control Register 1

Module 0

Wake-Up Interrupt

Control Register 1

Module 1

WUI15 PH4

WUI16 PH5

WUI17 PH6

WUI18 PJ0

WUI19 PJ1

WUI20 PJ2

WUI21 PJ3

WUI22 PJ4

WUI23 PJ5

WUI24 PJ6

WUI25 Reserved

WUI26 UART1 RXD

WUI27 UART2 RXD

WUI28 UART3 RXD

WUI29 Reserved

WUI30 ADC Done

WUI31 Reserved

WK0ICTL2 FF FC86h

WK1ICTL2 FF FCA6h

WK0PND FF FC88h

WK1PND FF FCA8h

WK0PCL FF FC8Ah

WK1PCL FF FCAAh

WK0IENA FF FC8Ch

WK1IENA FF FCACh

Wake-Up Interrupt

Control Register 2

Module 0

Wake-Up Interrupt

Control Register 2

Module 1

Wake-Up Pending

Register

Module 0

Wake-Up Pending

Register

Module 1

Wake-Up Pending

Clear Register

Module 0

Wake-Up Pending

Clear Register

Module 1

Wake-Up Interrupt

Enable Register

Module 0

Wake-Up Interrupt

Enable Register

Module 1

www.national.com 62

13.1.1 Wake-Up Edge Detection Register (WK0EDG)

The WK0EDG register is a word-wide read/write register
that controls the edge sensitivity of the MIWU channels. The
WK0EDG register is cleared upon reset, which configures
all channels to be triggered on rising edges. The register for­mat is shown below.

CP3BT26

13.1.4 Wake-Up 1 Enable Register (WK1ENA)

The WK1ENA register is a word-wide read/write register
that individually enables or disables wake-up events from
the MIWU channels. The WK1ENA register is cleared upon
reset, which disables all wake-up/interrupt channels. The
register format is shown below.

15 0

WKED

WKED The Wake-Up Edge Detection bits control the

edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI15:0
channels, respectively.

– Triggered on rising edge (low-to-high

0

transition).

1 – Triggered on falling edge (high-to-low

transition).

13.1.2 Wake-Up 1 Edge Detection Register (WK1EDG)

The WK1EDG register is a word-wide read/write register
that controls the edge sensitivity of the MIWU channels. The
WK1EDG register is cleared upon reset, which configures
all channels to be triggered on rising edges. The register for­mat is shown below.

15 0

WKED

WKED The Wake-Up Edge Detection bits control the

edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI31:16
channels, respectively.

– Triggered on rising edge (low-to-high

0

transition).

1 – Triggered on falling edge (high-to-low

transition).

13.1.3 Wake-Up Enable Register (WK0ENA)

The WK0ENA register is a word-wide read/write register
that individually enables or disables wake-up events from
the MIWU channels. The WK0ENA register is cleared upon
reset, which disables all wake-up/interrupt channels. The
register format is shown below.

15 0

WKEN

15 0

WKEN

WKEN The Wake-Up Enable bits enable and disable

the MIWU channels. The WKEN15:0 bits cor­respond to the WUI31:16 channels, respec­tively.

– MIWU channel wake-up events disabled.

0
1 – MIWU channel wake-up events enabled.

13.1.5 Wake-Up Interrupt Enable Register (WK0IENA)

The WK0IENA register is a word-wide read/write register
that enables and disables interrupts from the MIWU chan­nels. The register format is shown below.

15 0

WKIEN

WKIEN The Wake-Up Interrupt Enable bits control

whether MIWU channels generate interrupts.
The WKIEN15:0 bits correspond to the
WUI15:0 channels, respectively.

– Interrupt disabled.

0

– Interrupt enabled.

1

13.1.6 Wake-Up 1 Interrupt Enable Register
(WK1IENA)

The WK1IENA register is a word-wide read/write register
that enables and disables interrupts from the MIWU chan­nels. The register format is shown below.

15 0

WKIEN

WK1IEN The Wake-Up Interrupt Enable bits control

whether MIWU channels generate interrupts.
The WKIEN15:0 bits correspond to the
WUI31:16 channels, respectively.

– Interrupt disabled.

0

– Interrupt enabled.

1

WKEN The Wake-Up Enable bits enable and disable

the MIWU channels. The WKEN15:0 bits cor­respond to the WUI15:0 channels, respective­ly.

– MIWU channel wake-up events disabled.

0

– MIWU channel wake-up events enabled.

1

63 www.national.com

13.1.7 Wake-Up Interrupt Control Register 1
(WK0ICTL1)

The WK0ICTL1 register is a word-wide read/write register
that selects the interrupt request signal for the associated

CP3BT26

MIWU channels WUI7:0. At reset, the WK0ICTL1 register is
cleared, which selects MIWU Interrupt Request 0 for all
eight channels. The register format is shown below.

13.1.9 Wake-Up Interrupt Control Register 2
(WK0ICTL2)

The WK0ICTL2 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI15:8. At reset, the WK2ICTL2 register
is cleared, which selects MIWU Interrupt Request 0 for all
eight channels. The register format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

TR7

TR6

TR5

TR4

TR3

WKINTR The Wake-Up Interrupt Request Select fields

select which of the four MIWU interrupt re­quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
11 – Selects MIWU interrupt request 3.

13.1.8 Wake-Up 1 Interrupt Control Register 1
(WK1ICTL1)

The WK1ICTL1 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI23:16. At reset, the WK1ICTL1 register
is cleared, which selects MIWU Interrupt Request 4 for all
eight channels. The register format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

TR23

TR22

TR21

TR20

TR19

TR2

TR18

WKIN

TR1

WKIN
TR17

WKIN

TR0

WKIN

TR16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

TR15

TR14

TR13

TR12

TR11

TR10

WKINTR The Wake-Up Interrupt Request Select fields

select which of the four MIWU interrupt re­quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
11 – Selects MIWU interrupt request 3.

13.1.10 Wake-Up 1 Interrupt Control Register 2
(WK1ICTL2)

The WK1ICTL2 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI31:24. At reset, the WK1ICTL2 register
is cleared, which selects MIWU Interrupt Request 4 for all
eight channels. The register format is shown below.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKIN

WKIN

WKIN

WKIN

WKIN

WKIN

TR31

TR30

TR29

TR28

TR27

TR26

TR9

WKIN

TR25

TR8

WKIN

TR24

WKINTR The Wake-Up Interrupt Request Select fields

select which of the four MIWU interrupt re­quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 4.
01 – Selects MIWU interrupt request 5.
10 – Selects MIWU interrupt request 6.
11 – Selects MIWU interrupt request 7.

WKINTR The Wake-Up Interrupt Request Select fields

select which of the four MIWU interrupt re­quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 4.
01 – Selects MIWU interrupt request 5.
10 – Selects MIWU interrupt request 6.
11 – Selects MIWU interrupt request 7.

www.national.com 64

13.1.11 Wake-Up Pending Register (WK0PND)

The WK0PND register is a word-wide read/write register in
which the Multi-Input Wake-Up module latches any detect­ed trigger conditions. The CPU can only write a 1 to any bit
position in this register. If the CPU attempts to write a 0, it
has no effect on that bit. To clear a bit in this register, the
CPU must use the WK0PCL register. This implementation
prevents a potential hardware-software conflict during a
read-modify-write operation on the WK0PND register.

This register is cleared upon reset. The register format is
shown below.

15 0

WKPD

WKPD The Wake-Up Pending bits indicate which

MIWU channels have been triggered. The
WKPD15:0 bits correspond to the WUI15:0
channels. Writing 1 to a bit sets it.

– Trigger condition did not occur.

0
1 – Trigger condition occurred.

13.1.12 Wake-Up 1 Pending Register (WK1PND)

The WK1PND register is a word-wide read/write register in
which the Multi-Input Wake-Up module latches any detect­ed trigger conditions. The CPU can only write a 1 to any bit
position in this register. If the CPU attempts to write a 0, it
has no effect on that bit. To clear a bit in this register, the
CPU must use the WK1PCL register. This implementation
prevents a potential hardware-software conflict during a
read-modify-write operation on the WK1PND register.

This register is cleared upon reset. The register format is
shown below.

15 0

WKPD

13.1.13 Wake-Up Pending Clear Register (WK0PCL)

The WK0PCL register is a word-wide write-only register that
lets the CPU clear bits in the WKPND register. Writing a 1
to a bit position in the WKPCL register clears the corre­sponding bit in the WKPND register. Writing a 0 has no ef­fect. Do not modify this register with instructions that access
the register as a read-modify-write operand, such as the bit
manipulation instructions.

Reading this register location returns undefined data.
Therefore, do not use a read-modify-write sequence (such
as the SBIT instruction) to set individual bits. Do not attempt
to read the register, then perform a logical OR on the regis­ter value. Instead, write the mask directly to the register ad­dress. The register format is shown below.

15 0

WKCL

WKCL Writing 1 to a bit clears it.

– Writing 0 has no effect.

0
1 – Writing 1 clears the corresponding bit in

the WKPD register.

13.1.14 Wake-Up 1 Pending Clear Register (WK1PCL)

The WK1PCL register is a word-wide write-only register that
lets the CPU clear bits in the WK1PND register. Writing a 1
to a bit position in the WK1PCL register clears the corre­sponding bit in the WK1PND register. Writing a 0 has no ef­fect. Do not modify this register with instructions that access
the register as a read-modify-write operand, such as the bit
manipulation instructions.

Reading this register location returns undefined data.
Therefore, do not use a read-modify-write sequence (such
as the SBIT instruction) to set individual bits. Do not attempt
to read the register, then perform a logical OR on the regis­ter value. Instead, write the mask directly to the register ad­dress. The register format is shown below.

CP3BT26

WKPD The Wake-Up Pending bits indicate which

MIWU channels have been triggered. The
WKPD15:0 bits correspond to the WUI31:15
channels. Writing 1 to a bit sets it.

– Trigger condition did not occur.

0
1

– Trigger condition occurred.

15 0

WKCL

WKCL Writing 1 to a bit clears it.

– Writing 0 has no effect.

0

– Writing 1 clears the corresponding bit in

1

the WK1PD register.

65 www.national.com

13.2 PROGRAMMING PROCEDURES

To set up and use the Multi-Input Wake-Up function, use the
following procedure. Performing the steps in the order
shown will prevent false triggering of a wake-up condition.

CP3BT26

This same procedure should be used following a reset be­cause the wake-up inputs are left floating, resulting in un­known data on the input pins.

1. Clear the WK0ENA and WK1ENA registers to disable
the MIWU channels.

2. Write the WK0EDG and WK1EDG registers to select
the desired type of edge sensitivity (clear for rising
edge, set for falling edge).

3. Set all bits in the WK0PCL and WK0PCL registers to
clear any pending bits in the WK0PND and WK1PND
registers.

4. Set up the WK0ICTL1, WK1ICTL1, WK0ICTL2, and
WK1ICTL2 registers to define the interrupt request sig­nal used for each channel.

5. Set the bits in the WK0ENA and WK1ENA registers
corresponding to the wake-up channels to be activated.

To change the edge sensitivity of a wake-up channel, use
the following procedure. Performing the steps in the order
shown will prevent false triggering of a wake-up/interrupt
condition.

1. Clear the WK0ENA or WK1ENA bit associated with the
input to be reprogrammed.

2. Write the new value to the corresponding bit position in
the WK0EDG or WK1EDG register to reprogram the
edge sensitivity of the input.

3. Set the corresponding bit in the WK0PCL or WK1PCL
register to clear the pending bit in the WK0PND or
WK1PND register.

4. Set the same WK0ENA or WK1ENA bit to re-enable the
wake-up function.

www.national.com 66

14.0 Input/Output Ports

Each device has up to 54 software-configurable I/O pins, or­ganized into 8-bit ports (not all bits are used in some ports).
The ports are named Port B, Port C, Port E, Port F, Port G,
Port H, and Port J.

In addition to their general-purpose I/O capability, the I/O
pins of Ports E, F, G, H, and J have alternate functions for
use with on-chip peripheral modules such as the UART or
the Multi-Input Wake-Up unit. The alternate functions of all
I/O pins are shown in Table 94.

Ports B and C are used as the 16-bit data bus when an ex­ternal bus is enabled (144-pin devices only). This alternate
function is selected by enabling the DEV or ERE operating
environments, not by programming the port registers.

The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push­pull output, weak pull-up input, or high-impedance input.

CP3BT26

Different pins within the same port can be individually con­figured to operate in different modes.

Figure 10 is a diagram showing the I/O port pin logic. The
register bits, multiplexers, and buffers allow the port pin to
be configured into the various operating modes. The output
buffer is a TRI-STATE buffer with weak pull-up capability.
The weak pull-up, if used, prevents the port pin from going
to an undefined state when it operates as an input.

To reduce power consumption, input buffers configured for
general-purpose I/O are only enabled when they are read.
When configured for an alternate function, the input buffers
are enabled continuously. To minimize power consumption,
input signals to enabled buffers must be held within 0.2 volts
of the VCC or GND voltage.

The electrical characteristics and drive capabilities of the in­put and output buffers are described in Section 30.0.

PxALTS Register

PxALT Register

PxWKPU Register

Alt. A Device Direction

Alt. B Device Direction

PxDIR Register

Alt. A Device Data Outout

Alt. B Device Data Outout

PxDOUT Register

Alt. A Data Input

PxDIN Register

Alt. B Data Input

Data In Read Strobe

DQ

DQ

DQ

DQ

DQ

VCC

Weak Pull-Up Enable

Output Enable

Pin

Data Out

Data In

1

Analog Input

14.1 PORT REGISTERS

Each port has an associated set of memory-mapped regis­ters used for controlling the port and for holding the port da­ta:

DS190

Figure 10. I/O Port Pin Logic

 PxALT: Port alternate function register
 PxALTS: Port alternate function select register
 PxDIR: Port direction register
 PxDIN: Port data input register
 PxDOUT: Port data output register
 PxWPU: Port weak pull-up register
 PxHDRV: Port high drive strength register

67 www.national.com

Table 29 Port Registers

CP3BT26

Name Address Description

PBALT FF FB00h

PBDIR FF FB02h Port B Direction Register

PBDIN FF FB04h Port B Data Input Register

PBDOUT FF FB06h Port B Data Output Register

PBWPU FF FB08h

PBHDRV FF FB0Ah

PBALTS FF FB0Ch

PCALT FF FB10h

PCDIR FF FB12h Port C Direction Register

PCDIN FF FB14h Port C Data Input Register

PCDOUT FF FB16h Port C Data Output Register

PCWPU FF FB18h

PCHDRV FF FB1Ah

PCALTS FF FB1Ch

PEALT FF FCC0h

PEDIR FF FCC2h Port E Direction Register

PEDIN FF FCC4h Port E Data Input Register

PEDOUT FF FCC6h Port E Data Output Register

PEWPU FF FCC8h

PEHDRV FF FCCAh

PEALTS FF FCCCh

PFALT FF FCE0h

PFDIR FF FCE2h Port F Direction Register

Por t B Alternate

Function Register

Port B Weak Pull-Up

Register

Port B High Drive
Strength Register

Port B Alternate Function

Select Register

Port C Alternate

Function Register

Port C Weak Pull-Up

Register

Port C High Drive
Strength Register

Port C Alternate Function

Select Register

Por t E Alternate

Function Register

Port E Weak Pull-Up

Register

Port E High Drive
Strength Register

Port E Alternate Function

Select Register

Port F Alternate

Function Register

Table 29 Port Registers

Name Address Description

PFHDRV FF FCEAh

PFALTS FF FCECh

PGALT FF F300h

PGDIR FF F302h Port G Direction Register

PGDIN FF F304h Port G Data Input Register

PGDOUT FF F306h Port G Data Output Register

PGWPU FF F308h

PGHDRV FF F30Ah

PGALTS FF F30Ch

PHALT FF F320h

PHDIR FF F322h Port H Direction Register

PHDIN FF F324h Port H Data Input Register

PHDOUT FF F326h Port H Data Output Register

PHWPU FF F328h

PHHDRV FF F32Ah

PHALTS FF F32Ch

PJALT FF F340h

PJDIR FF F342h Port J Direction Register

PJDIN FF F344h Port J Data Input Register

PJDOUT FF F346h Port J Data Output Register

PJWPU FF F348h

PJHDRV FF F34Ah

PJALTS FF F34Ch

Port F High Drive
Strength Register

Port F Alternate Function

Select Register

Port G Alternate

Function Register

Port G Weak Pull-Up

Register

Port G High Drive
Strength Register

Port G Alternate Function

Select Register

Port H Alternate

Function Register

Port H Weak Pull-Up

Register

Port H High Drive
Strength Register

Port H Alternate Function

Select Register

Port J Alternate

Function Register

Port J Weak Pull-Up

Register

Port J High Drive

Strength Register

Port J Alternate Function

Select Register

PFDIN FF FCE4h Port F Data Input Register

PFDOUT FF FCE6h Port F Data Output Register

PFWPU FF FCE8h

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Port F Weak Pull-Up

Register

In the descriptions of the ports and port registers, the lower­case letter “x” represents the port designation, either B, C,
E, F, G, H, or J. For example, “PxDIR register” means any
one of the port direction registers: PBDIR, PCDIR, PEDIR,
PFDIR, PGDIR, PHDIR, or PJDIR.

All of the port registers are byte-wide read/write registers,
except for the port data input registers, which are read-only
registers. Each register bit controls the function of the cor­responding port pin. For example, PGDIR.2 (bit 2 of the
PGDIR register) controls the direction of port pin PG2.

14.1.1 Port Alternate Function Register (PxALT)

The PxALT registers control whether the port pins are used
for general-purpose I/O or for their alternate function. Each
port pin can be controlled independently.

A clear bit in the alternate function register causes the cor­responding pin to be used for general-purpose I/O. In this
configuration, the output buffer is controlled by the direction
register (PxDIR) and the data output register (PxDOUT).
The input buffer is visible to software as the data input reg­ister (PxDIN).

A set bit in the alternate function register (PxALT) causes
the corresponding pin to be used for its peripheral I/O func­tion. When the alternate function is selected, the output
buffer data and TRI-STATE configuration are controlled by
signals from the on-chip peripheral device.

A reset operation clears the port alternate function regis­ters, which initializes the pins as general-purpose I/O ports.
This register must be enabled before the corresponding al­ternate function is enabled.

7 0

PxALT

PxALT The PxALT bits control whether the corre-

sponding port pins are general-purpose I/O
ports or are used for their alternate function by
an on-chip peripheral.

– General-purpose I/O selected.

0
1 – Alternate function selected.

14.1.2 Port Direction Register (PxDIR)

The port direction register (PxDIR) determines whether
each port pin is used for input or for output. A clear bit in this
register causes the corresponding pin to operate as an in­put, which puts the output buffer in the high-impedance
state. A set bit causes the pin to operate as an output, which
enables the output buffer.

A reset operation clears the port direction registers, which
initializes the pins as inputs.

7 0

PxDIR

PxDIR The PxDIR bits select the direction of the cor-

responding port pin.

– Input.

0

– Output.

1

14.1.3 Port Data Input Register (PxDIN)

The data input register (PxDIN) is a read-only register that
returns the current state on each port pin. The CPU can
read this register at any time even when the pin is config­ured as an output.

7 0

PxDIN

PxDIN The PxDIN bits indicate the state on the cor-

responding port pin.

– Pin is low.

0
1 – Pin is high.

14.1.4 Port Data Output Register (PxDOUT)

The data output register (PxDOUT) holds the data to be
driven on output port pins. In this configuration, writing to
the register changes the output value. Reading the register
returns the last value written to the register.

A reset operation leaves the register contents unchanged.
At power-up, the PxDOUT registers contain unknown val­ues.

7 0

PxDOUT

PxDOUT The PxDOUT bits hold the data to be driven

on pins configured as outputs in general-pur­pose I/O mode.

– Drive the pin low.

0
1 – Drive the pin high.

14.1.5 Port Weak Pull-Up Register (PxWPU)

The weak pull-up register (PxWPU) determines whether the
port pins have a weak pull-up on the output buffer. The pull­up device, if enabled by the register bit, operates in the gen­eral-purpose I/O mode whenever the port output buffer is
disabled. In the alternate function mode, the pull-ups are al­ways disabled.

A reset operation clears the port weak pull-up registers,
which disables all pull-ups.

7 0

PxWPU

PxWPU The PxWPU bits control whether the weak

pull-up is enabled.

– Weak pull-up disabled.

0

– Weak pull-up enabled.

1

CP3BT26

69 www.national.com

14.1.6 Port High Drive Strength Register (PxHDRV)

The PxHDRV register is a byte-wide, read/write register that
controls the slew rate of the corresponding pins. The high
drive strength function is enabled when the corresponding

CP3BT26

bits of the PxHDRV register are set. In both GPIO and alter­nate function modes, the drive strength function is enabled
by the PxHDRV registers. At reset, the PxHDRV registers
are cleared, making the ports low speed.

7 0

PxHDRV

Table 30 Alternate Function Select

Port Pin PxALTS = 0 PxALTS = 1

PF7 SRD TIO8

PG0 RFSYNC Reserved

PG1 RFCE Reserved

PG2 BTSEQ1 SRCLK

PG3 SCLK Reserved

PG4 SDAT Reserved

PxHDRV The PxHDRV bits control whether output pins

are driven with slow or fast slew rate.

– Slow slew rate.

0
1 – Fast slew rate.

14.1.7 Port Alternate Function Select Register
(PxALTS)

The PxALTS register selects which of two alternate func­tions are selected for the port pin. These bits are ignored
unless the corresponding PxALT bits are set. Each port pin
can be controlled independently.

7 0

PxALTS

PxALTS The PxALTS bits select among two alternate

functions. Table 30 shows the mapping of the
PxALTS bits to the alternate functions. Un­used PxALTS bits must be clear.

Table 30 Alternate Function Select

Port Pin PxALTS = 0 PxALTS = 1

PE0 UART0 RXD0 Reserved

PE1 UART0 TXD0 Reserved

PE2 UART0 RTS Reserved

PG5 SLE

PG6 WUI10 BTSEQ2

PG7 TA BTSEQ3

PH0 UART1 RXD1 WUI11

PH1 UART1 TXD1 WUI12

PH2 UART2 RXD2 WUI13

PH3 UART2 TXD2 WUI14

PH4 UART3 RXD3 WUI15

PH5 UART3 TXD3 WUI16

PH6 CANRX WUI17

PH7 CANTX Reserved

PJ0 WUI18 Reserved

PJ1 WUI19 Reserved

PJ2 WUI20 Reserved

PJ3 WUI21 Reserved

PJ4 WUI22 Reserved

PJ5 WUI23 Reserved

PJ6 WUI24 Reserved

PJ7 ASYNC WUI9

Reserved

PE3 UART0 CTS

PE4 UART0 CKX TB

PE5 SRFS NMI

PF0 MSK TIO1

PF1 MDIDO TIO2

PF2 MDODI TIO3

PF3 MWCS

PF4 SCK TIO5

PF5 SFS TIO6

PF6 STD TIO7

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Reserved

TIO4

14.2 OPEN-DRAIN OPERATION

A port pin can be configured to operate as an inverting
open-drain output buffer. To do this, the CPU must clear the
bit in the data output register (PxDOUT) and then use the
port direction register (PxDIR) to set the value of the port
pin. With the direction register bit set (direction = out), the
value zero is forced on the pin. With the direction register bit
clear (direction = in), the pin is placed in the TRI-STATE
mode. If desired, the internal weak pull-up can be enabled
to pull the signal high when the output buffer is in TRI­STATE mode.

CP3BT26

71 www.national.com

15.0 Bluetooth Controller

The integrated hardware Bluetooth Lower Link Controller
(LLC) complies to the Bluetooth Specification Version 1.1

CP3BT26

and integrates the following functions:

 4.5K-byte dedicated Bluetooth data RAM
 1K-byte dedicated Bluetooth Sequencer RAM
 Support of all Bluetooth 1.1 packet types
 Support for fast frequency hopping of 1600 hops/s
 Access code correlation and slot timing recovery circuit
 Power Management Control Logic
 BlueRF-compatible interface to connect with National’s

LMX5252 and other RF transceiver chips

For a detailed description of the interface to the LMX5252,
consult the LMX5252 data sheet which is available from the
National Semiconductor wireless group. National provides
software libraries for using the Bluetooth LLC. Documenta­tion for the software libraries is also available from National
Semiconductor.

15.1 RF INTERFACE

The CP3BT26 interfaces to the LMX5251 or LMX5252 radio
chips though the RF interface.

Figure 11 shows the interface between the CP3BT26 and
the LMX5251 radio chip.

VCC

IOVCC VDD_DIG_IN

RFDATA

PG0/RFSYNC

CP3BT26 LMX5251

PG1/RFCE

PG3/SCLK

PG4/SDAT

PG5/SLE CCB_LATCH

X1CKI/BBCLK

Figure 11. LMX5251 Interface

TX_RX_DATA

TX_RX_SYNC

CE

CCB_CLOCK

CCB_DATA

BBP_CLOCK

DS316

Figure 12 shows the interface between the CP3BT26 and
the LMX5252 radio chip.

+2.8V

IOVCC VCC

RFDATA

PG1/RFCE

CP3BT26 LMX5252

PG2/BTSEQ1

PG3/SCLK

PG4/SDAT

PG5/SLE BDEN#

X1CKI/BBCLK

BBDATA_1

BXTLEN

BPKTCTL

BDCLK

BDDATA

BRCLK

DS320

Figure 12. LMX5252 Interface

The CP3BT26 implements a BlueRF-compatible interface,
which may be used with other RF transceiver chips.

15.1.1 RF Interface Signals

The RF interface signals are grouped as follows:

 Modem Signals (BBCLK, RFDATA, and RFSYNC)
 Control Signal (RFCE)
 Serial Interface Signals (SCLK, SDAT, and SLE

)

 Bluetooth Sequencer Status Signals (BTSEQ1,

BTSEQ2, and BTSEQ2)

X1CKI/BBCLK

The X1CKI/BBCLK pin is the input signal for the 12-MHz
clock signal. The radio chip uses this signal internally as the
12× oversampling clock and provides it externally to the
CP3BT26 for use as the Main Clock.

RFDATA

The RFDATA signal is the multiplexed Bluetooth data re­ceive and transmit signal. The data is provided at a bit rate
of 1 Mbit/s with 12× oversampling, synchronized to the 12
MHz BBCLK. The RFDATA signal is a dedicated RF inter­face pin. This signal is driven to a logic high level after reset.

RFSYNC

In receive mode (data direction from the radio chip to the
CP3BT26), the RFSYNC signal acts as the frequency cor­rection/DC compensation circuit control output to the radio
chip. The RFSYNC signal is driven low throughout the cor­relation phase and driven high when synchronization to the
received access code is achieved.

In transmit mode (data direction from the CP3BT26 to the
radio chip), the RFSYNC signal enables the RF output of
the radio chip. When the RFSYNC pin is driven high, the RF

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transmitter circuit of the radio chip is enabled, correspond­ing to the settings of the power control register in the radio
chip.

The RFSYNC signal is the alternate function of the general­purpose I/O pin PG0. At reset, this pin is in TRI-STATE
mode. Software must enable the alternate function of the
PG0 pin to give control over this signal to the RF interface.

RFCE

The RFCE signal is the chip enable output to the external
RF chip. When the RFCE signal is driven high, the RF chip
power is controlled by the settings of its power control reg­isters. When the RFCE signal is driven low, the RF chip is
powered-down. However, the serial interface is still opera­tional and the CP3BT26 can still access the RF chip internal
control registers.

The RFCE signal is the alternate function of the general­purpose I/O pin PG1. At reset, this pin is in TRI-STATE
mode. Software must enable the alternate function of the
PG1 pin to give control over this signal to the RF interface.

During Bluetooth power-down phases, the CP3BT26 pro­vides a mechanism to reduce the power consumption of an
external RF chip by driving the RFCE signal of the RF inter­face to a logic low level. This feature is available when the
Power Management Module of the CP3BT26 has enabled
the Hardware Clock Control mechanism. (However, the cur­rent version of the radio chip does not implement a power­reduction mode.)

SCLK

The SCLK signal is the serial interface shift clock output.
The CP3BT26 always acts as the master of the serial inter­face and therefore always provides the shift clock. The
SCLK signal is the alternate function of the general-purpose
I/O pin PG3. At reset, this pin is in TRI-STATE mode. Soft­ware must enable the alternate function of the PG3 pin to
give control over this signal to the RF interface.

SDAT

The SDAT signal is the multiplexed serial data receive and
transmit path between the radio chip and the CP3BT26.

The SDAT signal is the alternate function of the general-pur­pose I/O pin PG4. At reset, this pin is in TRI-STATE mode.
Software must enable the alternate function of the PG4 pin
to give control over this signal to the RF interface.

BTSEQ[3:1]

The BTSEQ[3:1] signals indicate internal states of the Blue­tooth sequencer, which are used for interfacing to some ex­ternal devices.

15.2 SERIAL INTERFACE

The radio chip register set can be accessed by the
CP3BT26 through the serial interface. The serial interface
uses three pins of the RF interface: SDAT, SCLK, and SLE

The serial interface of the CP3BT26 always operates as the
master, providing the shift clock (SCLK) and load enable

) signal to the radio chip. The radio chip always acts as

(SLE
the slave.

A 25-bit shift protocol is used to perform read/write access­es to the radio chip internal registers. The complete protocol
is comprised of the following sections:

 3-bit Header Field
 Read/Write Bit
 5-bit Address Field
 16-bit Data Field

Header

The 3-bit header contains the fixed data 101b (except for
Fast Write Operations).

Read/Write Bit

The header is followed by the read/write control bit (R/W). If
the Read/Write bit is clear, a write operation is performed
and the 16-bit data portion is copied into the addressed ra­dio chip register.

Address

The address field is used to select one of the radio chip in­ternal registers.

Data

The data field is used to transfer data to or from a radio chip
register. The timing is modified for reads, to transfer control
over the data signal from the CP3BT26 to the radio chip.

Figure 13 shows the serial interface protocol format.

15 0

Data[15:0]

CP3BT26

.

SLE

The SLE pin is the serial load enable output of the serial in­terface of the CP3BT26.

During write operations (to the radio chip registers), the data
received by the shift register of the radio chip is copied into
the address register on the next rising edge of SCLK after
the SLE

During read operations (read from the registers), the radio
chip releases the SDAT line on the next rising edge of SCLK
after the SLE

SLE
PG5. At reset, this pin is in TRI-STATE mode. Software must
enable the alternate function of the PG5 pin to give control
over this signal to the RF interface.

signal goes high.

signal goes high.

is the alternate function of the general-purpose I/O pin

24 22 21 20 16

Header[2:0] R/W Address[4:0]

Figure 13. Serial Interface Protocol Format

Data is transferred on the serial interface with the most sig­nificant bit (MSB) first.

73 www.national.com

Write Operation

When the R/W bit is clear, the 16 bits of the data field are
shifted out of the CP3BT26 on the falling edge of SCLK.
Data is sampled by the radio chip on the rising edge of

CP3BT26

SCLK. When SLE

is high, the 16-bit data are copied into the
radio chip register on the next rising edge of SCLK. The
data is loaded in the appropriate radio chip register depend­ing on the state of the four address bits, Address[4:0].
Figure 14 shows the timing for the write operation.

SDAT

used to address the write-only registers of the radio chip.
Fast writes load the same physical register as the corre­sponding normal write operation.

For the power control and CMOS output registers of the RF
chip, it is only necessary to transmit a total of 8 bits (3 ad­dress bits and 5 data bits), because the remaining eight bits
are unused.

While the FW bit is set, normal Read/Write operations are
still valid and may be used to access non-time-critical con­trol registers. Figure 16 shows the timing for a 16-bit Fast-

D0D14A0A1A2A3A4WH0H1H2 D15

Write transaction, and Figure 17 shows the timing for an 8­bit Fast-Write transaction.

SCLK

SLE

DS012

Figure 14. Serial Interface Write Timing

Read Operation

When the R/W bit is set, data is shifted out of the radio chip
on the rising edge of SCLK. Data is sampled by the
CP3BT26 on the falling edge of SCLK. On reception of the
read command (R/W = 1), the radio chip takes control of the
serial interface data line. The received 16-bit data is loaded
by the CP3BT26 after the first falling edge of SCLK when

is high. When SLE is high, the radio chip releases the

SLE
SDAT line again on the next rising edge of SCLK. The
CP3BT26 takes control of the SDAT line again after the fol­lowing rising edge of SCLK. Which radio chip register is
read, depends on the state of the four address bits, Ad­dress[4:0]. The transfer is always 16 bits, without regard to
the actual size of the register. Unimplemented bits contain
undefined data. Figure 15 shows the timing for the read op­eration.

SDAT Floating

Master drives SDAT

SDAT

SCLK

SLE

Slave drives SDAT

D0D1A0A1A2A3A4RH0H1H2 D15

DS013

Figure 15. Serial Interface Read Timing

Fast-Write Operation

An enhanced serial interface mode including fast write ca­pability is enabled when the FW bit in the radio chip is set.
This bit activates a mode with decreased addressing and
control overhead, which allows fast loading of time-critical
registers during normal operation. When the FW bit is set,
the 3-bit header may have a value other than 101b, and it is

SDAT

SCLK

SLE

D8 D7 D6 D1 D0D9D10D11D12A0A1A2

DS014

Figure 16. Serial Interface 16-bit Fast-Write Timing

SDAT

SCLK

SLE

D8D9D10D11D12A0A1A2

DS015

Figure 17. Serial Interface 8-bit Fast-Write Timing

32-Bit Write Operation

On the LMX5252, a 32-bit register is loaded by writing to the
same register address twice. The first write loads the high
word (bits 31:16), and the second write loads the low word
(bits 15:0). The two writes must be separated by at least two
clock cycles. For a 4-MHz clock, the minimum separation
time is 500 ns.

The value read from a 32-bit register is a counter value, not
the contents of the register. The counter value indicates
which words have been written. If the high word has been
written, the counter reads as 0000h. If both words have
been written, the counter reads as 0001h. The value re­turned by reading a 32-bit register is independent of the
contents of the register.

Figure 18 and Figure 19 show the timing for 32-bit register
writing and reading.

The order for accessing the registers is from high to low: 17,
15, 14, 12, 11, 10, 9, 8, 7, 6, 5, 4, 2, and 1. These registers
must be written during the initialization of the LMX5252.

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CP3BT26

SDAT

SCLK

SLE

D16D30A0A1A2A3A4WH0H1H2 D31 D0D14A0A1A2A3A4WH0H1H2 D15

>500 ns

Figure 18. 32-Bit Write Timing

SDAT

SCLK

SLE

D16D31A0A1A2A3A4RH0H1H2 D0D15A0A1A2A3A4RH0H1H2

>500 ns

Figure 19. 32-Bit Read Timing

An example of a 32-bit write is shown in Table 31. In this ex­ample, the 32-bit value FFFF DC04h is written to register
address 0Ah. In cycle 1, the high word (FFFFh) is written. In
the first part of cycle 2, the CP3BT26 drives the header, R/
W bit, and register address for a read cycle. In the second
part of cycle 2, the LMX5252 drives the counter value. The

Table 31 Example of 32-Bit Write with Interleaved Reads

DS322

DS323

counter value is 0, which indicates one word has been writ­ten. In cycle 3, the low word (DC04h) is written. In the first
part of cycle 4, the CP3BT26 drives the header, R/W bit,
and register address for a read cycle. In the second part of
cycle 4, the LMX5252 drives the counter value. The counter
value is 1, which indicates two words have been written.

Cycle Serial Data on SDAT Description

101 0 01010 1111111111111111

1

101 1 01010

2

0000000000000000

101 0 01010 1101110000000100

3

101 1 01010

4

0000000000000001

Write cycle driven by CP3BT26. Data is FFFFh. Address is 0Ah.

First part of read cycle driven by CP3BT26. Address is 0Ah.

Second part of read cycle driven by LMX5252. Counter value is 0.

Write cycle driven by CP3BT26. Data is DC04h. Address is 0Ah.

First part of read cycle driven by CP3BT26. Address is 0Ah.

Second part of read cycle driven by LMX5252. Counter value is 1.

75 www.national.com

15.3 LMX5251 POWER-UP SEQUENCE

To power-up a Bluetooth system based on the CP3BT26
and LMX5251 devices, the following sequence must be per­formed:

CP3BT26

1. Apply VDD to the LMX5251.

2. Apply IOVCC and VCC to the CP3BT26.

3. Drive the RESET# pin of the LMX5251 high a minimum
of 2 ms after the LMX5251 and CP3000 supply rails are
powered up. This resets the LMX5251 and CP3BT26.

4. After internal Power-On Reset (POR) of the CP3BT26,
the RFDATA pin is driven high. The RFCE, RFSYNC,
and SDAT pins are in TRI-STATE mode. Internal pull­up/pull-down resistors on the CCB_CLOCK (SCLK),
CCB_DATA (SDAT), CCB_LATCH (SLE
TX_RX_SYNC (RFSYNC) inputs of the LMX5251 pull
these signals to states required during the power-up
sequence.

5. When the RFDATA pin is driven high, the LMX5251 en­ables its oscillator. After an oscillator start-up delay, the
LMX5251 drives a stable 12-MHz BBP_CLOCK
(BBCLK) to the CP3BT26.

6. The Bluetooth baseband processor on the CP3BT26
now directly controls the RF interface pins and drives
the logic levels required during the power-up phase.
When the RFCE pin is driven high, the LMX5251
switches from “power-up” to “normal” mode and dis­ables the internal pull-up/pull-down resistors on its RF
interface inputs.

7. In “normal” mode, the oscillator of the LMX5251 is con­trolled by the RFCE signal. Driving RFCE high enables
the oscillator, and the LMX5251 drives its BBP_CLOCK
(BBCLK) output.

), and

15.4 LMX5252 POWER-UP SEQUENCE

A Bluetooth system based on the CP3BT26 and LMX5252
devices has the following states:

 Off—When the LMX5252 enters Off mode, all configura-

tion data is lost. In this state, the LMX5252 drives BPOR
low.

 Power-Up—When the power supply is on and the

LMX5252 RESET# input is high, the LMX5252 starts up
its crystal oscillator and enters Power-Up mode. After the
crystal oscillator is settled, the LMX5252 sends four
clock cycles on BRCLK (BBCLK) before driving BPOR
high.

 RF Init—The baseband controller on the CP3BT26 now

drives RFCE high and takes control of the crystal oscilla­tor. The baseband performs all the needed initialization
(such as writing the registers in the LMX5252 and crystal
oscillator trim).

 Idle—The baseband controller on the CP3BT26 drives

RFDATA low when the initialization is ready. The
LMX5252 is now ready to start transmitting, receiving, or
enter Sleep mode.

 Sleep—The LMX5252 can be forced into Sleep mode at

any time by driving RFCE low. All configuration settings
are kept, only the Bluetooth low power clock is running
(B3k2).

 Wait XTL—When RFCE goes high, the crystal oscillator

becomes operational. When it is stable, the LMX5252
enters Idle mode and drives BRCLK (BBCLK).

Any State

RESET# = Low or
Power is cycled

VDD

LMX5251

VCC

CP3000

IOVCC

RESET#
RESET

RFCE

BBCLK

RFDATA

RFSYNC

SDAT

SCLK

SLE

CP3000

LMX5251

CP3000

t

PTOR

Low

Low

High

Low

Low

Low

LMX5251
Oscillator

Start-Up

Power-Up Mode

CP3000

Initialization

LMX5251

Initialization

LMX5251 in Normal ModeLMX5251 in

Figure 20. LMX5251 Power-Up Sequence

High

Standby

Active

DS016

Wait for

Crystal Osc.

To Stabilize

RFCE = High

RFDATA = Don't Care

Write Registers

Off

RESET# = High and
Power is On

Power-Up

Crystal Osc. Stable

RF Init

Wait for

Crystal Osc.

To Stabilize

Idle

Any State

After RF Init

RFCE = Low

Sleep

RFCE = High

Wait XTL

Crystal Osc. Stable

DS324

Figure 21. LMX5252 Power States

The power-up sequence for a Bluetooth system based on
the CP3BT26 and LMX5252 devices is shown in Figure 22.

www.national.com 76

RESET

RFDATA

RFCE

BBCLK

BPOR

B3k2

SLE

SCLK

SDAT

t1

t2

t5

t3

t4

DS321

Figure 22. LMX5252 Power-Up Sequence

15.5 BLUETOOTH SLEEP MODE

The Bluetooth controller is capable of putting itself into a
sleep mode for a specified number of Slow Clock cycles. In
this mode, the controller clocks are stopped internally. The
only circuitry which remains active are two counters
(counter N and counter M) running at the Slow Clock rate.
These counters determine the duration of the sleep mode.

The sequence of events when entering the LLC sleep mode
is as follows:

1. The current Bluetooth counter contents are read by the
CPU.

2. Software “estimates” the Bluetooth counter value after
leaving the sleep mode.

3. The new Bluetooth counter value is written into the
Bluetooth counter register.

4. The Bluetooth sequencer RAM is updated with the
code required by the Bluetooth sequencer to enter/exit
Sleep mode.

5. The Bluetooth sequencer RAM and the Bluetooth LLC
registers are switched from the System Clock domain
to the local 12 MHz Bluetooth clock domain. At this
point, the Bluetooth sequencer RAM and Bluetooth
LLC registers cannot be updated by the CPU, because
the CPU no longer has access to the Bluetooth LLC.

6. Hardware Clock Control (HCC) is enabled, and the
CP3BT26 enters a power-saving mode (Power Save or
Idle mode). While in Power Save mode, the Slow Clock
is used as the System Clock. While in Idle mode, the
System Clock is turned off.

7. The Bluetooth sequencer checks if HCC is enabled. If
HCC is enabled, the sequencer asserts HCC to the
PMM. On the next rising edge of the low-frequency
clock, the 1MHz clock and the 12 MHz clock are
stopped locally within the Bluetooth LLC. At this point,
the Bluetooth sequencer is stopped.

8. The M-counter starts counting. After M + 1 Slow Clock
cycles, the HCC signal to the PMM is deasserted.

9. The PMM restarts the 12 MHz Main Clock (and the
PLL, if required). The N-counter starts counting. After
N + 1 Slow Clock cycles, the Bluetooth clocks (1 MHz

and 12 MHz) are turned on again. The Bluetooth se­quencer starts operating.

10. The Bluetooth sequencer waits for the completion of
the sleep mode. When completed, the Bluetooth se­quencer asserts a wake-up signal to the MIWU (see
Section 13.0).

11. The PMM switches the System Clock to the high-fre­quency clock and the CP3BT26 enters Active mode
again. HCC is disabled. The Bluetooth sequencer RAM
and Bluetooth LLC registers are switched back from the
local 12 MHz Bluetooth clock to the System Clock. At
this point, the Bluetooth sequencer RAM and Bluetooth
LLC registers are once again accessible by the CPU. If
enabled, an interrupt is issued to the CPU.

CPU

System Clock

HCC

BT LCC Clock

HCC

12 MHz

Main Clock

1 MHz/12 MHz

BT Clock

Sequencer

Active

Power Save

Active

Stopped/Slow

Enabled

Disabled

System Clock

Main Clock

Asserted

Deasserted

Active

Stopped

Active

Stopped

Active

Stopped

Prepare for

Sleep Mode

CPU

Start-up

N

M

CPU Handles
Wake-Up IRQ
from MIWU

DS017

Figure 23. Bluetooth Sleep Mode Sequence

15.6 BLUETOOTH GLOBAL REGISTERS

Table 32 shows the memory map of the Bluetooth LLC glo­bal registers.

Table 32 Memory Map of Bluetooth Global Registers

Address

(offset from 0E F180h)

–0048h Global LLC Configuration

0000h

Description

0049h–007Fh Unused

15.7 BLUETOOTH SEQUENCER RAM

The sequencer RAM is a 1K memory-mapped section of
RAM that contains the sequencer program. This RAM can
be read and written by the CPU in the same way as the Stat­ic RAM space and can also be read by the sequencer in the
Bluetooth LLC. Arbitration between these devices is per­formed in hardware.

CP3BT26

77 www.national.com

15.8 BLUETOOTH SHARED DATA RAM

The shared data RAM is a 4.5K memory-mapped section of
RAM that contains the link control data, RF programming
look-up table, and the link payload. This RAM can be read

CP3BT26

and written in the same way as the Static RAM space and
can also be read by the sequencer in the Bluetooth LLC. Ar­bitration between these devices is performed in hardware.
Table 33 shows the memory map of the Bluetooth LLC
shared Data RAM.

Table 33 Memory Map of Bluetooth Shared RAM

Address

(offset from 0E 8000h)

h–01D9h

0000

–01FFh Unused

01DAh

0200h–023Fh Link Control 0

0240h–027Fh Link Control 1

0280h–02BFh Link Control 2

02C0h–02FFh Link Control 3

0300h–033Fh Link Control 4

0340h–037Fh Link Control 5

0380h–03BFh Link Control 6

03C0h–03FFh Link Control 7

0400h–11FFh Link Payload 0–6

Description

RF Programming

Look-up Table

www.national.com 78

16.0 12-Bit Analog to Digital Converter

The integrated 12-bit ADC provides the following features:

 8-input analog multiplexer
 8 single-ended channels or 4 differential channels
 External filtering capability
 12-bit resolution with 11-bit accuracy
 Sign bit

CP3BT26

 15-microsecond conversion time
 Support for resistive touchscreen interface
 Internal or external start trigger
 Programmable start delay after start trigger
 Poll or interrupt on done

ADC0/TSX+

ADC1/TSY-

ADC2/TSX-

ADC3/TSY+

ADC4

ADC7

ASYNC

Pen-Down Detector

DRV

DRV

DRV

DRV

TOUCH_CFG

TRIGGER

MUXOUT0

ADC_DIV

Input

Multi-

plexer

MUX_CFG

DELAY1

MUXOUT1 ADCIN

+

-

CLKDIV

ADC2ADC0AVCC ADC1VREFP ADC3AGND

PREF_CFG NREF_CFG

Int/Ext

Multi­plexer

ADCIN

ADC Clock

Start

+

-

Clock

DELAY2

12-BIT ADC

Control

ADC

SEQUENCER

VREFNVREFP

Result

4-Word

FIFO

12

Pen Down

Done

Wake-Up
(WUI30)

Interrupt
(IRQ13)

ADC_CONTROL

ADC_DELAY1

System

Clock

Auxiliary
Clock 2

CLKSEL

Figure 24. Analog to Digital Converter Block Diagram

16.1 FUNCTIONAL DESCRIPTION

The ADC module consists of a 12-bit ADC converter and as­sociated state machine, together with analog multiplexers to
set up signal paths for sampling and voltage references, log­ic to control triggering of the converter, and a bus interface.

16.1.1 Data Path

Up to 8 GPIO pins may be configured as 8 singled-ended
analog inputs or 4 differential pairs. Analog/digital data
passes through four main blocks in the ADC module be­tween the input pins and the CPU bus:

 Input Multiplexer—an analog multiplexer that selects

among the input channels.

 Internal/External Multiplexer—an analog multiplexer

that selects between the output of the Input Multiplexer
and the ADCIN external analog input.

ADC_DELAY2

ADCRESLT

System
Bus
Interface

DS183

 12-Bit ADC—receives the output of the Internal/External

Multiplexer and performs the analog to digital conver­sion.

 ADCRESLT Register—makes conversion results from

the 12-Bit ADC available to the on-chip bus. The AD­CRESLT register includes the software-visible end of a 4­word FIFO used to queue conversion results.

The configuration of the analog signal paths is controlled by
fields in the ADCGCR register. The Input Multiplexer is con­trolled by the MUX_CFG field. The Internal/External Multi­plexer is controlled by the ADCIN bit. The analog
multiplexers for selecting the voltage references used by the
ADC are controlled by the PREF_CFG and NREF_CFG
fields. The low-ohmic drivers used for interface to resistive
touchscreens are controlled by the TOUCH_CFG field.

79 www.national.com

The output of the Input Multiplexer is available externally as
the MUXOUT0 and MUXOUT1 signals. In single-ended
mode, only MUXOUT0 is used. In differential mode,
MUXOUT0 is the positive side and MUXOUT1 is the nega-

CP3BT26

tive side. The MUXOUT0 and MUXOUT1 outputs and the
ADCIN external analog input are provided so that external
signal conditioning circuits (such as filters) may be applied
to the analog signals before conversion. The MUXOUT0,
MUXOUT1, and ADCIN signals are alternate functions of
GPIO pins used by the Input Multiplexer, so the number of
available analog input channels is reduced when these sig­nals are used.

16.1.2 Operation

The TRIGGER block may be configured to initiate a conver­sion from either of these sources:

 External ASYNC Input—an edge on the ASYNC input

triggers a conversion. This input may be configured to be
sensitive to rising or falling edges, as controlled by the
POL bit in the ADCCNTRL register.

 ADCSTART Register—writing any value to the ADC-

START register triggers a conversion.

The TRIGGER block incorporates a glitch filter to suppress
transient spikes on the ASYNC input. The TRIGGER block
will recognize ASYNC pulse widths of 10 ns or greater.
Once a trigger event has been recognized, no further trig­gering is recognized until the conversion is completed.

When the ASYNC input is selected as the trigger source, it
may be configured for automatic or non-automatic mode, as
controlled by the AUTO bit in the ADCCNTRL register:

 Automatic Mode—a conversion is triggered by any

qualified edge on the ASYNC input (unless a conversion
is already in progress).

 Non-Automatic Mode—before a conversion may be

triggered from the ASYNC input, software must “prime”
the TRIGGER block by writing the ADCSTART register.
Once the TRIGGER block is primed, a conversion is trig­gered by any qualified edge on the ASYNC input. After
the conversion is completed, no additional trigger events
will be recognized until software once again primes the
TRIGGER block by writing the ADCSTART register.

Once a trigger event is recognized, the DELAY1 block waits
for a programmable delay specified in the ADC_DELAY1
field of the ADCSCDLY register. Then, it asserts the Start
signal to the ADC SEQUENCER block.

When the Start signal is received, the ADC SEQUENCER
block initiates the conversion in the 12-Bit ADC. After the
conversion is complete, the result is loaded into the FIFO,
and the Done signal is asserted.

The ADCRESLT register includes the software-visible end
of a 4-word FIFO, which allows up to 4 conversion results to
be queued for reading. Reading the ADCRESLT register un­loads the FIFO. If the FIFO overflows, a bit is set in the AD­CRESLT register, and the most recent conversion data is
lost.

The Done signal is visible to software as the ADC_DONE bit
in the ADCRESLT register. The Done signal is also an input
to the interrupt controller (IRQ13). The interrupt will be as­serted whenever the FIFO is not empty (but will deassert for

one system clock after the ADCRESLT register is read). To­tal conversion time is around 15 microseconds.

The Done signal is also an input to the Multi-Input Wake-Up
unit (WUI30). The MIWU input is asserted whenever the
FIFO is not empty (but will deassert for one system clock af­ter the ADCRESLT register is read). The wake-up output is
provided so that the ADC module can bring the system out
of a power-saving mode when a conversion operation is
completed. It asserts earlier than the interrupt output. In the
pen-down detection mode of the ADC, the wake-up output
is ORed with the ADC pen-down detector output, to wake up
on a pen-down event.

16.1.3 ADC Clock Generation

The DELAY2 block generates ADC Clock, which is the clock
used internally by the ADC module. ADC Clock is derived
from either:

 System Clock—a programmable divider is available to

generate the 12 MHz clock required by the ADC from the
System Clock.

 Auxiliary Clock 2—may be used to perform conversions

when the System Clock is slowed down or suspended in
low-power modes.

The DELAY2 block receives the clock source selected by
the CLKSEL bit of the ADCACR register and adds a number
of asynchronous incremental delay units specified in the
ADC_DELAY2 field of the ADCSCDLY register. This de­layed clock (ADC Clock) then drives the TRIGGER, 12-BIT
ADC, and ADC SEQUENCER blocks. ADC Clock also
drives the ADC_DIV clock divider, which generates the
clock which drives the DELAY1 block.

Because the ADCRESLT FIFO is driven by System Clock
(not ADC Clock), a conversion result will not propagate to
the output of the FIFO when the System Clock is suspend­ed.

16.1.4 ADC Voltage References

The 12-BIT ADC block has positive and negative voltage
reference inputs, VREFP and VREFN. In single-ended
mode, only VREFP is used. An analog multiplexer allows
selecting an external VREFP pin, the analog supply voltage
AVCC, or the analog inputs ADC0 or ADC1 as the positive
voltage reference, as controlled by the PREF_CFG field of
the ADCGCR register. Another analog multiplexer allows
selecting the analog ground AGND or the analog inputs
ADC2 or ADC3 as the negative voltage reference, as con­trolled by the NREF_CFG field of the ADCGCR register.

16.1.5 Pen-Down Detector

A pen-down detector is provided on the ADC0 (TSX+) input
of the ADC. It consists of a Schmitt-trigger receiver, with a
minimum Vil of 0.7V. When pen-down detect mode is en­abled by loading 101b into the TOUCH_CFG field of the AD­CGCR register, the output of this detector is visible to
software in the PEN_DOWN bit of the ADCRESLT register,
and this output is ORed with the Done signal to become the
wake-up input (WUI30) to the Multi-Input Wake-Up unit.

www.national.com 80

16.2 TOUCHSCREEN INTERFACE

The ADC provides an interface for 4-wire resistive touch­screens with the resolution necessary for applications such
as signature analysis. A typical touchscreen configuration is
shown in Figure 25.

TSX+/ADC0

CP3BT26

16.2.1 Touchscreen Driver Configuration

An equivalent circuit for the touchscreen interface is shown
in Figure 26.

VCC

TSY+/ADC1

TSX-/ADC2

TSY-/ADC3

MUXOUT0

ADCIN

DS186

Figure 25. Touchscreen Interface

A touchscreen consists of two resistive plates normally sep­arated from each other. The TSX+ and TSX- signals are
connected to opposite ends of the X plate, while the TSY+
and TSY- signals are connected to the Y plate. If the pen is
down, the plates will be shorted together at the point of pen
contact. The location of the pen is sensed by driving one
end of a plate to VCC, driving the opposite end to ground,
and sensing the voltage at the point of pen contact using the
other plate. This is done twice, once for each coordinate.

An external RC low-pass filter is used to remove noise cou­pled to the touchscreen signals from the display drivers.

Ω 6Ω

6

TSY

+

TSX+

To ADC

TSX-

TSY

6Ω 6Ω

X Plate

RX1

A

RX2

-

Y Plate

RY1

RZ

B

RY2

DS187

Figure 26. Touchscreen Driver Equivalent Circuit

Low-ohmic drivers are provided to pull the TSX+ and TSY+
signals to VCC and the TSX- and TSY- signals to GND. The
on-resistance of these drivers is specified to be 6 ohms.

Two measurements are used to produce one (x,y) position
coordinate pair. To measure the x-coordinate, the TSX+ sig­nal is pulled to VCC, the TSX- signal is pulled to GND, and
the TSY+ and TSY- signals are undriven. A voltage divider
is formed across the X plate, with the center tap of the divid­er being the point of pen contact, represented in Figure 26
by node A. With TSY+ and TSY- undriven, the voltage at
node A can be measured by sampling either of the TSY+ or
TSY- signals. This voltage will be proportional to the position
of the pen contact on the X plate.

The position of the pen contact on the Y plate is measured
similarly, by driving the TSY+ signal to VCC, the TSY- signal
to GND, and leaving the TSX+ and TSX- signals undriven.
The voltage at node B can be sampled from either the TSX+
or TSX- signals. The TOUCH_CFG field of the ADCGCR
register specifies the configuration of the drivers, with 010b
used to sample node A and 001b used to sample node B.

Typically, two consecutive measurements are made of each
coordinate so that any interference coupled from the LCD
column drivers is averaged out.

The plate-to-plate resistance is shown in Figure 26 as RZ.
This measurement is used as an indication of the force of
pen contact. When 100b is loaded into the TOUCH_CFG
field, the TSY+ signal is pulled to VCC and the TSX- signal
is pulled to GND, to support measuring RZ.

81 www.national.com

16.2.2 Measuring Pen Force

Figure 27 shows equivalent circuits for the driver modes
used to measure the X, Y, and Z coordinates, in which Z rep­resents pen force. In this discussion, the ohmic resistance

CP3BT26

of the drivers is neglected (see Section 16.2.3), and series
resistance between the node of interest and the ADC is ig­nored because it has no significant effect.

VCC

VCC

VCC

RY1

Solving for RY1, the resistance is:

RY1 RYP 1

×=





2047

B





-------------

–

Now that the resistance values RX2 and RY1 are known, it
is possible to calculate the value of the plate-to-plate con­tact resistance, RZ, given the value measured at node C on
the TSX+ input in Sample Z mode. Node C is a tap in a re­sistor-divider network composed of three resistors, such
that:

C

------------­2047

RX2

----------------------------------------------=
RY1 RZ RX2++

RX1

RX2

Sample X

TOUCH_CFG = 001

A

TOUCH_CFG = 010

RY1

RY2

Sample Y

B

TOUCH_CFG = 100

RZ

C

RX2

Sample Z

DS188

Figure 27. Touchscreen Driver Modes

In the following examples, the ADC is assumed to operate
in single-ended mode to produce conversion values be­tween 0 and 2047, however the same principles could be
extended to differential mode to recover the full range of the
ADC.

In Sample X mode, the X plate is driven between VCC and
ground, so that a value measured at node A on the TSY+ or
TSY- inputs is the center tap of a resistor-divider network.
The end-to-end resistance RXP of the X plate is:

RXP RX1 RX2+=

The value measured at node A is proportional to the ratio
between the resistance to ground and the resistance of the
X plate:

A

------------­2047

RX2

-------------=
RXP

Solving for RX2, the resistance is:

A



-------------

RX2 RXP

×=



2047

Similarly, in Sample Y mode the value measured at node B
on the TSX+ or TSX- inputs is proportional to the ratio be­tween the resistance to ground and the resistance RYP of
the Y plate:

B

------------­2047

RY2

-------------=
RYP

Because end-to-end resistance RYP of the Y plate is:

RYP RY1 RY2+=

The previous equation can be rewritten as:

B

------------­2047

RYP RY1–

-------------------------------=
RYP

Solving for RZ, the resistance is:

2047 C–



RZ RX2





-----------------------

×



C

RY1–=

The resistance RZ is proportional to the force of pen con­tact.

16.2.3 Compensation for Driver Resistance

Plate resistances between opposite electrodes range from
100 ohms to 1k ohm. Because of the 6-ohm driver resis­tance, some significant voltage drop will be experienced be­tween, for example, TSX- and AGND. A 200-ohm plate will
drop:

6



-----------------------------



200 6 6++

AVCC AGND–()×

With a 2.5V supply, this is 70 mV. A 12-bit ADC has 4096
possible values, so each value covers a range of 610 µV at

2.5V. A voltage drop of 70 mV across each of the low-ohmic
drivers reduces the number of available ADC values by:

70 mV 2×

--------------------------

610 uV

230=

This effective loss of resolution can be handled in a number
of ways.

1. The voltages on, for example, TSY+ and TSY- can be
sampled before sampling TSX+ and TSX-. Then, scal­ing can be applied in software to convert the samples
to the full (4096-bit) range. This technique will not re­cover any resolution, however it is worthy of some con­sideration because touchscreen data is typically
passed to two applications:
Signature Analysis—only the raw data is required. No
absolute positioning is necessary.
Screen Overlay—for example, for cursor positioning.
In this application, a scaling or calibration is performed
to correctly overlay the touchscreen coordinates onto
the display. Because of this calibration, it is not even
necessary to sample TSY+ and TSY-.

2. The ADC has a positive voltage reference input which
can be internally connected to the TSY+ terminal. This
means that the number of available ADC values is in­creased to:

70 mV



4096

--------------------

– 3981=



610 uV

Software scaling could be applied to this value if re­quired (as with technique 1, above), but no additional
resolution is achieved.

www.national.com 82

3. By extension, the ADC negative voltage reference can
be internally connected to the TSY- terminal, to recover
the full 4096 values.

The Global Configuration Register (ADCGCR) provides the
flexibility to implement any of these techniques.

16.3 ADC OPERATION IN POWER-SAVING
MODES

To reduce the level of switching noise in the environment of
the ADC, it is possible to operate the CP3BT26 in low-power
modes, in which the System Clock is slowed or switched off.
Under these conditions, Auxiliary Clock 2 can be selected
as the clock source for the ADC module, however conver­sion results cannot be read by the system while the System
Clock is suspended. The expected operation in power-sav­ing modes is therefore:

1. ADC is configured and a conversion is primed or trig­gered.

2. A power-saving mode is entered.

3. ADC conversion completes and a wake-up signal is as­serted to the MIWU unit.

4. Device wakes up and processes the conversion result.

To conserve power, the ADC should be disabled before en­tering a low-power mode if its function is not required.

16.5 ADC REGISTER SET

Table 34 lists the ADC registers.

Table 34 ADC Registers

Name Address Description

ADCGCR FF F3C0h

ADCACR FF F3C2h

ADCCNTRL FF F3C4h

ADCSTART FF F3C6h

ADCSCDLY FF F3C8h

ADCRESLT FF F3CAh ADC Result Register

ADC Global

Configuration Register

ADC Auxiliary

Configuration Register

ADC Conversion

Control Register

ADC Start Conversion

Register

ADC Start Conversion

Delay Register

CP3BT26

16.4 FREEZE

The ADC module provides support for an In-System Emula­tor by means of a special FREEZE input. When FREEZE is
asserted the module will exhibit the following specific be­havior:

 The automatic clear-on-read function of the result regis-

ter (ADCRESLT) is disabled.

 The FIFO is updated as usual, and an interrupt for a

completed conversion can be asserted.

83 www.national.com

16.5.1 ADC Global Configuration Register (ADCGCR)

The ADCGCR register controls the basic operation of the in­terface. The CPU bus master has read/write access to the
ADCGCR register. After reset this register is set to 0000h.

CP3BT26

MUX_CFG The Multiplexer Configuration field and the

DIFF bit configure the analog circuits of the
ADC module, as shown in Table 35.

Table 35 MUX_CFG Operation

8765432 1 0

TOUCH_CFG MUX_CFG DIFF ADCIN CLKEN

15 14 13 12 11 10 9

MUXOUTEN INTEN Res. NREF_CFG PREF_CFG

CLKEN The Clock Enable bit controls whether the

ADC module is running. When this bit is clear,
all ADC clocks are disabled, the ADC analog
circuits are in a low-power state, and ADC
registers (other than the ADCGCR and AG­CACR registers) are not writeable. Clearing
this bit reinitializes the ADC state machine
and cancels any pending trigger event. When
this bit is set, the ADC clocks are enabled and
the ADC analog circuits are powered up. The
converter is operational within 0.25 µs of be­ing enabled.
0 – ADC disabled.
1 – ADC enabled.

ADCIN The ADCIN bit selects the source of the ADC

input. When the bit is clear, the source is the
8-channel Input Multiplexer. When the bit is
set, the source is the ADCIN pin.
0 – ADC input is from 8-channel multiplexer.
1 – ADC input is from ADCIN pin.

DIFF The Differential Operation Mode bit and the

MUX_CFG field configure the analog circuits
of the ADC module. When this bit is clear, the
ADC module operates in single-ended mode.
When this bit is set, the ADC operates in dif­ferential mode. See Table 35 .
0 – Single-ended mode.
1 – Differential mode.

Table 36 TOUCH_CFG Modes

TOUCH_CFG

Channels

Channel

MUX_CFG

000 0 0 1

001 1 1 0

010 2 2 3

011 3 3 2

100 4 4 5

101 5 5 4

110 6 6 7

111 7 7 6

For best noise immunity in touchscreen appli­cations, channel 2 should be used for sam­pling the X plate voltage, and channel 1
should be used for sampling the Y plate volt­age.

The Touchscreen Configuration field controls

the configuration of the low-ohmic drivers for
the TSX+, TSX-, TSY+, and TSY- signals, as
shown in Table 36. When TOUCH_CFG is
101b, the pen-down detector is enabled. The
output of the pen-down detector is visible to
software in the PEN_DOWN bit of the AD­SRESLT register, and it is ORed with the
Done signal to generate the wake-up signal
WUI30 passed to the MIWU unit.

Selected,

(DIFF = 0)

Selected

(DIFF = 1)

+-

TOUCH_CFG ADC0/TSX+ ADC1/TSY+ ADC2/TSX- ADC3/TSY- Mode

000 Inactive Inactive Inactive Inactive None

001 Inactive Driven High Inactive Driven Low Sample Y

010 Driven High Inactive Driven Low Inactive Sample X

011 Driven High Inactive Inactive Driven Low

100 Inactive Driven High Driven Low Inactive Sample Z (2)

101 Weakly Pulled High Inactive Inactive Driven Low Pen-Down Detect

11X Inactive Inactive Inactive inactive Reserved

www.national.com 84

Sample Z (1),

Pre-Pen Down

PREF_CFG The Positive Voltage Reference Configuration

field specifies the source of the ADC positive
voltage reference, according to the following
table:

PREF_CFG PREF Source

00 Internal (AVCC)

01 VREFP

10 ADC0

CP3BT26

16.5.2 ADC Auxiliary Configuration Register
(ADCACR)

The ADCACR register is used to control the clock configu­ration and report the status of the ADC module. The CPU
bus master has read/write access to the ADCACR register.
After reset, this register is clear.

15 14 13 12 3 2 1 0

CNVT TRG PRM Reserved CLKDIV CLKSEL

11 ADC1

NREF_CFG The Negative Voltage Reference Configura-

tion field specifies the source of the ADC neg­ative voltage reference, according to the
following table:

NREF_CFG NREF source

00 Internal (AGND)

01 Reserved

10 ADC2

11 ADC3

MUXOUTEN

INTEN The Interrupt Enable bit controls whether the

The MUXOUT Enable bit controls whether the
output of the Input Multiplexer is available ex­ternally. In single-ended mode, the
MUXOUT0 pin is active and the MUXOUT1
pin is disabled (TRI-STATE). In differential
mode, both MUXOUT0 and MUXOUT1 are
active.
0 – MUXOUT0 and MUXOUT1 disabled.
1 – MUXOUT0 and MUXOUT1 enabled.

ADC interrupt (IRQ13) is enabled. When en­abled, the interrupt request is asserted when
valid data is available in the ADCRESLT reg­ister. This bit has no effect on the wake_up
signal to the MIWU unit (WUI30).
0 – IRQ13 disabled.
1 – IRQ13 enabled.

CLKSEL The Clock Select bit selects the clock source

used by the DELAY2 block to generate the
ADC clock.
0 – ADC clock derived from System Clock.
1 – ADC clock derived from Auxiliary Clock 2.

CLKDIV The Clock Divisor field specifies the divisor

applied to System Clock to generate the 12
MHz clock required by the ADC module. Only
the System Clock is affected by this divisor.
The divisor is not used when Auxiliary Clock 2
is selected as the clock source.

CLKDIV Clock Divisor

00 1

01 2

10 4

11 Reserved

PRM The ADC Primed bit is a read-only bit that in-

dicates the ADC has been primed to perform
a conversion by writing to the ADCSTART reg­ister. The bit is cleared after the conversion is
completed.
0 – ADC has not been primed.
1 – ADC has been primed.

TRG The ADC Triggered bit is a read-only bit that

indicates the ADC has been triggered. The bit
is set during any pre-conversion delay. The bit
is cleared after the conversion is completed.
0 – ADC has not been triggered.
1 – ADC has been triggered.

CNVT The ADC Conversion bit is a read-only bit that

indicates the ADC has been primed to per­form a conversion, a valid internal or external
trigger event has occurred, any pre-conver­sion delay has expired, and the ADC conver­sion is in progress. The bit is cleared after the
conversion is completed.
0 – ADC is not performing a conversion.
1 – ADC conversion is in progress.

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16.5.3 ADC Conversion Control Register
(ADCCNTRL)

The ADCCNTRL register specifies the trigger conditions for
an ADC conversion.

CP3BT26

15 3 2 1 0

Reserved AUTO EXT POL

POL The ASYNC Polarity bit specifies the polarity

of edges which trigger ADC conversions.
0 – ASYNC input is sensitive to rising edges.
1 – ASYNC input is sensitive to falling edges.

EXT The External Trigger bit selects whether con-

versions are triggered by writing the ADC­START register or activity on the ASYNC
input.
0 – ADC conversions triggered by writing to

the ADCSTART register.

1 – ADC conversions triggered by qualified

edges on ASYNC input.

AUTO The Automatic bit controls whether automatic

mode is enabled, in which any qualified edge
on the ASYNC input is recognized as a trigger
event. When automatic mode is disabled, the
ADC module must be “primed” before a qual­ified edge on the ASYNC input can trigger a
conversion. To prime the ADC module, soft­ware must write the ADCSTART register with
any value before an edge on the ASYNC input
is recognized as a trigger event. After the con­version is completed, the ASYNC input will be
ignored until software again writes the ADC­START register. The AUTO bit is ignored
when the EXT bit is 0.
0 – Automatic mode disabled.
1 – Automatic mode enabled.

16.5.4 ADC Start Conversion Register (ADCSTART)

The ADCSTART register is a write-only register used by
software to initiate an ADC conversion. Writing any value to
this register will cause the ADC to initiate a conversion or
prime the ADC to initiate a conversion, as controlled by the
ADCCNTRL register.

16.5.5 ADC Start Conversion Delay Register
(ADCSCDLY)

The ADCSCDLY register controls critical timing parameters
for the operation of the ADC module.

15 14 13 5 4 0

ADC_DIV ADC_DELAY1 ADC_DELAY2

ADC_DELAY2

ADC_DELAY1

ADC_DIV The ADC Clock Divisor field specifies the divi-

The ADC Delay 2 field specifies the delay be-

tween the ADC module clock source (either
System Clock after a programmable divider or
Auxiliary Clock 2) and the ADC clock. The
range of effective values for this field is 0 to

20. Values above 20 produce the same delay
as 20, which is about 42 ns.

The ADC Delay 1 field specifies the number of

clock periods by which the trigger event will be
delayed before initiating a conversion. The
timebase for this delay is the ADC clock (12
MHz) divided by the ADC_DIV divisor. The
ADC_DELAY1 field has 9 bits, which corre­sponds to a maximum delay of 511 clock peri­ods.

sor applied to the ADC clock (12 MHz) to gen­erate the clock used to drive the DELAY1
block. A field value of n results in a division ra­tio of n+1. With a module clock of 12 MHz, the
maximum delay which can be provided by
ADC_DIV and ADC_DELAY settings is:

1



--------------------



12 MHz

4× 511× 170 us=

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16.5.6 ADC Result Register (ADCRESLT)

The ADCRESLT register includes the software-visible end
of a 4-word FIFO. Conversion results are loaded into the
FIFO from the 12-bit ADC and unloaded when software
reads the ADCRESLT register. The ADCRESLT register is
read-only. With the exception of the PEN_DOWN bit, the
fields in this register are cleared when the register is read.

11 0

ADC_RESULT

15 14 13 12

ADC_DONE ADC_OFLW PEN_DOWN SIGN

ADC_RESULT

SIGN The Sign bit indicates whether the - input has

The ADC Result field holds a 12-bit value for

the conversion result. If the ADC_DONE bit is
clear, there is no valid result in this field, and
the field will have a value of 0. The
ADC_RESULT field and the SIGN bit together
form the software-visible end of the ADC
FIFO.

a voltage greater than the + input (differential
mode only). For example if AD­CGCR.MUX_CFG is 000b, ADC0 is the + in­put and ADC1 is the - input. If the voltage on
ADC0 is greater than the voltage on ADC1,
the SIGN bit will be 0; if the voltage on ADC0
is less than the voltage on ADC1, the SIGN bit
will be 1. In single-ended mode, this bit always
reads as 0.
0 – In differential mode, + input has a voltage

greater than the - input. In single-ended
mode, this bit is always 0.

1 – In differential mode, - input has a voltage

greater than the + input.

PEN_DOWN

ADC_OFLW The ADC FIFO Overflow bit indicates whether

ADC_DONE The ADC Done bit indicates when an ADC

The Pen-Down bit indicates whether a pen-

down condition is being sensed. To enable
pen-down detection, the TOUCH_CFG field of
the ADCGCR register must be loaded with
101b. When pen-down detection is enabled
and a pen-down condition is sensed, the
PEN_DOWN bit is set. This bit is not carried
through the FIFO, so its value represents the
current status of the pen-down detector.
When pen-down detection is enabled, the sig­nal from the pen-down detector is ORed with
the Done signal to generate the wake-up sig­nal (WUI30) passed to the MIWU unit. If pen­down detection is not enabled, this bit reads
as 0.
0 – No pen-down condition is sensed, or pen-

down detection is disabled.

1 – Pen-down condition is sensed.

the 4-word FIFO behind the ADCRESLT reg­ister has overflowed. When this occurs, the
most recent conversion result is lost. This bit
is cleared when the ADCRESLT register is
read.
0 – FIFO overflow has not occurred.
1 – FIFO overflow has occurred.

conversion has completed. When this bit is
set, the data in the ADC_RESULT field is val­id. When this bit is clear, there is no valid data
in the ADC_RESULT field. The Done bit is
cleared when the ADCRESLT register is read,
but if there are queued conversion results in
the FIFO, the Done bit will become set again
after one System Clock period.
0 – No ADC conversion has completed since

the ADCRESLT register was last read.

1 – An ADC conversion has completed since

the ADCRESLT register was last read.

CP3BT26

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17.0 Random Number Generator (RNG)

The RNG unit is a hardware “true random” number genera­tor. When enabled, this unit provides up to 800 random bits

CP3BT26

per second. The bits are available for reading from a 16-bit
register.

The RNG unit includes two oscillators which operate inde­pendently of the System Clock:

 Fast Oscillator—a 24 MHz oscillator which drives a lin-

ear feedback shift register (LFSR).

 Slow Oscillator—an unstable oscillator which drives a

flip-flop for sampling the pseudorandom bitstream from
the LFSR. This oscillator operates at approximately 115
kHz, but it does not have a fixed frequency.

By sampling the pseudorandom bitstream at random inter­vals, a random bitstream is synthesized. This bitstream is
clocked into a 16-bit shift register. A programmable clock di­vider generates the clock signal for the shift register from the
System Clock.

When a new 16-bit word of random data is available, it is
loaded into the RNGD register. If enabled, an interrupt re­quest (IRQ3) is asserted when the word is available for
reading. When software reads the RNGD register, the reg­ister is cleared and the interrupt request is deasserted.

The RNGCST register provides control and status bits for
the RNG module:

 RNG Enable—enables or disables the RNG oscillators.
 Interrupt Mask—enables or disables the interrupt when

a new word of random data becomes available.

 Data Valid—indicates whether a new word is available.

17.1 FREEZE

The RNG module provides support for an In-System Emu­lator by means of a special FREEZE input. When FREEZE
is asserted, the automatic clear-on-read function of the
RNDGD register is disabled.

System
Clock

RNGCST

Enable

Fast Osc.

(~24 MHz)

Slow Osc.

(~115 kHz)

(Unstable)

D

31-Bit LFSR

Clock

RNGDIVH/RNGDIVL

Sample Strobe

Divider

Sample

Flip-Flop

Clock

Figure 28. RNG Module Block Diagram

DQQ

16-Bit Shift Register

Clock

RNGD

System
Bus

DS185

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17.2 RANDOM NUMBER GENERATOR
REGISTER SET

Table 34 lists the RNG registers.

Table 37 RNG Registers

Name Address Description

RNGCST FF F280h

RNGD FF F282h RNG Data Register

RNG Control and

Status Register

CP3BT26

17.2.2 RNG Data Register (RNGD)

The RNGD register holds random data generated by the
RNG module. After reading the register, it is cleared and the
DVALID bit of the RNGCST register is cleared. When a new
word of valid (random) data becomes available in the RNGD
register, the DVALID bit is set and (if enabled) and interrupt
request is asserted.

15 0

RNGD15:0

RNGDIVH FF F284h

RNGDIVL FF F286h

17.2.1 RNG Control and Status Register (RNGCST)

The RNGCST register provides control and status bits for
the RNG module. This register is cleared at reset.

15 654 2 1 0

Reserved IMSK Reserved DVALID RNGE

RNGE The Random Number Generator Enable bit

enables the operation of the RNG. When this
bit is clear, the RNG module is disabled, and
both RNG oscillators are suspended.
0 – RNG module disabled.
1 – RNG module enabled.

DVALID The Data Valid bit indicates whether valid

(random) data is available in the RNGD regis­ter. This bit is cleared when the RNGD regis­ter is read.
0 – RNGD register holds invalid data.
1 – RNGD register holds valid data.

IMASK The Interrupt Mask bit controls whether an in-

terrupt request (IRQ3) will be asserted when
valid (random) data is available in the RNGD
register.
0 – RNG interrupt disabled.
1 – RNG interrupt enabled.

RNG Divisor Register

High

RNG Divisor Register

Low

17.2.3 RNG Divisor Register High (RNGDIVH)

This register holds the two most significant bits of the
RNGDIV clock divisor. See the description of the RNGDIVL
register.

15 2 1 0

Reserved RNGDIV17:16

17.2.4 RNG Divisor Register Low (RNGDIVL)

This register holds the 16 least significant bits the RNGDIV
clock divisor.

15 0

RNGDIV15:0

The RNGDIV clock divisor is used to generate the sampling
strobe for loading random bits into the shift register. The di­visor is applied to the System Clock source. The maximum
frequency after division is 800 Hz. For example, a System
Clock frequency of 24 MHz would require an RNGDIV value
of 30,000 (7530h) or greater. The default RNGDIV value is
0000 83D6h.

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18.0 USB Controller

The CR16 USB node is an integrated USB node controller
that features enhanced DMA support with many automatic

CP3BT26

data handling features. It is compatible with USB specifica­tion versions 1.0 and 1.1.

It integrates the required USB transceiver, a Serial Interface
Engine (SIE), and USB endpoint (EP) FIFOs. Seven end­point pipes are supported: one for the mandatory control
endpoint and six to support interrupt, bulk, and isochronous
endpoints. Each endpoint pipe has a dedicated FIFO, 8
bytes for the control endpoint and 64 bytes for the other end­points.

18.1 FUNCTIONAL STATES

18.1.1 Line Condition Detection

At any given time, the CR16 USB node is in one of the fol­lowing states

Table 38 State Descriptions

State Descriptions

NodeOperational Normal operation

NodeSuspend Device operation suspend due to

USB inactivity

NodeResume Device wake-up from suspended

state

NodeReset Device reset

The NodeSuspend, NodeResume, or NodeReset line con­dition causes a transition from one operating state to anoth­er. These conditions are detected by specialized hardware
and reported in the Alternate Event (ALTEV) register. If in­terrupts are enabled, an interrupt is generated on the occur­rence of any of the specified conditions.

In addition to the dedicated input to the ICU for generating
interrupts on these USB state changes, a wake-up signal is
sent to the MIWU (see Section 13.0) when any activity is de­tected on the USB, if the bus was in the Idle state and the
USB node is in the NodeSuspend state. The MIWU can be
programmed to generate an edge-triggered interrupt when
this occurs.

NodeOperational

This is the normal operating state of the node. In this state,
the node is configured for operation on the USB.

NodeSuspend

A USB node is expected to enter NodeSuspend state when
3 ms have elapsed without any detectable bus activity. The
CR16 USB node looks for this event and signals it by setting
the SD3 bit in the ALTEV register, which causes an inter­rupt, to be generated (if enabled). Software should respond
by putting the CR16 USB node in the NodeSuspend state.

The CR16 USB node can resume normal operation under
software control in response to a local event in the device. It
can wake up the USB bus via a NodeResume, or when de­tecting a resume command on the USB bus, which signals
an interrupt to the CPU.

NodeResume

If the host has enabled remote wake-ups from the node, the
CR16 USB node can initiate a remote wake-up.

Once software detects the event, which wakes up the bus,
it releases the CR16 USB node from NodeSuspend state by
initiating a NodeResume on the USB using the NFSR reg­ister. The node software must ensure at least 5 ms of Idle
on the USB. While in NodeResume state, a constant “K” is
signalled on the USB. This should last for at least 1 ms and
no more than 5 ms, after which the USB host should contin­ue sending the NodeResume signal for at least an addition­al 20 ms, and then completes the NodeResume operation
by issuing the End Of Packet (EOP) sequence.

To successfully detect the EOP, software must enter the
USB NodeOperational state by setting the NFSR register.

If no EOP is received from the host within 100 ms, software
must re-initiate NodeResume.

NodeReset

When detecting a NodeResume or NodeReset signal while
in NodeSuspend state, the CR16 USB node can signal this
to the CPU by generating an interrupt.

USB specifications require that a device must be ready to
respond to USB tokens within 10 ms after wake-up or reset.

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18.2 ENDPOINT OPERATION

18.2.1 Address Detection

Packets are broadcast from the host controller to all nodes
on the USB network. Address detection is implemented in
hardware to allow selective reception of packets and to per­mit optimal use of CPU bandwidth. One function address
with seven different endpoint combinations is decoded in
parallel. If a match is found, then that particular packet is re­ceived into the FIFO; otherwise it is ignored.

The incoming USB Packet Address field and Endpoint field
are extracted from the incoming bit stream. Then the ad­dress field is compared to the Function Address register
(FADR). If a match is detected, the Endpoint field is com­pared to all of the Endpoint Control registers (EPCn) in par­allel. A match then causes the payload data to be received
or transmitted using the respective endpoint FIFO.

18.2.2 Transmit and Receive Endpoint FIFOs

The CR16 USB node uses a total of seven transmit and re­ceive FIFOs: one bidirectional transmit and receive FIFO for
the mandatory control endpoint, three transmit FIFOs, and
three receive FIFOs. As shown in Table 39, the bidirectional
FIFO for the control endpoint is 8 bytes deep. The additional
unidirectional FIFOs are 64 bytes each for both transmit and
receive. Each FIFO can be programmed for one exclusive
USB endpoint, used together with one globally decoded
USB function address. Software must not enable both trans­mit and receive FIFOs for endpoint zero at any given time.

Table 39 Endpoint FIFO Sizes

TX FIFO RX FIFO

Endpoint

Number

Size

(Bytes)

Name

Size

(Bytes)

Name

CP3BT26

USB Packet

ADDR Field Endpoint Field

FADR Register

Match

EPC0 Register

EPC1 Register

EPC2 Register

EPC3 Register

EPC4Register

EPC5 Register

Match

Receive/
Transmit FIFO0

Transmit FIFO1

Receive FIFO1

Transmit FIFO2

Receive FIFO2

Transmit FIFO3

0 FIFO0 (bidirectional, 8 bytes)

1 64 TXFIFO1 - -

2 - - 64 RXFIFO1

3 64 TXFIFO2 - -

4 - - 64 RXFIFO2

5 64 TXFIFO3 - -

6 - - 64 RXFIFO3

If two endpoints in the same direction are programmed with
the same endpoint number and both are enabled, data is re­ceived or transmitted to/from the endpoint with the lower
number, until that endpoint is disabled for bulk or interrupt
transfers, or becomes full or empty for ISO transfers. For ex­ample, if receive EP2 and receive EP4 both use endpoint 5
and are both isochronous, the first OUT packet is received
into EP2 and the second OUT packet into EP4, assuming
no software interaction in between. For ISO endpoints, this
allows implementing a ping-pong buffer scheme together
with the frame number match logic.

Endpoints in different directions programmed with the same
endpoint number operate independently.

EPC6 Register

Figure 29. USB Function Address/Endpoint Decoding

Receive FIFO3

DS049

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Bidirectional Control Endpoint FIFO0 Operation

FIFO0 should be used for the bidirectional control endpoint

0. It can be configured to receive data sent to the default ad-

dress with the DEF bit in the EPC0 register. Isochronous

CP3BT26

transfers are not supported for the control endpoint.

The Endpoint 0 FIFO can hold a single receive or transmit
packet with up to 8 bytes of data. Figure 30 shows the basic
operation in both receive and transmit direction.

Note: The actual current operating state is not directly vis­ible to software.

Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2,

TXFIFO3)

The Transmit FIFOs for endpoints 1, 3, and 5 support bulk,
interrupt, and isochronous USB packet transfers larger than
the actual FIFO size. Therefore, software must update the
FIFO contents while the USB packet is transmitted on the
bus. Figure 31 illustrates the operation of the transmit
FIFOs.

FLUSH (Resets TXRP and TXWP)

FLUSH Bit, TXC0 Register FLUSH Bit, RXC0 Register

TXFILL

TXWAIT

TX_EN Bit,
TXC0
Register

IN Token

Write to TXD0

TX_EN Bit,
TXC0 Register
(Zero-Length
Packet)

TX

IDLE

Transmission
Done

FIFO0 Empty
(All Data Read)

RX_EN Bit,
RXC0 Register

SETUP
To ke n

OUT or
SETUP
To ke n

RXWAIT

RX

DS050

Figure 30. Endpoint 0 Operation

A packet written to the FIFO is transmitted if an IN token for
the respective endpoint is received. If an error condition is
detected, the packet data remains in the FIFO and transmis­sion is retried with the next IN token.

The FIFO contents can be flushed to allow response to an
OUT token or to write new data into the FIFO for the next IN
token.

If an OUT token is received for the FIFO, software is in­formed that the FIFO has received data only if there was no
error condition (CRC or STUFF error). Erroneous recep­tions are automatically discarded.

- 1

TX FIFO n

0X0TFnS

TXRP

+

+

TXFL = TXWP

TXWP

- TXRP

+

TCOUNT = TXRP

- TXWP (= TFnS - TXFL)

DS051

Figure 31. Transmit FIFO Operation

TFnS The Transmit FIFO n Size is the total number

of bytes available within the FIFO.

TXRP The Transmit Read Pointer is incremented ev-

ery time the Endpoint Controller reads from
the transmit FIFO. This pointer wraps around
to zero if TFnS is reached. TXRP is never in­cremented beyond the value of the write
pointer TXWP. An underrun condition occurs if
TXRP equals TXWP and an attempt is made
to transmit more bytes when the LAST bit in
the TXCMDx register is not set.

TXWP The Transmit Write Pointer is incremented ev-

ery time software writes to the transmit FIFO.
This pointer wraps around to zero if TFnS is
reached. If an attempt is made to write more
bytes to the FIFO than actual space available
(FIFO overrun), the write to the FIFO is ig­nored. If so, TCOUNT is checked for an indi­cation of the number of empty bytes
remaining.

TXFL The Transmit FIFO Level indicates how many

bytes are currently in the FIFO. A FIFO warn­ing is issued if TXFL decreases to a specific
value. The respective WARNn bit in the FWR
register is set if TXFL is equal to or less than
the number specified by the TFWL bit in the
TXCn register.

TCOUNT The Transmit FIFO Count indicates how many

empty bytes can be filled within the transmit
FIFO. This value is accessible by software in
the TXSn register.

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Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2,

RXFIFO3)

The Receive FIFOs for endpoints 2, 4, and 6 support bulk,
interrupt, and isochronous USB packet transfers larger than
the actual FIFO size. If the packet length exceeds the FIFO
size, software must read the FIFO contents while the USB
packet is being received on the bus. Figure 32 shows the
detailed behavior of receive FIFOs.

FLUSH (Resets RXRP and RXWP)

CP3BT26

18.3 USB CONTROLLER REGISTERS

The CR16 USB node has a set of memory-mapped regis­ters that can be read/written from the CPU bus to control the
USB interface. Some register bits are reserved; reading
from these bits returns undefined data. Reserved register
bits must always be written with 0.

Table 40 USB Controller Registers

Name Address Description

MCNTRL FF FD80h Main Control Register

RXRP

+

+

RCOUNT = RXWP

RXWP

+

- RXRF

DS052

RXFL = RXRP

- 1

0X0RFnS

RX FIFO n

- RXWP (= RFnS - RCOUNT)

Figure 32. Receive FIFO Operation

RFnS The Receive FIFO n Size is the total number

of bytes available within the FIFO.

RXRP The Receive Read Pointer is incremented

with every read by software from the receive
FIFO. This pointer wraps around to zero if
RFnS is reached. RXRP is never incremented
beyond the value of RXWP. If an attempt is
made to read more bytes than are actually
available (FIFO underrun), the last byte is
read repeatedly.

RXWP The Receive Write Pointer is incremented ev-

ery time the Endpoint Controller writes to the
receive FIFO. This pointer wraps around to
zero if RFnS is reached. An overrun condition
occurs if RXRP equals RXWP and an attempt
is made to write an additional byte.

RXFL The Receive FIFO Level indicates how many

more bytes can be received until an overrun
condition occurs with the next write to the
FIFO. A FIFO warning is issued if RXFL de­creases to a specific value. The respective
WARNn bit in the FWR register is set if RXFL
is equal to or less than the number specified
by the RFWL bit in the RXCn register.

RCOUNT The Receive FIFO Count indicates how many

bytes can be read from the receive FIFO. This
value is accessible by software via the RXSn
register.

NFSR FF FD8Ah

Node Functional State

Register

MAEV FF FD8Ch Main Event Register

ALTEV FF FD90h

Alternate Event

Register

MAMSK FF FD8Eh Main Mask Register

ALTMSK FF FD92h

TXEV FF FD94h

TXMSK FF FD96h

RXEV FF FD98h

RXMSK FF FD9Ah

Alternate Mask

Register

Transmit Event

Register

Transmit Mask

Register

Receive Event

Register

Receive Mask

Register

NAKEV FF FD9Ch NAK Event Register

NAKMSK FF FD9Eh NAK Mask Register

FWEV FF FDA0h

FWMSK FF FDA2h

FNH FF FDA4h

FNL FF FDA6h

FAR FF F D 8 8h

FIFO Warning Event

Register

FIFO Warning Mask

Register

Frame Number High

Byte Register

Frame Number Low

Byte Register

Function Address

Register

DMACNTRL FF FDA8h DMA Control Register

DMAEV FF FDAAh DMA Event Register

DMAMSK FF FDACh DMA Mask Register

MIR FF FDAEh Mirror Register

DMACNT FF FDB0h DMA Count Register

DMAERR FF FDB2h DMA Error Register

93 www.national.com

Table 40 USB Controller Registers

Table 40 USB Controller Registers

Name Address Description

CP3BT26

EPC0 FF FDC0h

EPC1 FF FDD0h

EPC2 FF FDD8h

EPC3 FF FDE0h

EPC4 FF FDDE8h

EPC5 FF FDF0h

EPC6 FF FDF8h

TXS0 FF FDC4h

TXS1 FF FDD4h

TXS2 FF FDE4h

TXS3 FF FDF4h

TXC0 FF FDC6h

TXC1 FF FDD6

Endpoint Control 0

Register

Endpoint Control 1

Register

Endpoint Control 2

Register

Endpoint Control 3

Register

Endpoint Control 4

Register

Endpoint Control 5

Register

Endpoint Control 6

Register

Transmit Status 0

Register

Transmit Status 1

Register

Transmit Status 2

Register

Transmit Status 3

Register

Transmit Command 0

Register

Transmit Command 1

Register

Name Address Description

RXS3 FF FDFCh

RXC0 FF FDCEh

RXC1 FF FDDEh

RXC2 FF FDEEh

RXC3 FF FDFEh

RXD0 FF FDCAh

RXD1 FF FDDAh

RXD2 FF FDEAh

RXD3 FF FDFAh

18.3.1 Main Control Register (MCNTRL)

The MCNTRL register controls the main functions of the
CR16 USB node. The MCNTRL register provides read/write
access from the CPU bus. Reserved bits must be written
with 0, and they return 0 when read. It is clear after reset.

7 4 3 2 1 0

Reserved NAT Reserved USBEN

Receive Status 3

Register

Receive Command 0

Register

Receive Command 1

Register

Receive Command 2

Register

Receive Command 3

Register

Receive Data 0

Register

Receive Data 2

Register

Receive Data 2

Register

Receive Data 3

Register

TXC2 FF FDE6h

TXC3 FF FDF6h

TXD0 FF FDC2h

TXD1 FF FDD2h

TXD2 FF FDE2h

TXD3 FF FDF2h

RXS0 FF FDCCh

RXS1 FF FDDCh

RXS2 FF FDECh

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Transmit Command 2

Register

Transmit Command 3

Register

Transmit Data 0

Register

Transmit Data 1

Register

Transmit Data 2

Register

Transmit Data 3

Register

Receive Status 0

Register

Receive Status 1

Register

Receive Status 2

Register

USBEN The USB Enable controls whether the USB

module is enabled. If the USB module is dis­abled, the 48 MHz clock within the USB node
is stopped, all USB registers are initialized to
their reset state, and the USB transceiver forc­es SE0 on the bus to prevent the hub from de­tected the USB node. The USBEN bit is clear
after reset.
0 – The USB module is disabled.
1 – The USB module is enabled.

NAT The Node Attached indicates that this node is

ready to be detected as attached to USB.
When clear, the transceiver forces SE0 on the
USB node controller to prevent the hub (to
which this node is connected) from detecting
an attach event. After reset or when the USB
node is disabled, this bit is cleared to give the
device time before it must respond to com­mands. After this bit has been set, the device
no longer drives the USB and should be ready
to receive Reset signaling from the hub.
0 – Node not ready to be detected as at-

tached.

1 – Node ready to be detected as attached.

Table 41 USB Functional States

NFS Node State Description

This is the USB Reset state. This is entered upon a module reset or by software upon
detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint

00 NodeReset

Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be
cleared by software on entry to this state. On exit, DEF should be reset so the device
responds to the default address.

18.3.2 Node Functional State Register (NFSR)

The NFSR register reports and controls the current func­tional state of the USB node. The NFSR register provides
read/write access. It is clear after reset.

7 2 1 0

NFS The Node Functional State bits set the node

CP3BT26

Reserved NFS

state, as shown in Table 41. Software should
initiate all required state transitions according
to the respective status bits in the Alternate
Event (ALTEV) register.

In this state, resume “K” signalling is generated. This state should be entered by software to

01 NodeResume

10 NodeOperational This is the normal operational state for operation on the USB bus.

11 NodeSuspend

initiate a remote wake-up sequence by the device. The node must remain in this state for at
least 1 ms and no more than 15 ms.

Suspend state should be entered by software on detection of a Suspend event while in
Operational state. While in Suspend state, the transceivers operate in their low-power
suspend mode. All endpoint controllers and the bits TX_EN, LAST, and RX_EN are reset,
while all other internal states are frozen. On detection of bus activity, the RESUME bit in the
ALTEV register is set. In response, software can cause entry to NodeOperational state.

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18.3.3 Main Event Register (MAEV)

The Main Event Register summarizes and reports the main
events of the USB transactions. This register provides read­only access. The MAEV register is clear after reset.

CP3BT26

7 6 5 4 3 2 1 0

INTR RX_EV ULD NAK FRAME TX_EV ALT WARN

WARN The Warning Event bit indicates whether one

of the unmasked bits in the FIFO Warning
Event (FWEV) register has been set. This bit
is cleared by reading the FWEV register.
0 – No warning event occurred.
1 – A warning event has occurred.

ALT The Alternate Event bit indicates whether one

of the unmasked ALTEV register bits has
been set. This bit is cleared by reading the AL­TEV register.
0 – No alternate event has occurred.
1 – An alternate event has occurred.

TX_EV The Transmit Event bit indicates whether any

of the unmasked bits in the Transmit Event
(TXEV) register (TXFIFOn or TXUNDRNn) is
set. Therefore, it indicates that an IN transac­tion has been completed. This bit is cleared
when all the TX_DONE bits and the TXUN­DRN bits in each Transmit Status (TXSn) reg­ister are cleared.
0 – No transmit event has occurred.
1 – A transmit event has occurred.

FRAME The Frame Event bit indicates whether the

frame counter has been updated with a new
value, due to receipt of a valid SOF packet on
the USB or to an artificial update if the frame
counter was unlocked or a frame was missed.
This bit is cleared when the register is read.
0 – The frame counter has not been updated.
1 – Frame counter has been updated.

NAK The Negative Acknowledge Event indicates

whether one of the unmasked NAK Event
(NAKEV) register bits has been set. This bit is
cleared when the NAKEV register is read.
0 – No unmasked NAK event has occurred.
1 – An unmasked NAK event has occurred.

UL The Unlocked/Locked Detected bit is set

when the frame timer has either entered un­locked condition from a locked condition, or
has re-entered a locked condition from an un­locked condition as determined by the UL bit
in the Frame Number (FNH or FNL) register.
This bit is cleared when the register is read.
0 – Frame timer has not entered an unlocked

condition from a locked condition or re­entered a locked condition from an un­locked condition.

1 – Frame timer has either entered an un-

locked condition from a locked condition
or re-entered a locked condition from an
unlocked condition.

RX_EV The Receive Event bit is set if any of the un-

masked bits in the Receive Event (RXEV) reg­ister is set. It indicates that a SETUP or OUT
transaction has been completed. This bit is
cleared when all of the RX_LAST bits in each
Receive Status (RXSn) register and all RX­OVRRN bits in the RXEV register are cleared.
0 – No receive event has occurred.
1 – A receive event has occurred.

INTR The Master Interrupt Enable bit is hardwired

to 0 in the Main Event (MAEV) register; bit 7
in the Main Mask (MAMSK) register is the
Master Interrupt Enable.
0 – USB interrupts disabled.
1 – USB interrupts enabled.

18.3.4 Main Mask Register (MAMSK)

The MAMSK register masks out events reported in the
MAEV registers. A set bit enables the interrupts for the re­spective event in the MAEV register. If the corresponding bit
is clear, interrupt generation for this event is disabled. This
register provides read/write access. The MAMSK register is
clear after reset.

7 6 5 4 3 2 1 0

INTR RX_EV ULD NAK FRAME TX_EV ALT WARN

18.3.5 Alternate Event Register (ALTEV)

The ALTEV register summarizes and reports the further
events in the USB node. This register provides read-only ac­cess. The ALTEV register is clear after reset.

7 6 5 4 3 2 1 0

RESUME RESET SD5 SD3 EOP DMA Reserved

DMA The DMA Event bit indicates that one of the

unmasked bits in the DMA Event (DMAEV)
register has been set. The DMA bit is read­only and clear, when the DMAEV register is
cleared.
0 – No DMA event has occurred.
1 – A DMA event has occurred.

EOP The End of Packet bit indicates whether a val-

id EOP sequence has been detected on the
USB. It is used when this device has initiated a
Remote wake-up sequence to indicate that the
Resume sequence has been acknowledged
and completed by the host. This bit is cleared
when the register is read.
0 – No EOP sequence detected.
1 – EOP sequence detected.

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SD3 The Suspend Detect 3 ms bit is set after 3 ms

of IDLE have been detected on the upstream
port, indicating that the device should be sus­pended. The suspend occurs under software
control by writing the suspend value to the
Node Functional State (NFSR) register. This
bit is cleared when the register is read.
0 – No 3 ms in IDLE has been detected.
1 – 3 ms in IDLE has been detected.

SD5 The Suspend Detect 5 ms bit is set after 5 ms

of IDLE have been detected on the upstream
port, indicating that this device is permitted to
perform a remote wake-up operation. The re­sume may be initiated under software control
by writing the resume value to the NFSR reg­ister. This bit is cleared when the register is
read.
0 – No 5 ms in IDLE has been detected.
1 – 5 ms in IDLE has been detected.

RESET The Reset bit is set when 2.5 µs of SEO have

been detected on the upstream port. In re­sponse, the functional state should be reset
(NFS in the NFSR register is set to RESET),
where it must remain for at least 100 µs. The
functional state can then return to Operational
state. This bit is cleared when the register is
read.
0 – No 2.5 µs in SEO have been detected.
1 – 2.5 µs in SEO have been detected.

RESUME The Resume bit indicates whether resume

signalling has been detected on the USB
when the device is in Suspend state (NFS in
the NFSR register is set to SUSPEND), and a
non-IDLE signal is present on the USB, indi­cating that this device should begin its wake­up sequence and enter Operational state. Re­sume signalling can only be detected when
the 48 MHz PLL clock is enabled to the USB
controller. This bit is cleared when the register
is read.
0 – No resume signalling detected.
1 – Resume signalling detected.

18.3.6 Alternate Mask Register (ALTMSK)

A set bit in the ALTMSK register enables automatic setting
of the ALT bit in the MAEV register when the respective
event in the ALTEV register occurs. Otherwise, setting
MAEV.ALT bit is disabled. The ALTMSK register is clear af­ter reset. It provides read/write access from the CPU bus.

CP3BT26

18.3.7 Transmit Event Register (TXEV)

The TXEV register reports the current status of the FIFOs,
used by the three Transmit Endpoints. The TXEV register is
clear after reset. It provides read-only access.

7 4 3 0

TXUDRRN TXFIFO

TXFIFO The Transmit FIFO n bits are copies of the

TX_DONE bits from the corresponding Trans­mit Status registers (TXSn). A bit is set when
the IN transaction for the corresponding trans­mit endpoint n has been completed. These
bits are cleared when the corresponding
TXSn register is read.

TXUDRRN The Transmit Underrun n bits are copies of the

respective TX_URUN bits from the corre­sponding Transmit Status registers (TXSn).
Whenever any of the Transmit FIFOs under­flows, the respective TXUDRRN bit is set.
These bits are cleared when the correspond­ing Transmit Status register is read.
Note: Since Endpoint 0 implements a store
and forward principle, an underrun condition
for FIFO0 cannot occur. This results in the
TXUDRRN0 bit always being read as 0.

18.3.8 Transmit Mask Register (TXMSK)

The TXMSK register is used to select the bits of the TXEV
registers, which causes the TX_EV bit in the MAEV register
to be set. When a bit is set and the corresponding bit in the
TXEV register is set, the TX_EV bit in the MAEV register is
set. When clear, the corresponding bit in the TXEV register
does not cause TX_EV to be set. The TXMSK register pro­vides read/write access. It is clear after reset.

7 4 3 0

TXUDRRN TXFIFO

7 6 5 4 3 2 1 0

RESUME RESET SD5 SD3 EOP DMA Reserved

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18.3.9 Receive Event Register (RXEV)

The RXEV register reports the current status of the FIFO,
used by the three Receive Endpoints. The RXEV register is
clear after reset. It provides read-only access from the CPU

CP3BT26

bus.

18.3.11 NAK Event Register (NAKEV)

A bit in the NAKEV register is set when a Negative Acknowl­edge (NAK) was generated by the corresponding endpoint.
The NAKEV register provides read-only access from the
CPU bus. It is clear after reset.

7 4 3 0

RXOVRRN RXFIFO

RXFIFO The Receive FIFO n are set whenever either

RX_ERR or RX_LAST in the respective Re­ceive Status registers (RXSn) are set. Read­ing the corresponding RXSn register
automatically clears these bits. The CR16
USB node discards all packets for Endpoint 0
received with errors. This is necessary in case
of retransmission due to media errors, ensur­ing that a good copy of a SETUP packet is
captured. Otherwise, the FIFO may potentially
be tied up, holding corrupted data and unable
to receive a retransmission of the same pack­et (the RXFIFO0 bit only reflects the value of
RX_LAST for Endpoint 0). If data streaming is
used for the receive endpoints (EP2, EP4 and
EP6), software must check the respective
RX_ERR bits to ensure the packets received
are not corrupted by errors.

RXOVRRN The Receive Overrun n bits are set when an

overrun condition is indicated in the corre­sponding receive FIFO n. They are cleared
when the register is read. Software must
check the respective RX_ERR bits that pack­ets received for the other receive endpoints
(EP2, EP4 and EP6) are not corrupted by er­rors, as these endpoints support data stream­ing (packets which are longer than the actual
FIFO depth).

18.3.10 Receive Mask Register (RXMSK)

The RXMSK register is used to select the bits of the RXEV
register, which cause the RX_EV bit in the MAEV register to
be set. When set and the corresponding bit in the RXEV
register is set, RX_EV bit in the MAEV register is set. When
clear, the corresponding bit in the RXEV register does not
cause the RX_EV bit to be set. The RXMSK register pro­vides read/write access. This register is clear after reset.

7 4 3 0

OUT IN

IN The IN n bits are set when a NAK handshake

is generated for an enabled address/endpoint
combination (AD_EN in the Function Ad­dress, FAR, register is set and EP_EN in the
Endpoint Control, EPCx, register is set) in re­sponse to an IN token. These bits are cleared
when the register is read.

OUT The OUT n bits are set when a NAK hand-

shake is generated for an enabled address/
endpoint combination (AD_EN in the FAR reg­ister is set and EP_EN in the EPCx register is
set) in response to an OUT token. These bits
are not set if NAK is generated as result of an
overrun condition. They are cleared when the
register is read.

18.3.12 NAK Mask Register (NAKMSK)

The NAKMSK register is used to select the bits of the NA­KEV register, which cause the NAK bit in the MAEV register
to be set. When set and the corresponding bit in the NAKEV
register is set, the NAK bit in the MAEV register is set. When
cleared, the corresponding bit in the NAKEV register does
not cause NAK to be set. The NAKMSK register provides
read/write access. It is clear after reset.

7 4 3 0

OUT IN

7 4 3 0

RXOVRRN RXFIFO

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18.3.13 FIFO Warning Event Register (FWEV)

The FWEV register signals whether a receive or transmit
FIFO has reached its warning limit. It reports the status for
all FIFOs, except for the Endpoint 0 FIFO, as no warning
limit can be specified for this FIFO. The FWEV register pro­vides read-only access from the CPU bus. It is clear after re­set.

7 5 4 3 1 0

RXWARN3:1 Res. TXWARN3:1 Res.

TXWARN3:1

RXWARN3:1

18.3.14 FIFO Warning Mask Register (FWMSK)

The FWMSK register selects which FWEV bits are reported
in the MAEV register. A set FWMSK bit with the correspond­ing bit in the FWEV register set, causes the WARN bit in the
MAEV register to be set. When clear, the corresponding bit
in the FWEV register does not cause WARN to be set. The
FWMSK register provides read/write access. This register is
clear after reset.

754310

RXWARN3:1 Res. TXWARN3:1 Res.

The Transmit Warning n bits are set when the
respective transmit endpoint FIFO reaches
the warning limit, as specified by the TFWL
bits of the respective TXCn register, and
transmission from the respective endpoint is
enabled. These bits are cleared when the
warning condition is cleared by either writing
new data to the FIFO when the FIFO is
flushed, or when transmission is done, as in­dicated by the TX_DONE bit in the TXSn reg­ister.
The Receive Warning n bits are set when the
respective receive endpoint FIFO reaches the
warning limit, as specified by the RFWL bits of
the respective EPCx register. These bits are
cleared when the warning condition is cleared
by either reading data from the FIFO or when
the FIFO is flushed.

18.3.15 Frame Number High Byte Register (FNH)

The FNH register contains the three most significant bits
(MSB) of the current frame counter as well as status and
control bits for the frame counter. This register is loaded with
C0h after reset. It provides access from the CPU bus as de­scribed below.

FN10:8 The Frame Number field holds the three most

RFC The Reset Frame Count bit is used to reset

UL The Unlock Flag bit indicates that at least two

CP3BT26

7 6 5 4 3 2 0

MF UL RFC Reserved FN10:8

significant bits (MSB) of the current frame
number, received in the last SOF packet. If a
valid frame number is not received within
12060 bit times (Frame Length Maximum, FL­MAX, with tolerance) of the previous change,
the frame number is incremented artificially. If
two successive frames are missed or are in­correct, the current FN is frozen and loaded
with the next frame number from a valid SOF
packet. If the frame number low byte was read
by software before reading the FNH register,
software actually reads the contents of a buff­er register which holds the value of the three
frame number bits of this register when the
low byte was read. Therefore, the correct se­quence to read the frame number is: FNL,
FNH. Read operations to the FNH register,
without first reading the Frame Number Low
Byte (FNL) register directly, read the actual
value of the three MSBs of the frame number.
The FN bits provide read-only access. On re­set, the FN bits are cleared.

the frame number to 000h. This bit always
reads as 0. Due to the synchronization ele­ments the frame counter reset actually occurs
a maximum of 3 USB clock cycles (12 MHz)
plus 2.5 CPU clock cycles after the write to the
RFC bit.
0 – Writing 0 has no effect.
1 – Writing 1 resets the frame counter.

frames were received without an expected
frame number, or that no valid SOF was re­ceived within 12060 bit times. If this bit is set,
the frame number from the next valid SOF
packet is loaded in FN. The UL bit provides
read-only access. After reset, this bit is set.
This bit is set by the hardware and is cleared
by reading the FNH register.
0 – No condition indicated.
1 – At least two frames were received without

an expected frame number, or no valid
SOF was received within 12060 bit times.

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MF The Missed SOF bit is set when the frame

number in a valid received SOF does not
match the expected next value, or when an

CP3BT26

18.3.16 Frame Number Low Byte Register (FNL)

The FNL register holds the low byte of the frame number, as
described above. To ensure consistency, reading this low
byte causes the three frame number bits in the FNH register
to be locked until this register is read. The correct sequence
to read the frame number is: FNL first, followed by FNH.
This register provides read-only access. After reset, the
FNL register is clear.

SOF is not received within 12060 bit times.
The MF bit provides read-only access. On re­set, this bit is set. This bit is set by the hard­ware and is cleared by reading the FNH
register.
0 – No condition indicated.
1 – The frame number in a valid SOF does

not match the expected next value, or no
valid SOF was received within 12060 bit
times.

18.3.18 Control Register (DMACNTRL)

The DMACNTRL register controls the main DMA functions
of the CR16 USB node. The DMACTRL register provides
read/write access. This register is clear after reset.

7 6 5 4 3 2 0

DEN IGNRXTGL DTGL ADMA DMOD DSRC

DSRC The DMA Source bit field holds the binary-en-

coded value that specifies which of the end­points, 1 to 6, is enabled for DMA support. The
DSRC bits are cleared on reset. Table 42
summarizes the DSRC bit settings.

Table 42 DSRC Bit Description

DSRC Endpoint Number

000 1

001 2

7 0

FN7:0

Note: If the frame counter is updated due to a receipt of a
valid SOF or an artificial update (i.e. missed frame or un­locked/locked detect), it will take the synchronization ele­ments a maximum of 2.5 CPU clock cycles to update the
FNH and FNL registers.

18.3.17 Function Address Register (FAR)

The Function Address Register specifies the device func­tion address. The different endpoint numbers are set for
each endpoint individually using the Endpoint Control regis­ters. The FAR register provides read/write access. After re­set, this register is clear. If the DEF bit in the Endpoint
Control 0 register is set, Endpoint 0 responds to the default
address.

7 6 0

AD_EN AD

AD The Address field holds the 7-bit function ad-

dress used to transmit and receive all tokens
addressed to this device.

AD_EN The Address Enable bit controls whether the

AD field is used for address comparison. If
not, the device does not respond to any token
on the USB bus.
0 – The device does not respond to any token

on the USB bus.

1 – The AD field is used for address compar-

ison.

010 3

011 4

100 5

101 6

11x Reserved

DMOD The DMA Mode bit specifies when a DMA re-

quest is issued. If clear, a DMA request is is­sued on transfer completion. For transmit
endpoints EP1, EP3, and EP5, the data is
completely transferred, as indicated by the
TX_DONE bit (to fill the FIFO with new trans­mit data). For receive endpoints EP2, EP4,
and EP6, this is indicated by the RX_LAST bit.
When the DMOD bit is set, a DMA request is
issued when the respective FIFO warning bit
is set. The DMOD bit is cleared after reset.
0 – DMA request is issued on transfer com-

pletion.

1 – DMA request is issued when the respec-

tive FIFO warning bit is set.

ADMA The Automatic DMA bit enables Automatic

DMA (ADMA) and automatically enables the
selected receive or transmit endpoint. Before
ADMA mode can be enabled, the DEN bit in
the DMA Control (DMACNTRL) register must
be cleared. ADMA mode functions until any bit
in the DMA Event (DMAEV) register is set, ex­cept for NTGL. To initiate ADMA mode, all bits
in the DMAEV register must be cleared, ex­cept for NTGL.
0 – Automatic DMA disabled.
1 – Automatic DMA enabled.

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