National Semiconductor COP8ACC5 Technical data
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COP8ACC5
8-Bit CMOS ROM Based Microcontrollers with 4k
Memory and High Resolution A/D
General Description
The COP8ACC5 ROM based microcontrollers are highly integrated COP8
advanced features including a High-Resolution A/D. These
single-chip CMOS devices are suited for applications requiring a full featured, low EMI controller with an A/D (only one
external capacitor required). COP8ACC7 devices are pin
and software compatible (different V
EPROM versions for pre-production. Erasable windowed
versions are available for use with a range of COP8 software
and hardware development tools.
™
Feature core devices with 4k memory and
range) 16k OTP
CC
May 1999
Family features include an 8-bit memory mapped architecture, 4 MHz CKI with 2.5µs instruction cycle, 6 channel A/D
with 12-bit resolution, analog capture timer, analog current
source and V
counter, MICROWIRE/PLUS serial I/O, two power saving
HALT/IDLE modes, MIWU, high current outputs, software
selectable I/O options, WATCHDOG
tor,LowEMI 2.5V to 5.5V operation and 20/28 pin packages.
Devices included in this datasheet are:
/2 reference, one multi-function 16-bit timer/
CC
™
timer and Clock Moni-
COP8ACC5 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
COP8ACC5xxx9 4k ROM 128 15/23 20 SOIC, 28 DIP/SOIC 0 to +70˚C
COP8ACC5xxx8 4k ROM 128 15/23 20 SOIC, 28 DIP/SOIC -40 to +85˚C
Key Features
n Analog Function Block with 12-bit A/D including
— Analog comparator with seven input mux
— Constant Current Source and V
— 16-bit capture timer (upcounter) clocked from CKI
with auto reset on timer startup
n Quiet design (reduced radiated emissions)
n 4096 bytes on-board ROM
n 128 bytes on-board RAM
CC/2
Reference
Additional Peripheral Features
n Idle Timer
n One 16-bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Multi-Input Wake-Up (MIWU) with optional interrupts
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS
clock-polarity
™
serial I/O with programmable shift
CPU/Instruction Set Features
n 2.5 µs instruction cycle time
n Eight multi-source vectored interrupt servicing
— External Interrupt
— Idle Timer T0
— Timer T1 associated Interrupts
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS
— A/D (Capture Timer)
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Registers Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.5V to 5.5V
n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C
Development System
I/O Features
n Software selectable I/O options (Push-Pull Output, Weak
Pull-Up Input, High Impedance Input)
n High current outputs
n Schmitt Trigger inputs on ports G and L
n Packages: 28 DIP/SO with 23 I/O pins,
20 SO with 15 I/O pins
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink development system
Applications
n Battery Chargers
n Appliances
n Data Acquisition systems
COP8™, MICROWIRE™, MICROWIRE/PLUS™, and WATCHDOG™are trademarks of National Semiconductor Corporation.
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
®
iceMASTER
is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS012865 www.national.com
Block Diagram
Connection Diagrams
DS012865-1
FIGURE 1. Block Diagram
DS012865-2
Top View
Order Number COP8ACC528N9 or COP8ACC528N8
See NS Molded Package Number N28A
Order Number COP8ACC528M9 or COP8ACC528M8
See NS Molded Package Number M28B
FIGURE 2. Connection Diagrams
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DS012865-3
Top View
Order Number COP8ACC520M9 or COP8ACC520N8
See NS Molded Package Number M20B
Connection Diagrams (Continued)
Pinouts for 28-Pin, 20-Pin Packages
Port Type Alt. Fun Alt. Fun
L4 I/O MIWU Ext. Int. 4
L5 I/O MIWU Ext. Int. 5
L6 I/O MIWU Ext. Int. 6
L7 I/O MIWU Ext. Int. 7
G0 I/O INT 23 15
G1 WDOUT 24 16
G2 I/O T1B 25 17
G3 I/O T1A 26 18
G4 I/O SO 27 19
G5 I/O SK 28 20
G6 I SI 1 1
G7 I/CKO HALT Restart 2 2
D0 O 11 7
D1 O 12 8
D2 O 13 9
D3 O 14
I0 I Analog CH1 15 10
I1 I I
I2 I Analog CH2 17 12
I3 I Analog CH3 18 13
I4 I Analog CH4 19 14
I5 I Analog CH5 20
I6 I Analog CH6 21
I7 I C
V
CC
GND 8 4
CKI 3 3
RESET
SRC
OUT
28-Pin 20-Pin
DIP/SO SO
16 11
22
95
10 6
Ordering Inforamtion
DS012865-38
FIGURE 3. Part Numbering Scheme
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to V
)7V
CC
CC
+0.3V
Total Current into V
Pin (Source) 100 mA
CC
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage Peak-to-Peak 2.5 5.5 V
Power Supply Ripple (Note 2) 0.1 V
CC
Supply Current (Note 3)
CKI = 4 MHz V
CKI = 4 MHz V
CKI = 1 MHz V
HALT Current (Note 4) V
= 5.5V, tC= 2.5 µs 5.5 mA
CC
= 4V, tC= 2.5 µs 2.5 mA
CC
= 4V, tC= 10 µs 1.4 mA
CC
= 5.5V, CKI=0MHz
CC
V
= 4V, CKI = 0 MHz
CC
<
58 µA
<
34 µA
IDLE Current
CKI = 4 MHz V
CKI = 1 MHz V
Input Levels (V
IH,VIL
)
= 5.5V, tC= 2.5 µs 1.5 mA
CC
= 4V, tC= 10 µs 0.5 mA
CC
RESET
Logic High 0.8 V
Logic Low 0.2 V
CC
CC
CKI, All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
= 5.5V 1 1 µA
CC
= 5.5V, VIN= 0V −40 −250 µA
CC
G and L Port Input Hysteresis (Note 6) 0.35 V
CC
CC
CC
Output Current Levels
D Outputs
Source V
Sink V
= 4V, VOH= 3.3V −0.4 mA
CC
V
= 2.5V, VOH= 1.8V −0.2 mA
CC
= 4V, VOL=1V 10 mA
CC
V
= 2.5V, VOL= 0.4V 2.0 mA
CC
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE
®
Leakage VCC= 5.5V 1 1 µA
= 4V, VOH= 2.7V −10 −110 µA
CC
V
= 2.5V, VOH= 1.8V −2.5 −33 µA
CC
= 4V, VOH= 3.3V −0.4 mA
CC
V
= 2.5V, VOH= 1.8V −0.2 mA
CC
= 4V, VOL= 0.4V 1.6 mA
CC
V
= 2.5V, VOL= 0.4V 0.7 mA
CC
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
±
200 mA
without Latchup (Note 5)
RAM Retention Voltage, V
r
500 ns Rise and Fall Time (min) 2 V
V
V
V
V
V
V
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DC Electrical Characteristics (Continued)
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Capacitance (Note 6) 7 pF
Load Capacitance on D2 (Note 6) 1000 pF
AC Electrical Characteristics
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal, Resonator 2.5V ≤ V
R/C Oscillator 2.5V ≤ V
Inputs
t
SETUP
t
HOLD
Output Propagation Delay (Note 6) R
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 5.5V 0.7 µs
All Others 4V ≤ V
MICROWIRE
™
Setup Time (t
6)
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay
)
(t
UPD
Input Pulse Width (Note 7)
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer 1, 2, 3 Input High Time 1 t
Timer 1, 2, 3 Input Low Time 1 t
Reset Pulse Width 1 µs
Note 2: Maximum rate of voltage change must be<0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
clock monitorandcomparatordisabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALTin crystal
clock mode.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages V
biased at voltages VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 7: Parameter characterized but not tested.
Note 8: t
= Instruction Cycle Time.
C
)
C
4V ≤ V
4V ≤ V
≤ 4V 2.5 DC µs
CC
≤ 5.5V 1.0 DC µs
CC
≤ 4V 7.5 DC µs
CC
≤ 5.5V 3.0 DC µs
CC
4V ≤ VCC≤ 5.5V 200 ns
2.5V ≤ V
≤ 4V 500 ns
CC
4V ≤ VCC≤ 5.5V 60 ns
2.5V ≤ V
L
2.5V ≤ V
2.5V ≤ V
) (Note
UWS
) (Note 6) VCC≥ 4V 56 ns
UWH
VCC≥ 4V 20 ns
V
CC
≤ 4V 150 ns
CC
= 2.2k, CL= 100 pF
≤ 4V 1.75 µs
CC
≤ 5.5V 1 µs
CC
≤ 4V 2.5 µs
CC
≥ 4V 220 ns
HALT is done with device neither sourcing or
DD
and the pins will have sink current to VCCwhen
CC
C
C
C
C
;
CC
www.national.com5
Absolute Maximum Ratings (Note 9)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to V
)7V
CC
CC
+0.3V
Total Current into V
Pin (Source) 100 mA
CC
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 9: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.5 5.5 V
Power Supply Ripple (Note 10) Peak-to-Peak 0.1 V
CC
Supply Current (Note 11)
CKI = 4 MHz V
CKI = 4 MHz V
CKI = 1 MHz V
HALT Current (Note 12) V
= 5.5V, tC= 2.5 µs 5.5 mA
CC
= 4V, tC= 2.5 µs 2.5 mA
CC
= 4V, tC= 10 µs 1.4 mA
CC
= 5.5V, CKI=0MHz
CC
V
= 4V, CKI = 0 MHz
CC
<
510 µA
<
36 µA
IDLE Current
CKI = 4 MHz V
CKI = 1 MHz V
Input Levels (V
IH,VIL
)
= 5.5V, tC= 2.5 µs 1.5 mA
CC
= 4V, tC= 10 µs 0.5 mA
CC
RESET
Logic High 0.8 V
Logic Low 0.2 V
CC
CC
CKI, All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
= 5.5V −2 +2 µA
CC
= 5.5V, VIN= 0V −40 −250 µA
CC
G and L Port Input Hysteresis (Note 14) 0.35 V
CC
CC
CC
Output Current Levels
D Outputs
Source V
Sink V
= 4V, VOH= 3.3V −0.4 mA
CC
V
= 2.5V, VOH= 1.8V −0.2 mA
CC
= 4V, VOL=1V 10 mA
CC
V
= 2.5V, VOL= 0.4V 2.0 mA
CC
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
= 4V, VOH= 2.7V −10 −110 µA
CC
V
= 2.5V, VOH= 1.8V −2.5 −33 µA
CC
= 4V, VOH= 3.3V −0.4 mA
CC
V
= 2.5V, VOH= 1.8V −0.2 mA
CC
= 4V, VOL= 0.4V 1.6 mA
CC
V
= 2.5V, VOL= 0.4V 0.7 mA
CC
= 5.5V −2 +2 µA
CC
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
±
200 mA
without Latchup (Note 13)
RAM Retention Voltage, V
r
500 ns Rise and Fall Time (min) 2 V
V
V
V
V
V
V
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DC Electrical Characteristics (Continued)
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Capacitance (Note 14) 7 pF
Load Capacitance on D2 (Note 14) 1000 pF
AC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal, Resonator 2.5V ≤ V
R/C Oscillator 2.5V ≤ V
Inputs
t
SETUP
t
HOLD
Output Propagation Delay (Note 14) R
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 5.5V 0.7 µs
All Others 4V ≤ V
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 15)
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer 1, 2, 3 Input High Time 1 t
Timer 1, 2, 3 Input Low Time 1 t
Reset Pulse Width 1 µs
Note 10: Maximum rate of voltage change must be<0.5 V/ms.
Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 12: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALTin crystal
clock mode.
Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages V
biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical).
These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins.
This warning excludes ESD transients.
Note 14: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 15: Parameter characterized but not tested.
Note 16: t
= Instruction Cycle Time.
C
)
C
4V ≤ V
4V ≤ V
<
4V 2.5 DC µs
CC
≤ 5.5V 1.0 DC µs
CC
<
4V 7.5 DC µs
CC
<
5.5V 3.0 DC µs
CC
4V ≤ VCC≤ 5.5V 200 ns
2.5V ≤ V
<
4V 500 ns
CC
4V ≤ VCC≤ 5.5V 60 ns
2.5V ≤ V
L
2.5V ≤ V
2.5V ≤ V
) (Note 14) VCC≥ 4V 20 ns
UWS
) (Note 14) VCC≥ 4V 56 ns
UWH
)VCC≥ 4V 220 ns
UPD
<
4V 150 ns
CC
= 2.2k, CL= 100 pF
<
4V 1.75 µs
CC
≤ 5.5V 1 µs
CC
<
4V 2.5 µs
CC
HALTis done with device neither sourcing or
DD
and the pins will have sink current to VCCwhen
CC
C
C
C
C
;
CC
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Comparator AC and DC Characteristics
VCC= 5V, −40˚C ≤ TA≤ +85˚C
Parameter Conditions Min Typ Max Units
<
<
V
Input Offset Voltage 0.4V
−1.5V
Input Common Mode Voltage Range (Note
V
IN
CC
0.4 V
17)
Voltage Gain 300k V/V
V
/2 Reference 4.0V<V
CC
DC Supply Current V
CC
<
5.5V 0.5 V
CC
−0.04
CC
= 5.5V 250 µA
For Comparator (when enabled)
DC Supply Current V
For V
/2 reference (when enabled)
CC
DC Supply Current V
= 5.5V 50 80 µA
CC
= 5.5V 200 µA
CC
For Constant Current Source (when enabled)
<
Constant Current Source 4.0V
Current Source Variation 4.0V
<
V
5.5V 7 20 32 µA
CC
<
<
V
5.5V 2 µA
CC
Temp = Constant
Current Source Enable Time 1.5 2 µs
Comparator Response Time 10 mV overdrive, 1 µs
100 pF load
Note 17: The device is capable of operating over a common mode voltage range of 0 to VCC− 1.5V,however increased offset voltage will be observed between 0V
and 0.4V.
10 25 mV
−1.5 V
CC
0.5V
0.5V
CC
+0.04
CC
V
FIGURE 4. MICROWIRE/PLUS Timing
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DS012865-4
Typical Performance Characteristics (−55˚C ≤ T
DS012865-40 DS012865-41
A
=
+125˚C)
DS012865-42 DS012865-43
DS012865-44 DS012865-44
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Typical Performance Characteristics (−55˚C ≤ T
DS012865-46 DS012865-47
=
+125˚C) (Continued)
A
DS012865-48 DS012865-49
DS012865-50
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DS012865-51
Pin Descriptions
VCCand GND are the power supply pins. All VCCand GND
pins must be connected.
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset description section.
The device contains two bidirectional (one 8-bit, one 4-bit)
I/O ports (G and L), where each individual bit may be independently configured as a weak pullup input, TRI-STATE
(Hi-Z) input or push pull output under program control. Ports
G- and L- feature Schmitt trigger inputs. Three data memory
address locations are allocated for each of these I/O ports.
Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA
register.A memory mapped address is also reserved for the
input pins of each I/O port. (See the memory map for the
various addresses associated with the I/O ports.)
shows the I/O port configurations. The DATAand CONFIGURATION registers allow for each port bit to be individually
configured under software control as shown below:
PORT L is a 4-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
The Port L supports Multi-Input Wake Up on all four pins.
The Port L has the following alternate features:
L7 MIWU or external interrupt
L6 MIWU or external interrupt
L5 MIWU or external interrupt
L4 MIWU or external interrupt
FIGURE 5. I/P Port Configurations
Configuration Data
Register Register
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Port Set-Up
Please note:
The lower 4 L-bits read all ones (L0:L3). This is independant
from the states of the associated bits in the L-port Data- and
Configuration register. The lower 4 bits in the L-port Dataand Configuration register can be used as general purpose
status indicators (flags).
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
Figure 5
DS012865-5
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
®
Therefore, each of the 5 I/O bits (G0, G2–G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and G7
data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated
output.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
I7 C
(Comparator Output)
OUT
I6 Analog CH6 (Comparator Positive Input 6)
I5 Analog CH5 (Comparator Positive Input 5)
I4 Analog CH4 (Comparator Positive Input 4)
I3 Analog CH3 (Comparator Positive Input 3/Comparator
Output)
I2 Analog CH2 (Comparator Positive Input 2)
I1 I
(Comparator Negative Input/Current Source Out)
SRC
I0 Analog CH1 (Comparator Positive Input 1)
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
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Functional Description
The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
®
is the 15-bit Program Counter Register
PC
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the device vector to program
memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, B and SP are memory mapped into this space at
address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
) cycle time.
C
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L and G are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOGand/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL and
CNTRL-control registers are cleared. The Comparator Select Register is cleared. The S register is initialized to zero.
The Multi-Input Wakeup registers WKEN and WKEDG are
cleared. Wakeup register WKPND is unknown. The stack
pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
clock cycles. The Clock Monitor bit
C
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
-32 tCclock cycles following
C
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
Figure 6
should be used
to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
WARNING:
When the device is held in reset for a long time it will consume high current (typically about 7 mA). This is not true for
the equivalent ROM device (COP8ACC5).
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (t
RC>5 x POWER SUPPLY RISE TIME
Figure 7
).
C
DS012865-6
FIGURE 6. Recommended Reset Circuit
shows the Crystal and R/C Oscillator diagrams.
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Oscillator Circuits (Continued)
DS012865-7
DS012865-8
FIGURE 7. Crystal and R/C Oscillator Diagrams
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table 1
shows the component values required for various
standard crystal values.
TABLE 1. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V
0 1 30 30–36 4 V
0 1 200 100–150 0.455 V
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
emissions.
Table 2
shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TABLE 2. RC Oscillator Configuration, T
R C CKI Freq Instr. Cycle
(kΩ) (pF) (MHz) (µs)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note 18: 3k ≤ R ≤ 200k
Note 19: 50 pF ≤ C ≤ 200 pF
=
25˚C
A
Conditions
=
5V
CC
=
5V
CC
=
5V
CC
=
25˚C
A
Conditions
=
CC
=
CC
=
CC
5V
5V
5V
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C1 Timer T1 mode control bit
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag
C Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7 Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and should be zero.
LPEN L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND MICROWIRE/PLUS interrupt pending
µWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
T1ENB Timer T1 Interrupt Enable for T1B Input cap-
ture edge
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