National Semiconductor COP888GD Technical data

查询COP688GD供应商

COP888GD
8-Bit CMOS ROM Based Microcontrollers with 16k
Memory and 8-Channel A/D

General Description

The COP888GD ROM based microcontrollers are highly in­tegrated COP8
and advanced features including an A/D Converter. These
multi-chip CMOS devices are suited for applications requir­ing a full featured controller with an 8-bitA/D converter, and
as pre-production devices for a masked ROM design. Pin
and software compatible 16k or 32k OTP EPROM versions
are available (COP87L88GD/RD Family) for pre-production,
and for use with a range of COP8 software and hardware de­velopment tools.

™

Feature core devices with 16k memory

July 1999

Family features include an 8-bit memory mapped architec­ture, 10 MHz CKI with 1µs instruction cycle, three multi­function 16-bit timer/counters, MICROWIRE/PLUS
I/O, one 8-bit/8-channel A/D converter with prescaler and
both differential and single ended modes, two power saving
HALT/IDLE modes, MIWU, idle timer, high current outputs,
software selectable I/O options, WATCHDOG
Clock Monitor, 2.5V to 5.5V operation, program code secu­rity, and 44 pin package.

Devices included in this datasheet are:

™

timer and

™

serial

COP888GD 8-Bit CMOS ROM Based Microcontrollers with 16k Memory and 8-Channel A/D

Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature Comments

COP688GD 16k ROM 256 40 44 PLCC -55 to +125˚C 4.5V to 5.5V
COP888GD 16k ROM 256 40 44 PLCC -40 to +85˚C 2.5V to 5.5V
COP988GD 16k ROM 256 40 44 PLCC 0 to +70˚C 2.5V to 4.0V, GDH = 4.0V to

Key Features

n 8-channel A/D converter with prescaler and both

differential and single ended modes

n Three 16-bit timers, each with two 16-bit registers

supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode

n Quiet design (low radiated emissions)
n 16 kbytes on-board ROM
n 256 bytes on-board RAM

Additional Peripheral Features

n Idle Timer
n Multi-Input Wakeup (MIWU) with optional interrupts (8)
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS serial I/O

I/O Features

n Memory mapped I/O
n Software selectable I/O options (TRI-STATE

Push-Pull Output, Weak Pull Up Input, High Impedance
Input)

n Schmitt trigger inputs on ports G and L
n Package:

— 44 PLCC with 40 I/O pins

®

Output,

CPU/Instruction Set Features

n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing

— External Interrupt
— Idle Timer T0
— Three Timers (each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)

n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) – stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers (B

and X)

Fully Static CMOS

n Two power saving modes: HALT and IDLE
n Single supply operation: 2.5V to 5.5V
n Temperature range: −0˚C to +70˚C and −40˚C to +85˚C

Development Support

n Emulation and OTP devices
n Real time emulation and full program debug offered by

MetaLink Development System

6.0V

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
iceMASTER

© 1999 National Semiconductor Corporation DS100076 www.national.com

™

, COP8™, MICROWIRE™and WATCHDOG™are trademarks of National Semiconductor Corporation.

®

is a registered trademark of MetaLink Corporation.

Block Diagram

Connection Diagrams

DS100076-1

FIGURE 1. Block Diagram

Plastic Chip Carrier

Order Number COP888GD-XXXV, COP988GD-XXX/V

Top View

See NS Plastic Chip Package Number V44A

FIGURE 2. Connection Diagrams

www.national.com 2

DS100076-2

Connection Diagrams (Continued)

Pinouts for 44-Pin Package

Port Type Alt. Fun Alt. Fun

L0 I/O MIWU 17
L1 I/O MIWU 18
L2 I/O MIWU 19
L3 I/O MIWU 20
L4 I/O MIWU T2A 25
L5 I/O MIWU T2B 26
L6 I/O MIWU T3A 27
L7 I/O MIWU T3B 28
G0 I/O INT 39
G1 WDOUT 40
G2 I/O T1B 41
G3 I/O T1A 42
G4 I/O SO 3
G5 I/O SK 4
G6 I SI 5
G7 I/CKO HALT Restart 6
D0 O 29
D1 O 30
D2 O 31
D3 O 32
D4 O 33
D5 O 34
D6 O 35
D7 O 36
I0 I ACH0 9
I1 I ACH1 10
I2 I ACH2 11
I3 I ACH3 12
I4 I ACH4 13
I5 I ACH5 14
I6 I ACH6 15
I7 I ACH7 16
C0 I/O 43
C1 I/O 44
C2 I/O 1
C3 I/O 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
V

CC

GND 37
CKI 7
RESET

44-Pin

Pack.

8

38

www.national.com3

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Voltage at Any Pin −0.3V to V
Total Current into V

)7V

CC

Pin

CC

CC

+ 0.3V

(Source) 100 mA

Total Current out of GND Pin

(Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 1:

Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.

DC Electrical Characteristics

−0˚C ≤ TA≤ +70˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage 2.5 5.5 V
Power Supply Ripple (Note 3) Peak-to-Peak 0.1 V
Supply Current (Note 4)

CKI = 10 MHz V
CKI = 4 MHz V

HALT Current (Note 5) V

= 5.5V, tc=1µs 20 mA

CC

= 4.0V, tc= 2.5

CC

µs

= 5.5V, CKI = 0

CC

MHz

= 4.0V, CKI = 0

V

CC

MHz

IDLE Current (Note 4)

CKI = 10 MHz V
CKI = 4 MHz V

= 5.5V, tc= 1 µs 1.2 mA

CC

= 4.0V, tc= 2.5

CC

µs
Input Levels
RESET , CKI

Logic High 0.8

V

CC

Logic Low 0.2 V

All Other Inputs (L0-L7, G0-G6, C0-C7,
I0-I7)

Logic High 0.7

V

CC

Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V

= 5.5V −2 +2 µA

CC

= 5.5V, VIN= 0V −40 −250 µA

CC

G and L Port Input Hysteresis (Note 9) 0.35

Output Current Levels
D Outputs

Source V

Sink (Note 6) V

= 4.5V, VOH=

CC

3.3V
= 4.5V, VOL=1V 10 mA

CC

−0.4 mA

All Others

Source (Weak Pull-Up Mode) V

Source (Push-Pull Mode) V

Sink (Push-Pull Mode) V

TRI-STATE Leakage V

= 4.5V, VOH=

CC

2.7V
= 4.5V, VOH=

CC

3.3V
= 4.5V, VOL=

CC

0.4V
= 5.5V −2 +2 µA

CC

−10 −100 µA

−0.4 mA

1.6 mA

Allowable Sink/Source Current per Pin

D Outputs (Sink) 15 mA

CC

10 mA

12 µA

10 µA

1mA

CC

CC

V

CC

V

V

V

V

V

V

www.national.com 4

DC Electrical Characteristics (Continued)

−0˚C ≤ TA≤ +70˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

All others 3mA

Maximum Input Current Room Temp

±

100 mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, V

r

500 ns Rise 2 V

and Fall Time (min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF

Note 2: tc= Instruction Cycle Time
Note 3: Maximum rate of voltage change must be
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V

and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of I

neither sourcing nor sinking current; with L,C,G0,andG2–G5 programmed as low outputs and not drivingaload;alloutputsprogrammedlowandnotdrivingaload;
all inputs tied to V
CKI during HALT in crystal clock mode.

Note 6: The user must guarantee that D2 pin does not source more than 10 mA during RESET.If D2 sources more than 10 mA during reset, the device will go into
programming mode.

Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages V
biased at voltages VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to
transients.

Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.

; clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up

CC

<

0.5 V/ms.

HALTis done with device

DD

and the pins will have sink current to VCCwhen

CC

<

14V.WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD

CC

AC Electrical Characteristics

−40˚C ≤ TA≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

Crystal, Resonator, 4.5V ≤ V
R/C Oscillator 4.5V ≤ V

CKI Clock Duty Cycle (Note 9) f

Rise Time (Note 9) f
Fall Time (Note 9) f

Inputs

t

SETUP

t

HOLD

Output Propagation Delay (Note 8) R

t

PD1,tPD0

SO, SK 4.5V ≤ VCC≤ 5.5V 0.7 µs
All Others 4.5V ≤ V

MICROWIRE

™

9)
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay

)

(t

UPD

Input Pulse Width (Note 9)

Interrupt Input High Time 1.0 t
Interrupt Input Low Time 1.0 t
Timer 1, 2, 3 Input High Time 1.0 t
Timer 1, 2, 3 Input Low Time 1.0 t

Reset Pulse Width 1.0 µs

Note 10: tc= Instruction Cycle Time
Note 11: Maximum rate of voltage change must be

)

c

Setup Time (t

UWH

≤ 5.5V 1.0 DC µs

CC

≤ 5.5V 3.0 DC µs

CC

= Max 40 60

r

= 10 MHz Ext Clock 5 ns

r

= 10 MHz Ext Clock 5 ns

r

4.5V ≤ VCC≤ 5.5V 200 ns

4.5V ≤ VCC≤ 5.5V 60 ns
= 2.2k, CL= 100 pF

L

≤ 5.5V 1.0 µs

CC

20 ns

UWS

) (Note

) (Note 9) 56 ns

220 ns

<

0.5 V/ms.

c
c
c
c

www.national.com5

AC Electrical Characteristics (Continued)

Note 12: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V

and outputs driven low but not connected to a load.
Note 13: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of I

neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to V
CKI during HALT in crystal clock mode.

Note 14: The user must guarantee that D2 pin does not source more than 10 mAduring RESET. If D2 sources more than 10 mAduring reset, the device will go into
programming mode.

Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages V
biased at voltages VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to
transients.

Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.

; clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up

CC

and the pins will have sink current to VCCwhen

CC

<

14V.WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD

HALTis done with device

DD

CC

www.national.com 6

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Voltage at Any Pin −0.3V to V
Total Current into V

)7V

CC

Pin

CC

CC

+ 0.3V

(Source) 100 mA

Total Current out of GND Pin

(Sink) 110 mA

Storage Temperature Range −65˚C to +140˚C

Note 18:

Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.

DC Electrical Characteristics

−40˚C ≤ TA≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Operating Voltage 2.7 5.5 V
Power Supply Ripple (Note 3) Peak-to-Peak 0.1 V
Supply Current (Note 4)

CKI = 10 MHz V
CKI = 4 MHz V

HALT Current (Note 5) V

= 5.5V, tc=1µs 20 mA

CC

= 4.0V, tc= 2.5

CC

µs

= 5.5V, CKI = 0

CC

MHz

= 4.0V, CKI = 0

V

CC

MHz

IDLE Current (Note 4)

CKI = 10 MHz V
CKI = 4 MHz V

= 5.5V, tc= 1 µs 1.2 mA

CC

= 4.0V, tc= 2.5

CC

µs
Input Levels
RESET , CKI

Logic High 0.8

V

CC

Logic Low 0.2 V

All Other Inputs (L0-L7, G0-G6, C0-C7,
I0-I7)

Logic High 0.7

V

CC

Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V

= 5.5V −2 +2 µA

CC

= 5.5V, VIN= 0V −40 −250 µA

CC

G and L Port Input Hysteresis (Note 9) 0.35

Output Current Levels
D Outputs

Source V

Sink (Note 6) V

= 4.5V, VOH=

CC

3.3V
= 4.5V, VOL=1V 10 mA

CC

−0.4 mA

All Others

Source (Weak Pull-Up Mode) V

Source (Push-Pull Mode) V

Sink (Push-Pull Mode) V

TRI-STATE Leakage V

= 4.5V, VOH=

CC

2.7V
= 4.5V, VOH=

CC

3.3V
= 4.5V, VOL=

CC

0.4V
= 5.5V −2 +2 µA

CC

−10 −100 µA

−0.4 mA

1.6 mA

Allowable Sink/Source Current per Pin

D Outputs (Sink) 15 mA

CC

10 mA

12 µA

10 µA

1mA

CC

CC

V

CC

V

V

V

V

V

V

www.national.com7

DC Electrical Characteristics (Continued)

−40˚C ≤ TA≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

All others 3mA

Maximum Input Current Room Temp

±

100 mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, V

r

500 ns Rise 2 V

and Fall Time (min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF

AC Electrical Characteristics

−40˚C ≤ TA≤ +85˚C unless otherwise specified

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (t

Crystal, Resonator, 4.5V ≤ V
R/C Oscillator 4.5V ≤ V

CKI Clock Duty Cycle (Note 9) f

Rise Time (Note 9) f
Fall Time (Note 9) f

Inputs

t

SETUP

t

HOLD

Output Propagation Delay (Note 8) R

t

PD1,tPD0

SO, SK 4.5V ≤ VCC≤ 5.5V 0.7 µs

All Others 4.5V ≤ V
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay

)

(t

UPD

Input Pulse Width (Note 9)

Interrupt Input High Time 1.0 t

Interrupt Input Low Time 1.0 t

Timer 1, 2, 3 Input High Time 1.0 t

Timer 1, 2, 3 Input Low Time 1.0 t
Reset Pulse Width 1.0 µs

Note 19: tc= Instruction Cycle Time
Note 20: Maximum rate of voltage change must be
Note 21: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V

and outputs driven low but not connected to a load.
Note 22: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of I

neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to V
CKI during HALT in crystal clock mode.

Note 23: The user must guarantee that D2 pin does not source more than 10 mAduring RESET. If D2 sources more than 10 mAduring reset, the device will go into
programming mode.

Note 24: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages V
biased at voltages VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to
transients.

Note 25: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 26: Parameter characterized but not tested.

CC

)

c

= Max 40 60

r

= 10 MHz Ext Clock 5 ns

r

= 10 MHz Ext Clock 5 ns

r

≤ 5.5V 1.0 DC µs

CC

≤ 5.5V 3.0 DC µs

CC

4.5V ≤ VCC≤ 5.5V 200 ns

4.5V ≤ VCC≤ 5.5V 60 ns
= 2.2k, CL= 100 pF

L

≤ 5.5V 1.0 µs

) (Note 9) 20 ns

UWS

) (Note 9) 56 ns

UWH

CC

220 ns

c
c
c
c

<

0.5 V/ms.

HALTis done with device

DD

; clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up

and the pins will have sink current to VCCwhen

CC

<

14V.WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD

CC

www.national.com 8

A/D Converter Specifications

VCC=5V±10%,(VSS–0.050V) ≤ Any Input ≤ (VCC+ 0.050V)

Parameter Conditions Min Typ Max Units

Resolution 8 Bits
Absolute Accuracy
Non-Linearity Deviation from the Best Straight

Line
Differential Non-Linearity
Common Mode Input Range GND V
DC Common Mode Error
Off Channel Leakage Current 1 2 µA
On Channel Leakage Current 1 2 µA
A/D Clock Frequency 0.1 1.67 MHz
Converison Time 17 A/D Clock Cycles
Internal Reference Resistance 1µs
Tum-on Time

Note 27: Conversion Time includes 7 A/D clock cycles sample and hold time.
Note 28: See Prescaler description.
Note 29: For V

input voltages below ground or above the V
to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog V
voltage range will therefore require a minimum supply voltage of 4.950 V

Note 30: Time or internal reference reistance to turn on and settle after coming out of HALT or IDLE mode.

(−)=VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog

IN

does not exceed the supply voltage by more than 50 mV, the output code will be correct. Toachieve an absolute 0 VDCto5VDCinput

IN

supply.Be careful, during testing at low VCClevels (4.5V), as high level analog inputs (5V) can cause this input diode

CC

over temperature variations, initial tolerance and loading.

DC

±

2 LSB

±

1 LSB

±

1 LSB

CC

±

1/2 LSB

V

DS100076-4

FIGURE 3. MICROWIRE/PLUS Timing

www.national.com9

Typical Performance Characteristics (−55˚C ≤ T

DS100076-19 DS100076-20

A

=

+125˚C)

DS100076-21 DS100076-22

DS100076-23

www.national.com 10

Pin Descriptions

VCCand GND are the power supply pins. All VCCand GND
pins must be connected.

CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.

RESET is the master reset input. See Reset Description sec­tion.

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con­figured as an input (Schmitt Trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATAregister. A memory mapped address is also re­served for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)

Figure 4

shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be in­dividually configured under software control as shown below:

CONFIGURATION DATA Port Set-Up

Register Register

0 0 Hi-Z Input

0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

Port L supports Multi-Input Wake Up on all eight pins. L4 and
L5 are used for the timer input functions T2A and T2B. L6
and L7 are used for the timer input functions T3A and T3B.

Port L has the following alternate features:

L7 MIWU or T3B
L6 MIWU or T3A
L5 MIWU or T2B
L4 MIWU or T2A
L3 MIWU
L2 MIWU
L1 MIWU
L0 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option se­lected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALTmode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi­vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in­put (R/C clock option), the associated bits in the data and

(TRI-STATE Output)

configuration registers for G6 and G7 are used for special
purpose functions as outlined on the next page. Reading the
G6 and G7 data bits will return zeros.

DS100076-5

FIGURE 4. I/O Port Configurations

Note that the chip will be placed in the HALTmode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en­ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.

Config Reg. Data Reg.

G7 CLKDLY HALT
G6 Alternate SK IDLE

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.

Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to theA/D converter. The 28-pin device does not have
a full complement of Port I pins. The unavailable pins are not
terminated (i.e. they are floating). A read operation from
these unterminated pins will return unpredictable values.
The user should ensure that the software takes this into ac­count by either masking out these inputs, or else restricting
the accesses to bit operations only. If unterminated, Port I
pins will draw power only when addressed.

www.national.com11

Pin Descriptions (Continued)

Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex­cept D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay
above 0.8 V
keep the external loading on D2 to

to prevent the chip from entering special modes. Also

CC

<

1000 pF.

Functional Description

The architecture of the device is modified Harvard architec­ture. With the Harvard architecture, the control store pro­gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa­rate addressing space with separate address buses. The ar­chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t

There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad­dress 06F with reset.

S is the 8-bit Data Segment Address Register used to extend
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.

All the CPU registers are memory mapped with the excep­tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

The program memory consists of 16 kbytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID in­struction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location 0FF Hex.

DATA MEMORY

The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.

The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer

) cycle time.

c

registers X, SP, B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.

The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula­tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

Data Memory Segment RAM
Extension

Data memory address 0FF is used as a memory mapped lo­cation for the Data Segment Address Register (S).

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly rela­tive to the reference of the B, X, or SP pointers (each con­tains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex. The
upper bit of this single-byte address divides the data store
memory into two separate sections as outlined previously.
With the exception of the RAM register memory from ad­dress locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit of the single-byte ad­dress to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
for data segment 255. The base address range from 0000 to
007F represents data segment 0.

Figure 5

illustrates how the S register data memory exten­sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg­ments of 128 bytes each with an additional upper base seg­ment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data seg­ment (128 bytes) to another. However, the upper base seg­ment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg­ment extension.

The instructions that utilize the stack pointer (SP) always ref­erence the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always lo­cated in the base segment. The stack pointer will be initial­ized to point at data memory location 006F as a result of
reset.

www.national.com 12

Data Memory Segment RAM
Extension

(Continued)

output will continue until 16 t
the clock frequency reaching the minimum specified value,

–32 tCclock cycles following

C

at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in

Figure 6

should be used
to ensure that the RESET pin is held low until the power sup­ply to the chip stabilizes.

*

Reads as all ones.

DS100076-6

FIGURE 5. RAM Organization

The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad­dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.

Reset

The RESET input when pulled low initializes the microcon­troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATEmode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi­cated as the WATCHDOGand/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
Comparator Select Register is cleared. The S register is ini­tialized to zero. The Multi-Input Wakeup registers WKEN and
WKEDG are cleared. Wakeup register WKPND is unknown.
The stack pointer, SP, is initialized to 6F hex.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in­hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow­ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error

clock cycles. The Clock Monitor bit

C

RC>5 x Power Supply Rise Time

DS100076-7

FIGURE 6. Recommended Reset Circuit

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre­quency is divided down by 10 to produce the instruction
cycle clock (1/t

Note: External clocks with frequencies above about 4 MHz require the user

to drive the CKO (G7) pin with a signal 180 degrees out of phase with
CKI.

Figure 7

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys­tal (or resonator) controlled oscillator.

Table 1

standard crystal values.

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.

Note: Use of the R/C oscillator option will result in higher electromagnetic

emissions.

Table 1

functions of the component (R and C) values.

).

c

shows the Crystal and R/C oscillator diagrams.

shows the component values required for various

shows the variation in the oscillator frequencies as

www.national.com13