National Semiconductor COP888FH Technical data
查询COP684FH供应商
COP888FH
8-Bit CMOS ROM Based Microcontrollers with 12k
Memory, Comparators, USART and Hardware
Multiply/Divide
General Description
The COP888FH Family of ROM based microcontrollers are
highly integrated COP8
memory and advanced features including Analog comparators, and Hardware Multiply/Divide. These single-chip
CMOS devices are suited for more complex applications requiring a full featured controller, low EMI, two comparators, a
full-duplex USART, and hardware multiply/divide functions.
COP87L88FH devices are pin and software compatible (different V
sions for pre-production , and for use with a range of COP8
software and hardware development tools.
range) 16k OTP (One Time Programmable) ver-
CC
™
Feature core devices with 12k
September 1999
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, hardware
multiply/divide functions, three multi-function 16-bit timer/
counters with PWM, full duplex USART, MICROWIRE/
™
PLUS
, two Analog comparators, two power saving HALT/
IDLE modes, MIWU, idle timer, high current outputs,
software selectable options WATCHDOG
oscillator mode, low EMI 2.5V to 5.5V operation, and 28/
40/44 pin packages.
Devices included in this data sheet are:
™
and clock/
COP888FH 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and
Hardware Multiply/Divide
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature Comments
COP684FH 12k ROM 512 24 28 DIP/SOIC -55 to +125˚C 4.5V to 5.5V
COP884FH 12k ROM 512 24 28 DIP/SOIC -40 to +85˚C
COP984FH 12k ROM 512 24 28 DIP/SOIC 0 to +70˚C 2.5V to 4.0V, FHH=4.0V to
COP688FH 12k ROM 512 36/40 40 DIP, 44 PLCC -55 to +125˚C 4.5V to 5.5V
COP888FH 12k ROM 512 36/40 40 DIP, 44 PLCC -40 to +85˚C
COP988FH 12k ROM 512 36/40 40 DIP, 44 PLCC 0 to +70˚C 2.5V to 4.0V, FHH=4.0V to
Key Features
n Hardware Multiply/Divide Functions
n Full duplex USART
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Quiet design (low radiated emissions)
n 12 kbytes on-board ROM
n 512 bytes on-board RAM
Additional Peripheral Features
n Idle Timer
n Multi-Input Wakeup (MIWU) with optional interrupts (8)
n Two analog comparators
n WATCHDOG and Clock Monitor logic
n MICROWIRE/PLUS serial I/O
COP8™is a trademark of National Semiconductor Corporation.
™
MICROWIRE
MICROWIRE/PLUS
TRI-STATE
WATCHDOG
iceMASTER
© 1999 National Semiconductor Corporation DS012602 www.national.com
is a trademark of National Semiconductor Corporation.
™
is a trademark of National Semiconductor Corporation.
®
is a registered trademark of National SemiconductorCorporation.
™
is a trademark of National Semiconductor Corporation.
™
is a trademark of MetaLink Corporation.
I/O Features
n Software selectable I/O options ( TRI-STATE®,
Push-Pull, Weak Pull-Up, and High Impedance Input)
n Schmitt trigger inputs on ports G and L
n Packages:
— 40 DIP with 36 I/O pins
— 44 PLCC with 40 I/O pins
— 28 DIP/SO with 24 I/O pins
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Fourteen multi-source vectored interrupts servicing
— External Interrupt
— Idle Timer T0
— Three Timers (Each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— USART (2)
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
6.0V
6.0V
CPU/Instruction Set Features
(Continued)
n 8-bit Stack Pointer (SP)— stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Block Diagram
Fully Static CMOS
n Low current drain (typically<5 µA)
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.5V–5.5V
n Temperature ranges: 0˚C to +70˚C,
−40˚C to +85˚C
−55˚C to +125˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
FIGURE 1. COP888FH Block Diagram
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DS012602-1
Connection Diagrams
Plastic Chip Carrier
DS012602-2
Top View
Order Number COP688FH-XXX/V,
COP888FH-XXX/V or COP988FH-XXX/V
See NS Plastic Chip Package Number V44A
Dual-In-Line Package
DS012602-3
Top View Order
Number COP688FH-XXX/N,
COP888FH-XXX/N or COP988FH-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
DS012602-4
Order Number COP684FH-XXX/M, COP884FH-XXX/M,
COP984FH-XXX/M, COP684FH-XXX/N,
COP884FH-XXX/N or COP984FH-XXX/N
See NS Molded Package Number M28B or N28B
FIGURE 2. Connection Diagrams
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Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages
Port Type Alt. Fun Alt. Fun
L0 I/O MIWU 11 17 17
L1 I/O MIWU CKX 12 18 18
L2 I/O MIWU TDX 13 19 19
L3 I/O MIWU RDX 14 20 20
L4 I/O MIWU T2A 15 21 25
L5 I/O MIWU T2B 16 22 26
L6 I/O MIWU T3A 17 23 27
L7 I/O MIWU T3B 18 24 28
G0 I/O INT 25 35 39
G1 WDOUT 26 36 40
G2 I/O T1B 27 37 41
G3 I/O T1A 28 38 42
G4 I/O SO 1 3 3
G5 I/O SK 2 4 4
G6ISI 355
G7 I/CKO HALT Restart 4 6 6
D0O 192529
D1O 202630
D2O 212731
D3O 222832
D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36
I0I 799
I1 I COMP1IN− 8 10 10
I2 I COMP1IN+ 9 11 11
I3 I COMP1OUT 10 12 12
I4 I COMP2IN− 13 13
I5 I COMP2IN+ 14 14
I6 I COMP2OUT 15 15
I7 I 16 16
C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
V
CC
GND 23 33 37
CKI 5 7 7
RESET
28-Pin 40-Pin 44-Pin
Pack. Pack. Pack.
688
24 34 38
www.national.com 4
COP98xFH
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to V
)7V
CC
CC
+ 0.3V
Total Current into V
Pin (Source) 100 mA
CC
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP98xFH:
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage COP98XFH 2.5 4.0 V
COP98XFHH 4.0 6.0 V
Power Supply Ripple (Note 2) Peak-to-Peak 0.1 V
Supply Current (Note 3)
CKI=10 MHz V
CKI=4 MHz V
CKI=4 MHz V
CKI=1 MHz V
HALT Current (Note 4) V
=
CC
=
CC
=
CC
=
CC
=
CC
=
V
CC
=
5.5V, t
5.5V, t
4V, t
4V, t
5.5V, CKI=0 MHz
4V, CKI=0 MHz
1 µs 12.5 mA
c
=
2.5 µs 5.5 mA
c
=
2.5 µs 2.5 mA
c
=
10 µs 1.4 mA
c
<
58 µA
<
34 µA
IDLE Current
CKI=10 MHz V
CKI=4 MHz V
CKI=1 MHz V
=
CC
=
CC
=
CC
=
5.5V, t
5.5V, t
4V, t
1 µs 3.5 mA
c
=
2.5 µs 2.5 mA
c
=
10 µs 0.7 mA
c
Input Levels
RESET
Logic High 0.8 V
CC
Logic Low 0.2 V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
CC
Logic Low 0.2 V
All Other Inputs
Logic High 0.7 V
CC
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
=
5.5V, V
CC
=
5.5V, V
CC
=
0V −1 +1 µA
IN
=
0V −40 −250 µA
IN
G and L Port Input Hysteresis 0.35 V
CC
CC
CC
CC
CC
V
V
V
V
V
V
V
V
www.national.com5
DC Electrical Characteristics COP98xFH: (Continued)
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Output Current Levels
D Outputs
Source V
Sink V
=
CC
=
V
CC
=
CC
=
V
CC
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
=
CC
=
V
CC
=
CC
=
V
CC
=
CC
=
V
CC
=
CC
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All Others 3mA
Maximum Input Current T
=
25˚C
A
without Latchup (Note 5)
RAM Retention Voltage, V
r
500 ns Rise 2 V
and Fall Time (Min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
=
4V, V
2.5V, V
4V, V
2.5V, V
4V, V
2.5V, V
4V, V
2.5V, V
4V, V
2.5V, V
3.3V −0.4 mA
OH
=
1.8V −0.2 mA
OH
=
1V 10 mA
OL
=
0.4V 2.0 mA
OL
=
2.7V −10 −100 µA
OH
=
1.8V −2.5 −33 µA
OH
=
3.3V −0.4 mA
OH
=
1.8V −0.2 mA
OH
=
0.4V 1.6 mA
OL
=
0.4V 0.7 mA
OL
5.5V −1 +1 µA
±
100 mA
AC Electrical Characteristics COP98xFH:
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
)4V≤V
c
Crystal Resonator or External 2.5V ≤ V
R/C Oscillator 4V ≤ V
2.5V ≤ V
CKI Clock Duty Cycle (Note 6) f=Max 45 55
Rise Time (Note 6) f=10 MHz Ext Clock 5 µs
Fall Time (Note 6) f=10 MHz Ext Clock 5 µs
Inputs
t
SETUP
4V ≤ VCC≤ 5.5V 200 ns
2.5V ≤ V
t
HOLD
4V ≤ VCC≤ 5.5V 60 ns
2.5V ≤ V
Output Propagation Delay (Note 6) R
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 5.5V 0.7 µs
2.5V ≤ V
All Others 4V ≤ V
2.5V ≤ V
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≤ 5.5V 1 DC µs
CC
<
4V 2.5 DC µs
CC
≤ 5.5V 3 DC µs
CC
<
4V 7.5 DC µs
CC
<
4V 500 ns
CC
<
4V 150 ns
CC
=
L
=
2.2k, C
CC
100 pF
L
<
4V 1.75 µs
CC
≤ 5.5V 1 µs
<
4V 2.5 µs
CC
%
AC Electrical Characteristics COP98xFH: (Continued)
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
™
MICROWIRE
Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer Input High Time 1 t
Timer Input Low Time 1 t
Reset Pulse Width 1 µs
Note 2: Rate of voltage change must be less than 0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Testconditions:All inputs tied to V
mode and tied to ground, all outputs low and tied to ground. The clock monitor and the comparator are disabled.
Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V
have sink current to VCCwhen biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to V
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
CC
)20ns
UWS
)56ns
UWH
) 220 ns
UPD
, L and G ports in the TRI-STATE
CC
and the pins will
CC
c
c
c
c
DS012602-5
FIGURE 3. MICROWIRE/PLUS Timing
www.national.com7
COP88xFH
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
)7V
CC
(Note 7)
Voltage at Any Pin −0.3V to V
Total Current into V
Pin (Source) 100 mA
CC
CC
+ 0.3V
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 7: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP88xFH:
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.5 5.5 V
Power Supply Ripple (Note 8) Peak-to-Peak 0.1 V
CC
Supply Current (Note 9)
CKI=10 MHz V
CKI=4 MHz V
CKI=4 MHz V
CKI=1 MHz V
HALT Current (Note 10) V
=
CC
=
CC
=
CC
=
CC
=
CC
=
V
CC
=
5.5V, t
5.5V, t
4.0V, t
4.0V, t
1 µs 12.5 mA
c
=
2.5 µs 5.5 mA
c
=
2.5 µs 2.5 mA
c
=
10 µs 1.4 mA
c
5.5V, CKI=0 MHz
4.0V, CKI=0 MHz
<
510 µA
<
36 µA
IDLE Current
CKI=10 MHz V
CKI=4 MHz V
CKI=1 MHz V
=
CC
=
CC
=
CC
5.5V, t
5.5V, t
4.0V, t
=
1 µs 3.5 mA
c
=
2.5 µs 2.5 mA
c
=
10 µs 0.7 mA
c
Input Levels
RESET
Logic High 0.8 V
Logic Low 0.2 V
CC
CC
CKI (All Other Inputs)
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
=
5.5V, V
CC
=
5.5V, V
CC
=
0V −2 +2 µA
IN
=
0V −40 −250 µA
IN
G and L Port Input Hysteresis (Note 12) 0.35 V
CC
CC
CC
Output Current Levels
D Outputs
Source V
Sink V
=
CC
=
V
CC
=
CC
=
V
CC
4V, V
2.5V, V
4V, V
2.5V, V
=
3.3V −0.4 mA
OH
=
1.8V −0.2 mA
OH
=
1V 10 mA
OL
=
0.4V 2.0 mA
OL
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
=
CC
=
V
CC
=
CC
=
V
CC
=
CC
=
V
CC
=
CC
=
4V, V
2.5V, V
4V, V
2.5V, V
4V, V
2.5V, V
2.7V −10 −100 µA
OH
=
1.8V −2.5 −33 µA
OH
=
3.3V −0.4 mA
OH
=
1.8V −0.2 mA
OH
=
0.4V 1.6 mA
OL
=
0.4V 0.7 mA
OL
5.5V −2 +2 µA
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
V
V
V
V
V
V
www.national.com 8
DC Electrical Characteristics COP88xFH: (Continued)
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
±
Maximum Input Current Room Temp
100 mA
without Latchup (Notes 11, 12)
RAM Retention Voltage, V
r
500 ns Rise 2 V
and Fall Time (Min)
Input Capacitance (Note 12) 7 pF
Load Capacitance on D2 (Note 12) 1000 pF
AC Electrical Characteristics COP88xFH:
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal Resonator or External 2.5V ≤ V
R/C Oscillator 2.5V ≤ V
CKI Clock Duty Cycle (Note 12) f=Max 45 55
Rise Time (Note 12) f=10 MHz Ext Clock 5 µs
Fall Time (Note 12) f=10 MHz Ext Clock 5 µs
Inputs
t
SETUP
t
HOLD
Output Propagation Delay R
t
PD1,tPD0
SO, SK 4.0V ≤ VCC≤ 5.5V 0.7 µs
All Others 4.0V ≤ V
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 13)
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer 1, 2, 3 Input High Time 1 t
Timer 1, 2, 3 Input Low Time 1 t
Reset Pulse Width 1 µs
Note 8: Maximum rate of voltage change must be less than 0.5V/ms.
Note 9: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 10: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
clock monitor and comparators disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.Part will pull up CKI during HALTin crystal clock mode.
Note 11: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V
to VCCwhen biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 12: Parameter characterized but not tested.
Note 13: t
=
Instruction cycle time.
c
)
c
4.0V ≤ V
4.0V ≤ V
≤ 4.0V 2.5 DC µs
CC
≤ 5.5V 1.0 DC µs
CC
<
4.0V 7.5 DC µs
CC
≤ 5.5V 3.0 DC µs
CC
4.0V ≤ VCC≤ 5.5V 200 ns
2.5V ≤ V
<
4.0V 500 ns
CC
4.0V ≤ VCC≤ 5.5V 60 ns
2.5V ≤ V
L
2.5V ≤ V
2.5V ≤ V
) (Note 12) VCC≥ 4.0V 20 ns
UWS
) (Note 12) VCC≥ 4.0V 56 ns
UWH
)VCC≥ 4.0V 220 ns
UPD
<
4.0V 150 ns
CC
=
=
2.2k, C
100 pF
L
<
4.0V 1.75 µs
CC
≤ 5.5V 1 µs
CC
<
4.0V 2.5 µs
CC
HALTis done with device neither sourcing or
DD
and the pins will have sink current
CC
%
c
c
c
c
;
CC
www.national.com9
COP68xFH
Total Current into V
Pin (Source) 100 mA
CC
Total Current out of GND Pin (Sink) 110 mA
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to V
)7V
CC
(Note 14)
+ 0.3V
CC
Storage Temperature Range −65˚C to +140˚C
Note 14: Note:
age to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
Absolute maximum ratings indicate limits beyond which dam-
DC Electrical Characteristics COP68xFH:
−55˚C ≤ TA≤ +125˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 4.5 5.5 V
Power Supply Ripple (Note 15) Peak-to-Peak 0.1 V
Supply Current (Note 16)
CKI=10 MHz V
CKI=4 MHz V
HALT Current (Note 17) V
=
CC
=
CC
=
CC
=
5.5V, t
5.5V, t
1 µs 12.5 mA
c
=
2.5 µs 5.5 mA
c
5.5V, CKI=0 MHz
<
10 30 µA
IDLE Current
CKI=10 MHz V
CKI=4 MHz V
=
CC
=
CC
5.5V, t
5.5V, t
=
1 µs 3.5 mA
c
=
2.5 µs 2.5 mA
c
Input Levels
RESET
Logic High 0.8 V
CC
Logic Low 0.2 V
CKI (All Other Inputs)
Logic High 0.7 V
CC
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
=
5.5V, V
CC
=
5.5V, V
CC
=
0V −5 +5 µA
IN
=
0V −35 −400 µA
IN
G and L Port Input Hysteresis (Note 19) 0.35 V
Output Current Levels
D Outputs
Source V
Sink V
=
4.5V, V
CC
=
4.5V, V
CC
=
3.3V −0.4 mA
OH
=
1V 9 mA
OL
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
=
4.5V, V
CC
=
4.5V, V
CC
=
4.5V, V
CC
=
5.5V −5 +5 µA
CC
=
2.7V −9 −140 µA
OH
=
3.3V −0.4 mA
OH
=
0.4V 1.4 mA
OL
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 12 mA
All others 2.5 mA
Maximum Input Current Room Temp
without Latchup (Notes 18, 19)
RAM Retention Voltage, V
r
500 ns Rise 2 V
and Fall Time (Min)
Input Capacitance (Note 19) 7 pF
Load Capacitance on D2 (Note 19) 1000 pF
CC
CC
CC
CC
±
100 mA
V
V
V
V
V
V
www.national.com 10
AC Electrical Characteristics COP68xFH:
−55˚C ≤ TA≤ +125˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal Resonator or External V
CKI Clock Duty Cycle (Note 19) f=Max 45 55
Rise Time (Note 19) f=10 MHz Ext Clock 5 µs
Fall Time (Note 19) f=10 MHz Ext Clock 5 µs
Inputs
t
SETUP
t
HOLD
Output Propagation Delay (Note 20) R
t
PD1,tPD0
SO, SK VCC≥ 4.5V 0.7 µs
All Others V
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 20)
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer 1, 2, 3 Input High Time 1 t
Timer 1, 2, 3 Input Low Time 1 t
Reset Pulse Width 1 µs
Note 15: Maximum rate of voltage change must be less than 0.5V/ms.
Note 16: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 17: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
clock monitor and comparators disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.Part will pull up CKI during HALTin crystal clock mode.
Note 18: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V
to VCCwhen biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 19: Parameter characterized but not tested.
Note 20: t
=
Instruction cycle time.
c
)
c
≥ 4.5V 1.0 DC µs
CC
VCC≥ 4.5V 200 ns
VCC≥ 4.5V 60 ns
=
L
≥ 4.5V 1 µs
) (Note 19) 20 ns
UWS
) (Note 19) 56 ns
UWH
UPD
CC
) 220 ns
2.2k, C
L
=
100 pF
HALTis done with device neither sourcing or
DD
and the pins will have sink current
CC
%
c
c
c
c
;
CC
Comparators AC and DC Characteristics
=
V
5V, −40˚C ≤ T
CC
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4V ≤ V
Input Common Mode Voltage Range 0.4 V
Low Level Output Current V
High Level Output Current V
DC Supply Current Per Comparator 250 µA
(When Enabled)
Response Time 100 mV 1 µs
≤ +85˚C
A
≤ VCC− 1.5V
IN
=
0.4V 1.6 mA
OL
=
4.6V 1.6 mA
OH
±
10
±
25 mV
− 1.5 V
CC
Overdrive, 100 pF Load
www.national.com11
Pin Descriptions
VCCand GND are the power supply pins. All VCCand
GND pins must be connected.
CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C,
G and L), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports L
and G), output or TRI-STATE under program control.
Three data memory address locations are allocated for
each of these I/O ports. Each I/O port has two associated
8-bit memory mapped registers, the CONFIGURATION
register and the output DATA register. A memory mapped
address is also reserved for the input pins of each I/O
port. (See the memory map for the various addresses associated with the I/O ports.)
configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
CONFIGURA-
TION
Register
0 0 Hi-Z Input
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins. L1
is used for the USART external clock. L2 and L3 are used for
the USART transmit and receive. L4 and L5 are used for the
timer input functions T2A and T2B. L6 and L7 are used for
the timer input functions T3A and T3B.
The Port L has the following alternate features:
L7 MIWU or T3B
L6 MIWU or T3A
L5 MIWU or T2B
L4 MIWU or T2A
L3 MIWU or RDX
L2 MIWU or TDX
L1 MIWU or CKX
L0 MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALTmode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be individually configured under software control.
DATA
Register
Figure 4
shows the I/O port
Port Set-Up
(TRI-STATE Output)
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below.Reading the G6 and G7
data bits will return zeros.
Note that the chip will be placed in the HALTmode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
DS012602-6
FIGURE 4. I/O Port Configurations
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedi-
cated output
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.
PORTI is an eight-bit Hi-Z input port.The 28-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into
account by either masking or restricting the accesses to bit
operations. The unterminated Port I pins will draw power
only when addressed.
Port I1–I3 are used for Comparator 1. Port I4–I6 are used for
Comparator 2.
www.national.com 12
Pin Descriptions (Continued)
The Port I has the following alternate features.
I6 COMP2OUT (Comparator 2 Output)
I5 COMP2+IN (Comparator 2 Positive Input)
I4 COMP2−IN (Comparator 2 Negative Input)
I3 COMP1OUT (Comparator 1 Output)
I2 COMP1+IN (Comparator 1 Positive Input)
I1 COMP1−IN (Comparator 1 Negative Input)
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay
above 0.8 V
keep the external loading on D2 to less than 1000 pF.
to prevent the chip from entering special modes. Also
CC
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 12288 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the JID
instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
) cycle time.
c
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
The data memory consists of 512 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP,B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Data Memory Segment RAM
Extension
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex. The
upper bit of this single-byte address divides the data store
memory into two separate sections as outlined previously.
With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
for data segment 255. The base address range from 0000 to
007F represents data segment 0.
Figure 5
illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0),
regardless of the contents of the S register.The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always lo-
www.national.com13
Data Memory Segment RAM
Extension
cated in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
(Continued)
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATEmode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
USART registers PSR, ENU (except that TBMT bit is set),
ENUR and ENUI are cleared. The Comparator Select Register is cleared. The S register is initialized to zero. The
Multi-Input Wakeup registers WKEN, WKEDG and WKPND
are cleared. (Wakeup register WKPND is unknown.) The
stack pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
clock cycles. The Clock Monitor bit
C
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
–32 tCclock cycles following
C
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
Figure 6
should be used
to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
*Reads as all ones.
FIGURE 5. RAM Organization
DS012602-8
RC>5 x Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit
www.national.com 14
DS012602-7
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (t
Figure 7
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
).
c
shows the Crystal and R/C oscillator diagrams.
Oscillator Circuits (Continued)
Table 1
shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Table 2
shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is available as a general purpose input and/or HALT restart control.
Crystal Oscillator
DS012602-9
External Oscillator
DS012602-10
R/C Oscillator
DS012602-11
FIGURE 7. Crystal R/C, and
External Oscillator Diagrams
=
TABLE 1. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V
0 1 30 30–36 4 V
0 1 200 100–150 0.455 V
25˚C
A
Conditions
=
5V
CC
=
5V
CC
=
5V
CC
TABLE 2. RC Oscillator Configuration, T
R C CKI Freq Instr. Cycle
(kΩ) (pF) (MHz) (µs)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note: 3k ≤ R ≤ 200k
50 pF ≤ C ≤ 200 pF
=
25˚C
A
Conditions
=
CC
=
CC
=
CC
5V
5V
5V
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C1 Timer T1 mode control bit
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS
IEDG External interrupt edge polarity select
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag
C Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA Timer T1 Interrupt Enable for Timer Underflow
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7 Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be zero.
signals SK and SO respectively
(0 = Rising edge, 1 = Falling edge)
by (00 = 2, 01 = 4, 1x = 8)
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
or T1A Input capture edge
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