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COP87L84BC
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National Semiconductor COP87L84BC Technical data

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COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN Interface
General Description
The COP87L84BC OTP (One Time Programmable) micro­controllers are highly integrated COP8 vices with 16k OTP EPROM memory and advanced features including a CAN 2.0B (passive) interface and two Analog comparators. These multi-chip CMOS devices are suited for applications requiring a full featured controller with a CAN in­terface, and 8-bit 39 kHz PWM timer, and as pre-production devices for a masked ROM design. Pin and software com­patible 2k ROM versions are available (COP884BC) with a range of COP8 software and hardware development tools.
™
Feature core de-
September 1999
Note: The companion devices with CAN interface, more I/O and memory, A/D, and USART are the COP87L88EB/RB.
Device included in this datasheet is:
™
serial I/O, two Analog comparators,
COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN
Interface
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
COP87L84BC 16k OTP EPROM 64 18 28 SOIC -40 to +85˚C
Key Features
n CAN 2.0B (passive) Interface n One 16-bit timer, with two 16-bit registers supporting:
— Processor Independent PWM mode — External Event counter mode — Input Capture mode
n High speed, constant resolution 8-bit PWM/frequency
monitor timer with 2 output pins
n 16 kbytes on-board OTP EPROM with security feature n 64 bytes on-board RAM
Additional Peripheral Features
n Idle Timer n Multi-Input Wake Up (MIWU) with optional interrupts (7) n Two analog comparators n MICROWIRE/PLUS serial I/O
I/O Features
n Memory mapped I/O n Software selectable I/O options (TRI-STATE
Push-Pull Output, Weak Pull-Up Input, High Impedance Input)
n Schmitt trigger inputs on ports G and L n Packages: 28 SO with 18 I/O pins
®
Output,
CPU/Instruction Set Features
n 1 µs instruction cycle time n Eleven multi-source vectored interrupts servicing
— External Interrupt — Idle Timer T0 — Timer T1 (with 2 Interrupts) — MICROWIRE/PLUS — Multi-Input Wake Up — Software Trap — PWM Timer — CAN Interface (with 3 interrupts)
n Versatile and easy to use instruction set n 8-bit Stack Pointer (SP)—stack in RAM n Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE n Single supply operation: 4.5V–5.5V n Temperature ranges: −40˚C to +85˚C
Development Support
n Emulation device for COP884BC/COP885BC n Real time emulation and full program debug offered by
MetaLink Development Systems
COP8™, and MICROWIRE/PLUS™are trademarks of National Semiconductor Corporation.
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
®
iceMASTER
is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS101137 www.national.com
Block Diagram
Connection Diagrams
Note:X=Crystal Oscillator
E=Halt Mode Enabled
Order Number COP87L84BCM-XE
See NS Package Number M28B
FIGURE 2. Connection Diagrams
Top View
FIGURE 1. Block Diagram
Pinouts for 28-Pin SO Package
DS101137-2
DS101137-1
Port Pin Type Alt. Function 28-Pin SO
G0 I/O INTR 25 G1 I/O 26 G2 I/O T1B 27 G3 I/O T1A 28 G4 I/O SO 1 G5 I/O SK 2 G6 I SI 3 G7 I CKO 4 L0 I/O CMP1IN+/MIWU 7 L1 I/O CMP1IN−/MIWU 8 L2 I/O CMP10UT/MIWU 9 L3 I/O CMP2IN−/MIWU 10 L4 I/O CMP2IN+/MIWU 11 L5 I/O CMP2IN−/PWM1/MIWU 12 L6 I/O CMP2OUT/PWM0/
13
CAPTIN/MIWU
D0 O 19 D1 O 20 D2 O 21 D3 O 22 CAN V
REF
18 CAN Tx0 O 15 CAN Tx1 O 14 CAN Rx0 I MIWU 17 CAN Rx1 I MIWU 16 V
CC
6 GND 23 CKI I 5 RESET
I24
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V Voltage at Any Pin −0.3V to V
)6V
CC
CC
+0.3V
Total Current into V
Pin (Source) 90 mA
CC
Total Current out of GND Pin (Sink) 100 mA Storage Temperature Range −65˚C to +150˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C
Parameter Conditions Min Typ Max Units
Operating Voltage 4.5 5.5 V Power Supply Ripple (Note 2) Peak-to-Peak 0.1 V Supply Current CKI = 10 MHz (Note 3) V HALT Current (Notes 4, 5) V
= 5.5V, tc=1µs 19 mA
CC
= 5.5V, CKI=0MHz
CC
Power-On Reset Enabled 480 µA
Power-On Reset Disabled 380 µA IDLE Current (Note 5) CKI = 10 MHz V Input Levels (V
IH,VIL
)
= 5.5V, tc= 1 µs 5.5 mA
CC
Reset, CKI
Logic High 0.8 V
CC
Logic Low 0.2 V
All Other Inputs
Logic High 0.7 V
CC
Logic Low 0.2 V Hi-Z Input Leakage V Input Pull-up Current V G and L Port Input Hysteresis 0.05 V
= 5.5V
CC
= 5.5V, VIN= 0V −40 −250 µA
CC
CC
Output Current Levels D Outputs
Source V
Sink V
= 4.5V, VOH= 3.3V −0.4 mA
CC
= 4.5V, VOL= 1.0V 10 mA
CC
Comparator Output (L2, L6)
Source (Push-Pull) V
Sink (Push-Pull) V
= 4.5V, VOH= 3.3V −1.6 mA
CC
= 4.5V, VOL= 0.4V 1.6 mA
CC
CAN Transmitter Outputs
Source (Tx1) V
Sink (Tx0) V
= 4.5V, VOH=VCC− 0.1V −1.5 mA
CC
V
= 4.5V, VOH=VCC− 0.6V −10 mA
CC
= 4.5V, VOL= 0.1V 1.5 mA
CC
V
= 4.5V, VOL= 0.6V 10 mA
CC
All Others
Source (Weak Pull-Up) V
Source (Push-Pull) V
Sink (Push-Pull) V
TRl-STATE Leakage V
= 4.5V, VOH= 2.7V −10 −110 µA
CC
= 4.5V, VOH= 3.3V −0.4 mA
CC
= 4.5V, VOL= 0.4V 1.6 mA
CC
= 5.5V
CC
Allowable Sink/Source Current per Pin
D Outputs (Sink) 15 mA Tx0 (Sink) 30 mA Tx1 (Source)
All Other
CC
CC
CC
±
2µA
±
2.0 µA
30
3
V
V V
V V
V
mA mA
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DC Electrical Characteristics (Continued)
−40˚C ≤ TA≤ +85˚C
Parameter Conditions Min Typ Max Units
Maximum Input Current without Latchup Room Temp RAM Retention Voltage, V
r
500 ns Rise and Fall Time 2.0 V Input Capacitance 7pF Load Capacitance on D2 1000 pF
Note 2: Maximum rate of voltage change must be less than 0.5 V/ms Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V Note 4: The HALTmode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V
and programmed low; D outputs programmed low. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal clock mode.
Note 5: HALT and IDLE current specifications assume CAN block and comparators are disabled.
or GND, and outputs open.
CC
; L, and G port I/Os configured as outputs
CC
±
100 mA
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V Voltage at Any Pin −0.3V to V
)6V
CC
CC
+0.3V
Total Current into V
Pin (Source) 90 mA
CC
Total Current out of GND Pin (Sink) 100 mA Storage Temperature Range −65˚C to +150˚C
Note 6: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
AC Electrical Characteristics:
−40˚C ≤ TA≤ +85˚C
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal/Resonator V
Inputs
t
SETUP
t
HOLD
PWM Capture Input
t
SETUP
t
HOLD
Output Propagation Delay (t
)C
PD1,tPD0
SK, SO V PWM Outputs V All Others V
MICROWIRE
Setup Time (t Hold Time (t
UWS
UWH
Output Prop Delay (t
Input Pulse Width
Interrupt High Time 1 t Interrupt Low Time 1 t Timer 1,2 High Time 1 t
Timer 1,2 Low Time 1 t Reset Pulse Width 1.0 µs Power Supply Rise Time for Proper 50 µs 256*t
Operation of On-Chip RESET
Note 7: For device testing purposes of all AC parameters, VOHwill be tested at 0.5*VCC. Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 9: Parameter not tested. Note 10: t
= Instruction Cycle Time.
c
)
c
≥ 4.5V 1.0 DC µs
CC
VCC≥ 4.5V 200 ns VCC≥ 4.5V 60 ns
VCC≥ 4.5V 30 ns VCC≥ 4.5V 70 ns
= 100 pF, RL= 2.2 kΩ
L
≥ 4.5V 0.7 µs
CC
≥ 4.5V 75 ns
CC
≥ 4.5V 1 µs
CC
)20ns
)56ns
) 220 ns
UPD
c
c c c c
On-Chip Voltage Reference:
−40˚C ≤ TA≤ +85˚C
Parameter Conditions Min Max Units
<
Reference Voltage I V
REF
Reference Supply Current, I I
DD
Note 11: Reference supply IDDis supplied for information purposes only, it is not tested.
80 µA, 0.5 VCC−0.12 0.5 VCC+0.12 V
OUT
VCC=5V
= 0A, (No Load) 120 µA
OUT
VCC= 5V (Note 11)
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Comparator DC/AC Characteristics:
4.5V ≤ VCC≤ 5.5V, −55˚C ≤ TA≤ +125˚C
Parameter Conditions Min Typ Max Units
<
<
V
Input Offset Voltage 0.4V
IN
VCC−1.5V
Input Common Mode Voltage Range 0.4 V
±
10
±
25 mV
−1.5 V
CC
Voltage Gain 300k V/V Outputs Sink/Source See I/O-Port DC Specifications DC Supply Current (when enabled) V
= 6.0V 250 µA
CC
Response Time TBD mV Step, TBD mV Overdrive, 1 µs
100 pF Load
CAN Comparator DC and AC Characteristics:
4.8V ≤ VCC≤ 5.2V, −40˚C ≤ TA≤ +125˚C
Parameters Conditions Min Typ Max Units
±
Differential Input Voltage
<
Input Offset Voltage 1.5V
V
IN
<
VCC− 1.5V Input Common Mode Voltage Range 1.5 V Input Hysteresis 8mV
25 mV
±
10 mV
− 1.5 V
CC
DS101137-3
FIGURE 3. MICROWIRE/PLUS Timing Diagram
DS101137-4
FIGURE 4. PWM/CAPTURE Timer
Input/Output Timing Diagram
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Typical Performance Characteristics −55˚C ≤ T
Port D Source Current
Port D Sink Current
≤ +125˚C
A
Ports G/L Source Current
Ports G/L Weak Pull-Up Source Current
DS101137-39
DS101137-41
Port G/L Sink Current
Dynamic IDDvs V
CC
DS101137-40
DS101137-42
DS101137-43
DS101137-44
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Typical Performance Characteristics −55˚C ≤ T
Idle I
vs V
DD
CC
Halt Supply Current
≤ +125˚C (Continued)
A
DS101137-45
CAN Tx0 Sink Current
DS101137-47
Pin Descriptions
VCCand GND are the power supply pins. CKI is the clock input. The clockcan come from a crystalos-
cillator (in conjunction with CKO). See Oscillator Description section.
Figure 5
shows the I/O port con­figurations for the device. The DATAand CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
®
under
DS101137-46
CAN Tx1 Source Current
DS101137-48
Configuration Data
Register Register
Port Set-Up
0 0 Hi-Z Input (TRI-STATE
Output) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output
PORT L is a 7-bit I/O port. All L-pins have Schmitt triggers on the inputs.
Port L supports Multi-Input Wake Up (MIWU) on all seven pins.
Port L has the following alternate features: L6 MIWU or CMP2OUT or PWM0 or CAPTIN L5 MIWU or CMP2IN− or PWM1 L4 MIWU or CMP2IN+ L3 MIWU or CMP2IN− L2 MIWU or CMP1OUT L1 MIWU or CMP1IN− L0 MIWU or CMP1IN+ Port G is an 8-bit port with 5 I/O pins (G0–G5), an input pin
(G6), and one dedicated output pin (G7). Pins G0–G6 all have Schmitt Triggerson their inputs. G7 serves as the dedi­cated output pin for the CKO clock output. There are two reg-
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Pin Descriptions (Continued)
isters associated with the G Port, a data register and a con­figuration register. Therefore, each of the 6 I/O bits (G0–G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO clock output pin the associated bits in the data and configu­ration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeroes.
Note that the chip will be placed in the HALT mode bywriting a “1” to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a “1” tobit 6 of the Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en­ables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock.
Config. Register Data Register
G7 HALT G6 Alternate SK IDLE
CAN pins: For the on-chip CAN interface thisdevice has five dedicated pins with the following features:
V
On-chip reference voltage with the value of VCC/2
REF
Rx0 CAN receive data input pin. Rx1 CAN receive data input pin. Tx0 CAN transmit data output pin. This pin may beput in
the TRI-STATE mode with the TXEN0 bit in the CAN Bus control register.
Tx1 CAN transmit data output pin. This pin may beput in
the TRI-STATE mode with the TXEN1 bit in the CAN
Bus control register. Port G has the following alternate features: G6 SI (MICROWIRE Serial Data Input) G5 SK (MICROWIRE Serial Clock) G4 SO (MICROWIRE Serial Data Output) G3 T1A (Timer T1 I/O) G2 T1B (Timer T1 Capture Input) G0 INTR (External Interrupt Input) Port G has the following dedicated function: G7 CKO Oscillator dedicated output Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex­cept D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay above 0.8 V keep the external loading on D2 to less than 1000 pF.
to prevent the chip from entering special modes. Also
CC
DS101137-5
FIGURE 5. I/O Port Configurations
Functional Description
The architecture of the device utilizes a modifiedHarvard ar­chitecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own sepa­rate addressing space with separate address buses. The ar­chitecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t
There are five CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented. X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented. SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad­dress 02F with reset.
All the CPU registers are memory mapped with the excep­tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory for the device consists of 16 kbytes of OTP EPROM. These bytes may hold program instructions or con­stant data (data tables tor the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS in­struction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the device vector to program memory location 0FF Hex.
The device can be configured to inhibit external reads of the program memory. This is done by programming the Security Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte that is located outside of the program address range. This byte can be addressed only from programming mode by a programmer tool.
) cycle time.
c
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Functional Description (Continued)
Security is an optional feature and can only be asserted after the memory array has been programmed and verified. A se­cured part will read all 00(hex) by a programmer. The part will fail Blank Check and will fail Verify operations. A Read operation will fill the programmer’s memory with 00(hex). The Security Byte itself is always readable with value of 00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.
The device has 64 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (other than reserved register 0FF) being available for general us­age.
The instruction set permits any bit in memory to beset, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumula­tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcon­troller. lnitialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for Ports L and G, are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Port D is ini­tialized high with RESET. The PC, PSW, CNTRL, and ICN­TRL control registers are cleared. The Multi-Input Wake Up registers WKEN, WKEDG, and WKPND are cleared. The Stack Pointer, SP, is initialized to 02F Hex.
The following initializations occur with RESET:
Port L: TRI-STATE Port G: TRI-STATE Port D: HIGH PC: CLEARED PSW, CNTRL and ICNTRL registers: CLEARED
Accumulator and Timer 1:
RANDOM after RESET with power already applied
RANDOM after RESET at power-on SP (Stack Pointer): Loaded with 2F Hex CMPSL (Comparator control register): CLEARED PWMCON (PWM control register): CLEARED B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
CAN:
The CAN Interface comes out of external reset in the “error-active” state and waits until the user’s software sets either one or both of the TXEN0, TXEN1 bits to “1”. After that, the device will not start transmission or recep­tion of a frame until eleven consecutive “recessive” (un­driven) bits have been received. This is done to ensure that the output drivers are not enabled during an active message on the bus.
CSCAL, CTlM, TCNTL, TEC, REC: CLEARED RTSTAT: CLEARED with the exception of the TBE bit
which is set to 1 RID, RIDL, TID, TDLC: RANDOM
ON-CHIP POWER-ON RESET
The device is designed with an on-chip power-on reset cir­cuit which will trigger a 256 t minimum RAM retention voltage (V oscillator to stabilize before the device exits the reset state.
delay as VCCrises above the
c
). This delay allows the
r
The contents of data registers and RAM are unknown follow­ing an on-chip power-on reset. The external reset takes pri­ority over the on-chip reset and will deactivate the 256 t lay if in progress.
de-
c
When using external reset, the external RC network shown in
Figure 6
should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes. Under no circumstances should the RESET pin be allowed
. Be aware of
CC
DC Specifications Table. These requirements must be met for the on-chip power-on reset to function properly.
The on-chip power-on reset circuit may reset the device if the operating voltage (V
RC>5 x Power Supply Rise Time
) goes below Vr.
CC
DS101137-6
FIGURE 6. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7. The CKI input frequency is divided by 10 to produce the instruction cycle clock (1/t
Figure 7
shows the Crystal diagram.
).
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Oscillator Circuits (Continued)
DS101137-7
FIGURE 7. Crystal Oscillator Diagram
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closedloop crys­tal (or resonator) controlled oscillator.
Table 1
shows the component values required for various
standard crystal values.
TABLE 1. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq.
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V 0 1 30 30–36 4 V 0 1 200 100–150 0.455 V
= 25˚C
A
Conditions
=5V
CC
=5V
CC
=5V
CC
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7 Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be zero. LPEN L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge T1ENB Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:
T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
Timers
The device contains a very versatile set of timers (T0, T1, and an 8-bit PWM timer). All timers and associated autoreload/capture registers power up containing random data.
Figure 8
shows a block diagram for timers T1 and T0 on the
device.
TIMER T0 (IDLE TIMER)
The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description) Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the thir­teenth bit toggles. This toggle is latched into the T0PND pending flag, and will occur every 4.096 ms at the maximum clock frequency (t terrupt from the thirteenth bit of Timer T0 to be enabled or
= 1 µs). A control flag T0EN allows the in-
c
disabled. Setting T0EN will enable the interrupt, while reset­ting it will disable the interrupt.
TIMER T1
The device has a powerful timer/counter block, T1. The timer block consists of a 16-bit timer, T1, and two sup-
. The user cannot read or
c
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Timers (Continued)
while the pin T1B is an input to the timer block.The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Cap­ture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to gen­erate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM sig­nal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely indepen­dent of the microcontroller. The user software services the timer block only when the PWM parameters require updat­ing.
In this mode the timer T1 counts down at a fixed rate of t Upon every underflow the timer is alternately reloaded with the contents of supporting registers, R1Aand R1B. The very first underflow of the timer causes the timer to reload from the register R1A. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register R1B.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the timer for PWM mode operation.
Figure 9
shows a block diagram of the timer in PWM mode. The underflows can be programmed to toggle the T1Aoutput pin. The underflows can also be programmed to generate in­terrupts.
Underflows from the timer are alternately latched into two pending flags, T1PNDA and T1PNDB. The user must reset these pending flags under software control. Two control en­able flags, T1ENAand T1ENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag T1ENA will cause an interrupt when a timer un­derflow causes the R1A register to be reloaded into the timer. Setting the timer enable flag T1ENB will cause an in­terrupt when a timer underflow causes the R1B register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts.
Either or both of the timer underflow interrupts may be en­abled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.
FIGURE 8. Timers T1 and T0
.
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FIGURE 9. Timer 1 in PWM MODE
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer,T1, is clocked by the input signal from theT1A pin. The T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer to be clocked either on a positive or negative edge from the T1A pin. Underflows from the timer are latched into the T1PNDA pending flag. Setting the T1ENA control flag will cause an interrupt when the timer underflows.
In this mode the input pin T1B can be used as an indepen­dent positive edge sensitive interrupt input if the T1ENB con­trol flag is set. The occurrence of a positive edge on the T1B input pin is latched into the T1PNDB flag.
Figure 10
shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is be-
ing used as the counter input clock.
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the in­put capture mode.
In this mode, the timer T1 is constantly running at the fixed t rate. The two registers, R1A and R1B, act as capture regis­ters. Each register acts in conjunction with a pin. The register R1A acts in conjunction with the T1A pin and the register R1B acts in conjunction with the T1B pin.
DS101137-8
DS101137-9
c
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Timers (Continued)
The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be speci­fied either as a positive or a negative edge. The trigger con­dition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the T1A and T1B pins will be respectively latched into the pending flags, T1PNDA and T1PNDB. The control flag T1ENA allows the interrupt on T1A to be either enabled or disabled. Setting the T1ENA flag enables interrupts to be generated when the selected trigger condition occurs on the T1A pin. Similarly, the flag T1ENB controls the interrupts from the T1B pin.
Underflows from the timer can also be programmed to gen­erate interrupts. Underflows are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer under­flow interrupt pending flag in the Input Capture mode). Con­sequently, the T1C0 control bit should be reset when enter­ing the Input Capture mode. The timer underflow interrupt is enabled with the T1ENA control flag. When a T1A interrupt occurs in the Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt.
Figure 11
shows a block diagram of the timer in Input Cap-
ture mode.
FIGURE 10. Timer 1 in External Event Counter Mode
FIGURE 11. Timer 1 in Input Capture Mode
DS101137-10
DS101137-11
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Timers (Continued)
TIMER CONTROL FLAGS
T1PNDA Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag
The control bits and their functions are summarized below.
T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control
T1PNDB Timer Interrupt Pending Flag T1ENB Timer Interrupt Enable Flag
T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture)
The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:
1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled
1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled
Mode T1C3 T1C2 T1C1 Description
1 0 1 PWM: T1A Toggle Autoreload RA Autoreload RB t
1
1 0 0 PWM: No T1A
Toggle
0 0 0 External Event
2
0 0 1 External Event
Counter
Counter
0 1 0 Captures: Pos. T1A Edge Pos. T1B Edge t
T1A Pos. Edge or Timer T1B Pos. Edge Underflow
1 1 0 Captures: Pos. T1A Neg. T1B t
T1A Pos. Edge Edge or Timer Edge
3
0 1 1 Captures: Neg. T1A Neg. T1B t
T1B Neg. Edge Underflow
T1A Neg. Edge Edge or Timer Edge T1B Neg. Edge Underflow
1 1 1 Captures: Neg. T1A Neg. T1B t
T1A Neg. Edge Edge or Timer Edge T1B Neg. Edge Underflow
HIGH SPEED, CONSTANT RESOLUTION PWM TIMER
The device has one processor independent PWM timer.The PWM timer operates in two modes: PWM mode and capture mode. In PWM mode the timer outputs can be programmed to two pins PWM0 and PWM1. In capture mode, pin PWM0 functions as the capture input. gram for this timer in capture mode and
Figure 12
shows a block dia-
Figure 13
shows a
block diagram for the timer in PWM mode.
PWM Timer Registers
The PWM Timer has three registers: PWMCON, the PWM control register, RLON, the PWM on-time register and PSCAL, the prescaler register.
PWM Prescaler Register (PSCAL)(Address X’00A0)
The prescaler is the clock source for the counter in both PWM mode and in frequency monitor mode.
PSCAL is a read/write register that can be used to program the prescaler.The clock source to the timer in both PWM and capture modes can be programmed to CKI/N where N =
Interrupt A
Source
Autoreload RA Autoreload RB
Timer Underflow
Timer Underflow
Interrupt B
Source
Timer
Counts On
C
t
C
Pos. T1B Edge Pos. T1A
Edge
Pos. T1B Edge Pos. T1A
Edge
C
C
C
C
PSCAL + 1, so the maximum PWM clock frequency = CKI and the minimum PWM clock frequency = CKI/256. The pro­cessor is able to modify the PSCAL register regardless of whether the counter is running or not and the change in fre­quency occurs with the next underflow of the prescaler (CK­PWM).
PWM On-time Register (RLON)(Address X’00A1)
RLON is a read/write register. In PWM mode the timer output will be a “1” for RLON counts out of a total cycle of 255 PWM clocks. In capture mode it is used to program the threshold frequency.
The PWM timer is specially designed to have a resolution of 255 PWM clocks. This allows the duty cycle of the PWM out­put to be selected between 1/255 and 254/255. A value of 0 in the RLON register will result in the PWM output being con­tinuously low and a value of 255 will result in the PWM output being continuously high.
Note: The effect of changing the RLON register during active PWM mode op-
eration is delayed until the boundary of a PWM cycle. In capture mode the effect takes place immediately.
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Timers (Continued)
DS101137-12
FIGURE 12. PWM Timer Capture Mode Block Diagram
FIGURE 13. PWM Timer PWM Mode Block Diagram
PWM Control Register (PWMCON)(Address X’00A2)
Reserved ESEL PWPND PWIE PWMD PWON PWEN1 PWEN0 Bit 7 Bit 0
The PWMCON Register Bits are: Reserved This bit is reserved and should be zero. ESEL Edge select bit, “1” for falling edge, “0” for rising
edge. PWPND PWM interrupt pending bit. PWIE PWM interrupt enable bit. PWMD PWM Mode bit, “1” for PWM mode, “0” for fre-
quency monitor mode. PWON PWM start Bit, “1” to start timer, “0” to stop timer.
DS101137-13
PWEN1 Enable PWM1 output function on I/O port.
Note: The associated bits in the configuration and data register of the I/O-
port have to be setup as outputs and/or inputs in addition to setting the PWEN bits.
PWEN0 Enable PWM0 output/input function on I/O port.
PWM Mode
The PWM timer can generate PWM signals at frequencies up to 39 kHz (
@
tc= 1 µs) with a resolution of 255 parts. Lower PWM frequencies can be programmed via the pres­caler.
If the PWM mode bit (PWMD) in the PWM configurationreg­ister (PWMCON) is set to “1” the timer operates in PWM mode. In this mode, the timer generates a PWM signal with
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Timers (Continued)
a fixed, non-programmable repetition rate of 255 PWM clock cycles. The timer is clocked by the output of an 8-bit, pro­grammable prescaler, which is clocked with the chip’s CKI frequency. Thus the PWM signal frequency can be calcu­lated with the formula:
Selecting the PWM mode by setting PWMD to “1”, but not yet starting the timer (PWON is “0”), will set the timer output to “1”.
The contents of an 8-bit register, RLON, multiplied by the clock cycle of the prescaler output defines the time between overflow (or starting) and the falling edge of the PWM output.
Once the timer is started, the timer output goes low after RLON cycles and high after a total of 255cycles. The proce­dure is continually repeated. In PWM mode the timer is avail­able at pins PWM0 and/or PWM1,provided the port configu­ration bits for those pins are defined as outputs and the PWEN0 and/or PWEN1 bits in the PWMCON register are set.
The PWM timer is started by the software setting the PWON bit to “1”. Starting the timer initializes the timer register. From this point, the timer will continually generate the PWM signal, independent of any processor activity, until the timer is stopped by software setting the PWON bit to “0”. The pro­cessor is able to modify the RLON register regardless of whether the timer is running. If RLON is changed while the timer is running, the previous value of RLON is used for com­parison until the next overflow occurs, when the new value of RLON is latched into the comparator inputs.
When the timer overflows, the PWM pending flag (PWPND) is set to “1”. If the PWM interrupt enable bit (PWIE) is also set to “1”, timer overflow will generate an interrupt. The PWPND bit remains set until the user’s software writes a “0” to it. If the software writes a “1” to the PWPND bit, this has no effect. If the software writes a “0” to the PWPND bit at the same time as the hardware writes to the bit, the hardware has precedence.
Note: The software controlling the duty cycle is able to change the PWM duty
cycle without having to wait for the timer overflow.
Figure 14
shows how the PWM output is implemented. The PWM Timer output is set to “1” on an overflow of the timer and set to “0” when the timer is greater than RLON.The out­put can be multiplexed to two pins.
Capture Mode
If the PWM mode bit (PWMD) is set to “0” the PWM Timer operates in capture mode. Capture mode allows the pro­grammer to test whether the frequency of an external source exceeds a certain threshold.
If PWMD is “0” and PWON is “0”, the timer output is set to “0”. In capture mode the timer output is available at pin PWM1, provided the port configuration register bit for that pin is set up as an output and the PWEN1 bit in the PWMCON register is set. Setting PWON to “1” will initialize the timer register and start the counter.A rising edge, or if se­lected, a falling edge, on the FMONIN input pin will initialize the timer register and clear the timer output. The counter continues to count up after being initialized. The ESELbit de­termines whether the active edge is a rising or a falling edge.
FIGURE 14. PWM Mode Operation
If, in capture mode PWM0 is configured incorrectly as an output and is enabled via the PWEN0 bit, the timer output will feedback into the PWM block as the timer input.
The contents of the counter are continually compared with the RLON register. If the frequency of the input edges is suf­ficiently high, the contents of the counter will always be less
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DS101137-14
than the value in RLON. However, if the frequency of the in­put edges is too low, the free-running counter value will count up beyond the value in RLON.
When the counter is greater than RLON, the PWM timer out­put is set to “1”. It is set to “0” by a detected edge on the timer input or when the counter overflows. When the counter be-
Timers (Continued)
comes greater than RLON, the PWPND bit in the PWM con­trol register is set to “1”. If the PWIE bit is also set to “1”, the PWPND bit is enabled to request an interrupt.
It should be noted that two other conditions could also set the PWPND bit:
1. If the mode of operation is changed on the fly the timer output will toggle. If frequency monitor mode is entered on the fly such that the timer output changes from 0 to 1, PWPND will be set.
2. If the timer is operating in frequency monitor mode and the RLON value is changed on the fly so that RLON be-
comes less than the current timer value, PWPND will be set.
The PWPND bit remains set until the user’s software writes a “0” to it. If the software writes a “1” to the PWPND bit, this has no effect. If the software writes a “0” to the PWPND bit at the same time as the hardware writes to the bit, the hard­ware has precedence. (See
Figure 17
for Frequency Monitor
Mode Operation.) Note: If the clock to the device stops while PWM0 is high,
and a subsequent Reset occurs while the clock is stopped, the PWM0/L6 output will be put in the weak pull-up mode un­til the clock resumes.
FIGURE 15. Frequency Monitor Mode Operation
Power Save Modes
The device offers the user two power save modes of opera­tion: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscil­lator circuitry and timer T0 are active but all other microcon­troller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered.
HALT MODE
The contents of all PWM Timer registers are frozen during HALT mode and are left unchanged when exiting HALT mode. The PWM timer resumes its previous mode of opera­tion when exiting HALT mode.
The device supports two different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wake Up feature on the L port. The second method of exiting the HALT mode is by pulling the RESET pin low.
Since a crystal or ceramic resonator may be selected as the oscillator, the Wake Up signal is not allowed to start the chip
) may be decreased to Vr(Vr= 2.0V)
CC
DS101137-15
running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli­tude and frequency stability. The IDLE timer is used to gen­erate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid WakeUp signal, only the oscillator cir­cuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the t clock is derived by dividing the oscillator clock down by a fac-
instruction cycle clock. The t
c
tor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock signals to be routed to the rest of the chip.
The device has two mask options associated with the HALT mode. The first mask option enables the HALTmode feature, while the second mask option disables the HALTmode. With the HALT mode enable mask option, the device will enter and exit the HALT mode as described above. With the HALT disable mask option, the device cannot be placed in the HALT mode (writing a “1” to the HALT flag will have no ef­fect).
IDLE MODE
The device is placed in the IDLE mode bywriting a “1” to the IDLE flag (G6 data bit). In this mode, all activities,except the associated on-board oscillator circuitry, and the IDLE Timer
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Power Save Modes (Continued)
T0, are stopped. The power supply requirements of the mi­crocontroller in this mode of operation are typically around 30%of normal power requirement of the microcontroller.
As with the HALT mode, the device can be returned to nor­mal operation with a reset, or with a Multi-Input Wake Up from the L Port or CAN Interface. Alternately, the microcon­troller resumes normal operation from the IDLE mode when the thirteenth bit (representing 4.096 ms at internal clockfre­quency of 1 MHz, t
= 1 µs) of the IDLE Timer toggles.
c
This toggle condition of the thirteenth bit of the IDLE Timer T0 is latched into the T0PND pending flag.
Alternatively, the user can enter the IDLE mode with the IDLE TimerT0 interrupt disabled. In thiscase, the device will resume normal operation with the instruction immediately following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes.
Multi-Input Wake Up
The Multi-Input Wake Up feature is used to return (wake up) the device from either the HALT or IDLE modes. Alternately, the Multi-Input Wake Up/Interrupt feature may also be used to generate up to 7 edge selectable external interrupts.
Figure 18
controller. The Multi-Input Wake Up feature utilizes the L Port. The user selects which particular L port bit (or combina­tion of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN is an 8-bit read/write register, which con­tains a control bit for every L port bit. Setting a particular WKEN bit enables a Wake Up from the associated port pin.
The user can select whether the trigger condition on the se­lected L Port pin is going to be either a positive edge (low to
shows the Multi-Input Wake Up logic for the micro-
high transition) or a negative edge (high to low transition). This selection is made via the Reg: WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo Wake Up condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows:
RBIT 5, WKEN ; Disable MIWU SBIT 5, WKEDG ; Change edge polarity RBIT 5, WKPND ; Reset pending flag SBIT 5, WKEN ; Enable MIWU
If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake Up/Interrupt, a safety procedure should also be followed to avoid inherited pseudo wake up conditions. After the selected L port bits have been changed from output to input but before the asso­ciated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared.
This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The oc­currence of the selected trigger condition for Multi-Input Wake Up is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the correspond­ing Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wake up conditions, the device will not enter the HALT mode if any Wake Up bit is both en­abled and pending. Consequently, the user has the respon­sibility of clearing the pending flags before attempting to en­ter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write regis­ters, and are cleared at reset.
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Multi-Input Wake Up (Continued)
FIGURE 16. Multi-Input Wake Up Logic
CAN RECEIVE WAKE UP
The CAN Receive Wake Up source is always enabled and is always active on a falling edge of the CAN comparator out­put. There is no specific enable bit for the CAN Wake Up fea­ture. Although the wake up feature on pins L0..L6 can be programmed to generate an interrupt (L-port interrupt), no in­terrupt is generated upon a CAN receive wake up condition. The CAN block has its own, dedicated receiver interrupt upon receive buffer full.
PORT L INTERRUPTS
Port L provides theuser with an additional seven fullyselect­able, edge sensitive interrupts which are all vectored into the same service subroutine.
The interrupt from Port L shares logic with the wake up cir­cuitry.The register WKEN allows interrupts from Port Lto be individually enabled or disabled. The register WKEDG speci­fies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.
The GIE (global interrupt enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the HALTor IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart ex­ecution from the instruction immediately following the in­struction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the in­terrupt service routine and then revert to normal operation.
The Wake Up signal will not start the chip running immedi­ately since crystal oscillators or ceramic resonators have a fi-
DS101137-16
nite start up time. The IDLE Timer (T0) generates a fixed de­lay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case, upon detecting a valid WakeUp signal, only the oscillator cir­cuitry and the IDLE Timer T0 are enabled.The IDLE Timer is loaded with a value of 256 and is clocked from the t tion cycle clock. The t oscillator clock by a factor of 10. A Schmitt trigger following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large am­plitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock sig­nals to be routed to the rest of the chip.
clock is derived by dividing down the
c
instruc-
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CAN Block Description *
This device contains a CAN serial bus interface as described in the CAN Specification Rev. 2.0 part B.
*Patents Pending.
CAN Interface Block
This device supports applications which require a low speed CAN interface. It is designed to be programmed with two transmit and two receive registers. The user’s program may check the status bytes in order to get information of the bus state and the received or transmitted messages. The device has the capability to generate an interrupt as soon as one byte has been transmitted or received. Care must be taken if more than two bytes in a message frame are to be transmitted/received. In this case the user’s program must poll the transmit buffer empty (TBE)/receive buffer full (RBF) bits or enable their respective interrupts and perform a data exchange between the user data and the Tx/Rx registers.
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CAN Interface Block (Continued)
Fully automatic transmission on error is supported for mes­sages not longer than two bytes. Messages which are longer than two bytes have to be processed by software.
The interface is compatible with CAN Specification 2.0 part B, without the capability to receive/transmit extended frames. Extended frames on the bus are checked and ac­knowledged according to the CAN specification.
The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and soft-
ware overhead. The device can support a bus speed of up to 1 Mbit/s with a 10 MHz oscillator and 2 byte messages. The 1 Mbit/s bus speed refers to the rate at which protocol and data bits are transferred on the bus. Longer messages re­quire slower bus speeds due to the time required for soft­ware intervention between data bytes. The device will sup­port a maximum of 125k bit/s with eight byte messages and a 10 MHz oscillator.
FIGURE 17. CAN Interface Block Diagram
Functional Block Description of the CAN Interface
Interface Management Logic (IML)
The IML executes the CPU’s transmission and reception commands and controls the data transfer between CPU, Rx/Tx and CAN registers. It provides the CAN Interface with Rx/Tx data from the memory mapped Register Block. It also sets and resets the CAN status information and generates interrupts to the CPU.
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DS101137-49
Bit Stream Processor (BSP)
The BSP is a sequencer controlling the data stream between The Interface Management Logic (parallel data) and the bus line (serial data). It controls the transceive logic with regard to reception and arbitration, and creates error signals ac­cording to the bus specification
Functional Block Description of the CAN Interface
Transceive Logic (TCL)
The TCL is a state machine which incorporates the bit stuff logic and controls the output drivers, CRC logic and the Rx/Tx shift registers. It also controls the synchronization to the bus with the CAN clock signal generated by the BTL.
Error Management Logic (EML)
The EML is responsible for the fault confinement of the CAN protocol. It is also responsible for changing the error counters, setting the appropriate error flag bits and interrupts and changing the error status (passive, active and bus off).
Cyclic Redundancy Check (CRC) Generator and Register
The CRC Generator consists of a 15-bit shift register and the logic required to generate the checksum of the destuffed bit­stream. It informs the EML about the result of a receiver checksum.
The checksum is generated by the polynomial:
Receive/Transmit (Rx/Tx) Registers
The Rx/Tx registers are 8-bit shift registers controlled by the TCL and the BSP. They are loaded or read by the Interface Management Logic, which holds the data to be transmitted or the data that was received.
Bit Time Logic (BTL)
The bit time logic divider divides the CKI input clock by the value defined in the CAN prescaler (CSCAL) and bus timing register (CTIM). The resultig bit time (tcan) can be computed by the formula:
15
14
χ
+
χ
+
χ
10
8
+
χ
(Continued)
7
4
+
χ
+
χ
3
+
χ
+1
Where
divider
is the value of the clock prescaler,PSis the
programmable value of phase segment 1 and 2 (1..8) and
PPS
the programmed value of the propagation segment
(1..8) (located in CTIM).
Bus Timing Considerations
The internal architecture of the CAN interface has been op­timized to allow fast software response times within mes­sages of more than two data bytes. The TBE (Transmit Buffer Empty) bit is set on the last bit of odd data bytes when CAN internal sample points are high.
It is the user’s responsibility to ensure that the time between setting TBE and a reload of TxD2 is longer than the length of phase segment 2 as indicated in the following equation:
Table 2
shows examples of the minimum required t
different CSCAL settings based on a clock frequency of
LOAD
for
10 MHz. Lower clock speeds require recalculation of the CAN bit rate and the mimimum t
TABLE 2. CAN Timing (CKI = 10 MHz t
PS CSCAL CAN Bit Rate (kbit/s)
LOAD
.
= 1 µs)
c
Minimum
t
(µs)
LOAD
4 3 250 2.0 4 9 100 5.0 4 15 62 8.0 4 24 40 12.5 439 25 20 499 10 50 4 199 5 100
Figure 19
FIGURE 18. Bit Rate Generation
illustrates the minimum time required for t
.
LOAD
FIGURE 19. TBE Timing
DS101137-50
DS101137-51
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Functional Block Description of the CAN Interface (Continued)
In the case of an interrupt driven CAN interface, the calculation of the actual t
INT: ; Interrupt latency = 7t<inf>c<reset>=7µs
PUSH A ; 3t<inf>c<reset>=3µs LD A,AB ; 2t<inf>c<reset>=2µs PUSH A ; 3t<inf>c<reset>=3µs VIS ; 5t<inf>c<reset>=5µs
CANTX: ; 20t<inf>c<reset> = µs to this point
. ; additional time for instructions which check . ; status prior to reloading the transmit data . ; registers with subsequent data bytes.
LD TXD2,DATA . . .
Interrupt driven programs use more time than programs which poll the TBE flag, however programs which operate at lower baud rates (which are more likely to be sensitive to this issue) have more time for interrupt response.
Output Drivers/Input Comparators
The output drivers/input comparators are the physical inter­face to the bus. Control bits are provided to TRI-STATE the output drivers.
A dominant bit on the bus is represented as a “0” in the data registers and a recessive bit on the bus is represented as a “1” in the data registers.
TDLC3..TDLC0 Transmit Data Length Code These bits determine the number of data bytes to be trans-
mitted within a frame. The CAN specification allows a maxi­mum of eight data bytes in any message.
TRANSMIT IDENTIFIER HIGH (TID) (Address X’00B3)
TRTR TID10 TID9 TID8 TID7 TID6 TID5 TID4
Bit 7 Bit 0
This register is read/write. TRTR Transmit Remote Frame Request This bit is set if the frame to be transmitted is a remote frame
request.
TABLE 3. Bus Level Definition
Bus Level Pin Tx0 Pin Tx1 Data
“dominant”
drive low drive high
(GND) (V
)
CC
0
“recessive” TRI-STATE TRI-STATE 1
Register Block
The register block consists of fifteen 8-bit registers which are described in more detail in the following paragraphs.
Note: The contents of the receiver related registers RxD1, RxD2, RDLC,
RIDH and RTSTAT are only changed if a received frame passes the acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF) is set to accept all received messages.
TRANSMIT DATA REGISTER 1 (TXD1) (Address X’00B0)
The Transmit Data Register 1 contains the first data byte to be transmitted within a frame and then the successive odd byte numbers (i.e., bytes number 1,3,..,7).
TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00B1)
The Transit Data Register 2 contains the second data byte to be transmitted within a frame and then the successive even byte numbers (i.e., bytes number 2,4,..,8).
TRANSMIT DATA LENGTH CODE AND IDENTIFIER LOW REGISTER (TDLC) (Address X’00B2)
TID3 TID2 TID1 TID0 TDLC3 TDLC2 TDLC1 TDLC0 Bit 7 Bit 0
This register is read/write. TID3..TIDO Transmit Identifier Bits 3..0 (lower 4 bits) The transmit identifier is composed of eleven bits in total, bits
3 to 0 of the TID are stored in bits 7 to 4 of this register.
TID10..TID4 Transmit Identifier Bits 10 .. 4 (higher 7 bits) Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit
identifier.
RECEIVER DATA REGISTER 1 (RXD1) (Address X’00B4)
The Receive Data Register 1 (RXD1) contains the first data byte received in a frame andthen successive odd byte num­bers (i.e., bytes 1, 3,..7). This register is read-only.
RECEIVE DATA REGISTER 2 (RXD2) (Address X’00B5)
The Receive Data Register 2 (RXD2) contains the second data byte received in a frame and then successive even byte numbers (i.e., bytes 2,4,..,8). This register is read-only.
REGISTER DATA LENGTH CODE AND IDENTIFIERLOW REGISTER (RIDL) (Address X’00B6)
RID3 RID2 RID1 RID0 RDLC3 RDLC2 RDLC1 RDLC0 Bit 7 Bit 0
This register is read only. RID3..RID0 Receive Identifier bits (lower four bits) The RID3..RID0 bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches the upper 7 bits of the Receive Identifier (RID10..RID4) is ac­cepted if the Receive Identifier Acceptance Filter (RIAF) bit is set to zero.
RDLC3..RDLC0 Receive Data Length Code bits The RDLC3..RDLC0 bits determine the number of data
bytes within a received frame.
RECEIVE IDENTIFIER HIGH (RID) (Address X’00B7)
Reserved RID10 RID9 RID8 RID7 RID6 RID5 RID4
Bit 7 Bit 0
time would be done as follows:
LOAD
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Functional Block Description of the CAN Interface
This register is read/write. Reserved Bit 7 is reserved and must be zero. RID10..RID4 Receive Identifier bits (upper bits) The RID10...RID4 bits are the upper 7 bits of the eleven bit
CAN PRESCALER REGISTER (CSCAL) (Address X’00B8)
CKS7 CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0
Bit 7 Bit 0
This register is read/write. CKS7..0 Prescaler divider select. The resulting clock value is the CAN Prescaler clock.
CAN BUS TIMING REGISTER (CTIM) (00B9)
PPS2 PPS1 PPS0 PS2 PS1 PS0 Reserved Reserved
Bit 7 Bit 0
This register is read/write. PPS2..PPS0 Propagation Segment, bits 2..0 The PPS2..PPS0 bits determine the length of the propaga-
tion delay in Prescaler clock cycles (PSC) per bit time. (For a more detailed discussion of propagation delay and phase segments, see SYNCHRONIZATION.)
PS2..PS0 Phase Segment 1, bits 2..0 The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The PS2..PS0 bits also set the synchronization Jump Width to a value equal to the lesser of: 4 PSC, or the length of PS1/2 (Min: 4 l length of PS1/2).
TABLE 4. Synchronization Jump Width
PS2 PS1 PS0 Phase Jump Width
000 1t 001 2t 010 3t 011 4t 100 5t 101 6t 110 7t 111 8t
LENGTH OF TIME SEGMENTS (See
The Synchronization Segment is 1 CAN Prescaler clock
•
(PSC) The Propagation Segment can be programmed (PPS) to
•
be 1,2...,8 PSC in length. Phase Segment 1 and Phase Segment 2 are program-
•
mable (PS) to be 1,2,..,8 PSC long.
(Continued)
Length of Synchronization
Segment
1
⁄
2
Figure 31
1t 2t 3t 4t 4t 4t 4t 4t
can can can can can can can can
)
can can can can can can can can
Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
the rx-pins through the receive comparator (worst case assumption: 3 clocks delay * 2 (devices on the bus)+1txdelay) the user needs to set the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com­munication on the bus under all circumstances. With prescaler settings of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz CKI and CSCAL = 0.
CAN BUS CONTROL REGISTER (CBUS) (00BA)
Re- RIAF TxEN1 TxEN0 RxREF1 RxREF0 Re- FMOD
served served
Bit 7 Bit 0
Reserved This bit is reserved and must be zero. RIAF Receive identifier acceptance filter bit If the RIAF bit is set to zero, bits4 to 10 ofthe received iden-
tifier are compared with the mask bits of RID4..RID10 and if the corresponding bits match, the message is accepted. If the RIAF bit is set to a one, the filter function is disabled and all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
TABLE 5. Output Drivers
TxEN1 TxEN0 Output
0 0 Tx0, Tx1 TRI-STATE, CAN
input comparator disabled 0 1 Tx0 enabled 1 0 Tx1 enabled 1 1 Tx0 and Tx1 enabled
Bus synchronization of the device is done in the following way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either TxEN1 orTxEN0, or both are set to 1, the device will not start transmission or reception of a frame until eleven consecutive “recessive” bits have been received. Resetting the TxEN1 and TxEN0 bits will disable the output drivers and the CAN input comparator. All other CAN related registers and flags will be unaffected. It is recommended that the user reset the TxEN1 and TxEN0 bits before switching the device into the HALTmode (the CAN receive wakeup will still work) in order to reduce current consumption and to assure a proper resy­chronization to the bus after exiting the HALT mode.
Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE
(independent of the values of the TxEN1 and TxEN0 bits).
RXREF1 Reference voltage applied to Rx1 if bit is set RXREF0 Reference voltage applied to Rx0 if bit is set FMOD Fault Confinement Mode select Setting the FMOD bit to “0” (defaultafter power on reset) will
select the Standard Fault Confinement mode. In this mode the device goes from “bus off” to “error active” after monitor­ing 128*11recessive bits (including bus idle) on the bus. This mode has been implemented for compatibility with existing solutions. Setting the FMOD bit to “1” will select the En­hanced Fault Confinement mode. In this mode the device goes from “bus off” to “error active” after monitoring 128 “good” messages, as indicated by the reception of 11 con­secutive “recessive” bits including the End of Frame, whereas the standard mode may time out after 128 x 11 re­cessive bits (e.g., bus idle).
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Functional Block Description of the CAN Interface
TRANSMIT CONTROL/STATUS (TCNTL) (00BB)
NS1 NS0 TERR RERR CEIE TIE RIE TXSS
Bit 7 Bit 0
NS1..NS0 Node Status, i.e., Error Status.
TABLE 6. Node Status
NS1 NS0 Output
0 0 Error active 0 1 Error passive 1 0 Bus off
1 1 Bus off The Node Status bits are read only. TERR Transmit Error This bit is automatically set when an error occurs during the
transmission of a frame. TERR can be programmed to gen­erate an interrupt by setting the Can Error Interrupt Enable bit (CEIE). This bit must be cleared by the user’s software.
Note: This is used for messages for more than two bytes. If an error occurs
during the transmission of a frame with more than 2 data bytes, the us­er’s software has to handle the correct reloading of the data bytes to the TxD registers for retransmission of the frame. For frames with 2 or fewer data bytes the interface logic of this chip does an automatic re­transmission. Regardless of the number of data bytes, the user’s soft­ware must reset this bit if CEIE is enabled. Otherwise a new interrupt will be generated immediately after return from the interrupt service routine.
RERR Receiver Error This bit is automatically set when an error occurred during
the reception of a frame. RERR can be programmed to gen­erate an interrupt by setting the Can Error Interrupt Enable bit (CEIE). This bit has to be cleared by the user’s software.
CEIE CAN Error Interrupt Enable If set by the user’s software, this bit enables the transmit and
receive error interrupts. The interrupt pending flags are TERR and RERR. Resetting this bit with a pending error in­terrupt will inhibit the interrupt, but will not clear the cause of the interrupt (RERR or TERR). If the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur.
TIE Transmit Interrupt Enable If set by the user’s software, this bit enables the transmit in-
terrupt. (See TBE and TXPND.) Resetting this bit with a pending transmit interrupt will inhibit the interrupt, but will not clear the cause of the interrupt. If the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur.
RIE Receive Interrupt Enable If set by the user’s software, this bit enables the receive in-
terrupt or a remote transmission request interrupt (see RBF, RFV and RRTR). Resetting this bit with a pending receive in­terrupt will inhibit the interrupt, but will not clear the cause of the interrupt. If the bit is then set without clearing the cause of the interrupt, the interrupt will reoccur.
TXSS Transmission Start/Stop This bit is set by the user’s software to initiate the transmis-
(Continued)
sion. If the device has already started transmission (won ar­bitration) the TXPND and TXSS flags will stay set until the transmission is completed, even if the user’s software has written zero to the TXSS bit. If one or more data bytes are to be transmitted, care must be taken by the user, that the Transmit Data Register(s) have been loaded before the TXSS bit is set. TXSS will be cleared on three conditions only: Successful completion of a transmitted message; suc­cessful cancellation of a pending transmision; Transition of the CAN interface to the bus-off state.
DS101137-52
FIGURE 20. Acceptance Filter Block-Diagram
Writing a zero to the TXSS bit will request cancellation of a pending transmission but TXSS will not be cleared until completion of the operation. If an error occurs during trans­mission of a frame, the logic will check for cancellation re­quests prior to restarting transmission. If zero has been writ­ten to TXSS, retransmission will be canceled.
RECEIVE/TRANSMIT STATUS (RTSTAT) (Address X’00BC)
TBE TXPND RRTR ROLD RORN RFV RCV RBF
10 000000
Bit 7 Bit 0
This register is read only. TBE Transmit Buffer Empty This bit is set assoon as the TxD2 register is copied into the
Rx/Tx shift register, i.e., the 1st data byte of each pair has been transmitted. The TBE bit is automatically reset if the TxD2 register is written (the user should write a dummy byte to the TxD2 register when transmitting an odd number of bytes of zero bytes). TBE can be programmed to generate an interrupt by setting the Transmit Interrupt Enable bit (TIE). When servicing the interrupt the user has to make sure that TBE gets cleared by executing a WRITE instruction on the TxD2 register, otherwise a new interrupt will be generated immediately after return from the interrupt service routine. The TBE bit is read only. It isset to 1 uponreset. TBE is also set upon completion of transmission of a valid message.
TXPND Transmission Pending This bit is set as soon as the Transmit Start/Stop (TXSS) bit
is set by the user. It will stay setuntil the frame was success­fully transmitted, until the transmission was successfully can­celed by writing zero to the Transmission Start/Stop bit (TXSS), or the device enters the bus-off state. Resetting the TXSS bit will only cancel a transmission if the transmission of a frame hasn’t been started yet (bus idle) or if arbitration has been lost (receiving). If the device has already started transmission (won arbitration) the TXPND flag will stay set until the transmission is completed, even if the user’s soft­ware has requested cancellation of the message. If an error occurs during transmission, a requested cancellation may occur prior to the begining of retransmission.
RRTR Received Remote Transmission Request
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Functional Block Description of the CAN Interface
To detect RRTR the user can either poll this flag or enable the receive interrupt (the reception of a remote transmission request will also cause an interrupt if the receive interrupt is enabled). If the receive interrupt is enabled, the user should check the RRTR flag in the service routine in order to distin­guish between a RRTR interrupt and a RBF interrupt. It is the responsibility of the user to clear this bit by reading the RXD1 register, before the next frame is received.
ROLD Received Overload Frame This bit is automatically set when an Overload Frame was
RORN Receiver Overrun This bit is automatically set on an overrun of the receive data
register, i.e., if the user’s program does not maintain the RxDn registers when receiving a frame. It itautomatically re­set through a read of the Receive/TransmitStatus register. It is the responsibility of the user to clear thisbit by readingthe Receive/Transmit Status register beforethe next frame is re­ceived.
RFV Received Frame Valid This bit is set if the received frame is valid, i.e., after the pen-
ultimate bit of the End of Frame is received. It is automati­cally reset through a read of the Receive/Transmit Status register. It is the responsibility of the user to clear this bit by reading the receive/transmit status register (RTSTAT), be­fore the next frame is received. RFV will cause aReceive In­terrupt if enabled by RIE. The user should be careful to read the last data byte (RxD1) of odd length messages (1, 3, 5 or 7 data bytes) on receipt of RFV. RFV is the only indication that the last byte of the message has been received.
RCV Receive Mode This bit is set after the data length code of a message that
RBF Receive Buffer Full This bit is set if the second Rx data byte was received. It is
reset automatically, after the RxD1-Register has been read by the software. RBF can beprogrammed to generate an in­terrupt by setting the Receive Interrupt Enable bit (RIE). When servicing the interrupt, the user has to make sure that RBF gets cleared by executing a LD instruction from the RxD1 register, otherwise a new interrupt will be generated immediately after return from the interrupt service routine. The RBF bit is read only.
TRANSMIT ERROR COUNTER (TEC) (Address X’00BD)
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
Bit 7 Bit 0
This register is read/write.
(Continued)
For test purposes and to identify the node status, the trans­mit error counter, an 8-bit error counter, is mapped into the data memory. If the lower seven bits of the counter overflow, i.e., TEC7 is set, the device is error passive.
CAUTION
To prevent interference with the CAN fault confinement, the user must not write to the REC/TEC registers. Bothcounters are automatically updated following the CAN specification.
RECEIVE ERROR COUNTER (REC) (00BE)
ROVL REC6 REC5 REC4 REC3 REC2 REC1 REC0
Bit 7 Bit 0
This register is read/write. ROVL receive error counter overflow For test purposes and to identify the node status the receive
error counter, a 7-bit error counter, is mapped into the data memory. If the counter overflows the ROVL bit is set to indi­cate that the device is error passive and won’t transmit any active error frames. If ROVL is set then the counter is frozen.
MESSAGE IDENTIFICATION a. Transmitted Message
The user can select all 11 Transmit Identifier Bits to transmit any message whigh fulfills the CAN2.0, part B spec without an extended identifier (see note below). Fully automatic re­transmission is supported for messages no longer than 2 bytes.
b. Received Messages
The lower four bits of the Receive Identifier are don’t care, i.e., the controller will receive all messages that fit in that win­dow (16 messages). The upper 7 bits can be defined by the user in the Receive Identifier High Register to mask out groups of messages. If the RIAF bit is set, all messages will be received.
Note: The CAN interface tolerates the extended CAN frame format of 29
identifier bits and gives an acknowledgment. If an error occurs the re­ceive error counter will be increased, and decreased if the frame is valid.
BUS SYNCHRONIZATION DURING OPERATION
Resetting the TxEN1 and TxEN0 bits in Bus Control Register will disable the output drivers and do a resynchronization to the bus. All other CAN related registers and flags will be un­affected.
Bus synchronization of the device is this case is done in the following way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either TxEN1 orTxEN0, or both are set to 1, the device will not start transmission or reception of a frame until eleven consecutive “recessive” bits have been received.
For information on bus synchronization and status of the CAN related registers after external reset refer to the RESET section.
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Functional Block Description of the CAN Interface
ON-CHIP VOLTAGE REFERENCE
The on-chip voltage reference is a ratiometric reference. For electrical characteristics of the voltage reference refer to the electrical specifications section.
ANALOG SWITCHES
Analog switches are used for selecting between Rx0 and V
and between Rx1 and V
REF
(Continued)
.
REF
Basic CAN Concepts
The following paragraphs provide a generic overview of the basic concepts of the Controller Area Network (CAN) as de­scribed in lated issues of the National Semiconductor device will be discussed as well.
This device will process standard frame format only. Ex­tended frame formats will be acknowledged, however the data will be discarded. For this reason the description of frame formats in the following section will cover only the standard frame format.
The following section provides some more detail on how the device will handle received extended frames:
If the device’s remote identifier acceptancefilter bit (RIAF) is set to “1”, extended frame messages will be acknowledged. However, the data will be discarded and the device will not reply to a remote transmission request received in extended frame format. If the device’s RIAF bit is set to “0”, the upper 7 received ID bits of an extended frame that match the de­vice’s receive identifier (RID) acceptance filtler bits, are stroed in the device’s RID register. However,the device does not reply to an RTR and any data is discarded. The device will only acknowledge the message.
MULTI-MASTER PRIORITY BASED BUS ACCESS
MULTICAST FRAME TRANSFER BY ACCEPTANCE FILTERING
Every CAN Frame is put on the common bus. Each module receives every frame and filters out the frames which are not required for the module’s task.
REMOTE DATA REQUEST
A CAN master module has the ability to set a specific bit called the “remote transmission request bit” (RTR) in a frame. This causes another module, either another master or a slave, to transmit a data frame after the current frame has been completed.
SYSTEM FLEXIBILITY
Additional modules can be added to an existing network without a configuration change. These modules can either perform completely new functions requiring new data or pro­cess existing data to perform a new function.
Chapter 4 of ISO/DIS11519-1.
11
−16) different messages in the standard
29
−16) different messages in the
Implementation re-
SYSTEM WIDE DATA CONSISTENCY
As the CAN network is message oriented, a message can be used like a variable which is automatically updated by the controlling processor.If any module cannotprocess informa­tion it can send an overload frame. The device is incapable of initiating an overload frame, but will join a overload frame initiated by another device as required by CAN specifica­tions.
NON-DESTRUCTIVE CONTENTION-BASED ARBITRATION
The CAN protocol allows several transmitting modules to start a transmission at the same time as soon as they moni­tor the bus to be idle. During the start of transmission every node monitors the bus line to detect whether its message is overwritten by a message with a higher priority.As soon as a transmitting module detects another module with a higher priority accessing the bus, it stopstransmitting its own frame and switches to receive mode. Forillustration see
AUTOMATIC RETRANSMISSION OF FRAMES
If a data or remote frame is overwritten by either a higher­prioritized data frame, remote frame or an error frame, the transmitting module will automatically retransmit it. This de­vice will handle the automatic retransmission of up to two data bytes automatically. Messages with more than 2 data bytes require the user’s software to update the transmit reg­isters.
ERROR DETECTION AND ERROR SIGNALING
All messages on the bus are checked by each CAN node and acknowledge if they are correct. If any node detects an error it starts the transmission of an error frame.
Switching Off Defective Nodes
There are two error counters, one for transmitted data and one for received data, which are incremented, depending on the error type, as soon as an error occurs. If either counter goes beyond a specific value the node goes to an error state. A valid frame causes the error counters to decrease.
The device can be in one of three states with respect to error handling:
Error active
•
An error active unit can participate in bus communication and sends an active (“dominant”) error flag.
Error passive
•
An error passive unit can participate in bus communica­tion. However, if the unit detects an error it is not allowed to send an active error flag. The unit sends only a passive (“recessive”) error flag.
Bus off
•
A unit that is “bus off” has the output drivers disabled, i.e., it does not participate in any bus activity.
(See ERROR MANAGEMENT AND DETECTION for more detailed information.)
Figure 21
.
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Frame Formats
INTRODUCTION
There are basically two different types of frames used in the CAN protocol.
The data transmission frames are: data/remote frame The control frames are: error/overload frame
Note: This device cannot send an overload frame as a result of not being
able to process all information. However, the device is able to recog­nize an overload condition and join overload frames initiated by other devices.
If no message is being transmitted, i.e., the bus is idle, the bus is kept at the “recessive” level. give an overview of the various CAN frame formats.
DATA AND REMOTE FRAME
Data frames consist of seven bit fields and remote frames consist of six different bit fields:
1. Start of Frame (SOF)
2. Arbitration field
3. Control field (IDE bit, R0 bit, and DLC field)
4. Data field (not in remote frame)
5. CRC field
Figure 22
and
Figure 23
6. ACK field
7. End of Frame (EOF) A remote frame has no data field and is used for requesting
data from other (remote) CAN nodes.
Figure 24
shows the
format of a CAN data frame.
FRAME CODING
Remote and Data Frames are NRZ codes with bit-stuffing in every bit field which holds computable information for the in­terface, i.e., Start of Frame arbitration field, control field, data field (if present) and CRC field.
Error and overload frames are NRZ coded without bit stuff­ing.
BIT STUFFING
After five consecutive bits of the same value, a stuff bit of the inverted value is inserted by the transmitter and deleted by the receiver.
Destuffed Bit Stream 100000x 011111x Stuffed Bit Stream 1000001x 0111110x
Note: x = {0,1}
FIGURE 21. CAN Message Arbitration
DS101137-53
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Frame Formats (Continued)
DS101137-54
A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field. IDE = Identifier Extension Bit The IDE bit in the standard format is transmitted “dominant”, whereas in the extended format the IDE bit is “recessive” and the id is expanded to 29 bits. r = recessive d = dominant
DS101137-55
FIGURE 22. CAN Data Transmission Frames
An error frame can start anywhere in the middle of a frame.
INT = Intermission Suspend Transmission is only for error passive nodes.
DS101137-56
DS101137-57
An overload frame can only start at the end of a frame.
FIGURE 23. CAN Control Frames
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DS101137-58
Frame Formats (Continued)
FIGURE 24. CAN Frame Format
START OF FRAME (SOF)
The Start of Frame indicates the beginning of data and re­mote frames. It consists of a single “dominant” bit. A node is only allowed to start transmission when the bus is idle. All nodes have to synchronize to the leading edge (first edge af­ter the bus was idle) caused by SOF of the node which starts transmission first.
ARBITRATION FIELD
The arbitration field is composed of the identifier field and the RTR (Remote Transmission Request) bit. The value of the RTR bit is “dominant” in a data frame and “recessive” in a re­mote frame.
CONTROL FIELD
The control field consists of six bits. It starts with two bits re­served for future expansion followed by the four-bit Data Length Code. Receivers must accept all possible combina­tions of the two reserved bits. Until the function of these re­served bits is defined, the transmitter only sends “0” (domi­nant) bits. The first reserved bit (IDE) is actually defined to indicate an extended frame with 29 Identifierbits if setto “1”. CAN chips must tolerate extended frames, even if they can only understand standard frames, to prevent the destruction of an extended frames on an existing network.
The Data Length Code indicates the number of bytes in the data field. This Data Length Code consists of four bits. The data field can be of length zero. The permissible number of data bytes for a data frame ranges from 0 to 8.
DATA FIELD
The Data field consists of the data to be transferred within a data frame. It can contain 0 to 8 bytes and each byte con­tains 8 bits. A remote frame has no data field.
CRC FIELD
The remainder of this division is the CRC sequence transmit­ted over the bus. On the receiver side the module divides all bit fields up to the CRC delimiter, excluding stuff-bits, and checks if the result is zero. This will then be interpreted as a valid CRC. After the CRC sequence a single “recessive” bit is transmitted as the CRC delimiter.
15
χ
+ χ14+ χ10+ χ8+ χ7+ χ4+ χ3+1
DS101137-59
ACK FIELD
The ACK field is two bits long and contains the ACK slot and theACK delimiter. The ACK slotis filled witha “recessive” bit by the transmitter.This bit is overwritten with a “dominant” bit by every receiver that has received a correct CRC se­quence. The second bit of the ACK field is a “recessive” bit called the acknowledge delimiter.As a consequence the ac­knowledge flag of a valid frame is surrounded by two“reces­sive” bits, the CRC-delimiter and the ACK delimiter.
EOF FIELD
The End of Frame Field closes a data anda remote frame.It consists of seven “recessive” bits.
INTERFRAME SPACE
Data and remote frames are separate from every preceding frame (data, remote, error and overload frames) by theinter­frame space see
Figure 25
and
Figure 26
for details. Error and overload frames are not preceded by an interframe space. They can be transmitted as soon as the condition oc­curs. The interframe space consists of a minimum of three bit fields depending on the error state of the node.
These bit fields are coded as follows: The intermission has the fixed form of three “recessive” bits.
ERROR FRAME
Figure 27
shows how a local fault at one module (module 2) leads to a 12-bit error frame on the bus.
The bus level may either be “dominant” for an error-active node or “recessive” for an error-passive node. An error ac-
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Frame Formats (Continued)
tive node detecting an error, starts transmitting an active er­ror flag consisting of six “dominant” bits. This causes the de­struction of the actual frame on the bus. The other nodes detect the error flag as either a violation of the rule of bit­stuffing or the value of a fixed bit field is destroyed. As a con­sequence all other nodes start transmission of their own er­ror flag. This means, that the error sequence which can be monitored on the bus as a maximum length of twelve bits. If an error passive node detects an error it transmits six “reces-
FIGURE 25. Interframe Space for Nodes Which Are Not
Error Passive or Have Been Receiver for the Last Frame
FIGURE 26. Interframe Space for Nodes Which Are Error Passive
and Have Been Transmitter for the Last Frame
sive” bits on the bus. This sequence does not destroy a mes­sage sent by another node and is not detected by other nodes. However, if the node detecting an error was the transmitter of the frame the other modules will get an error condition by a violation ofthe fixed bit or stuff rule.
Figure 26
shows how an error passive transmitter transmits a passive error frame and when it is detected by the receivers.
After any module has transmitted its active or passive error flag it waits for the error delimiter which consists of eight “re­cessive” bits before continuing.
DS101137-60
DS101137-61
OVERLOAD FRAME
Like an error frame, an overload frame consists of two bit fields: the overload flag and the overload delimiter. The bit fields have the same length as the error frame field: six bits for the overload flag and eight bits for the delimiter. The over­load frame can only be sent after the end of frame (EOF) field and in they way destroys the fixed form of the intermis­sion field.
ORDER OF BIT TRANSMISSION
A frame is transmitted starting with the Start of Frame, se­quentially followed by the remaining bit fields. In every bit field the MSB is transmitted first.
FRAME VALIDATION
Frames have a different validation point for transmitters and receivers.A frame is valid for the transmitter of amessage, if there is no error until the end of the last bit of the End of Frame field. A frame is validfor a receiver, ifthere is no error until and including the end of the penultimate bit of the End of Frame.
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FRAME ARBITRATION AND PRIORITY
Except for an error passive node which transmitted the last frame, all nodes are allowed to start transmission of a frame after the intermission, which can lead to two or more nodes starting transmission at the same time. To prevent a node from destroying another node’s frame, it monitors the bus during transmission of the identifier field and the RTR-bit. As soon as it detects a “dominant” bit while transmitting a “re­cessive” bit it releases the bus, immediately stops transmis­sion and starts receiving the frame. This causes no data or remote frame to be destroyed by another. Therefore the highest priority message with the identifier 0x000 out of 0x7EF (including the remote data request (RTR) bit) always gets the bus. This is only valid for standard CAN frame for­mat. Note that while the CAN specification allows valid stan­dard identifiers only in the range 0x000 to 0x7EF, the device will allow identifiers to 0x7FF.
There are three more items that should be taken into consid­eration to avoid unrecoverable collisions on the bus:
Frame Formats (Continued)
module 1 = error active transmitter detects bit error at t2 module 2 = error active receiver with a local fault at t1 module 3 = error active receiver detects stuff error at t2
FIGURE 27. Error Frame—Error Active Transmitter
Within one system each message must be assigned a
•
unique identifier.This is to prevent bit errors, as one mod­ule may transmit a “dominant” data bit while the other is transmitting a “recessive” data bit. This could happen if two or more modules start transmission of a frame at the same time and all win arbitration.
Data frames with a given identifier and a non-zero data
•
length code may be initiated by one node only. Other­wise, in worst case, two nodes would count up to the bus­off state, due to bit errors, if they always start transmitting the same ID with different data.
Every remote frame should have a system-wide data
•
length code (DLC). Otherwise two modules starting transmission of a remote frame at the same time will overwrite each other’s DLC which result in bit errors.
DS101137-62
ACCEPTANCE FILTERING
Every node may perform acceptance filtering on the identi­fier of a data or a remote frame to filter out the messages which are not required by the node. In they way only the data of frames which match the acceptance filter is stored in the corresponding data buffers. However, every node which is not in the bus-off state and has received a correct CRC­sequence acknowledges each frame.
ERROR MANAGEMENT AND DETECTION
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Frame Formats (Continued)
module 1 = error active receiver with a local fault at t1 module 2 = error passive transmitter detects bit error at t2 module 3 = error passive receiver detects stuff error at t2
FIGURE 28. Error Frame—Error Passive Transmitter
FIGURE 29. Order of Bit Transmission within a CAN Frame
The following errors can be detected:
Bit Error
•
A CAN device that is sending also monitors the bus. If the monitored bit value is different fromthe bitvalue thatis sent, a bit error is detected. The reception of a “dominant” bit in­stead of a “recessive” bit during the transmission of a pas­sive error flag, during the stuffed bit stream of the arbitration field or during the acknowledge slot, is not interpreted as a bit error.
Stuff error
•
A stuff error is detected, if the bit level after 6 consecutive bit times has not changed in a message field that has to be coded according to the bit stuffing method.
Form Error
•
Aform error is detected, ifa fixed frame bit (e.g.,CRC delim­iter,ACK delimiter) does not have the specified value. For a receiver a “dominant” bit during the last bit of End of Frame does NOT constitute a form error.
Bit CRC Error
•
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ACRC error is detected ifthe remainder ofthe CRC calcula­tion of a received CRC polynomial is non-zero.
Acknowledgment Error
•
An acknowledgment error is detected whenever a transmit­ting node does not get an acknowledgment from any other node (i.e., when the transmitter does not receive a “domi­nant” bit during the ACK frame).
The device can be in one of three states with respect to error handling:
Error active
•
Error passive
•
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Frame Formats (Continued)
Bus off
•
A unit that is “bus off” has the output drivers disabled, i.e., it does not participate in any bus activity. A device is bus off when the transmit error counter is greater than 255. A bus off device will become error active again in one of two ways de­pending on which mode is selected by the user through the Fault Confinement Mode select bit (FMOD) in the CAN Bus Control Register (CBUS). Setting the FMOD bit to “0” (de­fault after power on reset) will select the Standard Fault Con­finement mode. In this mode the device goes from “bus off” to “error active” after monitoring 128*11 recessive bits (in­cluding bus idle) on the bus. This mode has been imple­mented for compatibility reasons with existing solutions. Set­ting the FMOD bit to “1” will select the Enhanced Fault Confinement mode. In this mode the device goes from “bus off” to “error active” after monitoring 128 “good” messages, as indicated by the reception of 11 consecutive “recessive” bits including the End of Frame. The enhanced mode offers the advantage that a “bus off” device (i.e., a device with a se­rious fault) is not allowed to destroy any messages on the bus until other devices can transmit at least 128 messages. This is not guaranteed in the standard mode,where a defec­tive device could seriously impact bus communication. When the device goes from “bus off” to “error active”, both error counters will have the value “0”.
In each CAN module there are two error counters toperform a sophisticated error management. The receive error counter (REC) is 7 bits wide and switches the device to the error passive state if it overflows. The transmit error counter (TEC) is 8 bits wide. If it is greater than 127, the device is switched to the error passive state. As soon as the TEC overflows, the device is switched bus-off, i.e., it does not par­ticipate in any bus activity.
The counters are modified by the device’s hardware accord­ing to the following rules:
TABLE 7. Receive Error Counter Handling
Condition
A receiver detects a Bit Error during sending an active error flag.
A receiver detects a “dominant” bit as the first bit after sending an error flag.
After detecting the 14th consecutive “dominant” bit following an active error flag or overload flag or after detecting the 8th consecutive “dominant” bit following a passive error flag. After each sequence of additional 8 consecutive “dominant” bits.
Any other error condition (stuff, frame, CRC, ACK).
A valid reception or transmission.
TABLE 8. Transmit Error Counter Handling
Condition
A transmitter detects a Bit Error during sending an active error flag.
After detecting the 14th consecutive “dominant” bit following an active error flag or overload flag or after detecting the 8th consecutive “dominant” bit following a passive error flag. After each sequence of additional 8 consecutive “dominant” bits.
Any other error condition (stuff, frame, CRC, ACK).
A valid reception or transmission.
Special error handling for the TEC counter is performed in the following situations:
A stuff error occurs during arbitration, when a transmitted
•
“recessive” stuff bit is received as a “dorminant” bit. This does not lead to an incrementation of the TEC.
Receive Error
Counter
Increment by 8
Increment by 8
Increment by 8
Increment by 1
Decrement by 1 if Counter is not 0
Transmit Error
Counter
Increment by 8
Increment by 8
Increment by 8
Decrement by 1 if Counter is not 0
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Frame Formats (Continued)
An ACK-error occurs in an error passive device and no
•
“dominant” bits are detected while sending the passive error flag. This does not lead to an incrementation of the TEC.
If only one device is on the bus and this device transmits
•
a message, it will get no acknowledgment. This will be detected as an error and message will be repeated. When the device goes “error passive” and detects an ac­knowledge error, the TEC counter is not incremented. Therefore the device will not go from “error passive” to the “bus off” state due to such a condition.
FIGURE 30. CAN Bus States
Figure 30
cording to the error counters.
shows the connection of different bus states ac-
DS101137-65
SYNCHRONIZATION
Every receiver starts with a “hard synchronization” on the falling edge of the SOF bit. One bit time consists of four bit segments: Synchronization segment, propagation segment, phase segment 1 and phase segment 2.
A falling edge of the data signal should be in the synchroni­zation segment. This segment has the fixed length of one time quanta. To compensate for the various delays within a network, the propagation segment is used. Its length is pro­grammable from 1 to 8 time quanta. Phase segment 1 and phase segment 2 are used to resynchronize during an active frame. The length of these segments is from 1 to 8 time quanta long.
Two types of synchronization are supported: Hard synchronization is done with the falling edge on the
bus while the bus is idle, which is then interpreted as the SOF. It restarts the internal logic.
Soft synchronization is used to lengthen or shorten the bit time while a data or remote frame is received. Whenever a falling edge is detected in the propagation segment or in phase segment 1, the segment is lengthened by a specific value, the resynchronization jump width (see
If a falling edge lies in the phase segment 2 (as shown in
ure 32
) it is shortened by the resynchronization jump width.
Figure 32
).
Fig-
Only one resynchronization is allowed during one bit time. The sample point lies between the two phase segments and is the point where the received data is supposed to be valid. The transmission point lies at the endof phase segment2 to start a new bit time with the synchronization segment.
Note 12: The resynchronization jump width (RJW) is automatically deter­mined from the programmed value of PS. If a soft resynchronization is done during phase segment 1 or the propagation segment, then RJW will either be equal to 4 internal CAN clocks (CKI/(1 PS, whichever is less. PS2 will never be shorter than 1 internal CAN clock.
Note 13: (PS1— BTL settings any PSC setting) The PS1 of the BTL should always be programmed to values greater than 1. To allow device resynchro­nization for positive and negative phase errors on the bus. (if PS1 is pro­grammed to one, a bit time could only be lengthened and never shortened which basically disables half of the synchronization).
+ divider)
) or the programmed value of
A) Synchronization segment B) Propagation segment
FIGURE 31. Bit Timing
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DS101137-66
Frame Formats (Continued)
DS101137-67
FIGURE 32. Resynchronization 1
FIGURE 33. Resynchronization 2
Comparators
The device has two differential comparators. Port L is used for the comparators. The output of the comparators is multi­plexed out to two pins. The following are the Port L assign­ments:
L6 Comparator 2 output L5 Comparator 2 negative input L4 Comparator 2 positive input L3 Comparator 2 negative input L2 Comparator 1 output L1 Comparator 1 negative input L0 Comparator 1 positive input Additionally the comparator output can be connected inter-
nally to the L-Port pin of the respective positive input and thereby generate an interrupt using the L-Port interrupt structure (neg/pos. edge, enable/disable).
Note that in of supporting the PWM0 output. The comparator 2 output MUST be disabled in order to use PWM0 output on L6.
Figure 34
Figure 34
, pin L6 has a second alternate function
shows the Comparator Block Diagram.
DS101137-68
COMPARATOR CONTROL REGISTER (CMPSL) (00D3)
These bits reside in the Comparator Register
CMP2 CMP2 CMP2 CMP2 CMP1 CMP1 CMP1 Re-
SEL OE RD EN OE RD EN served
Bit 7 Bit 0
The register contains the following bits: CMP2SEL Selects which L port pin to use for comparator2
negative input. (CMP2SEL = 0 selects L5; CMP2SEL = 1 selects pin L3).
CMP2OE Enables comparator 2 output (“1”=enable),
CMP2EN bit must be set to enable this function.
CMP2RD Reads comparator 2 output internally
(CMP2EN=1) Read-only, reads as a “0” if com­parator not enabled.
CMP2EN Enables comparator 2 (“1”=enable). If compara-
tor 2 is disabled the associated L-pins can be used as standard I/O.
CMP1OE Enables comparator 1 output (“1”=enable),
CMP1EN bit must be set to enable this function.
CMP1RD Reads comparator 1 output internally
(CMP1EN=1) Read-only, reads as a “0” if com­parator not enabled.
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Comparators (Continued)
CMP1EN Enables comparator 1 (“1”=enable). If compara-
tor 1 is disabled the associated L-pins can be
used as standard I/O. Reserved This bit is reserved and should be zero. The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power, the program should also disable the comparator before the device enters the HALT mode.
The Comparator rise and fall times are symmetrical. The user program must set up the Configuration and Data regis­ters of the L port correctly for comparator Inputs/Output.
The BOXED area shows logic from PWM Timer. Comparator 2 output (CMP2OE) must be disabled in order to use PWM0 output.
FIGURE 34. Comparator Block
Interrupts
INTRODUCTION
Each device supports eleven vectored interrupts. Interrupt sources include Timer 0, Timer 1, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input.
All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex.
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The Software trap has the highest priority while the default VIS has the lowest priority.
Each of the 11 maskable inputs has a fixed arbitration rank­ing and vector.
Figure 35
shows the Interrupt Block Diagram.
DS101137-36
Interrupts (Continued)
FIGURE 35. Interrupt Block Diagram
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, com­bined with the GIE bit determineswhether an active pending flag actually triggers an interrupt. All of the maskable inter­rupt pending and enable bits are contained in mapped con­trol registers, and thus can be controlled by the software.
Amaskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt condi­tion cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be ac­knowledged. If, at the time an interrupt is enabled, any pre­vious occurrences of the interrupt should be ignored, the as­sociated pending bit must be reset to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply en­abled; if the pending bit is already set, it will immediately trig­ger an interrupt. A maskable interrupt is active if its associ­ated enable and pending bits are set.
An interrupt is an asychronous event which may occur be­fore, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowl­edged until the start of the next normally executed instruction
DS101137-17
is to be skipped, the skip is performed before thepending in­terrupt is acknowledged.
At the start of interrupt acknowledgment, the following ac­tions occur:
1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the cur­rent service routine. This feature prevents one maskable interrupt from interrupting another one being serviced.
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.
If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register,and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions.
The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the interrupt, and jump to the interrupt handling routine corre­sponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the user’s program must decide which interrupt to service.
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Interrupts (Continued)
An interrupt service routine typically ends with an RETI in­struction. This instruction sets the GIE bit back to 1, pops the address stored on the stack, and restores that address to the program counter. Program execution then proceeds with the next instruction that would have been executed had there been no interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon re­turn from the previous interrupt.
VIS INSTRUCTION
The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all types of inter­rupts. The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling rou­tine based on the cause of the interrupt.
VIS is a single-byte instruction, typically used at the very be­ginning of the general interrupt service routine at address 00FF Hex, or shortly after that point, just after thecode used for context switching. The VIS instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all pos­sible interrupts sources are stored in a vector table.
The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block contain­ing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is lo­cated between addresses 01E0 and 01FFHex. If the VIS in­struction is located between 01FF and 02DF Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on.
Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rank and its vector is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the table.
Table9
shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table.
The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For ex­ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in­terrupt occurs and the VIS instruction is executed, the pro­gram jumps to the address specified in the vector table.
The interrupt sources in the vector tableare listed inorder of rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are en­abled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruc­tion which clears an enable flag at the same time that the pending flag is set. It can also result, however, from inadvert­ent execution of the VIS command outside of the context of an interrupt.
The default VIS interrupt vector can be useful for applica­tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro­gram context (A, B, X, etc.) and executing the RETI instruc­tion, an interrupt service routine can be terminated by return­ing to the VIS instruction. In this case, interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started. After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context and execute the RETI to return to the interrupted program.
This technique can save up to fifty instruction cycles (t more, (50µs at 10 MHz oscillator) of latency for pending in­terrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending.
To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Al­though it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be al­tered, but the reliability of the interrupt system is compro­mised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have the highest priority. Under certain con­ditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent “locking out”of all maskable inter­rupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction.
c
), or
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Interrupts (Continued)
TABLE 9. Interrupt Vector Table
Arbitration
Ranking Hi-Low
1 Software Trap 0yFE–0yFF 2 Reserved 0yFC–0yFD 3 CAN Receive 0yFA–0yFB 4 CAN Error 0yF8–0yF9
5 CAN Transmit 0yF6–0yF7 6 Pin G0 Edge 0yF4–0yF5 7 IDLE Timer Underflow 0yF2–0yF3 8 Timer T1A/Underflow 0yF0–0yF1
9 Timer T1B 0yEE–0yEF 10 MlCROWIRE/PLUS 0yEC–0yED 11 PWM timer 0YEA–0yEB 12 Reserved 0yE8–0yE9 13 Reserved 0yE6–0yE7 14 Reserved 0yE4–0yE5 15 Port L/Wake Up 0yE2–0yE3 16 Default VIS Interrupt 0yE0–0yE1
Source
(transmit/receive)
Vector
Address
Byte
Note 14: y is VIS page, y≠0
If, by accident, a VIS gets executed and no interrupt is ac­tive, then the PC (Program Counter) will branch to a vector located at 0yE0-0yE1.
VIS Execution
When the VIS instruction is executed it activates the arbitra­tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FAis generated and so forth. If the only active inter­rupt is software trap, than E0 is generated. This number re­places the lower byte of the PC. The upper byte of the PC re­mains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration rank­ing. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitra­tion ranking.
Figure 36
instruction.
illustrates the different steps performed by the VIS
Figure 37
shows a flowchart for the VIS instruc-
tion. The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET.
FIGURE 36. VIS Operation
DS101137-29
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Interrupts (Continued)
DS101137-30
FIGURE 37. VIS Flowchart
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Interrupts (Continued)
Programming Example: External Interrupt
PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD ; G0 pin configured Hi-Z SBIT IEDG, CNTRL ; Ext interrupt polarity; falling edge SBIT EXEN, PSW ; Enable the external interrupt
WAIT: JP WAIT ; Wait for external interrupt
INT_EXIT:
SERVICE: RBIT EXPND, PSW ; Interrupt Service Routine
SBIT GIE, PSW ; Set the GIE bit
. . . .=0FF ; The interrupt causes a VIS ; branch to address 0FF
; The VIS causes a branch to
;interrupt vector table . . . .=01FA ; Vector table (within 256 byte .ADDRW SERVICE ; of VIS inst.) containing the ext
; interrupt service routine . .
RETI . .
; Reset ext interrupt pend. bit . . . JP INT_EXIT ; Return, set the GIE bit
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Interrupts (Continued)
NON-MASKABLE INTERRUPT
Pending Flag
The pending flag is reset to zero when a device Reset oc­curs. When the non-maskable interrupt occurs, the associ­ated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to reset the pending flag to zero. The RPND instruction always resets the STPND flag.
Software Trap
The Software Trap is a special kind of non-maskable inter­rupt which occurs when the INTR instruction (used to ac­knowledge interrupts) is fetched from program memory and placed in the instruction register. This can happen in a vari­ety of ways, usually because of an errorcondition. Some ex­amples of causes are listed below.
If the program counter incorrectly points to a memory loca­tion beyond the available program memory space, the non­existent or unused memory location returns zeroes which is interpreted as the INTR instruction.
If the stack is popped beyond the allowed limit (address 06F Hex), a 7FFF will be loaded into the PC, if this last location in program memory is unprogrammed or unavailable, a Soft­ware Trap will be triggered.
A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch.
The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit is set.The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the pro­gram to the ST service routine with the VIS instruction. Noth­ing can interrupt a Software Trap service routine except for another Software Trap. The STPND can be reset only bythe RPND instruction or a chip Reset.
The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the point where the Software Trap occurred cannot be done re­liably. Therefore, the Software Trap service routine should reinitialize the stack pointer and perform a recovery proce­dure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the same functions as a device Reset. The routine must also ex­ecute the RPND instruction to reset the STPND flag. Other­wise, all other interrupts will be locked out. To the extent pos­sible, the interrupt routine should record or indicate the context of the device so that the cause of the Software Trap can be determined.
If the user wishes to return to normal execution from the point at which the Software Trap was triggered, the user must first execute RPND, followed by RETSK rather than RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur.
Programming a return to normal execution requires careful consideration. If the Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND
flag; upon return to the first Software Trap routine, the STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. Toavoid problems such as this, the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution.
Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service routine. If a programming error or hardware condition (brownout, power supply glitch, etc.) sets the STPND flag without providing a way for it to be cleared, all other interruptswill be lockedout. To alleviate this condition, the user can use extra RPND in­structions in the main program and in the WATCHDOG ser­vice routine (if present). There is no harm in executing extra RPND instructions in these parts of the program.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select­able, edge sensitive interrupts which are all vectored into the same service subroutine.
The interrupt from Port L shares logic with the wake up cir­cuitry.The register WKEN allows interrupts from Port Lto be individually enabled or disabled. The register WKEDG speci­fies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt function.
Since Port L is also used for waking the device out of the HALTor IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart ex­ecution from the instruction immediately following the in­struction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the in­terrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.)
INTERRUPT SUMMARY
The device uses the following types of interrupts, listed be­low in order of priority:
1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The Software Trap is acknowledged immediately. This interrupt service rou­tine can be interrupted only by another Software Trap. The Software Trap should end with two RPND instruc­tions followed by a restart procedure.
2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device.Un­der ordinary conditions, a maskable interrupt will not in­terrupt any other interrupt routine in progress. A maskable interrupt routine in progress can be inter­rupted by the non-maskable interrupt request. A maskable interrupt routine should end with an RETI in­struction or, prior to restoring context, should return to execute the VIS instruction. This is particularly useful when exiting long interrupt service routiness if the time between interrupts is short. In this case the RETI instruc­tion would only be executed when the default VIS rou­tine is reached.
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Detection of Illegal Conditions
The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc.
Reading of undefined ROM gets zeroes. The opcode for software interrupt is zero. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump tosub­routine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location 02F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 030 and 031 Hex (which are undefined RAM). Undefined RAM from ad­dresses 030 to 03F Hex is read as all 1’s, which in turn will cause the program to return to address 7FFF Hex. This is an undefined ROM location and the instruction fetched (all 0’s) from this location will generate a software interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM.
2. Over “POP”ing the stack by having more returns than calls.
When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restart­ing (this recovery program is probably similar to that follow­ing reset, but might not contain the same program initializa­tion procedures).
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the de­vice to interface with any of National Semiconductor’s MI­CROWIRE peripherals (i.e., A/D converters, display drivers, E2PROMs etc.) and with other microcontrollers which sup­port the MICROWIRE interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data out­put (SO) and serial shift clock (SK). diagram of the MICROWlRE/PLUS logic.
The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/ PLUS ar­rangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE ar­rangement with an external shift clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the mas­ter mode the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. clock rates that may be selected.
Figure 38
Table10
shows a block
details the different
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. two COP888 family microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS ar­rangements.
Warning:
The SIO register should only be loaded when the SK clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SlO register. SK clock is nor­mally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low.
MICROWIRE/PLUS Master Mode Operation
FIGURE 38. MICROWIRE/PLUS Block Diagram
Table 11
Figure 39
summarizes the bit settings
shows how
DS101137-37
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MICROWIRE/PLUS (Continued)
FIGURE 39. MICROWIRE/PLUS Application
TABLE 10. MICROWIRE/PLUS
Master Mode Clock Selection
SL1 SL0 SK
0 0 2xt 0 1 4xt 1 x 8xt
Where tcis the instruction cycle clock
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and re­setting the appropriate bit in the Port G configuration regis­ter.
Table 2
summarizes the settings required to enter the
Slave mode of operation. The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be re­peated.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate phase SK clock to shift data in and outof the SIO register. In both the modes the SK is normally low. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. The SIO register is shifted on each falling edge ofthe SK clockin the normal mode. In the alternate SK phase mode the SIO register is shifted on the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alter­nate SK clock. The SKSEL is mapped into the G6 configura­tion bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal.
c c c
DS101137-38
TABLE 11. MICROWIRE/PLUS Mode Selection
This table assumes that the control flag MSEL is set.
G4 (SO) G5 (SK) G4 G5
Config. Config. Fun. Fun. Operation
Bit Bit
1 1 SO Int. MICROWIRE/PLUS
SK Master
0 1 TRI- Int. MICROWIRE/PLUS
STATE SK Master
1 0 SO Ext. MICROWIRE/PLUS
SK Slave
0 0 TRI- Ext. MICROWIRE/PLUS
STATE SK Slave
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Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address Contents
00 to 2F On-Chip RAM bytes (48 bytes) 30 to 7F Unused RAM Address Space (Reads As All
Ones)
80 to 9F Unused RAM Address Space (Reads
Undefined Data) A0 PSCAL, PWM timer Prescaler Register A1 RLON, PWM timer On-Time Register A2 PWMCON, PWM Control Register A3 to AF Reserved B0 TXD1, Transmit 1 Data B1 TXD2, Transmit 2 Data B2 TDLC, Transmit Data Length Code and
Identifier Low B3 TID, Transmit Identifier High B4 RXD1, Receive Data 1 B5 RXD2, Receive Data 2 B6 RIDL, Receive Data Length Code B7 RID, Receive Identify High B8 CSCAL, CAN Prescaler B9 CTIM, Bus Timing Register BA CBUS, Bus Control Register BB TCNTL, Transmit/Receive Control Register BC RTSTAT Receive/Transmit Status Register BD TEC, Transmit Error Count Register BE REC, Receive Error Count Register BF Reserved C0 to C7 Reserved C8 WKEDG, MIWU Edge Select Register C9 WKEN, MIWU Enable Register CA WKPND, MIWU Pending Register CB to CF Reserved D0 PORTLD, Port L Data Register D1 PORTLC, Port L Configuration Register D2 PORTLP, Port L Input Pins (Read Only) D3 CMPSL, Comparator control register D4 PORTGD, Port G Data Register D5 PORTGC, Port G Configuration Register D6 PORTGP, Port G Input Pins (Read Only) D7 to DB Reserved DC PORTD, Port D output register DD to DF Reserved for Port D E0 to E5 Reserved E6 T1RBLO, Timer T1 Autoload Register Lower
Byte E7 T1RBHI, Timer T1 Autoload Register Upper
Byte E8 ICNTRL, Interrupt Control Register E9 SIOR, MICROWIRE/PLUS Shift Register
Address Contents
EA TMR1LO, Timer T1 Lower Byte EB TMR1HI, Timer T1 Upper Byte EC T1RALO, Timer T1 Autoload Register Lower
Byte
ED T1RAHI, Timer T1 Autoload Register T1RA
Upper Byte EE CNTRL, Control Register EF PSW, Processor Status Word Register F0 to FB On-Chip RAM Mapped as Registers FC X Register FD SP Register FE B Register FF Reserved (Note 16)
Note 15: Reading memory locations 30–7FHex will return all ones. Reading other unused memory locations will return undefined data.
Note 16: In devices with more than 128 bytes of RAM, location 0FF is used as the Segment register to switch between different Segments of RAM memory. In this device location 0FF can be used as a general purpose, on­chip RAM mapped register. However, the user is advised that caution should be taken in porting software utilizing this memory location to a chip with more than 128 bytes of RAM.
Addressing Modes
There are ten addressing modes, six for operand addressing and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or decrement of pointer)
This addressing mode is used with the LD and X instruc­tions. The operand is the data memory addressed by the B pointer or X pointer. This is a register indirect mode that au­tomatically post increments or decrements the B or X regis­ter after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the oper­and.
Short Immediate
This addressing mode is used with the Load B Immediate in­struction. The instruction contains a 4-bit immediate field as the operand.
Indirect
This addressing mode is used with the LAID instruction. The contents of the accumuiator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory.
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Addressing Modes (Continued)
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new pro­gram location. JP has a range from −31 to +32 to allow a 1-byte relative jump (JP + 1 is implemented by a NOP in­struction). There are no “pages” when using JP, since all 15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any loca­tion in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any loca­tion up to 32k in the program memory space.
Indirect
This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruc­tion.
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt ser­vice routine.
Instruction Set
Register and Symbol Definition
Registers
A 8-Bit Accumulator Register B 8-Bit Address Register X 8-Bit Address Register SP 8-Bit Stack Pointer Register PC 15-Bit Program Counter Register PU Upper 7 Bits of PC PL Lower 8 Bits of PC C 1-Bit of PSW Register for Carry HC 1-Bit of PSW Register for Half Carry GIE 1-Bit of PSW Register for Global Interrupt
VU Interrupt Vector Upper Byte VL Interrupt Vector Lower Byte
[B] Memory Indirectly Addressed by B Register [X] Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or
Imm 8-Bit Immediate Data Reg Register Memory: Addresses F0 to FF
Bit Bit Number (0 to 7)
←
↔
Enable
Symbols
Immediate Data
(Includes B, X and SP)
Loaded with Exchanged with
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Instruction Set (Continued)
INSTRUCTION SET
ADD A,Meml ADD A←A + Meml ADC A,Meml ADD with Carry A←A+Meml+C,C←Carry,
HC←Half Carry
SUBC A,Meml Subtract with Carry A←A−MemI+C,C←Carry,
HC←Half Carry AND A,Meml Logical AND A←A and Meml ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm) = 0 OR A,Meml Logical OR A←A or Meml XOR A,Meml Logical EXclusive OR A←A xor Meml IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD = Imm IFEQ A,Meml IF EQual Compare A and Meml, Do next if A = Meml IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A Meml IFBNE # If B Not Equal Do next if lower 4 bits of B DRSZ Reg Decrement Reg., Skip if Zero Reg←Reg − 1, Skip if Reg = 0 SBIT #,Mem Set BIT 1 to bit, Mem (bit=0to7immediate) RBIT #,Mem Reset BIT 0 to bit, Mem IFBIT #,Mem IF BIT If bit in A or Mem is true do next instruction RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag X A,Mem EXchange A with Memory A X A,[X] EXchange A with Memory [X] A LD A,Meml LoaD A with Memory A←Meml LD A,[X] LoaD A with Memory [X] A←[X] LD B,Imm LoaD B with Immed. B←Imm LD Mem,Imm LoaD Memory Immed. Mem←Imm LD Reg,Imm LoaD Register Memory Immed. Reg←Imm XA,[B XA,[X LD A, [B LD A, [X LD [B CLR A CLeaR A A←0 INC A INCrement A A←A+1 DEC A DECrementA A←A−1 LAID Load A InDirect from ROM A←ROM (PU,A) DCOR A Decimal CORrect A A←BCD correction of A (follows ADC, SUBC) RRC A Rotate A Right thru C C→A7→…→A0→C RLC A Rotate A Left thru C C←A7←…←A0←C SWAP A SWAP nibbles of A A7…A4 SC Set C C←1, HC←1 RC Reset C C←0, HC←0 IFC IF C IF C is true, do next instruction IFNC IF Not C If C is not true, do next instruction POP A POP the stack into A SP←SP+1,A←[SP] PUSH A PUSH A onto the stack [SP]←A, SP←SP−1 VIS Vector to Interrupt Service Routine PU←[VU], PL←[VL] JMPL Addr. Jump absolute Long PC←ii (ii = 15 bits, 0k to 32k) JMP Addr. Jump absolute PC9…0←i (i = 12 bits) JP Disp. Jump relative short PC←PC+r(ris−31to+32, except 1)
±
] EXchange A with Memory [B] A↔[B], (B←B±1)
±
] EXchange A with Memory [X] A↔[X], (X
±
] LoaD A with Memory [B] A←[B], (B←B±1)
±
] LoaD A with Memory [X] A←[X], (X←X±1)
±
],Imm LoaD Memory [B] Immed. [B]←Imm, (B←B±1)
↔
Mem
↔
[X]
←
±
1)
↔
A3…A0
≠
Meml
≠
Imm
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Instruction Set (Continued)
JSRL Addr. Jump SubRoutine Long [SP]←PL, [SP−1]←PU,SP−2, PC←ii JSR Addr. Jump SubRoutine [SP]←PL, [SP−1]←PU,SP−2, PC9…0←i JID Jump InDirect PL←ROM (PU,A) RET RETurn from subroutine SP + 2, PL←[SP], PU←[SP−1] RETSK RETurn and SKip SP + 2, PL←[SP],PU←[SP−1] RETI RETurn from Interrupt SP + 2, PL←[SP],PU←[SP−1],GIE←1 INTR Generate an Interrupt [SP]←PL, [SP−1]←PU, SP−2, PC←0FF NOP No OPeration PC←PC+1
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Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
skipped, where x equals the number of bytes in the skipped instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B] Direct Immed.
ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4
RPND 1/1
Instructions Using A and C
CLRA 1/1 INCA 1/1 DECA 1/1 LAID 1/3 DCORA 1/1 RRCA 1/1 RLCA 1/1 SWAPA 1/1 SC 1/1 RC 1/1 IFC 1/1 IFNC 1/1 PUSHA 1/3 POPA 1/3 ANDSZ 2/2
Transfer of Control Instructions
JMPL 3/4 JMP 2/3 JP 1/3 JSRL 3/5 JSR 2/5 JID 1/3 VIS 1/5 RET 1/5 RETSK 1/5 RETI 1/5 INTR 1/7 NOP 1/1
Memory Transfer Instructions
Register Direct Immed. Register Indirect
Indirect Auto Incr. and Decr.
[B] [X] [B+, B−] [X+, X−]
X A, (Note 17) 1/1 1/3 2/3 1/2 1/3 LD A, (Note 17) 1/1 1/3 2/3 2/2 1/2 1/3 LD B, Imm 1/1 (IF B LD B, Imm 2/3 (IF B LD Mem, Imm 2/2 3/3 2/2 LD Reg, Imm 2/3 IFEQ MD, Imm 3/3
Note 17:>Memory location addressed by B or X or directly.
<
16)
>
15)
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LOWER NIBBLE
UPPER NIBBLE
JP+17 INTR 0
JMP
x000–x0FF
x000–x0FF
IFBNE 0 JSR
#0F
LD B,
A, #i
ANDSZ
0,[B]
IFBIT
ADC
A,[B]
#i
JP+18 JP+2 1
JMP
x100–x1FF
x100–x1FF
IFBNE 1 JSR
#0E
*LDB,
1,[B]
IFBIT
SUB
A,[B]
A, #i
JP+19 JP+3 2
JMP
x200–x2FF
x200–x2FF
IFBNE 2 JSR
#0D
*LDB,
2,[B]
IFBIT
A,[B]
IFEQ
A, #i
IFEQ
[B+]
XA,
JP+20 JP+4 3
JMP
x300–x3FF
x300–x3FF
IFBNE 3 JSR
#0C
*LDB,
3,[B]
IFBIT
A,[B]
IFGT
#i
IFGT A,
[B−]
XA,
JP+21 JP+5 4
JMP
IFBNE 4 JSR
CLRA LD B,
IFBIT
ADD
x400–x4FF
x400–x4FF
#0B
4,[B]
A,[B]
#i
JP+22 JP+6 5
JMP
IFBNE 5 JSR
SWAPA LD B,
IFBIT
AND
x500–x5FF
x500–x5FF
#0A
5,[B]
A,[B]
#i
JP+23 JP+7 6
JMP
IFBNE 6 JSR
DCORA LD B,
IFBIT
XOR
XOR A,
x600–x6FF
x600–x6FF
#09
6,[B]
A,[B]
#i
[B]
JP+24 JP+8 7
JMP
x700–x7FF
x700–x7FF
IFBNE 7 JSR
#08
PUSHA LD B,
7,[B]
IFBIT
A,[B]
JP+25 JP+9 8
JMP
IFBNE 8 JSR
LD B,
RBIT
x800–x8FF
x800–x8FF
#07
0,[B]
0,[B]
JP+26 JP+10 9
JMP
IFBNE 9 JSR
LD B,
RBIT
IFNC SBIT
IFNE
IFEQ
x900–x9FF
x900–x9FF
#06
1,[B]
1,[B]
A,#i
Md,#i
JP+27 JP+11 A
JMP
IFBNE 0A JSR
LD B,
RBIT
INCA SBIT
LD
LD A,
xA00–xAFF
xA00–xAFF
#05
2,[B]
2,[B]
[B+], #i
[B+]
JP+28 JP+12 B
JMP
IFBNE 0B JSR
LD B,
RBIT
DECA SBIT
LD
LD A,
xB00–xBFF
xB00–xBFF
#04
3,[B]
3,[B]
[B−], #i
[B−]
JP+29 JP+13 C
JMP
IFBNE 0C JSR
LD B,
RBIT
JMPL X A,Md POPA SBIT
xC00–xCFF
xC00–xCFF
#03
4,[B]
4,[B]
JP+30 JP+14 D
JMP
IFBNE 0D JSR
LD B,
RBIT
RETSK SBIT
xD00–xDFF
xD00–xDFF
#02
5,[B]
5,[B]
A,Md
JP+31 JP+15 E
JMP
IFBNE 0E JSR
LD B,
RBIT
RET SBIT
LD
LD A,
xE00–xEFF
xE00–xEFF
#01
6,[B]
6,[B]
[B],#i
[B]
JP+32 JP+16 F
JMP
IFBNE 0F JSR
LD B,
RBIT
xF00–xFFF
xF00–xFFF
#00
7,[B]
7,[B]
XA,[X] XA,
0F6
JP−9 JP−25 LD 0F6, #i DRSZ
* * OR A,#i OR
JP−8 JP−24 LD 0F7, #i DRSZ
* SC SUBC
[X+]
0F1
JP−14 JP−30 LD 0F1, #i DRSZ
XA,
0F2
JP−13 JP−29 LD 0F2, #i DRSZ
RRCA RC ADC A,
0F0
F E D C BA9 876 5 4 3 2 10
Opcode Table
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JP−15 JP−31 LD 0F0, #i DRSZ
[X−]
XA,
0F3
JP−12 JP−28 LD 0F3, #i DRSZ
VIS LAID ADD A,
0F4
JP−11 JP−27 LD 0F4, #i DRSZ
RPND JID AND A,
0F5
JP−10 JP−26 LD 0F5, #i DRSZ
0F7
NOP RLCA LD A,#i IFC SBIT
0F8
JP−7 JP−23 LD 0F8, #i DRSZ
[B]
IFNE A,
0F9
JP−6 JP−22 LD 0F9, #i DRSZ
[X+]
LD A,
0FA
JP−5 JP−21 LD 0FA, #i DRSZ
[X−]
LD A,
0FB
JP−4 JP−20 LD 0FB, #i DRSZ
LD
Md,#i
0FC
JP−3 JP−19 LD 0FC, #i DRSZ
DIR JSRL LD
0FD
JP−2 JP−18 LD 0FD, #i DRSZ
[X]
LD A,
0FE
JP−1 JP−17 LD 0FE, #i DRSZ
* * LD B,#i RETI SBIT
0FF
JP−0 JP−16 LD 0FF, #i DRSZ
is the immediate data
where,
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
Development Tools Support
OVERVIEW
National is engaged with an international community of inde­pendent 3rd party vendors who provide hardware and soft­ware development tool support. Through National’s interac­tion and guidance, these tools cooperate to form a choice of solutions that fits each developer’s needs.
This section provides a summary of the tool and develop­ment kits currently available. Up-to-date information, selec­tion guides, free tools, demos, updates, and purchase infor­mation can be obtained at our web site at: www.national.com/cop8.
SUMMARY OF TOOLS COP8 Evaluation Tools
COP8–NSEVAL: Free Software Evaluation package for
•
Windows. A fully integrated evaluation environment for COP8, including versions of WCOP8 IDE (Integrated De­velopment Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWay information.
COP8–MLSIM: Free Instruction Level Simulator tool for
•
Windows. For testing and debugging software instruc­tions only (No I/O or interrupt support).
COP8–EPU: Very Low cost COP8 Evaluation & Pro-
•
gramming Unit. Windows based evaluation and hardware-simulation tool, with COP8 device programmer and erasable samples. Includes COP8-NSDEV, Drive­way COP8 Demo, MetaLink Debugger, I/O cables and power supply.
COP8–EVAL-ICUxx: Very Low cost evaluation and de-
•
sign test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EEPROM. Includes software routines and reference designs.
Manuals,Applications Notes, Literature: Available free
•
from our web site at: www.national.com/cop8.
COP8 Integrated Software/Hardware Design Develop­ment Kits
COP8-EPU: Very Low cost Evaluation & Programming
•
Unit. Windows based development and hardware­simulation tool for COPSx/xG families, with COP8 device programmer and samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables and power supply.
COP8-DM: Moderate cost Debug Module from MetaLink.
•
A Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power sup­ply, emulation cables and adapters.
COP8 Development Languages and Environments
COP8-NSASM: Free COP8 Assembler v5 for Win32.
•
Macro assembler, linker, and librarian for COP8 software development. Supports all COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, and DriveWay COP8).
COP8-NSDEV: Very low cost Software Development
•
Package for Windows. An integrated development envi­ronment for COP8, including WCOP8 IDE, COP8­NSASM, COP8-MLSIM.
COP8C: Moderately priced C Cross-Compiler and Code
•
Development System from Byte Craft (no code limit). In-
™
COP8, Manuals, and other COP8
cludes BCLIDE (Byte Craft Limited Integrated Develop­ment Environment) for Win32, editor, optimizing C Cross­Compiler, macro cross assembler, BC-Linker, and MetaLink tools support. (DOS/SUN versions available; Compiler is installable under WCOP8 IDE; Compatible with DriveWay COP8).
EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-
•
bedded Workbench from IAR (Kickstart version: COP8Sx/Fx only with 2k code limit; No FP). A fully inte­grated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support.
EWCOP8-AS: Moderately priced COP8 Assembler and
•
Embedded Workbenchfrom IAR (no code limit).A fully in­tegrated Win32 IDE, macro assembler, editor, linker, li­brarian, and C-Spy high-level simulator/debugger with I/O and interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator sup­port).
EWCOP8-BL: Moderately priced ANSI C-Compiler and
•
Embedded Workbench from IAR (Baseline version: All COP8 devices; 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker,librarian, and C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface sup­port optional).
EWCOP8: Full featured ANSI C-Compiler and Embed-
•
ded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro as­sembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools inter­face support optional).
EWCOP8-M: Full featuredANSI C-Compiler and Embed-
•
ded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro as­sembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M).
COP8 Productivity Enhancement Tools
WCOP8 IDE: Very Low cost IDE (Integrated Develop-
•
ment Environment) from KKD. Supports COP8C, COP8­NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Manage­ment environment. Code development, debug, and emu­lation tools can be launched from the project window framework.
DriveWay-COP8: Low cost COP8 Peripherals Code
•
Generation tool from Aisys Corporation. Automatically generates tested and documented C orAssembly source code modules containing I/O drivers and interrupt han­dlers for each on-chip peripheral. Application specific code can be inserted for customization using the inte­grated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.)
COP8-UTILS: Free set of COP8 assembly code ex-
•
amples, device drivers, and utilities to speed up code de­velopment.
COP8-MLSIM: Free Instruction Level Simulator tool for
•
Windows. For testing and debugging software instruc­tions only (No I/O or interrupt support).
www.national.com51
Development Tools Support
(Continued)
COP8 Real-Time Emulation Tools
COP8-DM: MetaLink Debug Module. A moderately
•
priced real-time in-circuit emulation tool, with COP8 de­vice programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emula­tion cables and adapters.
IM-COP8: MetaLink iceMASTER®. A full featured, real-
•
time in-circuit emulator for COP8 devices. Includes Met­aLink Windows Debugger, and power supply. Package­specific probes and surface mount adaptors are ordered separately.
TOOLS ORDERING NUMBERS FOR THE COP87L84BC FAMILY DEVICES
Vendor Tools Order Number Cost Notes
National COP8-NSEVAL COP8-NSEVAL Free Web site download
COP8-NSASM COP8-NSASM Free Included in EPU and DM. Web site download COP8-MLSIM COP8-MLSIM Free Included in EPU and DM. Web site download COP8-NSDEV COP8-NSDEV VL Included in EPU and DM. Order CD from website COP8-EPU Not available for this device COP8-DM Contact MetaLink Development
Devices IM-COP8 Contact MetaLink
MetaLink COP8-EPU Not available for this device
COP8-DM DM4-COP8-888BC (10
DM Target Adapters
IM-COP8 IM-COP8-AD-464 (-220)
IM-Probe Card PC-888BC28D5-AD-10 M 10 MHz 28 DIP probe card; 2.5V to 6.0V IM Probe Target
Adapter
ICU COP8-EVAL Not available for this device
KKD WCOP8-IDE WCOP8-IDE VL Included in EPU and DM
IAR EWCOP8-xx See summary above L - H Included all software and manuals
Byte
COP8C COP8C M Included all software and manuals
Craft
Aisys DriveWay COP8 DriveWay COP8 L Included all software and manuals
OTP Programmers Contact vendor L - H For approved programmer listings and vendor
Cost: Free; VL =
<
$100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k
COP87L84BC VL 16k OTP devices. No wondowed devices.
MHz), plus PS-10, plus DM-COP8/xxx (ie. 28D)
MHW-CONV39 L DM target converters for 28SO
(10 MHz maximum)
MHW-SOIC28 L 28 pin SOIC adapter for probe card
COP8 Device Programmer Support
MetaLink’s EPU and Debug Module include development
•
device programming capability for COP8 devices. Third-party programmers and automatic handling equip-
•
ment cover needs from engineering prototype and pilot production, to full production environments.
Factory programming available for high-volume require-
•
ments.
M Included p/s (PS-10), target cable of choice (i.e.
DM-COP8/28D), 16/20/28/40 DIP/SO and 44 PLCC programming sockets
H Base unit 10 MHz; -220 = 220V; add probe card
(required) and target adapter (if needed); included software and manuals
information, go to our OTP support page at: www.national.com/cop8
www.national.com 52
Development Tools Support (Continued)
WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor Home Office Electronic Sites Other Main Offices
Aisys U.S.A.: Santa Clara, CA www.aisysinc.com Distributors
1-408-327-8820 info fax: 1-408-327-8830
Byte Craft U.S.A. www.bytecraft.com Distributors
1-519-888-6911 info fax: 1-519-746-6751
IAR Sweden: Uppsala www.iar.se U.S.A.: San Francisco
+46 18 16 78 00 info fax: +46 18 16 78 38 info
ICU Sweden: Polygonvaegen www.icu.se Switzeland: Hoehe
+46 8 630 11 20 support
fax: +46 8 630 11 70 support KKD Denmark: www.kkd.dk MetaLink U.S.A.: Chandler, AZ www.metaice.com Germany: Kirchseeon
1-800-638-2423 sales
fax: 1-602-926-1198 support
National U.S.A.: Santa Clara, CA www.national.com/cop8 Europe: +49 (0) 180 530 8585
1-800-272-9959 support
fax: 1-800-737-7018 europe.support
The following companies have approved COP8 program­mers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the lat­est listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8.
Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys­tems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; Sys­tem General; Tribal Microsystems; Xeltek.
@
aisysinc.com
@
bytecraft.com
@
iar.se 1-415-765-5500
@
iar.com fax: 1-415-765-5503
@
info
iarsys.co.uk U.K.: London
@
info
iar.de +44 171 924 33 34
fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956
@
icu.se +41 34 497 28 20
@
icu.ch fax: +41 34 497 28 21
@
metaice.com 80-91-5696-0
@
metaice.com fax: 80-91-2386
bbs: 1-602-962-0013 islanger
@
metalink.de
www.metalink.de Distributors Worldwide
@
nsc.com fax: +49 (0) 180 530 8586
@
nsc.com Distributors Worldwide
Customer Support
Complete product information and technical support is avail­able from National’s customer response centers, and from our on-line COP8 customer support sites.
www.national.com53
Physical Dimensions inches (millimeters) unless otherwise noted
Interface
COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN
Order Number COP87L84BC-xxx/M or COP684BC-xxx/M
NS Package Number M28B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation
Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com
www.national.com
National Semiconductor Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor Asia Pacific Customer Response Group
Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com
National Semiconductor Japan Ltd.
Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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