National Semiconductor COP8780C, COP8781C, COP8782C Technical data
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COP8780C/COP8781C/COP8782C
8-Bit One-Time Programmable (OTP) Microcontroller
General Description
The COP8780C, COP8781C and COP8782C are members
of the COPS
static microcontrollers, fabricated using double-metal, double poly silicon gate microCMOS EPROM technology.
These devices are available as UV erasable or One Time
Programmable (OTP). These low cost microcontrollers are
complete microcomputers containing all system timing, interrupt logic, EPROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications.
Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS
associated 16-bit autoreload/capture register, and a multisourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific application. These
devices operate over a voltage range of 4.5V to 6.0V. An
efficient, regular instruction set operating at a 1 ms instruction cycle rate provides optimal throughput.
The COP8780C, COP8781C and COP8782C can be configured to EMULATE the COP880C, COP840C and COP820C
microcontrollers.
Key Features
Y
16-bit multi-function timer supporting
Ð PWM mode
Ð External event counter mode
Ð Input capture mode
Y
Crystal, RC or External Oscillator, user configurable
Y
4 kbytes on-chip OTP EPROM with security feature
Y
128 or 64 bytes of on-chip RAM, user configurable
I/O Features
Y
Memory-mapped I/O
Y
Software selectable I/O options (TRI-STATEÉ, PushPull, Weak Pull-Up Input, High Impedance input)
TM
8-bit microcontroller family. They are fully
TM
serial I/O, a 16-bit timer/counter with
August 1996
Y
Schmitt trigger inputs on Port G
Y
MICROWIRE/PLUS serial I/O
Y
Packages:
Ð 44 PLCC, OTP, Emulates COP880C, 36 I/O pins
Ð 40 DIP, OTP, Emulates COP880C, 36 I/O pins
Ð 28 DIP, OTP, Emulates COP820C/840C/881C,
24 I/O pins
Ð 20 DIP, OTP, Emulates COP822C/842C, 16 I/O pins
Ð 28 SO, 20 SO, OTP
Ð 44 LDCC, UV Erasable
Ð 40 CERDIP, 28 CERDIP, 20 CERDIP, UV Erasable
CPU/Instruction Set Features
Y
1 ms instruction cycle time
Y
Three multi-source interrupts servicing
Ð External interrupt with selectable edge
Ð Timer interrupt
Ð Software interrupt
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer (SP)Ðstack in RAM
Y
Two 8-bit Register Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
Y
Low current drain (typicallyk1 mA)
Y
Extra-low current static HALT mode
Y
Single supply operation: 4.5V to 6.0V
Y
Temperature range:b40§Ctoa85§C
Development Support
Y
Emulation device for the COP880C, COP840C, and
COP820C
Y
Real-time emulation and full program debug offered by
MetaLink development system
COP8780C/COP8781C/COP8782C 8-Bit One-Time Programmable (OTP) Microcontroller
Block Diagram
FIGURE 1. Block Diagram
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
microcontrollers, MICROWIRETM, MICROWIRE/PLUSTMand WATCHDOGTMare trademarks of National Semiconductor Corporation.
TM
iceMASTER
C
1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A.
is a trademark of MetaLink Corporation.
TL/DD11299
TL/DD/11299– 1
http://www.national.com
Connection Diagrams
Top View
TL/DD/11299– 3
Order Number COP8780C-XXX/N or COP8780C-XXX/J
See NS Package Number J40AQ or N40A
TL/DD/11299– 5
Top View
Order Number COP78782C/XXX/J, COP8782C-XXX/N
or COP8782C-XXX/WM
See NS Package Number J20AQ, M20B or N20B
FIGURE 3. Connection Diagrams
Top View
TL/DD/11299– 4
Order Number COP8780C-XXX/V or COP8780C-XXX/EL
See NS Package Number EL40C or V44A
TL/DD/11299– 6
Top View
Order Number COP8781C-XXX/J, COP8781C-XXX/N or
COP8781C-XXX/WM
See NS Package Number J28AQ, M28B or N28B
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COP8780C/COP8781C/COP8782C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
)7V
CC
Programming Voltage VPP(RESET pin)
and ME (pin G6) 13.4V
Voltage at any Pin
b
0.3V to V
CC
a
0.3V
DC Electrical Characteristics COP87XXC;
Parameter Condition Min Typ Max Units
Operating Voltage 4.5 6.0 V
Power Supply Ripple (Note 1) Peak to Peak 0.1 V
Supply Current
e
CKI
10 MHz (Note 2) V
HALT Current (Note 3) V
Input Levels
RESET, CKI
Logic High 0.9 V
Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
G Port Input Hysteresis (Note 6) 0.05 V
Output Current Levels
D Outputs
Source V
Sink V
All Others
Source (Weak Pull-Up) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All Others 3mA
Maximum Input Current (Notes 4, 6)
without Latchup (Room Temp)
RAM Retention Voltage, Vr
(Note 5)
Input Capacitance (Note 6) 7 pF
Load Capacitance on D2 (Note 6) 1000 pF
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the crystal configurations. Halt test conditions: All Inputs tied to V
configured as outputs and programmed low; D outputs programmed low; the window for UV erasable packages is completely covered with an opaque cover to
prevent light from falling onto the die during HALT mode test. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 4: Pins G6 and RESET
have sink current to V
resistance to V
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
Note 6: Parameter characterized but not tested.
CC
are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
CC
is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
e
e
6V, t
CC
CC
CC
CC
CC
CC
CC
CC
CC
c
e
6V, CKIe0 MHz 10 mA
e
6.0V
e
6.0V, V
IN
e
4.5V, V
4.5V, V
4.5V, V
4.5V, V
4.5V, V
OH
OL
OH
OH
OL
e
e
e
e
Room Temp
Total Current into V
Pin (Source) 50 mA
CC
Total Current out of GND Pin (Sink) 60 mA
b
Storage Temperature Range
Note:
Absolute maximum ratings indicate limits beyond
65§Ctoa150§C
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
b
40§CsT
s
a
85§C unless otherwise specified
A
CC
V
1 ms21mA
CC
CC
b
e
0V
e
3.8V
e
1.0V 10 mA
e
3.2V
e
3.8V
e
0.4V 1.6 mA
2
b
40
CC
b
0.4 mA
b
10
b
0.4 mA
b
2.0
CC
CC
a
2 mA
b
250 mA
b
110 mA
a
2.0 mA
g
200 mA
V
V
V
V
V
2.0 V
. L, C, and G port I/O’s
CC
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COP8780C/COP8781C/COP8782C
AC Electrical Characteristics
b
40§CkT
k
a
85§C unless otherwise specified
A
Parameter Condition Min Typ Max Units
Instruction Cycle Time (tc)
Crystal/Resonator or External Clock V
R/C Oscillator Mode V
t
4.5V 1 DC ms
CC
t
4.5V 3 DC ms
CC
CKI Clock Duty Cycle (Note 7) freMax 45 55 %
e
Rise Time (Note 7) fr
Fall Time (Note 7) fr
Inputs
t
SETUP
t
HOLD
Output Propagation Delay C
t
PD1,tPD0
SO, SK V
All Others V
MICROWIRETMSetup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output
Propagation Delay (t
UWS)
UWH)
) 220 ns
UPD
10 MHz Ext Clock 12 ns
e
10 MHz Ext Clock 8 ns
t
V
4.5V 200 ns
CC
t
V
4.5V 60 ns
CC
e
100 pF, R
L
t
4.5V 0.7 ms
CC
t
4.5V 1 ms
CC
e
2.2 kX
L
20 ns
56 ns
Input Pulse Width
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer Input High Time 1 t
Timer Input Low Time 1 t
Reset Pulse Width 1.0 ms
Note 7: Parameter guaranteed by design, but not tested.
e
t
Instruction Cycle Time.
c
c
c
c
c
Timing Diagram
FIGURE 2. MICROWIRE/PLUS Timing
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TL/DD/10802– 2
Pin Descriptions
VCCand GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description.
RESET
is the master reset input. See Reset description.
PORT I is an 8-bit Hi-Z input port. The 28-pin device does
not have a full complement of PORT I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable
values. The user must ensure that the software takes this
into account by either masking or restricting the accesses to
bit operations. The unterminated PORT I pins will draw power only when addressed.
PORT L is an 8-bit I/O port.
PORT C is a 4-bit I/O port.
Three memory locations are allocated for the L, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4 – 7 of the C-Configuration register, data register, and input pins returns undefined data.
There are two registers associated with the L and C ports: a
data register and a configuration register. Therefore, each L
and C I/O bit can be individually configured under software
control as shown below:
Config. Data Ports L and C Setup
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Pull-Up (Weak One Output)
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
On the 20- and 28-pin parts, it is recommended that all bits
of Port C be configured as outputs to minimize current.
PORT G is an 8-bit port with 6 I/O pins (G0 – G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore, each G port
bit can be individually configured under software control as
shown below:
Config. Data Port G Setup
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Pull-Up (Weak One Output)
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Since G6 and G7 are input only pins, any attempt by the
user to configure them as outputs by writing a one to the
configuration register will be disregarded. Reading the G6
and G7 configuration bits will return zeros. The device will
be placed in the HALT mode by writing a one to the G7 bit in
the G-port data register.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE/PLUS serial data output)
G5 SK (MICROWIRE/PLUS clock I/O)
G6 SI (MICROWIRE/PLUS serial data input)
G7 CKO crystal oscillator output (selected by programming
the ECON register) or HALT Restart/general purpose
input
Pins G1 and G2 currently do not have any alternate functions.
PORT D is an 8-bit output port that is preset high when
RESET
goes low. Care must be exercised with the D2 pin
operation. At reset, the external load on this pin must ensure that the output voltage stay above 0.7 V
the chip from entering special modes. Also, keep the external loading on D2 to less than 1000 pF.
to prevent
CC
Functional Description
Figure 1
shows the block diagram of the internal architecture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each other in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented.
X is the 8-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack in RAM. The SP must be initialized with software (usually to RAM address 06F Hex with 128 bytes of
on-chip RAM selected, or to RAM address 02F Hex with 64
bytes of on-chip RAM selected). The SP is used with the
subroutine call and return instructions, and with the interrupts.
B, X and SP registers are mapped into the on-chip RAM.
The B and X registers are used to address the on-chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns.
PROGRAM MEMORY
The device contains 4096 bytes of UV erasable or OTP
EPROM memory. This memory is mapped in the program
memory address space from 0000 to 0FFF Hex. The program memory may contain either instructions or data constants, and is addressed by the 15-bit program counter (PC).
The program memory can be indirectly read by the LAID
(Load Accumulator Indirect) instruction for table lookup of
constant data.
All locations in the EPROM program memory will contain
0FF Hex (all 1’s) after the device is erased. OTP parts are
shipped with all locations already erased to 0FF Hex. Unused EPROM locations should always be programmed to 00
Hex so that the software trap can be used to halt runaway
program operation.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the security
bit in the ECON (EPROM configuration) register to zero. See
the ECON REGISTER section for more details.
DATA MEMORY
The data memory address space includes on-chip RAM,
I/O, and registers. Data memory is addressed directly by
instructions, or indirectly by means of the B, X, or SP point-
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Functional Description (Continued)
ers. The device can be configured to have either 64 or 128
bytes of RAM, depending on the value of the ‘‘RAM SIZE’’
bit in the ECON (EPROM CONFIGURATION) register. The
sixteen bytes of RAM located at data memory address 0F0 –
0FF are designated as ‘‘registers’’. These sixteen registers
can be decremented and tested with the DRSZ (Decrement
Register and Skip if Zero) instruction.
The three pointers X, B, and SP are memory mapped into
this register address space at addresses 0FC, 0FE, and
0FD respectively. The remaining registers are available for
general usage.
Any bit of data memory can be directly set, reset or tested.
All of the I/O registers and control registers (except A and
PC) are memory mapped. Consequently, any of the I/O bits
or control register bits can be directly and individually set,
reset, or tested.
Note: RAM contents are undefined upon power-up.
ECON (EPROM CONFIGURATION) REGISTER
The ECON register is used to configure the user selectable
clock, security, and RAM size options. The register can be
programmed and read only in EPROM programming mode.
Therefore, the register should be programmed at the same
time as the program memory locations 0000 through 0FFF
Hex. UV erasable parts are shipped with 0FF Hex in this
register while the OTP parts are shipped with 07F Hex in
this register. Erasing the EPROM program memory also
erases the ECON register.
The device has a security feature which, when enabled, prevents reading of the EPROM program memory. The security
bit in the ECON register determines whether security is enabled or disabled. If the security option is enabled, then any
attempt to externally read the contents of the EPROM will
result in the value E0 Hex being read from all program memory locations. If the security option is disabled, the contents
of the internal EPROM may be read. The ECON register is
readable regardless of the state of the security bit.
The format of the ECON register is as follows:
TABLE I
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X SECURITY CKI 2 CKI 1 X RAM SIZE X
Bit 7eX Don’t care.
Bit 6eX Don’t care.
Bit 5e1 Security disabled. EPROM read and write are
Bits 4,3
Bit 2eX Don’t care.
Bit 1e1 Selects 128 byte RAM option. This emulates
Bit 0
allowed.
e
0 Security enabled. EPROM read and write are
not allowed.
e
1,1 External CKI option selected.
e
0,1 Not allowed.
e
1,0 RC oscillator option selected.
e
0,0 Crystal oscillator option selected.
COP840 and COP880.
e
0 Selects 64 byte RAM option. This emulates
COP820.
e
X Don’t care.
RESET
The RESET
troller. Initialization will occur whenever the RESET
input when pulled low initializes the microcon-
input is
pulled low. Upon initialization, the Ports L, G and C are
placed in the TRI-STATE mode and the Port D is set high.
The PC, PSW and CNTRL registers are cleared. The data
and configuration registers for Ports L, G and C are cleared.
The external RC network shown in
to ensure that the RESET
Figure 4
should be used
pin is held low until the power
supply to the chip stabilizes.
RCt5X Power Supply Rise Time
TL/DD/11299– 7
FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5
shows the three clock oscillator configurations
available for the device. The CKI 1 and CKI 2 bits in the
ECON register are used to select the clock option. See the
ECON REGISTER section for more details.
FIGURE 5. Crystal, External and
TL/DD/11299– 8
R-C Connection Diagrams
A. Crystal Oscillator
The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table II shows the component values required for various
standard crystal frequencies.
B. External Oscillator
CKI can be driven by an external clock signal provided it
meets the specified duty cycle, rise and fall times, and input
levels. In External oscillator mode, G7 is available as a general purpose input and/or HALT restart control.
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Functional Description (Continued)
TABLE II. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq
(kX)(MX) (pF) (pF) (MHz)
0 1 30 30–36 10 V
0 1 30 30–36 4 V
TABLE III. RC Oscillator Configuration, T
R C CKI Freq. Instr. Cycle
(kX) (pF) (MHz) (ms)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note: (R/C Oscillator Configuration): 3ksRs200k, 50 pFsCs200 pF.
C. R/C Oscillator
CKI can be configured as a single pin RC controlled oscillator. In RC oscillator mode, G7 is available as a general purpose input and/or HALT restart control.
Table III shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. (Stopping the clock input will draw more current than
setting the G7 data bit.) In the HALT mode all internal processor activities including the clock oscillator are stopped.
The fully static architecture freezes the state of the controller and retains all information until continuing. In the HALT
mode, power requirements are minimal as it draws only
leakage currents and output current. The applied voltage
(V
) may be decreased down to Vr (minimum RAM reten-
CC
tion voltage) without altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the G7 pin. A low on the RESET line reinitializes the
microcontroller and starts execution from address 0000H. In
external and RC oscillator modes, a low to high transition on
the G7 pin also causes the microcontroller to come out of
the HALT mode. Execution resumes at the address following the HALT instruction. Except for the G7 data bit, which
gets reset, all RAM locations retain the values they had prior
to execution of the ‘‘HALT’’ instruction. It is required that the
first instruction following the ‘‘HALT’’ instruction be a
‘‘NOP’’ in order to synchronize the clock.
INTERRUPTS
The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible
interrupt sources, as shown below.
A maskable interrupt on external G0 input (positive or negative edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupts respectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0
e
1
falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other interrupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
Note: There is always the possiblity of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset
but an interrupt may still occur. This is because interrupt processing
is started at the same time as the interrupt bit is being reset. To avoid
this scenario, the user should always use a two, three, or four cycle
instruction to reset interrupt enable bits.
e
25§C
A
e
25§C
A
Conditions
e
CC
e
CC
Conditions
e
5V
CC
e
5V
CC
e
5V
CC
e
rising edge,
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5V
5V
Functional Description (Continued)
FIGURE 6. Interrupt Block Diagram
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors, noise and ‘‘brown out’’ voltage drop situations. Specifically, it detects cases of executing out of undefined EPROM area and unbalanced stack situations.
Reading an undefined EPROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is
also ‘‘00’’. Thus a program accessing undefined EPROM
will cause a software interrupt.
Reading an undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined EPROM location and will trigger a
software interrupt.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK).
Figure 7
shows the block diagram of the MICRO-
WIRE/PLUS interface.
FIGURE 7. MICROWIRE/PLUS Block Diagram
TL/DD/11299– 10
TL/DD/11299– 9
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Operating the MICROWIRE/
PLUS interface with an external shift clock is called the
Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS ,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SL0 and SL1, in the
CNTRL register. Table IV details the different clock rates
that may be selected.
TABLE IV
SL1 SL0 SK Cycle Time
00 2t
01 4t
1x 8t
c
c
c
where,
tcis the instruction cycle time.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave.
Figure 8
shows how
two device microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangement.
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE/PLUS Master always initiates all data exchanges
(Figure 8)
. The MSEL bit in the CNTRL register
must be set to enable the SO and SK functions on the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration register. Table V summarizes the bit settings required for Master
mode of operation.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
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Functional Description (Continued)
FIGURE 8. MICROWIRE/PLUS Application
bit in the CNTRL register enables the SO and SK functions
on the G Port. The SK pin must be selected as an input and
the SO pin selected as an output pin by appropriately setting
up the Port G configuration register. Table V summarizes
the settings required to enter the Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated
(Figure 8).
TABLE V
G4 G5
Config. Config.
Bit Bit
1 1 SO Int. SK SI MICROWIRE Master
0 1 TRI-STATE Int. SK SI MICROWIRE Master
1 0 SO Ext. SK SI MICROWIRE Slave
0 0 TRI-STATE Ext. SK SI MICROWIRE Slave
G4 G5 G6
Fun. Fun. Fun.
Operation
TIMER/COUNTER
The device has a powerful 16-bit timer with an associated
16-bit register enabling it to perform extensive timer functions. The timer T1 and its register R1 are each organized
as two 8-bit read/write registers. Control bits in the register
CNTRL allow the timer to be started and stopped under
software control. The timer-register pair can be operated in
one of three possible modes. Table VI details various timer
operating modes and their requisite control settings.
TL/DD/11299– 11
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allows the generation of square-wave
outputs or pulse width modulated outputs under software
control
(Figure 9)
.
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt
(Figure 9)
.
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge
(Figure 10)
.
TABLE VI. Timer Operating Modes
CNTRL Timer
Bits Operation Mode T Interrupt Counts
765 On
0 0 0 External Counter w/Auto-Load Reg. Timer Underflow TIO Pos. Edge
0 0 1 External Counter w/Auto-Load Reg. Timer Underflow TIO Neg. Edge
0 1 0 Not Allowed Not Allowed Not Allowed
0 1 1 Not Allowed Not Allowed Not Allowed
1 0 0 Timer w/Auto-Load Reg. Timer Underflow t
1 0 1 Timer w/Auto-Load Reg./Toggle TIO Out Timer Underflow t
1 1 0 Timer w/Capture Register TIO Pos. Edge t
1 1 1 Timer w/Capture Register TIO Neg. Edge t
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