National Semiconductor COP424C Technical data
查询COP324C供应商
COP424C, COP425C, COP426C, COP324C, COP325C,
COP326C and COP444C, COP445C, COP344C, COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
April 1992
COP424C, COP425C, COP426C, COP324C, COP325C, COP326C and COP444C, COP445C,
COP344C, COP345C Single-Chip 1k and 2k CMOS Microcontrollers
General Description
The COP424C, COP425C, COP426C, COP444C and
COP445C fully static, Single-Chip CMOS Microcontrollers
are members of the COPS
TM
family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP424C and COP444C are 28 pin
chips. The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many demanding control environments especially those with human
interface.
The COP424C is an improved product which replaces the
COP420C.
COPSTM, MicrobusTM, and MICROWIRETMare trademarks of National Semiconductor Corp.
TRI-STATE
is a registered trademark of National Semiconductor Corp.
É
Block Diagram
Features
Y
Lowest power dissipation (50 mW typical)
Y
Fully static (can turn off the clock)
Y
Power saving IDLE state and HALT mode
Y
4 ms instruction time, plus software selectable clocks
Y
2k x 8 ROM, 128 x 4 RAM (COP444C/COP445C)
Y
1k x 8 ROM, 64 x 4 RAM (COP424C/COP425C/
COP426C)
Y
23 I/O lines (COP444C and COP424C)
Y
True vectored interrupt, plus restart
Y
Three-level subroutine stack
Y
Single supply operation (2.4V to 5.5V)
Y
Programmable read/write 8-bit timer/event counter
Y
Internal binary counter register with MICROWIRE
serial I/O capability
Y
General purpose and TRI-STATEÉoutputs
Y
LSTTL/CMOS output compatible
Y
MicrobusTMcompatible
Y
Software/hardware compatible with COP400 family
Y
Extended temperature range devices COP324C/
COP325C/COP326C and COP344C/COP345C (
a
to
85§C)
Y
Military devices (b55§Ctoa125§C) to be available
b
TM
40§C
* Not available on COP426C/COP326C
TL/DD/5259– 1
FIGURE 1
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/DD/5259
COP424C/COP425C/COP426C and COP444C/COP445C
Absolute Maximum Ratings
Note:
Supply Voltage (VCC)6V
Voltage at any Pin
b
0.3V to V
Total Allowable Source Current 25 mA
CC
a
0.3V
Total Allowable Sink Current 25 mA
Operating Temperature Range 0
Storage Temperature Range
Ctoa70§C
§
b
65§Ctoa150§C
Lead Temperature
(soldering, 10 seconds) 300
DC Electrical Characteristics 0
C
§
s
CsT
70§C unless otherwise specified
§
A
Parameter Conditions Min Max Units
Operating Voltage 2.4 5.5 V
Power Supply Ripple (Notes 4, 5) Peak to Peak 0.1 V
Supply Current V
(Note 1) V
HALT Mode Current V
(Note 2) V
Input Voltage Levels
, CKI, D0(clock input)
RESET
Logic High 0.9 V
Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Input Pull-Up Current V
e
2.4V, tce64 ms 120 mA
CC
e
5.0V, tce16 ms 700 mA
CC
e
5.0V, tce4 ms 3000 mA
V
CC
(tc is instruction cycle time)
CC
CC
CC
e
e
e
5.0V, F
2.4V, F
4.5V, V
e
0 kHz 40 mA
IN
e
0 kHz 12 mA
IN
e
0
IN
Hi-Z Input Leakage
Input Capacitance (Note 4) 7pF
Output Voltage Levels Standard Outputs
LSTTL Operation V
Logic High I
Logic Low I
CMOS Operation
Logic High I
Logic Low I
Output Current Levels (except CKO)
Sink (Note 6) V
Source (Standard Option) V
Source (Low Current Option) V
CKO Current Levels (As Clock Out)
Sink
Source
Allowable Sink/Source Current per Pin 5 mA
(Note 6)
d
4 0.3 mA
d
8V
d
16 ( 1.2 mA
d
4
d
8V
d
16 (
e
5.0Vg10%
CC
eb
100 mA 2.7 V
OH
e
400 mA 0.4 V
OL
eb
10 mAV
OH
e
10 mA 0.2 V
OL
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, CKIeVCC,V
CC
e
4.5V, CKIe0V, V
CC
OUT
OUT
OUT
OUT
OUT
OUT
e
e
e
e
e
e
Allowable Loading on CKO (as HALT) 100 pF
Current Needed to Over-Ride HALT
(Note 3)
To Continue V
To Halt V
TRI-STATE or Open Drain
Leakage Current
CC
CC
e
4.5V, V
e
4.5V, V
e
0.2V
IN
e
0.7V
IN
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
CC
V
V
0V
0V
0V
0V
CC
CC
CC
CC
OUT
OUT
CC
CC
b
30
b
1
b
0.2 V
CC
1.2 mA
0.2 mA
b
0.5 mA
b
0.1 mA
b
30
b
6
e
V
CC
e
0V
0.6 mA
b
0.3 mA
b
0.6 mA
b
1.2 mA
b
2.5
CC
CC
b
330 mA
a
1 mA
b
330 mA
b
80 mA
0.7 mA
1.6 mA
a
2.5 mA
V
V
V
V
V
2
COP324C/COP325C/COP326C and COP344C/COP345C
Absolute Maximum Ratings
Note:
Supply Voltage 6V
Voltage at any Pin
b
0.3V to V
Total Allowable Source Current 25 mA
CC
a
0.3V
Total Allowable Sink Current 25 mA
b
Operating Temperature Range
Storage Temperature Range
40§Ctoa85§C
b
65§Ctoa150§C
Lead Temperature
b
40§CsT
C
§
s
a
A
(soldering, 10 seconds) 300
DC Electrical Characteristics
Parameter Conditions Min Max Units
Operating Voltage 3.0 5.5 V
Power Supply Ripple (Notes 4, 5) Peak to Peak 0.1 V
Supply Current V
(Note 1) V
HALT Mode Current V
(Note 2) V
Input Voltage Levels
, CKI, DO(clock input)
RESET
Logic High 0.9 V
Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Input Pull-Up Current V
e
3.0V, tce64 ms 180 m A
CC
e
5.0V, tce16 ms 800 m A
CC
e
5.0V, tce4 ms 3600 m A
V
CC
(tc is instruction cycle time)
CC
CC
CC
e
e
e
5.0V, F
3.0V, F
4.5V, V
e
0 kHz 60 m A
IN
e
0 kHz 30 m A
IN
e
0
IN
Hi-Z Input Leakage
Input Capacitance (Note 4) 7pF
Output Voltage Levels Standard Outputs
LSTTL Operation V
Logic High I
Logic Low I
CMOS Operation
Logic High I
Logic Low I
Output Current Levels (except CKO)
Sink (Note 6) V
Source (Standard Option) V
Source (Low Current Option) V
CKO Current Levels (As Clock Out)
Sink
Source
Allowable Sink/Source Current per 5mA
Pin (Note 6)
d
4 0.3 mA
d
8V
d
16 ( 1.2 mA
d
4
d
8V
d
16 (
e
5.0Vg10%
CC
eb
100 mA 2.7 V
OH
e
400 mA 0.4 V
OL
eb
10 mAV
OH
e
10 mA 0.2 V
OL
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, CKIeVCC,V
CC
e
4.5V, CKIe0V, V
CC
OUT
OUT
OUT
OUT
OUT
OUT
e
e
e
e
e
e
Allowable Loading on CKO (as HALT) 100 pF
Current Needed to Over-Ride HALT
(Note 3)
To Continue V
To Halt V
TRI-STATE or Open Drain
Leakage Current
CC
CC
e
4.5V, V
e
4.5V, V
e
0.2V
IN
e
0.7V
IN
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
85§C unless otherwise specified
CC
V
V
0V
0V
0V
0V
CC
CC
CC
CC
OUT
OUT
CC
CC
b
30
b
2
b
0.2 V
CC
1.2 mA
0.2 mA
b
0.5 mA
b
0.1 mA
b
30
b
8
e
V
CC
e
0V
0.6 mA
b
0.3 mA
b
0.6 mA
b
1.2 mA
b
5
CC
CC
b
440 m A
a
2 mA
b
440 m A
b
200 m A
0.9 mA
2.1 mA
a
5 mA
V
V
V
V
V
3
COP424C/COP425C/COP426C and COP444C/COP445C
s
AC Electrical Characteristics
0§CsT
Parameter Conditions Min Max Units
Instruction Cycle Time (tc) V
Operating CKI
Frequency
d
4 mode DC 1.0 MHz
d
8 mode V
d
16 mode ( DC 4.0 MHz
d
4 mode DC 250 kHz
d
8 mode 4.5VlV
d
16 mode ( DC 1.0 MHz
Duty Cycle (Note 4) f
Rise Time (Note 4) f
Fall Time (Note 4) f
Instruction Cycle Time Re30kg5%, V
RC Oscillator (Note 4) C
Inputs: (See
t
SETUP
t
HOLD
Figure 3
)
Output Propagation Delay V
t
PD1,tPD0
t
PD1,tPD0
Microbus Timing CLe50 pF, V
Read Operation (
Chip Select Stable before RD
Chip Select Hold Time for RDbt
RD
Pulse Widthbt
Data Delay from RD
RD
to Data FloatingbtDF(Note 4) 250 ns
Write Operation (
Chip Select Stable before WR
Chip Select Hold Time for WR
WR Pulse Widthbt
Data Set-Up Time for WR
Data Hold Time for WR
INTR Transition Time from WR
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCCwith 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to V
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts ina1msperiod.
Note 6: SO output sink current must be limited to keep V
Figure 4
RR
b
Figure 5
WW
)
b
t
CSR
RCS
t
RD
)
b
t
CSW
b
t
WCS
b
t
DW
b
t
WD
b
t
WI
less than 0.2VCCwhen part is running in order to prevent entering test mode.
OL
70§C unless otherwise specified.
A
t
4.5V 4 DC ms
CC
t
l
4.5V
V
2.4V 16 DC ms
CC
t
4.5V DC 2.0 MHz
CC
t
2.4V DC 500 kHz
CC
e
4 MHz 40 60 %
1
e
4 MHz External Clock 60 ns
1
e
4 MHz External Clock 40 ns
1
e
5V
e
82 pFg5% (d4 Mode)
CC
511ms
G Inputs tc/4a.7 ms
SI Input V
All Others
t
V
4.5V 0.25 m s
CC
4.5VlV
CC
e
1.5V, C
OUT
t
V
4.5V 1.0 ms
CC
4.5VlV
CC
t
4.5V 0.3 ms
CC
( 1.7 ms
t
2.4V 1.0 ms
e
100 pF, R
L
t
2.4V 4.0 ms
e
5Vg5%
CC
e
5k
L
65 ns
20 ns
400 ns
375 ns
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
, L lines in TRI-STATE mode and
CC
4
COP324C/COP325C/COP326C and COP344C/COP345C
AC Electrical Characteristics
b
40§CsT
s
a
85§C unless otherwise specified.
A
Parameter Conditions Min Max Units
Instruction Cycle Time (tc) V
Operating CKI
Frequency
d
4 mode DC 1.0 MHz
d
8 mode V
d
16 mode ( DC 4.0 MHz
d
4 mode DC 250 kHz
d
8 mode 4.5VlV
d
16 mode ( DC 1.0 MHz
Duty Cycle (Note 4) f
Rise Time (Note 4) f
Fall Time (Note 4) f
Instruction Cycle Time Re30kg5%, V
RC Oscillator (Note 4) C
Inputs: (See
t
SETUP
t
HOLD
Figure 3
)
Output Propagation Delay V
t
PD1,tPD0
t
PD1,tPD0
Microbus Timing C
Read Operation (
Chip Select Stable before RD
Chip Select Hold Time for RDbt
RD
Pulse Widthbt
Data Delay from RD
RD
to Data FloatingbtDF(Note 4) 250 ns
Write Operation (
Chip Select Stable before WR
Chip Select Hold Time for WR
WR Pulse Widthbt
Data Set-Up Time for WR
Data Hold Time for WR
INTR Transition Time from WR
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCCwith 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to V
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts ina1msperiod.
Note 6: SO output sink current must be limited to keep V
Figure 4
RR
b
Figure 5
WW
)
b
t
CSR
RCS
t
RD
)
b
t
CSW
b
t
WCS
b
t
DW
b
t
WD
b
t
WI
t
4.5V 4 DC ms
CC
t
l
4.5V
V
3.0V 16 DC ms
CC
t
4.5V DC 2.0 MHz
CC
t
3.0V DC 500 kHz
CC
e
4 MHz 40 60 %
1
e
4 MHz external clock 60 ns
1
e
4 MHz external clock 40 ns
1
e
5V
e
82 pFg5% (d4 Mode)
CC
511ms
G Inputs tc/4a.7 ms
SI Inputs V
All Others
t
V
4.5V 0.25 m s
CC
4.5VlV
CC
e
1.5V, C
OUT
t
V
4.5V 1.0 ms
CC
4.5VlV
CC
e
50 pF, V
L
t
4.5V 0.3 ms
CC
( 1.7 ms
t
3.0V 1.0 ms
e
100 pF, R
L
t
3.0V 4.0 ms
e
5Vg5%
CC
e
5k
L
65 ns
20 ns
400 ns
375 ns
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
, L lines in TRI-STATE mode and
CC
less than 0.2VCCwhen part is running in order to prevent entering test mode.
OL
5
Connection Diagrams
DIP and S.O. Wide
DIP and S.O. Wide
Top View
TL/DD/5259– 16
Order Number COP326C-XXX/D
or COP426C-XXX/D
See NS Hermetic Package D20A
(Prototype Package Only)
Order Number COP326C-XXX/N
or COP426C-XXX/N
See NS Molded Package N20A
Order Number COP326C-XXX/WM
or COP426C-XXX/WM
See NS Surface Mount Package M20B
Order Number COP324C-XXX/D, COPC324-XXX/WM, COP344C-XXX/D,
COP424C-XXX/D, COPC424-XXX/WM or COP444C-XXX/D
See NS Hermetic Package D28C
Order Number COP324C-XXX/N, COP344C-XXX/N, COPC344-XXX/WM,
COP424C-XXX/N, COP444C-XXX/N or COPC444-XXX/WM
See NS Molded Package N28B
Pin Description
L7– L0 8-bit bidirectional port with TRI-STATE
G3– G0 4-bit bidirectional I/O port
D3– D0 4-bit output port
IN3– IN0 4-bit input port (28-pin package only)
SI Serial input or counter input
SO Serial or general purpose output
Order Number COP325C-XXX/D, COP445C-XXX/D,
Order Number COP325C-XXX/N, COP345C-XXX/N,
Order Number COP325C-XXX/WM, COP345C-XXX/WM,
Dual-In-Line Package
Top View
(Prototype Package Only)
FIGURE 2
Pin Description
SK Logic controlled clock output
CKI Chip oscillator input
CKO Oscillator output, HALT I/O port or general
RESET
V
CC
GND Ground
6
Top View
TL/DD/5259– 2
COP425C-XXX/D or COP345C-XXX/D
See NS Hermetic Package D24C
(Prototype Package Only)
COP425C-XXX/N or COP445C-XXX/N
See NS Molded Package N24A
COP425C-XXX/WM or COP445C-XXX/WM
See NS Surface Mount Package M24B
TL/DD/5259– 3
purpose input
Reset input
Most positive power supply
Functional Description
The internal architecture is shown in
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a
logic ‘‘0’’.
For ease of reading only the COP424C/425C/COP426C/
444C/445C are referenced; however, all such references
apply equally to COP324C/325C/COP326C/344C/345C.
PROGRAM MEMORY
Program Memory consists of ROM, 1024 bytes for the
COP424C/425C/426C and 2048 bytes for the COP444C/
445C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequential 11-bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP444C/
445C, organized as 8 data registers of 16
RAM addressing is implemented by a 7-bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4-bit digits in the selected data register.
Data memory consists of a 256-bit RAM for the COP424C/
425C/426C, organized as 4 data registers of 16
digits. The B register is 6 bits long. Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions.
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs.
Figure 1
. Data paths
c
4-bit digits.
c
4-bits
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most I/O,
arithmetic, logic, and data memory access operations. It can
also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch or T counter,
to input 4 bits of L I/O ports data, to input 4-bit G, or IN
ports, and to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instructions. When the T counter overflows, an overflow flag will be
set (see SKT and IT instructions below). The T counter is
cleared on reset. A functional block diagram of the timer/
counter is illustrated in
Four general-purpose inputs, IN3-IN0, are provided. IN1,
IN2 and IN3 may be selected, by a mask-programmable option as Read Strobe, Chip Select, and Write Strobe inputs,
respectively, for use in Microbus application.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
In the dual clock mode, D0 latch controls the clock selection
(see dual oscillator below).
The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. G0 may be mask-programmed
as an output for Microbus applications.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. With
the Microbus option selected, Q can also be loaded with the
8-bit contents of the L I/O ports upon the occurrence of a
write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M. As explained above, the
Microbus option allows L I/O port data to be latched into the
Q register.
Figure 10a
.
7
Functional Description (Continued)
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE I/O and COPS peripherals, or as a
binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
0. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon
FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With EN0 reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input
state.
TL/DD/5259– 4
FIGURE 4. Microbus Read Operation Timing
FIGURE 5. Microbus Write Operation Timing
8
TL/DD/5259– 5
TL/DD/5259– 6
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