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COP424C, COP425C, COP426C, COP324C, COP325C,
COP326C and COP444C, COP445C, COP344C, COP345C
Single-Chip 1k and 2k CMOS Microcontrollers
April 1992
COP424C, COP425C, COP426C, COP324C, COP325C, COP326C and COP444C, COP445C,
COP344C, COP345C Single-Chip 1k and 2k CMOS Microcontrollers
General Description
The COP424C, COP425C, COP426C, COP444C and
COP445C fully static, Single-Chip CMOS Microcontrollers
are members of the COPS
TM
family, fabricated using double-poly, silicon gate microCMOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP424C and COP444C are 28 pin
chips. The COP425C and COP445C are 24-pin versions (4
inputs removed) and COP426C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many demanding control environments especially those with human
interface.
The COP424C is an improved product which replaces the
COP420C.
COPSTM, MicrobusTM, and MICROWIRETMare trademarks of National Semiconductor Corp.
TRI-STATE
is a registered trademark of National Semiconductor Corp.
É
Block Diagram
Features
Y
Lowest power dissipation (50 mW typical)
Y
Fully static (can turn off the clock)
Y
Power saving IDLE state and HALT mode
Y
4 ms instruction time, plus software selectable clocks
Y
2k x 8 ROM, 128 x 4 RAM (COP444C/COP445C)
Y
1k x 8 ROM, 64 x 4 RAM (COP424C/COP425C/
COP426C)
Y
23 I/O lines (COP444C and COP424C)
Y
True vectored interrupt, plus restart
Y
Three-level subroutine stack
Y
Single supply operation (2.4V to 5.5V)
Y
Programmable read/write 8-bit timer/event counter
Y
Internal binary counter register with MICROWIRE
serial I/O capability
Y
General purpose and TRI-STATEÉoutputs
Y
LSTTL/CMOS output compatible
Y
MicrobusTMcompatible
Y
Software/hardware compatible with COP400 family
Y
Extended temperature range devices COP324C/
COP325C/COP326C and COP344C/COP345C (
a
to
85§C)
Y
Military devices (b55§Ctoa125§C) to be available
b
TM
40§C
* Not available on COP426C/COP326C
TL/DD/5259– 1
FIGURE 1
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/DD/5259
COP424C/COP425C/COP426C and COP444C/COP445C
Absolute Maximum Ratings
Note:
Supply Voltage (VCC)6V
Voltage at any Pin
b
0.3V to V
Total Allowable Source Current 25 mA
CC
a
0.3V
Total Allowable Sink Current 25 mA
Operating Temperature Range 0
Storage Temperature Range
Ctoa70§C
§
b
65§Ctoa150§C
Lead Temperature
(soldering, 10 seconds) 300
DC Electrical Characteristics 0
C
§
s
CsT
70§C unless otherwise specified
§
A
Parameter Conditions Min Max Units
Operating Voltage 2.4 5.5 V
Power Supply Ripple (Notes 4, 5) Peak to Peak 0.1 V
Supply Current V
(Note 1) V
HALT Mode Current V
(Note 2) V
Input Voltage Levels
, CKI, D0(clock input)
RESET
Logic High 0.9 V
Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Input Pull-Up Current V
e
2.4V, tce64 ms 120 mA
CC
e
5.0V, tce16 ms 700 mA
CC
e
5.0V, tce4 ms 3000 mA
V
CC
(tc is instruction cycle time)
CC
CC
CC
e
e
e
5.0V, F
2.4V, F
4.5V, V
e
0 kHz 40 mA
IN
e
0 kHz 12 mA
IN
e
0
IN
Hi-Z Input Leakage
Input Capacitance (Note 4) 7pF
Output Voltage Levels Standard Outputs
LSTTL Operation V
Logic High I
Logic Low I
CMOS Operation
Logic High I
Logic Low I
Output Current Levels (except CKO)
Sink (Note 6) V
Source (Standard Option) V
Source (Low Current Option) V
CKO Current Levels (As Clock Out)
Sink
Source
Allowable Sink/Source Current per Pin 5 mA
(Note 6)
d
4 0.3 mA
d
8V
d
16 ( 1.2 mA
d
4
d
8V
d
16 (
e
5.0Vg10%
CC
eb
100 mA 2.7 V
OH
e
400 mA 0.4 V
OL
eb
10 mAV
OH
e
10 mA 0.2 V
OL
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, V
CC
e
2.4V, V
V
CC
e
4.5V, CKIeVCC,V
CC
e
4.5V, CKIe0V, V
CC
OUT
OUT
OUT
OUT
OUT
OUT
e
e
e
e
e
e
Allowable Loading on CKO (as HALT) 100 pF
Current Needed to Over-Ride HALT
(Note 3)
To Continue V
To Halt V
TRI-STATE or Open Drain
Leakage Current
CC
CC
e
4.5V, V
e
4.5V, V
e
0.2V
IN
e
0.7V
IN
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
CC
V
V
0V
0V
0V
0V
CC
CC
CC
CC
OUT
OUT
CC
CC
b
30
b
1
b
0.2 V
CC
1.2 mA
0.2 mA
b
0.5 mA
b
0.1 mA
b
30
b
6
e
V
CC
e
0V
0.6 mA
b
0.3 mA
b
0.6 mA
b
1.2 mA
b
2.5
CC
CC
b
330 mA
a
1 mA
b
330 mA
b
80 mA
0.7 mA
1.6 mA
a
2.5 mA
V
V
V
V
V
2
COP324C/COP325C/COP326C and COP344C/COP345C
Absolute Maximum Ratings
Note:
Supply Voltage 6V
Voltage at any Pin
b
0.3V to V
Total Allowable Source Current 25 mA
CC
a
0.3V
Total Allowable Sink Current 25 mA
b
Operating Temperature Range
Storage Temperature Range
40§Ctoa85§C
b
65§Ctoa150§C
Lead Temperature
b
40§CsT
C
§
s
a
A
(soldering, 10 seconds) 300
DC Electrical Characteristics
Parameter Conditions Min Max Units
Operating Voltage 3.0 5.5 V
Power Supply Ripple (Notes 4, 5) Peak to Peak 0.1 V
Supply Current V
(Note 1) V
HALT Mode Current V
(Note 2) V
Input Voltage Levels
, CKI, DO(clock input)
RESET
Logic High 0.9 V
Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Input Pull-Up Current V
e
3.0V, tce64 ms 180 m A
CC
e
5.0V, tce16 ms 800 m A
CC
e
5.0V, tce4 ms 3600 m A
V
CC
(tc is instruction cycle time)
CC
CC
CC
e
e
e
5.0V, F
3.0V, F
4.5V, V
e
0 kHz 60 m A
IN
e
0 kHz 30 m A
IN
e
0
IN
Hi-Z Input Leakage
Input Capacitance (Note 4) 7pF
Output Voltage Levels Standard Outputs
LSTTL Operation V
Logic High I
Logic Low I
CMOS Operation
Logic High I
Logic Low I
Output Current Levels (except CKO)
Sink (Note 6) V
Source (Standard Option) V
Source (Low Current Option) V
CKO Current Levels (As Clock Out)
Sink
Source
Allowable Sink/Source Current per 5mA
Pin (Note 6)
d
4 0.3 mA
d
8V
d
16 ( 1.2 mA
d
4
d
8V
d
16 (
e
5.0Vg10%
CC
eb
100 mA 2.7 V
OH
e
400 mA 0.4 V
OL
eb
10 mAV
OH
e
10 mA 0.2 V
OL
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, V
CC
e
3.0V, V
V
CC
e
4.5V, CKIeVCC,V
CC
e
4.5V, CKIe0V, V
CC
OUT
OUT
OUT
OUT
OUT
OUT
e
e
e
e
e
e
Allowable Loading on CKO (as HALT) 100 pF
Current Needed to Over-Ride HALT
(Note 3)
To Continue V
To Halt V
TRI-STATE or Open Drain
Leakage Current
CC
CC
e
4.5V, V
e
4.5V, V
e
0.2V
IN
e
0.7V
IN
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
85§C unless otherwise specified
CC
V
V
0V
0V
0V
0V
CC
CC
CC
CC
OUT
OUT
CC
CC
b
30
b
2
b
0.2 V
CC
1.2 mA
0.2 mA
b
0.5 mA
b
0.1 mA
b
30
b
8
e
V
CC
e
0V
0.6 mA
b
0.3 mA
b
0.6 mA
b
1.2 mA
b
5
CC
CC
b
440 m A
a
2 mA
b
440 m A
b
200 m A
0.9 mA
2.1 mA
a
5 mA
V
V
V
V
V
3
COP424C/COP425C/COP426C and COP444C/COP445C
s
AC Electrical Characteristics
0§CsT
Parameter Conditions Min Max Units
Instruction Cycle Time (tc) V
Operating CKI
Frequency
d
4 mode DC 1.0 MHz
d
8 mode V
d
16 mode ( DC 4.0 MHz
d
4 mode DC 250 kHz
d
8 mode 4.5VlV
d
16 mode ( DC 1.0 MHz
Duty Cycle (Note 4) f
Rise Time (Note 4) f
Fall Time (Note 4) f
Instruction Cycle Time Re30kg5%, V
RC Oscillator (Note 4) C
Inputs: (See
t
SETUP
t
HOLD
Figure 3
)
Output Propagation Delay V
t
PD1,tPD0
t
PD1,tPD0
Microbus Timing CLe50 pF, V
Read Operation (
Chip Select Stable before RD
Chip Select Hold Time for RDbt
RD
Pulse Widthbt
Data Delay from RD
RD
to Data FloatingbtDF(Note 4) 250 ns
Write Operation (
Chip Select Stable before WR
Chip Select Hold Time for WR
WR Pulse Widthbt
Data Set-Up Time for WR
Data Hold Time for WR
INTR Transition Time from WR
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCCwith 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to V
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts ina1msperiod.
Note 6: SO output sink current must be limited to keep V
Figure 4
RR
b
Figure 5
WW
)
b
t
CSR
RCS
t
RD
)
b
t
CSW
b
t
WCS
b
t
DW
b
t
WD
b
t
WI
less than 0.2VCCwhen part is running in order to prevent entering test mode.
OL
70§C unless otherwise specified.
A
t
4.5V 4 DC ms
CC
t
l
4.5V
V
2.4V 16 DC ms
CC
t
4.5V DC 2.0 MHz
CC
t
2.4V DC 500 kHz
CC
e
4 MHz 40 60 %
1
e
4 MHz External Clock 60 ns
1
e
4 MHz External Clock 40 ns
1
e
5V
e
82 pFg5% (d4 Mode)
CC
511ms
G Inputs tc/4a.7 ms
SI Input V
All Others
t
V
4.5V 0.25 m s
CC
4.5VlV
CC
e
1.5V, C
OUT
t
V
4.5V 1.0 ms
CC
4.5VlV
CC
t
4.5V 0.3 ms
CC
( 1.7 ms
t
2.4V 1.0 ms
e
100 pF, R
L
t
2.4V 4.0 ms
e
5Vg5%
CC
e
5k
L
65 ns
20 ns
400 ns
375 ns
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
, L lines in TRI-STATE mode and
CC
4
COP324C/COP325C/COP326C and COP344C/COP345C
AC Electrical Characteristics
b
40§CsT
s
a
85§C unless otherwise specified.
A
Parameter Conditions Min Max Units
Instruction Cycle Time (tc) V
Operating CKI
Frequency
d
4 mode DC 1.0 MHz
d
8 mode V
d
16 mode ( DC 4.0 MHz
d
4 mode DC 250 kHz
d
8 mode 4.5VlV
d
16 mode ( DC 1.0 MHz
Duty Cycle (Note 4) f
Rise Time (Note 4) f
Fall Time (Note 4) f
Instruction Cycle Time Re30kg5%, V
RC Oscillator (Note 4) C
Inputs: (See
t
SETUP
t
HOLD
Figure 3
)
Output Propagation Delay V
t
PD1,tPD0
t
PD1,tPD0
Microbus Timing C
Read Operation (
Chip Select Stable before RD
Chip Select Hold Time for RDbt
RD
Pulse Widthbt
Data Delay from RD
RD
to Data FloatingbtDF(Note 4) 250 ns
Write Operation (
Chip Select Stable before WR
Chip Select Hold Time for WR
WR Pulse Widthbt
Data Set-Up Time for WR
Data Hold Time for WR
INTR Transition Time from WR
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCCwith 5k
resistors. See current drain equation on page 17.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to V
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.5 volts ina1msperiod.
Note 6: SO output sink current must be limited to keep V
Figure 4
RR
b
Figure 5
WW
)
b
t
CSR
RCS
t
RD
)
b
t
CSW
b
t
WCS
b
t
DW
b
t
WD
b
t
WI
t
4.5V 4 DC ms
CC
t
l
4.5V
V
3.0V 16 DC ms
CC
t
4.5V DC 2.0 MHz
CC
t
3.0V DC 500 kHz
CC
e
4 MHz 40 60 %
1
e
4 MHz external clock 60 ns
1
e
4 MHz external clock 40 ns
1
e
5V
e
82 pFg5% (d4 Mode)
CC
511ms
G Inputs tc/4a.7 ms
SI Inputs V
All Others
t
V
4.5V 0.25 m s
CC
4.5VlV
CC
e
1.5V, C
OUT
t
V
4.5V 1.0 ms
CC
4.5VlV
CC
e
50 pF, V
L
t
4.5V 0.3 ms
CC
( 1.7 ms
t
3.0V 1.0 ms
e
100 pF, R
L
t
3.0V 4.0 ms
e
5Vg5%
CC
e
5k
L
65 ns
20 ns
400 ns
375 ns
65 ns
20 ns
400 ns
320 ns
100 ns
700 ns
, L lines in TRI-STATE mode and
CC
less than 0.2VCCwhen part is running in order to prevent entering test mode.
OL
5
Connection Diagrams
DIP and S.O. Wide
DIP and S.O. Wide
Top View
TL/DD/5259– 16
Order Number COP326C-XXX/D
or COP426C-XXX/D
See NS Hermetic Package D20A
(Prototype Package Only)
Order Number COP326C-XXX/N
or COP426C-XXX/N
See NS Molded Package N20A
Order Number COP326C-XXX/WM
or COP426C-XXX/WM
See NS Surface Mount Package M20B
Order Number COP324C-XXX/D, COPC324-XXX/WM, COP344C-XXX/D,
COP424C-XXX/D, COPC424-XXX/WM or COP444C-XXX/D
See NS Hermetic Package D28C
Order Number COP324C-XXX/N, COP344C-XXX/N, COPC344-XXX/WM,
COP424C-XXX/N, COP444C-XXX/N or COPC444-XXX/WM
See NS Molded Package N28B
Pin Description
L7– L0 8-bit bidirectional port with TRI-STATE
G3– G0 4-bit bidirectional I/O port
D3– D0 4-bit output port
IN3– IN0 4-bit input port (28-pin package only)
SI Serial input or counter input
SO Serial or general purpose output
Order Number COP325C-XXX/D, COP445C-XXX/D,
Order Number COP325C-XXX/N, COP345C-XXX/N,
Order Number COP325C-XXX/WM, COP345C-XXX/WM,
Dual-In-Line Package
Top View
(Prototype Package Only)
FIGURE 2
Pin Description
SK Logic controlled clock output
CKI Chip oscillator input
CKO Oscillator output, HALT I/O port or general
RESET
V
CC
GND Ground
6
Top View
TL/DD/5259– 2
COP425C-XXX/D or COP345C-XXX/D
See NS Hermetic Package D24C
(Prototype Package Only)
COP425C-XXX/N or COP445C-XXX/N
See NS Molded Package N24A
COP425C-XXX/WM or COP445C-XXX/WM
See NS Surface Mount Package M24B
TL/DD/5259– 3
purpose input
Reset input
Most positive power supply
Functional Description
The internal architecture is shown in
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a
logic ‘‘0’’.
For ease of reading only the COP424C/425C/COP426C/
444C/445C are referenced; however, all such references
apply equally to COP324C/325C/COP326C/344C/345C.
PROGRAM MEMORY
Program Memory consists of ROM, 1024 bytes for the
COP424C/425C/426C and 2048 bytes for the COP444C/
445C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequential 11-bit binary count value.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP444C/
445C, organized as 8 data registers of 16
RAM addressing is implemented by a 7-bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4-bit digits in the selected data register.
Data memory consists of a 256-bit RAM for the COP424C/
425C/426C, organized as 4 data registers of 16
digits. The B register is 6 bits long. Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions.
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs.
Figure 1
. Data paths
c
4-bit digits.
c
4-bits
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumulator) which is the source and destination register for most I/O,
arithmetic, logic, and data memory access operations. It can
also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch or T counter,
to input 4 bits of L I/O ports data, to input 4-bit G, or IN
ports, and to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic overflow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instructions. When the T counter overflows, an overflow flag will be
set (see SKT and IT instructions below). The T counter is
cleared on reset. A functional block diagram of the timer/
counter is illustrated in
Four general-purpose inputs, IN3-IN0, are provided. IN1,
IN2 and IN3 may be selected, by a mask-programmable option as Read Strobe, Chip Select, and Write Strobe inputs,
respectively, for use in Microbus application.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
In the dual clock mode, D0 latch controls the clock selection
(see dual oscillator below).
The G register contents are outputs to a 4-bit general-purpose bidirectional I/O port. G0 may be mask-programmed
as an output for Microbus applications.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control. With
the Microbus option selected, Q can also be loaded with the
8-bit contents of the L I/O ports upon the occurrence of a
write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M. As explained above, the
Microbus option allows L I/O port data to be latched into the
Q register.
Figure 10a
.
7
Functional Description (Continued)
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE I/O and COPS peripherals, or as a
binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN register:
0. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon
FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With EN0 reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L drivers, placing the L I/O port in a high-impedance input
state.
TL/DD/5259– 4
FIGURE 4. Microbus Read Operation Timing
FIGURE 5. Microbus Write Operation Timing
8
TL/DD/5259– 5
TL/DD/5259– 6
Functional Description (Continued)
3. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to ‘‘0’’.
INTERRUPT
The following features are associated with interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
a
(PC
1) onto the stack. Any previous contents at the bottom of the stack are lost. The program counter is set to
hex address 0FF (the last word of page 3) and EN1 is
reset.
b. An interrupt will be recognized only on the following con-
ditions:
1. EN1 has been set.
2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN
3. A currently executing instruction has been completed.
4. All successive transfer of control instructions and suc-
cessive LBIs have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruction has been executed).
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address 0FF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will enable any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
1
input.
d. The instruction at hex address 0FF must be a NOP.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
MICROBUS INTERFACE
The COP444C/424C has an option which allows it to be
used as a peripheral microprocessor device, inputting and
outputting data from and to a host microprocessor (m P).
IN1, IN2 and IN3 general purpose inputs become Microbus
compatible read-strobe, chip-select, and write-strobe lines,
respectively. IN1 becomes RD
Ð a logic ‘‘0’’ on this input
will cause Q latch data to be enabled to the L ports for input
to the uP. IN2 becomes CS
Ð a logic ‘‘0’’ on this line selects the COP444C/424C as the uP peripheral device by
enabling the operation of the RD
and WR lines and allows
for the selection of one of several peripheral components.
IN3 becomes WR
Ð a logic ‘‘0’’ on this line will write bus
data from the L ports to the Q latches for input to the
COP444C/424C. G0 becomes INTR a ‘‘ready’’ output, reset
by a write pulse from the uP on the WR
line, providing the
‘‘handshaking’’ capability necessary for asynchronous data
transfer between the host CPU and the COP444C/424C.
This option has been designed for compatibility with National’s Microbus Ð a standard interconnect system for 8-bit
parallel data transfer between MOS/LSI CPUs and interfacing devices. (See Microbus National Publication.) The functioning and timing relationships between the signal lines affected by this option are as specified for the Microbus interface, and are given in the AC electrical characteristics and
shown in the timing diagrams (
of the COP444C/424C to the Microbus is shown in
Figures 4
and5). Connection
Figure 6
TL/DD/5259– 7
FIGURE 6. Microbus Option Interconnect
.
TABLE I. Enable Register Modes Ð Bits EN0 and EN3
EN0 EN3 SIO SI SO SK
0 0 Shift Input to Shift 0 If SKLe1,SKeclock
e
0 1 Shift Input to Shift Serial If SKL
Register Register If SKL
Register Register out If SKL
1 0 Binary Input to 0 SK
0,SKe0
e
1,SKeclock
e
0,SKe0
e
SKL
Counter Counter
1 1 Binary Input to 1 SKeSKL
Counter Counter
9
Functional Description (Continued)
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in
connected to the RESET
pin (the conditions in
must be met). The RESET pin is configured as a Schmitt
trigger input. If not used, it should be connected to V
Initialization will occur whenever a logic ‘‘0’’ is applied to the
RESET
input, providing it stays low for at least three instruc-
tion cycle times.
Note: If CKI clock is less than 32 kHz, the internal reset logic (option
Ý
29e1) MUST be disabled and the external RC circuit must be used.
FIGURE 7. Power-Up Circuit
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA
(clear A register).
Figure 7
must be
Figure 7
CC
TL/DD/5259– 8
TIMER
The timer can be operated as a time-base counter.
The instruction cycle frequency generated from CKI passes
through a 2-bit divide-by-4 prescaler. The output of this prescaler increments the 8-bit T counter thus providing a 10-bit
timer. The pre-scaler is cleared during execution of a CAMT
instruction and on reset.
.
For example, using a 4 MHz crystal with a divide-by-16 option, the instruction cycle frequency of 250 kHz increments
the 10-bit timer every 4 ms. By presetting the counter and
detecting overflow, accurate timeouts between 16 ms
(4 counts) and 4.096 ms (1024 counts) are possible. Longer
timeouts can be achieved by accumulating, under software
control, multiple overflows.
HALT MODE
The COP444C/445C/424C/425C/426C is a FULLY STATIC circuit; therefore, the user may stop the system oscillator
at any time to halt the chip. The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as an HALT I/O port. Once in the HALT
mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when
halted. All information is retained until continuing. The chip
may be awakened by one of two different methods:
Continue function: by forcing CKO low, if it mask-pro-
#
grammed as an HALT I/O port, the system clock is reenabled and the circuit continues to operate from the
point where it was stopped.
Restart: by forcing the RESET pin low (see Initializa-
#
tion).
Crystal or Resonator
Crystal Component Values
Value R1 R2 C1(pF) C2(pF)
32 kHz 220k 20M 30 6–36
455 kHz 5k 10M 80 40
2.096 MHz 2k 1M 30 6– 36
4.0 MHz 1k 1M 30 6 –36
FIGURE 8. Oscillator Component Values
RC Controlled Oscillator (g5% R,g5% C)
RC
30k 82 pF 5 –11 m s
60k 100 pF 12 –24 ms 2.4– 4.5V
Note: 15ksRs150k
sCs
150 pF
50 pF
Cycle
Time
10
TL/DD/5259– 9
V
CC
t
4.5V
Functional Description (Continued)
The HALT mode is the minimum power dissipation state.
Note: If the user has selected dual-clock with D0 as external
oscillator (option 30
running with the D0 clock, the HALT mode Ð either
hardware or software Ð will NOT be entered. Thus,
the user should switch to the CKI clock to HALT. Alternatively, the user may stop the D0 clock to minimize power.
CKO PIN OPTIONS
a. Two-pin oscillator Ð (Crystal). See
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high, thus inhibiting the crystal network. The
circuit can be awakened only by forcing the RESET
a logic ‘‘0’’ (restart).
b. One-pin oscillator Ð (RC or external). See
If a one-pin oscillator system is chosen, two options are
available for CKO:
CKO can be selected as the HALT I/O port. In that
#
case, it is an I/O flip-flop which is an indicator of the
HALT status. An external signal can over-ride this pin
to start and stop the chip. By forcing a high level to
CKO, the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
the external driver returns to high impedance state.
By forcing a low level to CKO, the chip will continue
and CKO will stay low.
As another option, CKO can be a general purpose in-
#
put, read into bit 2 of A (accumulator) upon execution
of an INIL instruction.
OSCILLATOR OPTIONS
There are four basic clock oscillator configurations available
as shown by
a. Crystal Controlled Oscillator. CKI and CKO are connect-
ed to an external crystal. The instruction cycle time equals
the crystal frequency optionally divided by 4, 8 or 16.
b. External Oscillator. The external frequency is optionally
divided by 4, 8 or 16 to give the instruction cycle time.
CKO is the HALT I/O port or a general purpose input.
Figure 8
e
2) AND the COP444C/424C is
Figure 9A
.
.
Figure 9B
pin to
.
c. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT I/O port or a general purpose input.
d. Dual oscillator. By selecting the dual clock option, pin D0
is now a single pin oscillator input. Two configurations are
available: RC controlled Schmitt trigger oscillator or external oscillator.
The user may software select between the D0 oscillator
(in that case, the instruction cycle time equals the D0
oscillation frequency divided by 4) by setting the D0 latch
high or the CKI (CKO) oscillator by resetting D0 latch low.
Note that even in dual clock mode, the counter, if maskprogrammed as a time-base counter, is always connected to the CKI oscillator.
For example, the user may connect up to a 1 MHz RC
circuit to D0 for faster processing and a 32 kHz watch
crystal to CKI and CKO for minimum current drain and
time keeping.
Note: CTMA instruction is not allowed when chip is running
from D0 clock.
Figures 10A
with and without Dual clock.
COP445C AND COP425C 24-PIN PACKAGE OPTION
If the COP444C/424C is bonded in a 24-pin package, it becomes the COP445C/425C, illustrated in
tion diagrams. Note that the COP445C/425C does not contain the four general purpose IN inputs (IN3 –IN0). Use of
this option precludes, of course, use of the IN options, interrupt feature, external event counter feature, and the
Microbus option which uses IN1 –IN3. All other options are
available for the COP445C/425C.
Note: If user selects the 24-pin package, options 9, 10, 19
COP426C 20-PIN PACKAGE OPTION
If the COP425C is bonded as 20-pin device it becomes the
COP426C. Note that the COP426C contains all the
COP425C pins except D
and
10B
show the clock and timer diagrams
Figure 2
and 20 must be selected as a ‘‘0’’ (load to V
IN inputs). See option list.
, and G1.
0,D1,G0
, Connec-
on the
CC
Block Diagram (Continued)
TL/DD/5259– 10
FIGURE 9A. Halt Mode Ð Two-Pin Oscillator
11
Block Diagram (Continued)
FIGURE 9B. Halt Mode Ð One-Pin Oscillator
FIGURE 10A. Clock and Timer without Dual-Clock
TL/DD/5259– 11
TL/DD/5259– 12
FIGURE 10B. Clock and Timer with Dual-Clock
12
TL/DD/5259– 13
Instruction Set
Table II is a symbol table providing internal architecture, instruction operan and operation symbols used in the instruction set table.
TABLE II. Instruction Set Table Symbols
Symbol Definition
Internal Architecture Symbols
A 4-bit accumulator
B 7-bit RAM address register (6-bit for COP424C)
Br Upper 3 bits of B (register address)
(2-bit for COP424C)
Bd Lower 4 bits of B (digit address)
C 1-bit carry register
D 4-bit data output port
EN 4-bit enable register
G 4-bit general purpose I/O port
IL two 1-bit (IN0 and IN3) latches
IN 4-bit input port
L 8-bit TRI-STATE I/O port
M 4-bit contents of RAM addressed by B
PC 11-bit ROM address program counter
Q 8-bit latch for L port
SA,SB,SC 11-bit 3-level subroutine stack
SIO 4-bit shift register and counter
SK Logic-controlled clock output
SKL 1-bit latch for SK output
T 8-bit timer
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruction.
Instruction Operand Symbols
d 4-bit operand field, 0 –15 binary (RAM digit select)
r 3(2)-bit operand field, 0 –7(3) binary
(RAM register select)
a 11-bit operand field, 0 – 2047 (1023)
y 4-bit operand field, 0 –15 (immediate data)
RAM(x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
Operational Symbols
a
Plus
b
Minus
x
Replaces
Ý
Is exchanged with
e
Is equal to
One’s complement of A
A
Z
Exclusive-or
: Range of values
Mnemonic Operand
ARITHMETIC INSTRUCTIONS
ASC 30
ADD 31
ADT 4A
AISC y 5
CASC 10
CLRA 00
COMP 40
NOP 44
RC 32
SC 22
XOR 02
Hex Language
Code Code Conditions
TABLE III. COP444C/445C Instruction Set
Machine
Data Flow
(Binary)
0011À0000ÀAaCaRAM(B)xA Carry Add with Carry, Skip on
À
0011À0001
À
0100À1010
À
b
0101Ày
À
0001À0000
À
0000À0000
À
0100À0000
À
0100À0100ÀNone None No Operation
À
0011À0010
À
0010À0010
À
0000À0010ÀAZRAM(B)xA None Exclusive-OR RAM with A
À
Carry
x
C Carry
AaRAM(B)xA None Add RAM to A
À
Aa10
x
A None Add Ten to A
À
À
À
À
À
À
À
10
AayxA Carry Add Immediate. Skip on
AaRAM(B)aCxA Carry Complement and Add with
Carry
x
C Carry, Skip on Carry
0xA None Clear A
AxA None Ones complement of A to A
‘‘0’’xC None Reset C
‘‘1’’xC None Set C
13
Skip
Carry (yi0)
Description
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic Operand
Hex Language
Code Code Conditions
TRANSFER CONTROL INSTRUCTIONS
JID FFÀ1111À1111
JMP a 6
JP a
JSRP a
JSR a 6
b
bb
bb
bb
bb
b
bb
RET 48À0100À1000
RETSK 49À0100À1001
HALT 33À0011À0011
38À0011À1000
IT 33À0011À0011
39À0011À1001
MEMORY REFERENCE INSTRUCTIONS
CAMT 33À0011À0011
3FÀ0011À1111
CTMA 33À0011À0011
2FÀ0010À1111
CAMQ 33À0011À0011
3CÀ0011À1100
CQMA 33À0011À0011
2CÀ0010À1100
LD r
b
LDD r,d 23À0010À0011
bb
LQID BFÀ1011À1111
RMB 0 4CÀ0100À1100
145
242
343
SMB 0 4DÀ0100À1101
147
246
34B
Machine
(Binary)
0110À0Àa
À
a
7:0
À
a
6:0
À1À
(pages 2,3 only)
or
a
5:0
À11À
(all other pages)
a
5:0
À10À
0110À1Àa
À
a
7:0
À
5À00ÀrÀ0101
e
(r
0:3) BrZrxBr Exclusive-OR Br with r
À0ÀrÀdÀ
0100À0101
À
0100À0010
À
0100À0011
À
0100À0111
À
0100À0110
À
0100À1011
À
Data Flow
ROM (PC
À
axPC None Jump
10:8
À
A,M)xPC
10:8
Skip
None Jump Indirect (Notes 1, 3)
7:0
Description
À
axPC
À
À
À
10:8
À
À
À
À
6:0
axPC
5:0
PCa1xSAxSBxSC None Jump to Subroutine Page
00010
x
PC
PC
10:6
5:0
a
x
PCa1xSAxSBxSC None Jump to Subroutine
axPC
SCxSBxSAxPC None Return from Subroutine
SCxSBxSAxPC Always Skip Return from Subroutine
À
À
À
À
AxT
À
À
À
À
À
À
À
À
À
À
À
À
À
À
À
À
À
À
À
7:4
RAM(B)xT
T
x
7:4
T
x
3:0
AxQ
RAM(B)xQ
Q
7:4
Q
3:0
3:0
RAM(B)
A None Copy T to RAM, A (Note 9)
7:4
3:0
x
RAM(B) None Copy Q to RAM, A
x
A
RAM(B)xA None Load RAM into A,
RAM(r,d)xA None Load A with RAM pointed
ROM(PC
SB
0xRAM(B)
0xRAM(B)
0xRAM(B)
0xRAM(B)
1xRAM(B)
1xRAM(B)
1xRAM(B)
1xRAM(B)
,A,M)xQ None Load Q Indirect (Note 3)
10:8
x
SC
0
1
2
3
0
1
2
3
None Jump within Page (Note 4)
(Note 5)
on Return then Skip
None HALT Processor
IDLE till Timer
None Overflows then Continues
None Copy A, RAM to T
None Copy A, RAM to Q
to directly by r,d
None Reset RAM Bit
None Set RAM Bit
14
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic Operand
Hex Language
Code Code Conditions
MEMORY REFERENCE INSTRUCTIONS (Continued)
STII y 7
Xr
b
b
6
XAD r,d 23
bb
XDS r
XIS r
b
7
b
4
REGISTER REFERENCE INSTRUCTIONS
CAB 50
CBA 4E
LBI r,d
bb
33
bb
LEI y 33
b
6
XABR 12
TEST INSTRUCTIONS
SKC 20
SKE 21
SKGZ 33
21
SKGBZ 33
001
111
203
313
SKMBZ 0 01
111
203
313
SKT 41
Machine
(Binary)
0111Ày
À
00ÀrÀ0110ÀRAM(B)ÝA None Exchange RAM with A,
À
e
0:3) BrZrxBr Exclusive-OR Br with r
(r
0010À0011
À
À1ÀrÀdÀ
0111
À00ÀrÀ
e
0:3) Bdb1xBd decrements and Decrement Bd.
(r
0100ÀRAM(B)ÝA Bd Exchange RAM with A
À00ÀrÀ
e
0:3) Bda1xBd increments and Increment Bd,
(r
0101À0000
À
0100À1110
À
(d–1)
À00ÀrÀ
e
0:3: not a LBI (Note 6)
(r
e
0,9:15)
d
or
0011À0011
À
À1ÀrÀdÀ
(any r, any d)
0011À0011
À
0110Ày
À
0001À0010
À
0010À0000
À
0010À0001
À
0011À0011
À
0010À0001
À
0011À0011
À
0000À0001
À
0001À0001
À
0000À0011
À
0001À0011
À
0000À0001
À
0001À0001
À
0000À0011
À
0001À0011
À
0100À0001
À
Data Flow
yxRAM(B) None Store Memory Immediate
À
À
À
À
À
À
a
1xBd 1 and Increment Bd
Bd
RAM(r,d)ÝA None Exchange A with RAM
RAM(B)
Ý
A Bd Exchange RAM with A
Z
rxBr past 0 Exclusive-OR Br with r
Br
Z
rxBr past 15 Exclusive-OR Br with r
Br
AxBd None Copy A to Bd
BdxA None Copy Bd to A
r,dxB Skip until Load B Immediate with r,d
Skip
Description
Pointed to Directly by r,d
À
yxEN None Load EN Immediate (Note 7)
À
À
AÝBr None Exchange A with Br (Note 8)
À
À
À
À
À
1st byte Skip if G Bit is Zero
À
À
À
2nd byte
À
* G
À
À
À
À
À
À
Ce‘‘1’’ Skip if C is True
AeRAM(B) Skip if A Equals RAM
e
G
0 Skip if G is Zero
3:0
e
G
0
0
e
G
0
1
e
G
0
2
e
0
3
RAM(B)
RAM(B)
RAM(B)
RAM(B)
0
1
2
3
(all 4 bits)
e
0 Skip if RAM Bit is Zero
e
0
e
0
e
0
A time-base Skip on Timer
counter carry (Note 3)
has occurred
since last test
15
Instruction Set (Continued)
Table III. COP444C/445C Instruction Set (Continued)
Mnemonic Operand
Hex Language
Code Code Conditions
INPUT/OUTPUT INSTRUCTIONS
ING 33
2A
ININ 33
28
INIL 33
29
INL 33
2E
OBD 33
3E
OGI y 33
b
5
OMG 33
3A
XAS 4F
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
0 signifies the least significant bit (low-order, right-most bit). For example, A
Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 6: LBI is a single-byte instruction if d
e.g., to load the lower four bits of B(Bd) with the value 9 (1001
instruction should equal 15 (1111
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: For 2K ROM devices, A
Note 9: Do not use CTMA instruction when dual-clock option is selected and part is running from D
e
).
2
Ý
Br (0xA3). For 1K ROM devices, AÝBr (0,0xA3, A2).
Machine
Data Flow
Skip
Description
(Binary)
0011À0011ÀGxA None Input G Ports to A
À
0010À1010
À
0011À0011ÀINxA None Input IN Inputs to A
À
0010À1000
À
0011À0011
À
0010À1001
À
0011À0011ÀL
À
0010À1110
À
0011À0011
À
0011À1110
À
0011À0011ÀyxG None Output to G Ports
À
0101Ày
À
0011À0011
À
0011À1010
À
0100À1111ÀAÝSIO, CxSKL None Exchange A with SIO
À
0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data
À
À
IL3, CKO,‘‘0’’, IL
À
x
A None Input IL Latches to A
0
À
x
RAM(B) None Input L Ports to RAM,A
7:4
L
x
A
3:0
À
BdxD None Output Bd to D Outputs
À
(Note 2)
(Note 3)
À
À
RAM(B)xG None Output RAM to G Ports
À
Immediate
À
(Note 3)
indicates the most significant (left-most) bit of the 4-bit A register.
3
), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI
2
clocks.
0
minus 1
,
16
Description of Selected Instructions
XAS INSTRUCTION
XAS (Exchange A with SIO) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the
value of the EN register. If SIO is selected as a shift register,
an XAS instruction can be performed once every 4 instruction cycles to effect a continuous data stream.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 11-bit word
PC10:PC8,A,M. LQID can be used for table lookup or code
conversion such as BCD to seven-segment. The LQID instruction ‘‘pushes’’ the stack (PC
and replaces the least significant 8 bits of the PC as follows:
A
x
PC(7:4), RAM(B)xPC(3:0), leaving PC(10), PC(9)
and PC(8) unchanged. The ROM data pointed to by the new
address is fetched and loaded into the Q latches. Next, the
stack is ‘‘popped’’ (SC
xSBxSAx
saved value of PC to continue sequential program execution. Since LQID pushes SB
of SC are lost.
Note: LQID uses 2 instruction cycles if executed, one if skipped.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not
affected by JID.
Note: JID uses 2 instruction cycles if executed, one if skipped.
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of the T
counter overflow latch (see internal logic, above), executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to generate its own time-base for real-time processing, rather than
relying on an external input signal.
Note: If the most significant bit of the T counter is a 1 when a CAMT instruc-
tion loads the counter, the overflow flag will be set. The following
sample of codes should be used when loading the counter:
; load T counterCAMT
; skip if overflow flag is set and reset itSKT
NOP
IT INSTRUCTION
The IT (idle till timer) instruction halts the processor and
puts it in an idle state until the time-base counter overflows.
This idle state reduces current drain since all logic (except
the oscillator and time base counter) is stopped.
INIL INSTRUCTION
INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0,
CKO and 0 into A. The IL3 and IL0 latches are set if a lowgoing pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0
inputs since the last INIL instruction, provided the input
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and IL0 into A3 and A0 respectively,
a
1xSAxSBxSC)
PC), restoring the
x
SC, the previous contents
and resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and IN0 lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a ‘‘1’’ will be placed in A2. A0 is input into A1.
IL latches are cleared on reset. IL latches are not available
on the COP445C/425C, and COP426C.
INSTRUCTION SET NOTES
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instructions are skipped or executed except for JID, and LQID.
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LQID is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LQID located in the last word of every fourth page (i.e.
hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
Note: The COP424C/425C/426C needs only 10 bits to address its ROM.
Therefore, the eleventh bit (P10) is ignored.
Power Dissipation
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, the user should run
at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full
supply levels to insure that outputs are not loaded down and
that inputs are not at some intermediate level which may
draw current. Any input with a slow rise or fall time will draw
additional current. A crystal or resonator generated clock
input will draw additional current. An R/C oscillator will draw
even more current since the input is a slow rising signal.
If using an external squarewave oscillator, the following
equation can be used to calculate operating current drain.
e
a
I
I
CO
where I
quiescent leakage current (from curve)
CKI frequency in MegaHertz
chip V
divide by option selected
For example at 5 volts VCCand 400 kHz (divide by 4)
I
CO
I
CO
At 2.4 volts VCCand 30 kHz (divide by 4)
I
CO
I
CO
Vc40cFiaVc1400cFi/Dv
Q
e
chip operating current drain in microamps
CO
in volts
CC
e20a
5c40c0.4a5c1400c0.4/4
e20a80a
e6a
e6a
700e800 mA
2.4c40c0.03a2.4c1400c0.03/4
2.88a25.2e34.08 mA
17
Power Dissipation (Continued)
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
e
a
Ici
I
Vc40cFi
Q
c
CC
ToaTi
and 400 kHz
To
a
Ici
c
Ti
ToaTi
For example, at 5 volts V
Icie20a5c40c0.4e100 mA
The total average current will then be the weighted average
of the operating current and the idle current:
e
I
Ita
CO
e
where: Ita
total average current
e
I
operating current
CO
Icieidle current
Toeoperating time
e
idle time
Ti
I/O OPTIONS
Outputs have the following optional configurations, illustrated in
Figure 11
:
a. Standard Ð A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to V
, compatible with CMOS and LSTTL.
CC
b. Low Current Ð This is the same configuration as a.
above except that the sourcing current is much less.
c. Open Drain Ð An N-channel device to ground only, allow-
ing external pull-up as required by the user’s application.
d. Standard TRI-STATE L Output Ð A CMOS output buffer
similar to a. which may be disabled by program control.
e. Low-Current TRI-STATE L Output Ð This is the same as
d. above except that the sourcing current is much less.
f. Open-Drain TRI-STATE L Output Ð This has the N-chan-
nel device to ground only.
All inputs have the following options:
g. Input with on chip load device to V
CC
.
h. Hi-Z input which must be driven by the users logic.
When using either the G or L I/O ports as inputs, a pull-up
device is necessary. This can be an external device or the
following alternative is available: Select the low-current output option. Now, by setting the output registers to a logic
‘‘1’’ level, the P-channel devices will act as the pull-up load.
Note that when using the L ports in this fashion the Q registers must be set to a logic ‘‘1’’ level and the L drivers MUST
BE ENABLED by an LEI instruction (see description above).
All output drivers use one or more of three common devices
numbered 1 to 3. Minimum and maximum current (I
V
) curves are given in
OUT
vices to allow the designer to effectively use these I/O con-
Figure 12
for each of these de-
OUT
and
figurations.
a. Standard Push-Pull Output b. Low Current Push-Pull Output c. Open-Drain Output
d. Standard TRI-STATE ‘‘L’’ Output e. Low Current TRI-STATE
‘‘L’’ Output
g. Input with Load
f. Open Drain TRI-STATE
‘‘L’’ Output
h. Hi-Z Input
FIGURE 11. Input/Output Configurations
18
TL/DD/5259– 14
Power Dissipation (Continued)
Minimum Sink Current
Standard
Minimum Source Current
Low Current Option
Minimum Source Current
COP444C/424C/445C/425C
Low Current Option
Maximum Source Current
COP344C/345C/324C/325C
Low Current Option
Maximum Source Current Maximum Quiescent Current
FIGURE 12. Input/Output Characteristics
Option List
The COP444C/445C/424C/425C/COP426C mask-programmable options are assigned numbers which correspond with the COP444C/424C pins.
The following is a list of options. The options are programmed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interface to various
I/O components using little or no external circuitry.
PLEASE FILL OUT THE OPTION TABLE on the next page.
Xerox the option data and send it in with your disk or
EPROM.
e
Option 1
Option 2: CKO Pin
Option 3: CKI input
0: Ground Pin Ð no options available
e
0: clock generator output to crystal/resonator
e
1: HALT I/O port
e
2: general purpose input with load device to V
e
3: general purpose input, high-Z
e
0: Crystal controlled oscillator input divide by 4
e
1: Crystal controlled oscillator input divide by 8
e
2: Crystal controlled oscillator input divide by 16
e
4: Single-pin RC controlled oscillator (divide by 4)
e
5: External oscillator input divide by 4
e
6: External oscillator input divide by 8
e
7: External oscillator input divide by 16
CC
Option 4: RESET
e
0: load device to V
e
1: Hi-Z input
input
CC
Option 5: L7 Driver
e
0: Standard TRI-STATE push-pull output
e
1: Low-current TRI-STATE push-pull output
e
2: Open-drain TRI-STATE output
Option 6: L6 Driver Ð (same as option 5)
Option 7: L5 Driver Ð (same as option 5)
Option 8: L4 Driver Ð (same as option 5)
Option 9: IN1 input
e
0: load device to V
e
1: Hi-Z input
CC
Option 10: IN2 input Ð (same as option 9)
Option 11e0: VCCPin Ð no option available
Option 12: L3 Driver Ð (same as option 5)
Option 13: L2 Driver Ð (same as option 5)
Option 14: L1 Driver Ð (same as option 5)
Option 15: L0 Driver Ð (same as option 5)
Option 16: SI input Ð (same as option 9)
Option 17: SO Driver
e
0: Standard push-pull output
e
1: Low-current push-pull output
e
2: Open-drain output
19
TL/DD/5259– 15
Option List (Continued)
Option 18: SK Driver Ð (same as option 17)
Option 19: IN0 Input Ð (same as option 9)
Option 20: IN3 Input Ð (same as option 9)
Option 21: G0 I/O Port Ð (same as option 17)
Option 22: G1 I/O Port Ð (same as option 17)
Option 23: G2 I/O Port Ð (same as option 17)
Option 24: G3 I/O Port Ð (same as option 17)
Option 25: D3 Output Ð (same as option 17)
Option 26: D2 Output Ð (same as option 17)
Option 27: D1 Output Ð (same as option 17)
Option 28: D0 Output Ð (same as option 17)
Option 29: Internal Initialization Logic
e
0: Normal operation
e
1: No internal initialization logic
Option 30: Dual Clock
e
0: Normal operation
e
1: Dual Clock. D0 RC oscillator
e
2: Dual Clock. D0 ext. clock input
(opt.Ý28 muste2)
(
Option 31: Timer
e
0: No Option Available
Option 32: Microbus
e
0: Normal
e
1: Microbus (opt.Ý31 muste0)
Option 33: COP bonding
(1k and 2K Microcontroller)
e
0: 28-pin package
e
1: 24-pin package
e
2: Same die purchased in both
24 and 28 pin version.
(1K Microcontroller only)
e
3: 20-pin package
e
4: 28- and 20-pin package
e
5: 24- and 20-pin package
e
6: 28-, 24- and 20-pin package
Note:Ðif opt.
e
must
0Ðif opt.Ý33e3, 4, 5 or 6 then opt.Ý9, 10, 19,
20, 21, 22, 30 and 32 must
Option Table
The following option information is to be sent to National along with the EPROM.
Ý
33e1 or 2 then opt.Ý9, 10, 19, 20 and 32
e
0.
OPTION 1 VALUE
OPTION 2 VALUE
OPTION 3 VALUE
OPTION 4 VALUE
OPTION 5 VALUE
OPTION 6 VALUE
OPTION 7 VALUE
OPTION 8 VALUE
OPTION 9 VALUE
OPTION 10 VALUE
OPTION 11 VALUE
OPTION 12 VALUE
OPTION 13 VALUE
OPTION 14 VALUE
OPTION 15 VALUE
OPTION 16 VALUE
OPTION DATA
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
0 IS: GROUND PIN
IS: CKO PIN
IS: CKI INPUT
IS: RESET INPUT
IS: L(7) DRIVER
IS: L(6) DRIVER
IS: L(5) DRIVER
IS: L(4) DRIVER
IS: IN1 INPUT
IS: IN2 INPUT
IS: VCC PIN
IS: L(3) DRIVER
IS: L(2) DRIVER
IS: L(1) DRIVER
IS: L(0) DRIVER
IS: SI INPUT
OPTION 17 VALUE
OPTION 18 VALUE
OPTION 19 VALUE
OPTION 20 VALUE
OPTION 21 VALUE
OPTION 22 VALUE
OPTION 23 VALUE
OPTION 24 VALUE
OPTION 25 VALUE
OPTION 26 VALUE
OPTION 27 VALUE
OPTION 28 VALUE
OPTION 29 VALUE
OPTION 30 VALUE
OPTION 31 VALUE
OPTION 32 VALUE
OPTION 33 VALUE
OPTION DATA
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
0 IS: TIMER
IS: SO DRIVER
IS: SK DRIVER
IS: IN0 INPUT
IS: IN3 INPUT
IS: G0 I/O PORT
IS: G1 I/O PORT
IS: G2 I/O PORT
IS: G3 I/O PORT
IS: D3 OUTPUT
IS: D2 OUTPUT
IS: D1 OUTPUT
IS: D0 OUTPUT
IS: INT INIT LOGIC
IS: DUAL CLOCK
IS: MICROBUS
IS: COP BONDING
20
21
Physical Dimensions inches (millimeters)
20-Lead Hermetic Dual-In-Line Package (D)
Order Number COP326C-XXX/D, COP426C-XXX/D
NS Package Number D20A
24-Lead Hermetic Dual-In-Line Package (D)
Order Number COP425C-XXX/D, COP325C-XXX/D,
COP445C-XXX/D, COP345C-XXX/D
NS Package Number D24C
22
Physical Dimensions inches (millimeters) (Continued)
28-Lead Hermetic Dual-In-Line Package (D)
Order Number COP424C-XXX/D, COP324C-XXX/D,
COP444C-XXX/D, COP344C-XXX/D
NS Package Number D28C
20-Lead Molded Dual-In-Line Package (N)
Order Number COP426C-XXX/N and COP326C-XXX/N
NS Package Number N20A
23
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Dual-In-Line Package (N)
Order Number COP425C-XXX/N, COP325C-XXX/N,
COP445C-XXX/N, COP345C-XXX/N
NS Package Number N24A
28-Lead Molded Dual-In-Line Package (N)
Order Number COP424C-XXX/N, COP324C-XXX/N,
COP344C, COP345C Single-Chip 1k and 2k CMOS Microcontrollers
LIFE SUPPORT POLICY
COP444C-XXX/N, COP344C-XXX/N
NS Package Number N28B
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
COP424C, COP425C, COP426C, COP324C, COP325C, COP326C and COP444C, COP445C,
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: (
Italiano Tel: (
a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
49) 0-180-530 85 85 Tsimshatsui, Kowloon
a
49) 0-180-532 78 32 Hong Kong
a
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a
49) 0-180-534 16 80 Fax: (852) 2736-9960
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