Mystery MMK-702U Service manual

Page 1
SERVICE
SERVICE MANUAL
4
4
MMK-702U
DM802
Page 2
Page 3
Page 4
Page 5
Page 6
2. Reference Information
2-1 Component Descripti
2-1-1 DVD
Conn
SONY HM 313-
ector Pin Definition
PUH
ons
-5-
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
Page 16
Page 17
Page 18
Page 19
Page 20
Page 21
Page 22
Page 23
Page 24
Page 25
Page 26
Page 27
Page 28
Page 29
Page 30
Page 31
Page 32
Page 33
Page 34
Page 35
Page 36
Page 37
Page 38
Page 39
Page 40
Page 41
Page 42
Page 43
Page 44
Page 45
2-1-4:   
Boot Sector Flash Memory
A29L800 Series
1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only,
Features
n Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
n Access times:
- 70/90 (max.)
n Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors
n Extended operating temperature range: -45°C ~ +85°C
for -U series
n Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple program command sequence
n Top or bottom boot block configurations available n Embedded Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies data at specified addresses
n Typical 100,000 program/erase cycles per sector n 20-year data retention at 125°C
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
n
n Ready /
- Provides a hardware method of detecting completion
n Erase Suspend/Erase Resume
n Hardware reset pin (
n Package options
- Reliable operation for the life of the system
supply Flash memory standard
- Superior inadvertent write protection Polling and toggle bits
Data
- Provides a software method of detecting completion
of program or erase operations
pin (RY / BY)
BUSY
of program or erase operations (not available on 44­pin SOP)
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then resumes the erase operation
RESET
- Hardware method to reset the device to reading array
data
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
)
-20-
Page 46
General Description
The A29L800 is an 8Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes of 8 bits or 524,288 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L800 is offered in 48-ball TFBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L800 can also be programmed in standard EPROM programmers. The A29L800 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L800 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L800 also offers the ability to program in the Erase Suspend mode. The standard A29L800 offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE), write enable (WE) and output enable (OE) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29L800 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by reading the I/O7 (
After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L800 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.
The hardware progress and resets the internal state machine to reading array data. The circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
Polling) and I/O6 (toggle) status bits.
Data
RESET
RESET
pin terminates any operation in
pin may be tied to the system reset
-21-
Page 47
Pin Configurations
n SOP n TSOP (I)
A18 A17
A7 A6 A5 A4 A3 A2 A1 A0
CE
VSS
OE
I/O0
I/O1 I/O9 I/O2
I/O10
I/O3
I/O11
1 2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 17 18 19 20 21 22
RY/BY
44 43 42 41 40 39 38 37 36 35 34 33
A29L800
32 31 30
28 27 26 25 24 23
RESET WE
A8 A9
A10 A11 A12 A13 A14
A15 A16
BYTE VSS
I/O15 (A-1) I/O7 I/O14I/O8 I/O6 I/O13 I/O5 I/O12 I/O4 VCC
1 2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
NC
10
NC
11
WE
RESET
12 13
NC
14
NC
15
RY/BY
16
A18
17
A17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24 25
A1
n TFBGA
TFBGA
Top View, Balls Facing Down
A29L800V
48
A16A15
47
BYTE
46
VSS
45
I/O15 (A-1)
44
I/O7
43
I/O14
42
I/O6
41
I/O13
40
I/O5
39
I/O12
38
I/O4
37
VCC
36
I/O11
35
I/O3
34
I/O10
33 I/O2
32 I/O9 31
I/O1
30
I/O8
29
I/O0
28
OE
27
VSS
26
CE A0
A6 B6 C6 D6 E6 F6
G6
H6
A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS
A5 B5 C5 D5 E5 F5
G5
H5
A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6
A4 B4 C4 D4 E4 F4
G4
H4
WE RESET NC NC I/O5 I/O12 VCC I/O4
A3 B3 C3 D3 E3 F3
G3
H3
RY/BY NC A18 NC I/O2 I/O10 I/O11 I/O3
A2 B2 C2 D2 E2 F2
G2
H2
A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1
A1 B1 C1 D1 E1 F1
G1
H1
A3 A4 A2 A1 A0 CE OE VSS
-22-
Page 48
Block Diagram
WE
BYTE
VCC
VSS
RESET
BYTE
A0-A18
WE
CE OE
RY/BY
State
Control
Command
Register
VCC Detector
PGM Voltage
Generator
Timer
Sector Switches
Erase Voltage
Generator
STB
Chip Enable
Output Enable
Logic
Y-Decoder
X-decoder
Address Latch
STB
I/O0 - I/O
15
Input/Output
Buffers
Data Latch
Y-Gating
Cell Matrix
(A-1)
Pin Descriptions
A0 - A18 Address Inputs
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1)
RESET
Pin No. Description
I/O15
Data Input/Output, Word Mode
A-1 LSB Address Input, Byte Mode
CE
OE
RY/BY
Chip Enable Write Enable Output Enable Hardware Reset Selects Byte Mode or Word Mode
Ready/
BUSY
- Output
VSS Ground
VCC Power Supply
NC Pin not connected internally
-23-
Page 49
Page 50
Page 51
Page 52
Page 53
Troubleshooting
Before resorting to maintenance service, please kindly check by yourself with the following chart.
Symptom Cause(s)
No Power
Picture
There is no picture or the picture is distorted.
Sound
There is no sound or the sound is distorted.
Unable to play a disc
The player breaks down when a USB drive is inserted into the player.
The buttons on the unit doesn't work.
The remote control does not function.
The AC power cord is not connected to the power supply or is not connected to a power supply securely.
The video cable isn't connected securely. Video output mode of the unit isn't correctly set. Video input mode of the connected TV isn't correctly set.
The audio cables aren't connected securely.
The volume is set to the minimum level.
The sound is switched off.
The disc is in fast forward/reverse playback.
This disc is placed in the disc tray in a wrong way.
The rating of the disc is higher than the rate set in the parental control item.
The unit isn't compatible with the disc.
The disc is dirty.
The connected USB drive is probably not a certified one.
The unit is being interfered with static electricity
etc.
There is no battery in the remote control.
The batteries are out of charge.
The remote control isn't pointed to the remote sensor.
The remote control is out of its operating area.
The unit is shut down.
Please check that the AC power cord
is connected securely.
Connect the video cable securely. Press [V-MODE] repeatedly until the
picture becomes normal again.
Set an appropriate video input mode.
Connect the audio cables securely. Turn up the volume. Press [MUTE] on the remote control to
switch on the sound.
Press [PLAY/PAUSE].
Check that the disc is placed in the disc
tray with its label side upwards.
Reset the settings in the parental control
item.
/ Clean the disc.
The player cannot play any uncertified USB drive. In case the player breaks down, turn it off, disconnect the power cord from the AC outlet and unplug the USB drive from the player. Then, power on the player again. The player will resume the normal status.
Switch off and unplug the unit. Then connect the plug to the power supply and switch it on again.
Install two AAA/1.5V batteries in it.
Replace the batteries with new ones.
Make sure that the remote control is pointed to the remote control sensor.
Make sure the remote control is within the operating area.
Switch off the unit and disconnect it from the AC outlet. Then power on the unit again.
Remedy
-24-
Page 54
Specifications
Power supply
Power consumption
Working environment
Disc output
Tuner
Power output (Max) Frequency response
Temperature
Relative humidity
TV System
Frequency Response
S/N(A weight)
Frequency Range
THD+NOISE
WOW FLUTTER
FM band Range
AC ~100 240V/5~ 0Hz/60Hz
75W
-10~+40
5%~90%
PAL/NTSC
20Hz~20KHz
80dB( )1KHz
70dB( )1KHz
-60dB(1KHz)
Below the limit of apparatus measure
87.5MHz~108MHz
12WX2
1.5dB(20Hz~20KHz)
-25-
Page 55
Page 56
Page 57
5
D D
12
12
D504
D503
1 2
50MH2A
L501
C501 275v224
R189 510K
R516 10K
1
+
1 3
1N5399
C503
275v224
3 4
34
1
Q502 3904
2 3
Q501
8550
2 3
ZD503
5.1V
A_MUTE
1
R25 4.7K
2
D502
1N5399
1 2
12
12
R190 510K
R519 470R
1
Q503 3904
2 3
R524
4.7K
LOUT
ROUT
1
Q11 3904
2 3
1N5399
275v102
CY3
CY4
275v102
1
1
2
C C
B B
A A
1
2P3.96 AC 220V
CN501
1
改开关电源芯片为
在功放输入加静音三极管解决开关机有冲击声
2
改功放输出脚,相位反。
3
2
1
2P3.96 SW CN502
2
FUSE1
1 2
12
+13V
R518
3.3K
2
FSDM0565 。
T2AL 250V
D512 4148
100U25V
MUTE AMP
+
TC15
R520 10K
D514 4148
Q29 8050
R517 10K
ZD504
5.1V
TC14
220U25V
1N5399
MUTE
68U400V
D501
R522 10K
2 3
+
TC1
U7
FSDM0565
4148 D513
681
R521
C518
4.7K
Q8 3904
4
T1 EC2828
18
FR107
17
VCC
45T
两线并绕
4
Z204
5.1V
220U25V
3
OUT1 OUT2 OUT3 OUT4
14
1 2
17
16
3
15
3
14 4 6
+
7 9 5 8
C1
250V102
TC3 1UF
23
1
+13V
C515 104
Q207 8050
13
12
11
3T
10
23
1
+
R223
470R
1 3
9T
R69
3.3k
U502
4
817
TC20
1
VCC
2 18 19
+13V
R222 5K1
FB
L57
R503
56K2W
C504
1KV101
1
1
2
2
3
3
4
4
5
5
6
6
R523
10K
+
TC16
47U25V
R525
10K
C506 104
R40
30k
STBYMUTE AMP
4
C91 10U
5
+
15 16
+
C105 10U
C523
104
47U25V
TC19
FR107
L502 FB
IN1 IN2 IN3 IN4
D505
R504 22R
+
10U50V
C316 473
C317
473
9
7
7
STBY
REF1011
810111213
+
1 2
TC2
R63 22R
6
U4
STA540
C505
1KV222
D506
6
DIAG1314
14T
7T
两线并绕
Q22 8550
1 3
2
2
C207
R507
1UF
1K
1 2
R222
D511
HER303 C511 1KV102
TL431
D5 HER303
C510 1KV102 D515 HER303
R508
680
C509
104
3
U503
2K
3
POWER +5V
R222 10K
MUTE
+
R505 10K
1
2
3
4
NC
TC11 2200U25V
L504 22uH
+
TC9 1000U16V
R506
10K
WP1
1
2
3
4
WP
STBY
L505 8uH
TC12
2200U25V
TC10
2200U10V
D508 FR107
D510 FR107
D509
POWER +5V
+
+
C514 104
C513 104
FR107D507
FR204
IR LED
R114 10K/NC
R512 NC
+
220U/50V
+
220U/35V
1 2
+
TC5
470U/25V
R27 10K
2
7T
五线并绕
R513 20K1/4W
3T
三线并绕
1 3
TC4
R514 20K
-24V
R509 4R7
TC7
C204 104
220U/35V
L503 20uH/1A
C206 104
IR
10K/NC
R117
10K/NC
R119
10K/NC
R121
+12V
-12V CD5V
RCH
LCH
+13V
POWER +5V
F+
Q17
F+
8050
Q27
R142 2.2K
TC8
2
Z203 12V/1W
R1131K
R148 10K
-24V
+
+
TC6
470U/25V
R123100R
R118 10K/NC
R120 10K/NC
+P12V
-P12V (1) 5V RCH
LCH
F-
C205 104
+12V
R110
20K
R122 10K/NC
(1)
(1)
8550
2
2
1 3
8550
Q23
R217 5K1
13
R147 10K
R138 470R
Q21
80550
1 3
R14610K
R511 560R/1W
Q25 8550
1 3
2
MUTE CD-POWER STB
1
1
2
2
3
3
4
4
5
5
6
6
7 8
78
IC1 JA5956
R137
R515
1 3
5K1
2
R139 2K
2
+12V
2
Q26 8550
13
1K
+12V
14
14
13
13
12
12
11
11
10
10
9
9
Q19 B772
CD-POWER STB
-12V
ZD502 12V
R129 10K/NC
R130 1K
F­F+ GND
-24V
+
220U/16V
TC13 220U25V
R144
+
E217
CD5V
470R
R115 100R
KEY
CN503
1 2 3 4
4P2.0mm
R127 10K/NC
R128 1K
Q24
8050
10R
R231
C215 104
E211 1UF/16V
1 2
J9
4 3
R231 10K
+
2
1 3
IR
KEY
LED
GND
POWER+5VPOWER+5V
R145
10K
1
CD5V
POWER +5V
CN2
5 4 3 2 1
5P2.0mm
MT1389L+AMP+TUNER+POWER
Title
VTREK
5
4
3
2
Size Document Number Rev
Date: Sheet
C
制作:
RF & MPEG
VTREK DM801
罗学华
1
审核:
原理图
1.2
25
of
Page 58
5
4
3
2
1
C173 1u
IN1_R
R152 27k
R158
D D
TUNER-L
C168 1u
R156 100k
C C
TUNER-R
C179 1u
R163 100k
B B
R154 1k
C171
1000p
R161 1k
C184
1000p
C166 82p
-12V
-
2
+
3
8 4
+12V
R159 27k
C177 82p
-12V
-
6
+
5
8 4
+12V
U14A
1
NJM4558 OPA
U14B
7
NJM4558 OPA
C169 1u
C181 1u
R162
TUN_L
100
R160 100
TUN_ R
TUNER-RST TUNER-SEN TUNER-RCLK TUNER-RSDIO
100k
DV33
R167 10K(NC)
AUXR AUXL
R168 10K
R169 10K
R170 10K
IN1R
R31
R29
100k
100k
R171 47K
FMI
AMI
R172 22
R175 22
R173 22
R174 22
C175
1U
C176
L509
100UH
L506
470UH
1U
0R
AKIN2
AKIN1
L507
T-SEN T-RCLK
IN1_L
C517 1u C516 1u
R2 100k
T-RST
T-SDIO
33P(NC)
C82
C172 1u
R4
100k
AUX1R
AUX1L
C194
30P
C195
0.47uF
R157 100k
R180
100R R181 100R
33P(NC)
C87
C192
22P
IN1L
IN1_L IN1_R
P3
3 2 1
1 2 3 4 5
SI4730
MIC
CP2
3 2 1
U508
+12V
NC FMI FRGND AMI RST
P1
P2
NC
SEN
SCLK
SDIO
678910
Y2
32.768
CN16 3P,2mm
1 2 3
CN15 3P,2mm
1 2 3
AV2X2
P3
1617181920
P3P2P1
LOUT
ROUT
GND
VDD
RCLK
C193 22P
URST# AKIN1 AKIN2
AUDIO_MUTE SCART1 SCART2
URST# (1) AKIN1 (5) AKIN2 (5)
AUDIO_MUTE (5) SCART1 (5) SCART2 (5)
IO
AKIN1 AKIN2
TUNER-RST TUNER-RCLK TUNER-RSDIO TUNER-SEN AIN_SW1 AIN_SW2
5V
+12V
AKIN1 (2) AKIN2 (2)
TUNER-RST (2) TUNER-RCLK (2) TUNER-RSDIO (2) TUNER-SEN (2) AIN_SW1 (2) AIN_SW2 5V +12V
(2) (6) (1)
IO
10K
R183
+
C519
220u
R182
R166
R184
10K(NC)
10K(NC)
10K(NC)
L508
C68
104uF
FB 0805
AMI
FMI
L5V
U504
1
1
2
78L05
2
1 2 3 4 5
3
CN1
+P12V
3
R179
R177
10K
10K
L5V
NC
15
NC
VIO
R178
10K
R178
0R(NC)
14 13 12 11
R176
10K
TUNER-L TUNER-R
TUNER-SEN
A A
VTREK
5
4
3
2
MT1389L+AMP+TUNER+POWER
Title
Size Document Number Rev
B
制作:
Date: Sheet
RF & MPEG
VTREK DM801
罗学华
审核:
1
原理图
of
25
1.2
Page 59
5
4
3
2
1
+12V -12V
+12V
C95
C96
C97
0.1u
0.1u
D D
C98
0.1u
0.1u
DV33
MUTE_Circuit
AUDIO_MUTE
+
C88
1U
D8 1N4148
R89
C122 100pF
30k
C C
B B
A A
C123 10uF/16v
+
AL
R96 100k
C131 10uF/16v
+
AR
R107 100k
R91
10k
R104
10k
C125 1000pF
C133 1000pF
R92
5.1k
R100
30k
R105
5.1k
-12V
U11A
-
2
+
3
NJM4558 OPA
8 4
+12V
C128 100pF
-12V
U11B
-
6
+
5
NJM4558 OPA
8 4
+12V
ASPECT
RGB/CVBS
LCH RCH B/U_OUT G/Y_OUT R/V_OUT CVBSO
C124
1
7
10uF/16v
C132
+
10uF/16v
A_MUTE
A_MUTE
470
R106
470
CN10 16PIN1.0MM
1
1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
R95
+
3 2
3 2
Q13 2N3904
Q16 2N3904
LCH
R97 100k
R108 100k
C126 1000pF
RCH
C134 1000pF
+12V
+
R86 NC
D10 1N4148
R82 100k
R87 47k
C119 47uF/16v
R102 100
R103 100
DV33
R81
4.7k
SCART1
SCART2
1
C129 0.1uF
C130 330pF
R77 75
R84 2.2k
R93
2.2k
R98
2.2k
1
Q14
2N3904
R70 10k
R75 470
32
Q20 2N3906
+12V
R90
2.2k
3 2
COAXIALASPDIF
Q10 2N3906
3 2
1
ASPECT
+
100uF/16v
-12V
C99
C100
0.1u
0.1u
R71 510
32
Q9
1
2N3906
C155
R140 100k
R141 470
RGB/CVBS
R94 NC
R99 NC
1
Q15
3 2
NC
C101
0.1u
R85 10k
Q12 2N3906
SCART3
1
C522
220uF/10v
A_MUTE
C102
0.1u
VCC
D7 1N4148
32
+
-12V
SC
R/V_OUT COAXIAL
B/U_OUT RCH
G/Y_OUT LCH
V_R
V_B
V_G
CVBS_OUT
L48 1.8FB
R88 75 1%
L50 1.8uH L51 1.8uH
L52 1.8uH L53 1.8uH
L54 1.8uH L55 1.8uH
R62 75 1%
R68 75 1%
R78 75 1%
C103 100pF
C108 100pF
C114 100pF
L28 1.8uH
C120 100pF
L25 1.8uH
C104 100pF
L26 1.8uH
C109 100pF
L27 1.8uH
C115 100pF
C121 100pF
4 6
CP4
S-video
5
5
6
6
9
9
3
3
4
4
8
8
1
1
2
2
7
7
359
CP1
AV3X2
SY
R/V_OUT
D12
D13
D19
1N4148
D15
D17
CVBSO
1N4148
1N4148
1N4148
VCC
VCC
G/Y_OUT
VCC
VCC
CVBSO
L49 fb
1N4148
SC
B/U_OUT
D14
1N4148
D16
1N4148
D18
1N4148
87
21
L50 1.8uH
AR AL
ASPDIF CVBS_OUT
V_R V_B V_G
AUDIO_MUTE SCART1
SCART2 SCART3
SY
AR (2) AL (2)
ASPDIF (2) CVBS_OUT (2)
V_R (2) V_B (2) V_G (2)
AUDIO_MUTE (2) SCART1 (2)
SCART2 (2) SCART3
(2)
LCH
LCH
RCH
RCH
MT1389L+AMP+TUNER+POWER
Title
VTREK
5
4
3
2
Size Document Number Rev
Date: Sheet
C
制作:
RF & MPEG
VTREK DM801
罗学华
1
审核:
原理图
1.2
25
of
Page 60
5
4
3
2
1
SDRAM (Dual Layout)
U5
MA0
23
MA1
D D
SD33
C C
R50 10k
R51 10k
R52 33
DCLK BA1 DBA1
RAS# CAS#
SDCKE
DCS#
SDCLK
DBA0BA0 DRAS# DCAS# DWE#WE#
MA2 MA4
MA5 MA6 MA7 MA8 MA9 MA10 MA11 DBA0 DBA1
SDCLK SDCKE
DCS# DRAS# DCAS# DWE#
DQM0 DQM1
A0
24
A1
25
A2
26
A3
29
A4
30
A5
31
A6
32
A7
33
A8
34
A9
22
A10/AP
35
A11
20
BA0/A13
21
BA1/A12
38
CLK
37
CKE
19
CS
18
RAS
17
CAS
16
WE
15
DQML
39
DQMH
36
NC
40
NC
54
VSS
41
VSS
28
VSS
ESMT M12L64164A/N.C
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
VCC
VCC
VCC
VCCQ VCCQ VCCQ VCCQ
VSSQ VSSQ VSSQ VSSQ
DQ0
2
DQ1
4
DQ2
5
DQ3MA3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
42
DQ9
44
DQ10
45
DQ11
47
DQ12
48
DQ13
50
DQ14
51
DQ15
53
SD33
1 14 27
SD33
3 9 43 49
6 12 46 52
DV33 SD33
L23 FB
C77
+
47uF/10v
SD33
C79
C80
0.1uF
0.1uF
SD33
C83
0.1uF
C84
0.1uF
C85
0.1uF
C78
+
100uF/10v
C81
0.1uF
C86
0.1uF
DQ[0..15] MA[0..11] DQM[0..1] BA[0..1] DCLK
RAS# CAS# WE#
DRAM I/F
SF_CK SF_CS SF_DI SF_DO
S-FLASH
USB_DP USB_DM
USB
DQ[0..15] (2) MA[0..11] (2) DQM[0..1] (2) BA[0..1] (2) DCLK (2)
RAS# (2) CAS# (2) WE# (2)
SF_CK (2) SF_CS (2) SF_DI (2) SF_DO (2)
USB_DP (2) USB_DM (2)
S-FLASH
SF_CK SF_DI
DV33
R57 10k C92
0.1uF
DV33
DV33
SF_CS
DV33
B B
SF_DO
R58 10k
R59 10k
U9
1
CE#
VDD
2
SO
HOLD#
3
WP#
SCK
4 5
VSS SI
SST25VF040B
512KB
NexFlash 25P16S1
SF_CS
8 7 6
R60 10k/NC
A A
VTREK
5
4
3
MT1389L+AMP+TUNER+POWER
Title
Size Document Number Rev
Custom
制作:
Date: Sheet
2
RF & MPEG
VTREK DM801
罗学华
审核:
25
1
of
原理图
1.2
Page 61
5
4
3
2
1
DV33
VCC
IR
CN4
4P,2mm
1 2 3 4
96 95 94 93 92 91 90 89 88 87 86 85 8413 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
16 15 14 13 12 11 10
R3 10
R5 10
R8 1k R9 1k R10 1k
C44
0.1uF
Chip Decap.
89L_3V3
VREF DACVDD3 GPIO13 GPIO12 GPIO11 GPIO10
GPIO9 GPIO8 GPIO7 MA3 MA2
MA1 MA0 MA10 BA1
BA0 RAS# CAS# WE# MA4 MA5 MA6 MA7 MA8 MA9
MA11 DCLK DQM1
VDD OEN Q5 Q6 Q7 Q8 OSA
U6 CD4094B
TUNER-SEN
113
114
ADACVSS1
ARF / GPIO
ARS / GPIO
RD1
RD2
RD3
DQ2
DQ3
L13 FB
+
C27 10uF/16v
+
C36 100uF/6.3v
C41 0.1uF
C48 1500pF
GPIO21
AADVDD
APLLVDD3
111
110
109
108
112
AADVDD
APLLCAP
APLLVDD
ADACVSS2
RD4
RD5
RD6
DVDD33
DQ5
DQ6
DQ7
DQ4
V1889L_3V3
89L_3V3
GPIO20
107
AKIN1 / GPIO21 / Audio_Mute
RD7
ADVCM / GPIO20
DVDD18
GPIO19
106
AKIN2 / GPIO19 / Audio_Mute
DQM0
DQM0
DV33
105
AADVSS
RD15
DQ15
VCC
V_R
V_B
104
103
R
RD14
DQ13
DQ14
C28 100pF
DV33
GPIO9
RxD
GPIO10
TxD
V_G
102
B
G
RD13
RD12
DQ12
DACVDD3
R16
FS
560
CVBS_OUT
DACVDD3
101
1009998
97
FS
CVBS
DACVSSC
DACVDDA
DACVDDB
VREF
DACVDDC
GPIO13
SPDIF / GPIO12
GPIO11 GPIO10
DVDD18
GPIO9 GPIO8
GPIO7 / CKE
RA3 RA2
DVDD33V14
RA1 RA0
RA10
BA1
DVSS18
BA0 RAS# CAS#
RWE#
RA4
RA5
RA6
RA7
RA8
RA9
DVDD33
RA11 RCLK
DQM1
RD11
RD10
RD9
DVSS33
RD8
MT1389L/K/SMD
LQFP128/SMD/D14X14
DQ10
DQ11
DQ8
DQ9
R6 NC R7 0
Q5 4094_SCK Q6
Q4
C26 1uF
2
V18
V18 RFV18-1
L9 FB
V18
L12 FB
CN3 6P,2mm
D
2
2SK3018
E
3
S
1
R13 100k
32
1
Q2
R19
0
C60 0.1uF
T­T+
FMSO
TRSO V1P4 STBY
R46 10K
5
SP-A
2
C
C
B 2SB1132
3 2
32
1
Q3
2SK3018
R20
0
C62 120pF
C76
0.1u
15 16 17 18 19 20 21
22 23 24 25 26 27 28
6 5 4 3 2 1
E
Q1
2N3904
3
1
R17 100k
L17
10uH
U2
VOTK+ VOTK­VOLD+ VOLD­VCC2 OP1OUT PVCC2
PREGND VINLD OP1IN­OP1IN+ VINTK BIAS STBY
AM5888
2
C
1
3
E
B
2N3904
R14 10k
R15 10k
L15 FB
C55
0.1uF
L18 10uH
Q4
2SB1132
3 2
R23 4.7 R24 4.7
32
Q5
2SB1132
OP2OUT
AVCC
IOA
AVCC
C54
+
100uF/10v
Very Important to reduce Noise
1
1
14
VOFC+
13
VOFC-
12
VOSL-
11
VOSL+
10
VOTR+
9
VOTR-
8
VCC
2930
G1G2
7
REV
6
FWD
5 4
VINSL
3
OP2IN+
2
OP2IN-
1
VINFC
C75 47u
+
C64 47uF/6.3v
C67
+
47uF/6.3v
RFV33
F+ F-
R39 10k R41 10k
R47 10k
+
LDO2
LDO1
FOSO
SP+ LOAD+ LOAD-
C37
0.1uF
R11 1
SP­SP+
D D
LIMIT SL-
SL+
G
1
2SK3018
F-
1
F+
2
T+
3
T-
4
C/c
5
D/d
6
CD/DVD SW
7
RF
8
A/a
9
B/b
10
F
11
GND-PD
12
Vc(Vref)
13
Vcc
14
E
15
NC
16
VR-CD
17
VR-DVD
18
CD-LD
19
MD
20
HFM
21
C C
B B
1
A A
NC
22
DVD-LD
23
GND-LD
24
SANYO HD6x
24
LD-DVD
23 22
AVCC1
21
MDI1
20
LD-CD
19 18 17 16 15
AVCC1
14
V20
13 12
F
11
B
10
TOP
A
9
RFO
8
IOA
7
D
6
C
5
T-
4
T+
3
F+
2
F-
1
CN5 SMD24P0.5mm
SL+ SP­SL-
C73
0.1u
C22 0.1uF
RFV18-2
C23 0.1uF
SERVO RF DeCAP.
V20
+
C33 47uF/6.3v
RF Reference
SP-
R134 10k
SP-A
R136 10k
XI
C56 22pF
L16 FB
89L_3V3
L19 FB
89L_3V3
L20 FB
V18
VCC
VCC
MO_VCCMO_VCC
TRCLOSE TROPEN
DMSO
R36
20.0k
R44 12k
4
C163
0.1uF
C164
0.1uF
4.7uF/10v
10uF/10v
10uF/10v
V1P4
C38
+
C34 47uF/6.3v
0.1uF
R18 100k
Y1
27MHz
C58
C61
C65
L21 FB
L22 FB
D2 IN5399
1 2
PV33
Q6 8550
32
1
89L_3V3
89L_3V3
1
D11 BAT54C
3
C57 22pF
AVDD33
C59
0.1uF
USB_V33
C63
0.1uF
USB_V18
C66
0.1uF
AVCC
D3 IN5399
1 2
L10
RFVDD3
C25
C24
FB
RFV33
OP-
DV33
2
OP+
XO
AVCC
MO_VCC
Q7 8550
3 2
1
4.7uF
ADVCM
PV18
0.1uF
L14
AADVDD
150uH
C35
C32
+
6800pF
C B A D F E
RFV18-2 RFVDD3 XI XO
R21 15k
AVDD33
USB_V33
R22 5.1k
USB_V18
R37
4.7k
R45 10k
470uF/6.3v
C47 10uF/10v
C49 0.1uF
U1
1 2 3 4 5 6 7 8
9 10 11
V20
12
V1P4
14
MDI1
15
MDI2
16
LDO1
17
LDO2
18 19
DMO
20
FMO
21
GPO_A
22
GPO_B
23
TRO
24
FOO
25
GPIO2
26
USB_DP
27
USB_DM
28 29 30 31 32
FOSO FOO TRSO FMSO DMSO
DV33
C70
C69
330pF
330pF
C74 0.1uF R48 10k R49 10k
ADACVDD APLLVDD3 DACVDD3DACVDD3
C29
0.1uF
RFO
OP-
OP+
C161 1uF
128
127
126
125
RFG / OPINP
RFA
RFH / OPINN
RFIN / OPOUT RFB RFC RFD RFE RFF AVDD18 AVDD33 XTALI XTALO AGND V20
REXT MDI1 MDI2 LDO1 LDO2 AVDD33 DMO FMO TRAY_OPEN TRAY_CLOSE TRO FOO FG / GPIO2 USB_DP USB_DM USB_V33 USB_GND PAD_VRT USB_V18
GPIO3 / INT#
GPIO4
GPIO6
33343637383940414243444546474849515253505556575458596162636064
35
GPIO6
GPIO4
GPIO3
SF_CS
R26 27k R28 27k R30 15k R32 10k
C71
C72
0.1uF
0.015uF
LOAD­LOAD+ TROUT
TRIN
3
L8 150uH L11 47uH
C30
C31
0.1uF
0.1uF
C40470uF/10v
+
C39 0.1uF
C43 4.7uF
AL
ADACVDD
RFV18-1
TUNER-RST
TUNER-RCLK
C162 220pF
124
123
118
117
122
121
120
119
RFIP
AGND18
AVDD18
ADACVDD2
ALF / GPIO
ALS / GPIO
ADACVDD1
AVCM
AL / GPIO1
MT1389L/K
LQFP 128
Desktop
SF_CS_
SF_DO
SF_DI
SF_CK
UP1_6 / SCL
UP1_7 / SDA
ICE
PRST#IRRD0
IR
SF_CK
UP1_6
UP1_7
URST#
SF_DI
SF_DO
TRO FMO DMO
V1P4
CN6
5P,2mm
1 2 3 4 5
C42 10uF/10v
AR
TUNER-RSDIO
116
115
AR / GPIO0
V1.0
DQ1
DQ0
VCC
C45
C46
0.1uF
0.1uF
C53 0.1uF
V18
1
STROBE
2
DATA
3
CLOCK
4
Q1
5
Q2
6
Q3
7
Q4
89
VSSOSB
VTREK
C21 100uF/10v
VFDVCC
VSCK VSTB VSDA
+
USB_DP USB_DM
V1889L_3V3
C50
0.1uF
GPIO7 GPIO8 GPIO9 GPIO10
DV33
CN2
6P,2mm
1 2 3 4 5 6
CN7
4P,2mm
1 2 3 4
DQ[0..15] MA[0..11] DQM[0..1] BA[0..1] DCLK
RAS# CAS# WE#
DRAM I/F
SF_CK SF_CS SF_DI SF_DO
S-FLASH
C51
0.1uF
C52
0.1uF
CN14
6P,2mm
1 2 3 4 5 6
ASPDIF AR AL
AUDIO I/F
CVBS_OUT V_R V_B V_G
VIDEO I/F
USB_DP USB_DM
USB I/F
AUDIO_MUTE
罗学华
URST# AKIN1 AKIN2
AUDIO_MUTE SCART1 SCART2 SCART3
IO
AKIN1 AKIN2
TUNER-RST TUNER-RCLK TUNER-RSDIO TUNER-SEN
AIN_SW1 AIN_SW2
IO
1
GPIO19 AKIN2 GPIO20 ADVCM GPIO21 AKIN1 GPIO12
GPIO6 TRCLOSE
GPO_A STBY GPIO3 4094_STB GPIO11
GPO_B
4094_STB 4094_SDA
Q2 Q3
ASPDIF VSTBGPIO13 TRINGPIO2
LIMIT
TROUTGPIO4
VSCKUP1_6 4094_SCK VSDAUP1_7 4094_SDA
IOA TROPEN
Q2 AIN_SW1 Q3 AIN_SW2 Q4 SCART1 Q5 SCART2 Q6 SCART3
MT1389L+AMP+TUNER+POWER
Title
Size Document Number Rev
Date: Sheet
C
制作:
RF & MPEG
VTREK DM801
MA[0..11] (4) DQM[0..1] (4) BA[0..1] (4) DCLK (4)
RAS# (4) CAS# (4) WE# (4)
SF_CK (4) SF_CS (4) SF_DI (4) SF_DO (4)
ASPDIF (6) AR (5) AL (5)
CVBS_OUT (6) V_R (6) V_B (6) V_G (6)
USB_DP (7) USB_DM (7)
URST# (1) AKIN1 (5) AKIN2 (5)
AUDIO_MUTE (5) SCART1 (5)
SCART2 (5)
SCART3 (5)
AKIN1 (5) AKIN2 (5)
TUNER-RST (5) TUNER-RCLK (5) TUNER-RSDIO (5) TUNER-SEN (5)
AIN_SW1 (5) AIN_SW2 (5)
审核:
25
DQ[0..15] (4)
原理图
1.2
of
Page 62
5
4
3
2
1
COMMON1389L/K_RECEIVER_HD65_V1.0
MT1389L Receiver General GPIO List
MT1389L/K (LQFP128) DVD Receiver Board For Sanyo HD 6x Series PUH s
D D
1 INDEX & POWER, RESET 2 MT1389L/K LQFP128 3 MEMORY & CARDS 4 AV PORT
C C
B B
-P12V
C521
0.1uF
-12V
-12V
L3
FB
C8
+
47uF/16v
5V
L4
FB
+
C9 220uF/10v
MT1389L V6 Full Function GPIO List
PIN
33 34GPIO4 35 87 22 23 26
89 91 92 93 94 106 107 108 27 28 31 40 41 114 115 119
C5
0.1uF
GAME_SW
LIMIT TRCLOSE
MS_CLK
STBY TROPEN TRINGPIO2
MS_BS88 MS_D0 SD_D0
SCART1
ASPDIF
VSTB
SCART2
ADVCM AKIN1
USB_DP USB_DM PAD_VRT
VSCK VSDA
AUDIO_ARF AUDIO_ARS AUDIO_ALSALS AUDIO_ALF
PV33
PV33
+
C3 220uF/6.3v
VCC
C11
0.1uF
Name
GPIO3
GPIO6 GPIO7 GPO_A GPO_B
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO19 GPIO20 GPIO21 GPIOK0 GPIOK1 GPIOK2 UP1_6 UP1_7 ARF ARS
ALF
VCC
Features
SCART3
TROUT
IOA
SD_CLK SD_CMD
HSYNC
VSYNC
AUDIO_MUTE
GAME_LOAD GAME_CLK GAME_DA1 GAME_DA2120
L1 FB
C10
220uF/6.3v
L2 FB
C4 47uF/6.3v
89L_3V3
89L_3V3
C2
+
0.1uF
DV33
DV33
+
C6
0.1uF
MT1389L Receiver GPIO List
Name
GPIO3 GPIO4 GPIO6 GPIO7 GPO_A GPO_B GPIO2 GPIO8 MS_BS GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO19 GPIO20 GPIO21 UP1_6 UP1_7
4094_GPO 4094 GPO Features
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
RESET Circuit
PIN
33 34 35 87 22 23 26 88 89 91 92 93 94 106 107 108 40 41
4094_PIN
4 5 6 7 14 13 12 11
DV33
2
2
1
1
Q504
78L05
Features
4094_STB
LIMIT TRCLOSE
MS_CLK
STBY TROPEN TRIN
MS_D0 SD_D0
ASPDIF
VSTB
AKIN2 ADVCM AKIN1
VSCK VSDA
AUDIO_MUTE
AIN_SW1 AIN_SW2
SCART1 SCART2
PLL_CE PLL_CL PLL_DO
3
3
URST#
C20 104
TROUT
IOA
SD_CLK SD_CMD
RDS_DATPLL_DI
4094_SCK 4094_SDA
RDS_SCK
PV18
+P12V
L6
FB
+
C16 47uF/16v
A A
5
C17
0.1uF
+12V
+12V
L7
FB
C18
+
47uF/6.3v
RFV33DV33
RFV33
C19
0.1uF
4
C14
0.1uF
+
L5 FB
C12 220uF/6.3v
3
C13 47uF/6.3v
+
C15
0.1uF
V18
V18
H1 HOLE
H2
1
HOLE
1
VTREK
MT1389L+AMP+TUNER+POWER
Title
Size Document Number Rev
C
Date: Sheet
1
1
2
-P12V +P12V
VTREK DM801
制作:
URST#
-P12V +P12V 5V
5V
RF & MPEG
罗学华
URST# (2)
-P12V (6) +P12V
(6)
5V
(6)
原理图
1.2
审核:
25
1
of
Page 63
Loading...