MXIC MX26L3220XAC-12, MX26L3220XAI-12, MX26L3220XAC-90, MX26L3220XBI-90, MX26L3220MC-12 Datasheet

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FEATURES
ADVANCED INFORMATION
MX26L3220
32M-BIT [2M x 16] CMOS
MULTIPLE-TIME-PROGRAMMABLE EPROM
2,097,152 x 16 byte structure
- 2.7 to 3.6 volt for read, erase, and program operations
Low Vcc write inhibit is equal to or less than 2.5V
Compatible with JEDEC standard
High Performance
- Fast access time: 90/120ns (typ.)
- Fast program time: 70s/chip (typ.)
- Fast erase time: 90s/chip (typ.)
Low Power Consumption
- Low active read current: 17mA (typ.) at 5MHz
- Low standby current: 30uA (typ.)
Minimum 100 erase/program cycle
GENERAL DESCRIPTION
Status Reply
- Data polling & Toggle bits provide detection of program and erase operation completion
12V ACC input pin provides accelerated program
capability
Output voltages and input voltages on the device is
deterined by the voltage on the VI/O pin.
- VI/O voltage range:1.65V~3.6V
10 years data retention
Package
- 44-Pin SOP
- 48-Pin TSOP
- 48-Ball CSP
The MX26L3220 is a 32M bit MTP EPROMTM organized as 2M bytes of 16 bits. MXIC's MTP EPROM most cost-effective and reliable read/write non-volatile random access memory. The MX26L3220 is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX26L3220 offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX26L3220 has separate chip enable (CE) and output enable OE controls. MXIC's MTP EPROMTM augment EPROM functionality with in-circuit electrical erasure and programming. The MX26L3220 uses a command register to manage this functionality.
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TM
offer the
MXIC's MTP EPROM memory contents even after 100 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.
The MX26L3220 uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epiprocess. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC +1V.
1
TM
technology reliably stores
PIN CONFIGURATION
48 CSP
1. Ball pitch=0.75mm for MX26L3220XA (TOP view, Ball down)
12345678
MX26L3220
A
B
C
D
E
F
A13
A14
A15
A16
V I/O
GND
A11
A10
A12
Q14
Q15
Q7
A8
WE
A9
Q5
Q6
Q13
ACC
RESET
NC
Q11
Q12
Q4
NC
A18
A20
Q2
Q3
VCC
9.0 mm
A19 A7
A17
A6
Q8
Q9
Q10
2. Ball pitch=0.8mm for MX26L3220XB(TOP view, Ball down)
ABCDEFGH
A5
A3
CE
Q0
Q1
A4
A2
A1
8.0 mm
A0
GND
OE
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6
5
4
3
2
1
A13
A9
WE
NC
A7
A3
A12
A8
RESET
ACC
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
A20
A5
A1
Q7
Q5
Q2
Q0
A0
9.0 mm
A16
V I/O
Q14
Q12
Q10
Q8
CE
Q15
Q13
VCC
Q11
Q9
OE
GND
Q6
Q4
8.0 mm
Q3
Q1
GND
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MX26L3220
A15 A14 A13 A12 A11 A10
A9 A8
NC
A20
WE
RESET
ACC VCC
A19 A18 A17
A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A16 V
I/O
GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 V
CC
Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
MX26L3220
44 SOP
44
NC A18 A17
CE
GND
OE
Q0
Q8
Q1
Q9
Q2 Q10
Q3 Q11
2 3 4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12 13 14
MX26L3220
15 16 17 18 19 20 21 22
A20
43
A19
42
A8
41
A9
40
A10
39
A11
38
A12
37
A13
36
A14
35
A15
34
A16
33
WE
32
GND
31
Q15
30
Q7
29
Q14
28
Q6
27
Q13
26
Q5
25
Q12
24
Q4
23
VCC
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A20 Address Input Q0~Q15 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input RESET Hardware Reset Pin, Active Low VC C +3.0V single power supply ACC Hardware Acceleration Pin V I/O I/O power supply (for 48 TSOP and
48 CSP package only) GN D Device Ground N C Pin Not Connected Internally
48 TSOP
LOGIC SYMBOL
21
A0-A20
CE OE WE RESET
ACC
16
Q0-Q15
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BLOCK DIAGRAM
CE OE WE
CONTROL INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
MX26L3220
WRITE
STATE
MACHINE
(WSM)
A0-A20
ADDRESS
LATCH
AND
BUFFER
X-DECODER
MX26L3220
FLASH ARRA Y
Y-DECODER
Y-PASS GATE
SENSE
AMPLIFIER
DATA LATCH
STATE
REGISTER
ARRAY
SOURCE
HV
COMMAND
DATA DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
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Q0-Q15
I/O BUFFER
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MX26L3220
AUTOMATIC PROGRAMMING
The MX26L3220 is word programmable using the Auto­matic Programming algorithm. The Automatic Progr am­ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro­grammed. The typical chip programming time at room temperature of the MX26L3220 is less than 90 seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 un­lock write cycle and A0H) and a program command (pro­gram data and address). The de vice automatically times the programming pulse width, provides the program veri­fication, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling be­tween consecutive read cycles, provide feedback to the user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
All data are latched on the rising edge of WE or CE, whichever happens later .
MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia­bility, and cost effectiveness. The MX26L3220 electri­cally erases all bits simultaneously using Fowler-Nord­heim tunneling. The bytes are programmed b y using the EPROM programming mechanism of hot electron injec­tion.
During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. After the state machine has completed its task, it will allow the command regis­ter to respond to its full command set.
The entire chip is bulk erased using 50 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temper ature is accomplished in less than 45 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand­ard microprocessor write timings. The device will auto­matically pre-program and verify the entire arra y. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu­tive read cycles provides feedback to the user as to the status of the programming operation.
Register contents serve as inputs to an internal state­machine which controls the erase and programming cir­cuitry . During write cycles, the command register inter­nally latches address and data needed for the program­ming and erase operations. All address are latched on the falling edge of WE or CE, whiche ver happens later.
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MX26L3220
Table 1. BUS OPERATION(1)
Operation CE OE WE RESET Address Q15~Q0
Read L L H H A Write(Note 1) L H L H A
IN
IN
Standby VCC±0.3V X X VCC±0.3V X High-Z Output Disable L H H H X High-Z Reset X X X L X High-Z
Legend: L=Logic LOW=VIL,H=Logic High=VIH,VID=12.0±0.5V,X=Don't Care, AIN=Address IN, DIN=Data IN, D
Notes:
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Prog ram Operations" for more information.
D
OUT
D
IN
=Data OUT
OUT
Table 2. AUTOSELECT CODES (High Voltage Method)
A5 A8 A14
Operation CE OE WE A0 A1 to A6 to A9 to A15~A21 Q15~Q0
A2 A7 A10
Read Silicon ID L L H L L X L X V Manufactures Code Read Silicon ID L L H H L X L X V Device Code Secured Silscon xx88h Sector Indicator L L H H H X L X V Bit(Q7) xx08h
X X00 C2 H
ID
X X 22FDH
ID
X X (factory locked)
ID
(non-factory locked)
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REQUIREMENTS FOR READING ARRAY DATA
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the po wer control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory contect occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The de vice remains enabled for read access until the command register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device the system must drive WE and CE to VIL, and OE to VIH.
An erase operation can erase the entire device. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing the entire chip.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal reqister (which is separate from the memory array) on Q15-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.
STANDBY MODE
MX26L3220 can be set into Standby mode with two dif­ferent approaches. One is using both CE and RESET pins and the other one is using RESET pin only .
When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±
0.3V . Under this condition, the current consumed is less than 50uA (typ.). If both of the CE and RESET are held at VIH, b ut not within the range of VCC ± 0.3V , the de vice will still be in the standby mode, but the standby currect will be larger. During Auto Algorithm operation, Vcc ac­tive current (Icc2) is required even CE = "H" until the operation is complated. The de vice can be read with stan­dard access time (tCE) from either of these standby modes.
When using only RESET, a CMOS standby mode is achieved with RESET input held at Vss ± 0.3V, Under this condition the current is consumed less than 50uA (typ.). Once the RESET pin is taken high,the device is back to active without recovery delay.
In the standby mode the outputs are in the high imped­ance state, independent of the OE input.
MX26L3220 is capable to provide the Automatic Standby Mode to restrain power consumption during read-out of data. This mode can be used eff ectively with an applica­tion requested low power consumption such as handy terminals.
To active this mode, MX26L3220 automatically switch themselves to low power mode when MX26L3220 ad­dresses remain stable during access time of tACC+30ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typi­cally 50uA (CMOS level).
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
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MX26L3220
RESET OPERATION
The RESET pin provides a hardware method of resetting the device to reading arra y data. When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pluse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitated once the device is ready to accept another command sequence, to ensure data integrity
Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater.
The RESET pin may be tied to system reset circuitry . A system reset would that also reset the MTP EPROM.
Refer to the AC Characteristics tables for RESET parameters and to Figure 14 for the timing diagram.
SILICON ID READ OPERATION
Table 3
VCC / VI/O Volta ge Range
Part No. VCC=2.7V to 3.6V VCC=2.7V to 3.6V
VI/O=2.7V to 3.6VVI/O=1.65V to 2.6V
MX26L3220-90 90ns 100ns MX26L3220-12 120ns 130ns
Notes: T ypical v alues measured at VCC=2.7V to 3.6V,
VI/O=2.7V to 3.6V
DATA PROTECTION
The MX26L3220 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi­tion. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe­cific command sequences. The device also incorporates several features to prevent inadvertent write cycles re­sulting from VCC power-up and po wer-down transition or system noise.
MTP EPROM are intended for use in applications where the local CPU alters memory contents. As such, manu­facturer and device codes must be accessible while the device resides in the target system. EPROM program­mers typically access signature codes by raising A9 to a high voltage. Howe ver , multiple xing high voltage onto address lines is not generally desired system design prac­tice.
MX26L3220 provides hardware method to access the silicon ID read operation. Which method requires VID on A9 pin, VIL on CE, OE, A6, and A1 pins. Which apply VIL on A0 pin, the device will output MXIC's manufac­ture code of C2H. Which apply VIH on A0 pin, the device will output MX26L3220 device code of 22FDH.
VI/O PIN OPERATION
MX26L3220 is capable to provide the I/O prower supply (VI/O) pin to control Input/Output voltage levels of the device. The data outputs and voltage tolerated at its data input is determined by the voltage on the VI/O pin. This device is allows to operate in 1.8V or 3V system as re­quired.
SECURED SILICON SECTOR
The MX26L3220 features a Flash memory region where the system may access through a command sequence to create a permant part identification as so called Elec­tronic Serial Number (ESN) in the device. Once this re­gion is programmed, any further modification on the re­gion is impossible. The secured silicon sector is a 512 words in length, and uses a Secured Silicon Sector Indi­cator Bit (Q7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the f actory. This bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. This ensures the security of the ESN once the prod­uct is shipped to the field.
The MX26L3220 offers the device with Secured Silicon Sector either factory locked or custor lockab le. The fac­tory-locked version is always protected when shipped from the factory , and has the Secured Silicon Sector Indicator Bit permanently set to a "1". The customer­lockable version is shipped with the Secured Silicon Sector unprotected, allowing customer to utilize that sec­tor in any form they prefer . The customer-lockab le ver-
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MX26L3220
sion has the secured sector Indicator Bit permanently set to a "0". Therefore, the Secured Silicon Sector Indi­cator Bit permanently set to a "0". Therefore, the Second Silicon Sector Indicator Bit prevents customer , loc kable device from being used to replace devices that are fac­tory locked.
The system access the Secured Silicon Sector through a command sequence (refer to "Enter Secured Silicon/ Exit Secured Silicon Sector command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the address normally occupied by the address 000000h-0001FFh. This mode of operation con­tinues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device rever ts to sending command to ad­dress 000000h-0001FFFh.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac­cept any write cycles. This protects dataduring VCC power-up and power-do wn. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater thanVLKO . The system must provide the proper signals to the control pins to prevent unintentional write when VCC is greater than VLK O.
FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory
In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. A f actory locked device has an 8-w ord random ESN at address 000000h-000007h.
CUSTOMER LOCKABLE:Secured Silicon Sector NOT Programmed or Protected At the Factory
As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 512-word Secured Silicon Sector. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.
The Secured Silicon Sector area can be protected using the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command sequence. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that method is only applicable to the Secured Silicon Sector.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a wr ite cycle CE and WE must be a logical zero while OE is a logical one.
POWER-UP SEQUENCE
The MX26L3220 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command se­quences.
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Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array .
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SOFTWARE COMMAND DEFINTIONS
MX26L3220
Device operations are selected by writing specific ad­dress and data sequences into the command register. Writing incorrect address and data values or writing them
All addresses are latched on the falling edge of WE or CE, whichever happens later . All data are latched on ris-
ing edge of WE or CE, whiche ver happens first. in the improper sequence will reset the device to the read mode. Table 4 defines the valid register command sequences. Either of the two reset command sequences will reset the device(when applicable).
TABLE4. MX26L3220 COMMAND DEFINITIONS
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read(Note 5) 1 RA RD Reset(Note 6) 1 XXX F0 Autoselect(Note 7) Manufacturer ID 4 555 AA 2AA 55 555 90 X00 C2 Device ID 4 555 AA 2AA 55 555 90 X01 22FD Secured Sector 4 555 AA 2AA 55 555 90 x03 see Factory Protect Note9 Enter Secured Silicon 3 555 AA 2AA 55 55 5 8 8 Sector Exit Secured Silicon 4 5 55 AA 2AA 55 5 55 9 0 xxx 0 0 Sector Porgram 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 55 5 8 0 55 5 AA 2AA 55 55 5 10
Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. P A=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
Notes:
1.See Table 1 for descriptions of bus operations.
2.All values are in hexadecimal.
3.Except when reading array or autoselect data, all bus cycles are write operation.
4.Address bits are don't care for unlock and command cycles , except when PA is required.
5.No unlock or command cycles required when device is in read mode.
6.The Reset command is required to return to the read mode when the device is in the autoselect mode or if Q5 goes high.
7.The fourth cycle of the autoselect command sequence is a read cycle.
8.Command is valid when device is ready to read array data or when device is in autoselect mode.
9.The data is 88h for factory locked and 48h for non-factory locked.
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MX26L3220
READING ARRAY DATA
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read arra y data after completing an Automatic Program or Automatic Erase algorithm.
The system must issue the reset command to re-en­able the device for reading array data if Q5 goes high, or while in the autoselect mode. See the "Reset Command" section, next.
RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command.
The reset command may be written between the se­quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the se­quence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins ,howe ver , the device ignores reset commands until the operation is complete.
The reset command may be written between the se­quence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command data.
must be written to return to reading array
ID READ mode, and the system may read at any address any number of times, without init iating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h re­turns the device code.
The system must write the reset command to exit the autoselect mode and return to reading array data.
WORD PROGRAM COMMAND SEQUENCE
The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 4 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6. See "Write Operation Status" for information on these status bits.
Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.
not required
If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data.
SILICON ID READ COMMAND SEQUENCE
The SILICON ID READ command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not. Table 4 shows the address and data requirements. This method is an alternative to that shown in Table 1, which is intended for EPROM programmers and requires VID on address bit A9.
The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by the SILICON ID READ command. The device then enters the SILICON
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Programming is allowed in any sequence. A bit cannot be programmed from a "0" back to a "1". Cause the Data Polling algorithm to indicate the operation w as successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
ACCELERATED PROGRAM OPERATIONS
The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically bypass the two "Unlock" write cycle. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH an y operation other than accelerated programming, or device damage may result.
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MX26L3220
SETUP AUTOMATIC CHIP ERASE
Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are f ollow ed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.
The MX26L3220 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology . The operation is initiated by writing the read silicon ID command sequence into the command register. F ollow­ing the command write, a read cycle with A6=VIL, A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A6=VIL, A1=VIL, A0=VIH returns the device code of 22FDH for MX26L3220.
AUTOMATIC CHIP ERASE COMMAND
The device does not require the system to preprogram prior to erase. The A utomatic Erase algorithm automati­cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system
TABLE 5. SILICON ID CODE
is not required to provide any controls or timings during these operations. Table 4 shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase op­eration by using Q7, Q6. See "Write Operation Status" for inf ormation on these status bits. When the Automatic Erase algorithm is complete, the device returns to read­ing array data and addresses are no longer latched.
Figure 5 illustrates the algorithm for the erase opera­tion.See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 4 for tim­ing diagrams.
Pins A 0 A1 A 6 Q15 Q7 Q6 Q 5 Q4 Q3 Q 2 Q1 Q0 Code(Hex)
| Q8
Manufacture code VIL VIL VIL 00H 1 1 0 0 001000C2H Device code for MX26L3220 VIH VIL VIL 22 H 1 1 1 1 110122FDH
WRITE OPERSTION STATUS
The device provides several bits to determine the sta­tus of a write operation: Q5, Q6, Q7. The following sub-
sections describe the functions of these bits. Q7, and Q6 each offer a method for determining whether a pro­gram or erase operation is complete or in progress. These three bits are discussed first.
Table 6. Write Operation Status
Status Q7 Q6 Q5
Note1
In Progress Word Program in Auto Program Algorithm Q7 Toggle 0
Auto Erase Algorithm 0 Toggle 0 Exceeded Word Program in Auto Program Algorithm Q7 Toggle 1 Time Limits Auto Erase Algorithm 0 Toggle 1
Notes:
1.Perf orming successive read operations from any address will cause Q6 to toggle .
P/N:PM0826
12
REV. 0.5, JAN. 29, 2002
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