MXIC MX23C1611PC-10, MX23C1611PC-12, MX23C1611MC-12, MX23C1611MC-10, MX23C1611TC-12 Datasheet
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MX23C1611
5 Volt 16-Mbit (2M x 8 / 1M x 16) Mask ROM with Page Mode
FEATURES
• Bit organization
- 2M x 8 (byte mode)
- 1M x 16 (word mode)
• Fast access time
- Random access: 100ns (max.)
- Page access: 50ns (max.)
• Page Size
- 8 double words per page
• Current
- Operating: 60mA
- Standby: 100uA
• Supply voltage
- 5V±10%
• Package
- 44 pin SOP (500mil)
- 42 pin PDIP (600mm)
- 48 pin TSOP (20mm x 12mm)
PIN CONFIGURATION
44 SOP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
MX23C1611
31
30
29
28
27
26
25
24
23
42 PDIP
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
A18
A17
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
ORDER INFORMATION
Part No. Access Page Access Package
Time Time
MX23C1611MC-10 100ns 50ns 44 pin SOP
MX23C1611MC-12 120ns 60ns 44 pin SOP
MX23C1611PC-10 100ns 50ns 42 pin PDIP
MX23C1611PC-12 120ns 60ns 42 pin PDIP
MX23C1611TC-10 100ns 50ns 48 pin TSOP
MX23C1611TC-12 120ns 60ns 48 pin TSOP
PIN DESCRIPTION
Symbol Pin Function
A0~A19 Address Inputs
D0~D14 Data Outputs
D15/A-1 D15 (Word Mode)/ LSB Address
A19
1
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
11
12
13
14
15
16
17
18
19
20
21
42
A8
41
A9
40
A10
39
A11
38
A12
37
A13
36
A14
35
A15
34
A16
33
BYTE
32
VSS
31
D15/A-1
30
MX23C1611
D7
29
D14
28
D6
27
D13
26
D5
25
D12
24
D4
23
VCC
22
CE Chip Enable Input
OE Output Enable Input
Byte Word/ Byte Mode Selection
VC C Po wer Supply Pin
VSS Ground Pin
N C No Connection
(Byte Mode)
MODE SELECTION
CE OE Byte D31/A-1 D0~D15 D16~D31 Mode Power
H X X X High Z High Z - Stand-by
L H X X High Z High Z - Active
L L H Output D0~D7 D8~D15 Word Active
L L L Input D0~D7 High Z Byte Active
P/N:PM0241 REV. 2.1, JUL. 18, 2001
1
48 TSOP (Normal Type)
MX23C1611
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
VSS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
BLOCK DIAGRAM
A0/(A-1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX23C1611
(Normal T ype)
48
VSS
47
VSS
46
D15/A-1
45
D7
44
D14
43
D6
42
D13
41
D5
40
D12
39
D4
38
VCC
37
VCC
36
NC
35
D11
34
D3
33
D10
32
D2
31
D9
30
D1
29
D8
28
D0
27
OE
26
VSS
25
VSS
A2
A3
Address
Buffer
Memory
Array
Page
Buffer
Page
Decoder
Word/
Byte
A19
CE
BYTE
OE
Note: Chip Enable active low input activates the chip's control logic, Address buffer and Page buffer.
Output
Buffer
D0
D15/(D7)
P/N:PM0241
REV. 2.1, JUL. 18, 2001
2
MX23C1611
ABSOLUTE MAXIMUM RATINGS
Item Symbol Ratings
V oltage on any Pin Relativ e to VSS VIN -1.3V to VCC+2.0V (Note)
Ambient Operating Temperature T opr -40°C to 85°C
Storage T emperature Tstg -65°C to 125°C
Note: Minimum DC v oltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5V±10%)
Item Symbol MIN. MAX. Conditions
Output High Voltage V OH 2.4V - IOH = -1.0mA
Output Low Voltage VOL - 0.4V IOL = 2.1mA
Input High Voltage VIH 2.2V VCC+0.3V
Input Low Voltage VIL -0.3V 0.2 x VCC
Input Leakage Current ILI - 5uA 0V, VCC
Output Leakage Current ILO - 5uA 0V , VCC
Operating Current ICC1 - 60mA tRC = 100ns, all output open
Standby Current (TTL) ISTB1 - 1mA CE = VIH
Standby Current (cmos) ISTB2 - 100uA CE>VCC-0.2V
Input Capacitance CIN - 10pF Ta = 25°C, f = 1MHZ
Output Capacitance COUT - 10pF Ta = 25°C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5V±10%)
Item Symbol 23C1611-10 23C1611-12
MIN. MAX. MIN. MAX.
Read Cycle Time tR C 100ns - 120ns Address Access Time tAA - 100ns - 120ns
Chip Enable Access Time tACE - 100ns - 120ns
Page Mode Access Time tP A - 50ns - 60ns
Output Enable Time tOE - 50ns - 60ns
Output Hold After Address tOH 10ns - 10ns Output High Z Delay tHZ - 20ns - 20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.
P/N:PM0241
3
REV. 2.1, JUL. 18, 2001
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