MSI MS-9826 Schematics rev.1.0

5

4

3

2

1

MSI

D D

CPU:

MS-9826
Ver:1.0

AMD M2 Athlon 64

System Chipset:

ATI RS690T
ATI SB600

On Board Chipset:

WINBOND Super I/O -- W83627DHG
LAN*2 -- MARVELL 88E8056

BIOS -- SPI ROM 8M

C C

Main Memory:

DDR * 2 (Max 2GB)

Expansion Slots:

PCI 2.2 Slot X 1

PWM:

Controller--Intersil ISL6312CR 3 Phase

B B

Clock Generator:

Controller--ICS951464AGLFT

Title Page

Cover Sheet 1
Block Diagram

SB600 GPIO Config

AMD M2 940
SYSTEM Memory
DDR Terminations

2
3
4,5,6
7
8

ATI RS690T 9-11

CLOCK Generator ICS 951464
ATI SB600
PCI-Express X 1,PCI SLOT1
LAN*2 MARVELL 88E8056

LPC SUPER I/O& COM PORT
FAN/KB&MS/GPIO

HD Audio - ALC888

USB connectors

TV-OUT & VGA Connector & LVDS
ATX Connector / Front Panel /EMI
MS-6 ACPI Controller & MS-6+
MS- 11 DDR2 1.8V POWER

PWM - ISL6312CR

RESERVE

MANUAL PARTS

RESERVE

12
13-16
17
18,19
20
21
22
23
24
25
26
27
28
29
30

31-33
34 GPIO&JUMPER/Option Part 34
POWER OK MAP
POWER MAP
RESET MAP
History

35

36

37

38

A A

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

5

4

3

2

http://www.msi.com.tw

Cover Sheet

Cover Sheet

Cover Sheet

1

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:

Monday, February 25, 2008

Monday, February 25, 2008

Monday, February 25, 2008

Sheet

Sheet

Sheet

Rev

Rev

Rev

0A

0A

0A

134

134

134

of

of

of

5

4

3

2

1

MS-9826

DDRII

EXTERNAL CLOCK GENERATOR

AMD
M2

ICS951464

D D

M2 SOCKET

OUT

IN

16x16

HyperTransport

400,533,667,800

128bit

DDRII
400,533,667,800

ECC UNBUFFERED
DDRII DIMM1

ECC UNBUFFERED
DDRII DIMM2

VGA PINHEAD

ATI NB - RS690T

HyperTransport LINK0 CPU I/F
INTEGRATED GRAPHICS
DDR2 MEMORY (X16)

VGA CONN

X1 PCIE INTERFACE

C C

Gb LAN
MARVELL
88E8056

Gb LAN
MARVELL
88E8056

CRT

LVDS/TVOUT/HDMI

1 X4 PCIE I/F WITH SB
3 X1 PCIE I/F

VER:A12

PCIE

X4

rear IO

USB#3

USB#1USB#2

USB#0

USB 2.0

pinhead

USB#5

USB#4

reserverd

SPI ROM

B B

SPI I/F

ATI SB - SB600

USB2.0 (10)
SATA II (2 PORTS)
AZALIA HD AUDIO
ATA 66/100/133
SPI I/F
LPC I/F
ACPI 1.1
INT RTC
HW MONITOR

SATA II I/F

ATA 66/100/133 I/F

SATA#0

IDE CONNECTOR

SATA#1

PCI/PCI BDGE

PCI SLOT

PCI BUS

VER:A21

Winbond LPC SIO W83627DHG

A A

PWM
SMART
FAN*2

5

4

KBD
MOUSE

COM
PORT
* 1

3

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

2

http://www.msi.com.tw

Block Diagram

Block Diagram

Block Diagram

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

Friday, January 25, 2008

Friday, January 25, 2008

Friday, January 25, 2008

2

2

2

Rev

Rev

Rev

0A

0A

0A

34

34

34

of

of

of

5

4

3

2

1

SB600 GPIO Config.

GPIO Pin

SSMUXSEL

ROM_CS#/
SPKR/

D D

FANOUT0/

SMARTVOLT/SATA_IS2#/

SHUTDOWN#/

GHI#

WD_PWRGD/
DDC1_SDA/
DDC1_SCL/
SATA_IS0#/

SPI_DO
SPI_DI
LAN_RST#
ROM_RST#
IDE_D[0..15]
SPI_HOLD#
SPI_CS#
INTE#

C C

INTF#
INTG#
INTH#
DPSLP_OD#
AC_BITCLK
AC_SDOUT
AC_SYNC
SPDIF_OUT
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
AC_RST#
AC_SDIN3
SPI_CLK

FANOUT1/

B B

FANOUT2/
FANIN0/
FANIN1/
FANIN2/
VIN[0..7]/
TEMPIN0/
TEMPIN1/
TEMPIN2/
TEMPIN3/TALERT#/
BMREQ#/REQ5#/
LLB#/

SATA_ACT#

LDRQ1#/GNT5#/
RTC_IRQ#/

REQ3#

A A

REQ4#
GNT3#
GNT4#

/SATA_IS3#/GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

/SATA_IS1#/GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

/GPIO11
/GPIO12

/GPIO13
/GPIO14

/GPIO[15..30]

/GPIO31

/GPIO32
/GPIO33
/GPIO34
/GPIO35
/GPIO36

/GPIO37
/GPIO38

/GPIO39

/GPIO40

/PCICLK7/GPIO41
/GPIO42
/GPIO43
/GPIO44

/GPIO45

/GPIO46

/GPIO47

GPIO48

GPIO49
GPIO50
GPIO51
GPIO52

GPIO[53..60]
GPIO61
GPIO62
GPIO63

GPIO64

GPIO65

GPIO66

/GPIO67

GPIO68

GPIO69

/GPIO70
/GPIO71
/GPIO72
/GPIO73

5

Type

I/OD(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/OD(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
OD(3.3V)
I/O(3.3V)

I/O(S5_3.3V)/VBAT

I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)

Default Power

Output(Low)
by Strapping
Input(TS)
Input(PU)
Input(TS)
Input(TS)
Output(TS)
by Strapping
Input(TS)
Input(TS)
Input(TS)
Output(PD)
Output(PD)

Standby

Standby
Output(Low)
Output(Low)
Output(High)
Input(PU)
Input(PU)

Standby

Standby
Input(PU)
Input(PU)
Input(PU)
Input(PU)
Input(TS)
Input(PD)
Output(Low)
Output(Low)
Output(Low)
Input(PD)
Input(PD)
Input(PD)
Output(Low)
Input(PD)
Input(PD)

Standby

Standby

Standby

Standby

Standby

Standby
Input(PU)
Input(PU)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(TS)
Input(PU)

Standby
Output(TS)
Input(PU)
Input(PU)

Standby
Input(PU)
Input(PU)
Output(TS)
Output(TS)

4

Main
Main
Main
Main
Main
Main
Main
Main
Main
Main
Main

Main
Main
Main

Main
Main
Main
Main
Main
Main
Main
Main
Main

Main
Main
Main
Main
Main
Main
Main
Main
Main
Main
Main

Main
Main

Main
Main
Main
Main

Function

NC
NC
NC
NC
NC
NC
NC
NC

AUXGPIO_DIR2
IDE Detect
AUXGPIO_DIR1

SPI_DO
SPI_DI

NC
NC

IDE_D[0..15]

SPI_HOLD#
SPI_CS#

INTE#
INTF#
INTG#
INTH#

NC
NC

PIN Straps

NC
NC

NC

NC
NC
NC

GPIO46
SPI_CLK

AMP_GAIN0
AMP_GAIN0
AMP_EN

NC
NC
NC
NC
NC
NC

TALERT#

BMREQ#

NC

SATA_ACT#

(Program to Output)
(Program to Output)

(Program to Output)
(Program to Output)
(Program to Output)
(Program to Output)
(Program to Output)
(Program to Output)

(Not Default)

(Not Default)

NC
NC
NC
NC
NC
NC

(Not Default)

(Not Default)

(Not Default)

SB600 GPM Config.

GPM Pin Type Function

USB_OC0#/
USB_OC1#/
USB_OC2#/
USB_OC3#/
USB_OC4#/
USB_OC5#/DDR3_RST#/
BLINK/
SYS_RESET#/
USB_OC8#/AZ_DOCK_RST#/
USB_OC9#/SLP_S2#/

GPM#0
GPM#1
GPM#2
GPM#3
GPM#4

GPM#5

GPM#6

GPM#7

GPM#9

GPM#8

I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O/OD(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

SB600 GPOC Config.

GPOC Pin Type Function

SCL0/
SDA0/
SCL1/
SDA1/

GPOC0#
GPOC1#
GPOC2#
GPOC3#

I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

Default

Input(TS)
Input(TS)
Input(TS)
Input(TS)

SB600 EXTEVENT & GEVENT Config.

RI#/
LPC_SMI#/
SMBALERT#/ /GEVENT2#
LPC_PME#/
PCI_PME#/
S3_STATE/
USB_OC6#/
USB_OC7#/
WAKE#/

EXTEVENT1#

THRMTRIP#
GEVENT3#
GEVENT4#

GEVENT5#

GEVENT6#
GEVENT7#

GEVENT8#

GPM Pin Type Function

EXTEVENT0#

I/O(S5_3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

Default

Input(PU)
Input(PU)
Input(PU)
Input(PU)
Input(PU)
by Strapping
Input(PU)
Input(PU)
Input(PU)

PCI Config.

IEEE 1394

GIGA LAN

PCI1

PCI2

Super I/O

3

CLOCK

REQ# GNT# INTA# INTB# INTC# INTD#

IDSEL

2

Default Power

Input(PU)
Input(PU)
Input(PU)
Input(PU)
Output(Low)
Input(PU)
Input(PU)
Input(PU)
Input(PU)
Input(PD)

Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby

Power

Main

Main
Standby
Standby

Standby
Main
Standby
Standby
Standby
Standby
Standby
Standby
Standby

USB OverCurrent for PORT0,1,2,3
USB OverCurrent for PORT0,1,2,3
USB OverCurrent for PORT0,1,2,3
USB OverCurrent for PORT0,1,2,3

USB OverCurrent for PORT4,5
USB OverCurrent for PORT4,5

GPM6#

SYS_RESET#

NC
NC

SMBUS1
SMBUS1
SMBUS2
SMBUS2

(Not Default)
(Not Default)
(Not Default)
(Not Default)

Power

NC
NC

THRMTRIP#
LPC_PME#
PCI_PME#

NC
NC
NC

PCIE_WAKE#

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

GPIO

GPIO

GPIO

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

(Not Default)

(Reserved)
(Not Default)
(Not Default)

(Not Default)

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:

Monday, December 24, 2007

Monday, December 24, 2007

Monday, December 24, 2007

Sheet

Sheet

Sheet

334

334

1

334

Rev

Rev

Rev

0A

0A

0A

of

of

of

5

4

3

2

1

VCC_1V2

C247

C247

X_C180P50N0402

X_C180P50N0402

CLOSE TO VLDT PIN

HT_CLKOUT_H1 9
HT_CLKOUT_L1 9
HT_CLKOUT_H0 9
HT_CLKOUT_L0 9

HT_CTLOUT_H0 9
HT_CTLOUT_L0 9

HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3HT_CADIN_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

OE

OE

1

A

A

2

GND

GND

3

SN74LVC1G17

SN74LVC1G17

4

C221

C221

X_C180P50N0402

X_C180P50N0402

TP26TP26
TP27TP27

U25

U25

VCC

VCC

5

Y

Y

4

C222

C222
C180P50N0402

C180P50N0402

CPU_CLK12

CPU_CLK#12

VCC_DDR

R142

R142
X_300/4

X_300/4

CPU_SIC13

CPU_SID13

VCC_DDR

R153

R153

39.2R1%0402

39.2R1%0402

R137

R137

39.2R1%0402

39.2R1%0402

R180,R170 TO CPU LESS THAN 1000MIL

+1.8V_S0

CPU_LDTSTOP#

LDT_RST#
LDT_PWRGD

C141

C141

C3900P25X

C3900P25X

C140

C140

C3900P25X

C3900P25X

M_ZN
M_ZP

R126 680R126 680
R128 680R128 680

R141

R141
300/4

300/4

R93

R93
169R1%0402

169R1%0402

LDT_PWRGD13

THERMDC_CPU20
THERMDA_CPU20

3

C4.7U10Y0805

C4.7U10Y0805

C139

C139

CPUCLKIN
CPUCLKIN#

LDT_RST#13

C204

C204

X_1000P/50V/X7R/4

X_1000P/50V/X7R/4

TP17TP17
TP20TP20
TP23TP23
TP16TP16

TP10TP10

COREFB+27

COREFB-27

TP34TP34

CPU_M_VREF

TP5TP5
TP6TP6
TP7TP7
TP8TP8
TP24TP24

at least 15mil

C143

C143

0.22u_10V_0402

0.22u_10V_0402

LDT_PWRGD
CPU_LDTSTOP#
LDT_RST#

CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS

CPU_DBREQ_L
COREFB+

COREFB­CPU_VTT_SENSE

CPU_TEST25_H

CPU_TEST25_L

R91 300/4R91 300/4
R90 300/4R90 300/4

300mA

C142

C142

3300P/50V/4

3300P/50V/4

CPU_PRESENT_L

VDDA25

AK6

AL10
AJ10

AH10

AH11

AJ11

AH9

AG9
AG8
AH7

C10
D10

A8
B8

C9
D8
C7

AL3

AL6

AL9

A5
G2

G1

E12

F12

A10
B10
F10

E9

AJ7

F6
D6

E7
F8
C5

E5

AJ5

AJ6

CPU1D

CPU1D

VDDA1
VDDA2

CLKIN_H
CLKIN_L

PWROK
LDTSTOP_L
RESET_L

CPU_PRESENT_L

SIC
SID

TDI
TRST_L
TCK
TMS

DBREQ_L
VDD_FB_H

VDD_FB_L
VTT_SENSE

M_VREF
M_ZN
M_ZP

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9

TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
TEST5
TEST4
TEST3
TEST2

ZIF-SOCKET940

ZIF-SOCKET940

MISC

MISC

THERMTRIP_L

PROCHOT_L

DBRDY

VDDIO_FB_H

VDDIO_FB_L

HTREF1
HTREF0

TEST29_H

TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

2

VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)

TDO

PSI_L

80S/0805L880S/0805

2 1

D2
D1
C1
E3
E2
E1

AK7
AL7

AK10

B6
AK11

AL11
F1

V8
V7

C11
D11

AK8
AH8
AJ9
AL8
AJ8

J10
H9
AK9
AK5
G7
D4

VCC_DDR

R82

R82

16.9 1%

16.9 1%

VDDA25VDDA_25

L8

Required for compatibility
with future processors

VID5
VID4
VID3
VID2
VID1
VID0

CPU_THRIP_L#
PROCHOT_L

CPU_TDO

CPU_DBRDY
CPU_VDDIOFB_H

CPU_VDDIOFB_L

CPU_PSI_L

HTREF1
HTREF0

TEST29H

TEST29L

R140 300/4R140 300/4

R83

R83

16.9 1%

16.9 1%

C118

C118

0.1u/10V/4

0.1u/10V/4

VCC_DDR

TP19TP19

TP11TP11

TP9TP9

VCC_DDR

CPU_M_VREF

R89

R89
300/4

300/4

From SIO for System-Initiated throttling

R138

R138

VCC_DDR

300/4

300/4

C212

C212

1000P/50V/X7R/4

1000P/50V/X7R/4

R92

R92

80.6R1%0402

80.6R1%0402

TEST29_L and TEST29_H should be routed as
a differential pair with 80 Ohm impedance

TP21TP21
TP25TP25
TP18TP18

TP22TP22

R145

R145
300/4

300/4

CPU_PRESENT_L
CPU_TEST25_H

CPU_TEST25_L

C117

C117
1000P/50V/X7R/4

1000P/50V/X7R/4

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

M2 HT I/F CTRL & DEBUG

M2 HT I/F CTRL & DEBUG

M2 HT I/F CTRL & DEBUG

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

VCC_DDRVCC_DDR

R152

R152

R143

R143
300/4

300/4

4.7K/4

4.7K/4

Q20 N-MMBT3904_NL_SOT23Q20 N-MMBT3904_NL_SOT23

PROCHOT_L 20

R131 44.2KR1%0402R131 44.2KR1%0402

R129 44.2KR1%0402R129 44.2KR1%0402

C207

C207

1000P/50V/X7R/4

1000P/50V/X7R/4

R139 1K/4 1%R139 1K/4 1%
R88 510RR88 510R

R87 510RR87 510R

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

VID[0..5] 27

VCC_DDR

CPU_THRIP# 14

VCC_1V2

VCC_DDR

Friday, February 22, 2008

Friday, February 22, 2008

Friday, February 22, 2008

of

of

of

434

434

434

R144

R144
300/4

300/4

Rev

Rev

Rev

0A

0A

0A

C219

C219

C4.7U10Y0805

C4.7U10Y0805

0.22u_10V_0402

0.22u_10V_0402

CPU1A

CPU1A

HYPERTRANSPORT

HYPERTRANSPORT

680

680
R309

R309

HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]

C248

C248

C220

C220

0.22u_10V_0402

0.22u_10V_0402

L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)

L0_CTLOUT_H(1)

L0_CTLOUT_L(1)

L0_CTLOUT_H(0)

L0_CTLOUT_L(0)

L0_CADOUT_H(15)

L0_CADOUT_L(15)

L0_CADOUT_H(14)

L0_CADOUT_L(14)

L0_CADOUT_H(13)

L0_CADOUT_L(13)

L0_CADOUT_H(12)

L0_CADOUT_L(12)

L0_CADOUT_H(11)

L0_CADOUT_L(11)

L0_CADOUT_H(10)

L0_CADOUT_L(10)

L0_CADOUT_H(9)

L0_CADOUT_L(9)

L0_CADOUT_H(8)

L0_CADOUT_L(8)

L0_CADOUT_H(7)

L0_CADOUT_L(7)

L0_CADOUT_H(6)

L0_CADOUT_L(6)

L0_CADOUT_H(5)

L0_CADOUT_L(5)

L0_CADOUT_H(4)

L0_CADOUT_L(4)

L0_CADOUT_H(3)

L0_CADOUT_L(3)

L0_CADOUT_H(2)

L0_CADOUT_L(2)

L0_CADOUT_H(1)

L0_CADOUT_L(1)

L0_CADOUT_H(0)

L0_CADOUT_L(0)

3

2

1

D6
BAT54S9D6BAT54S9

R307 8.87K/4R307 8.87K/4

C245

C245
C180P50N0402

C180P50N0402

C467

C467
47p

47p

AD5
AD4
AD1
AC1

Y6
W6
W2
W3

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4

Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

C246

C246

X_C180P50N0402

X_C180P50N0402

HT_CADIN_H[15..0]9

HT_CADIN_L[15..0]9

HT_CADOUT_H[15..0]9

HT_CADOUT_L[15..0]9

D D

VCC_1V2

C251

C251

C4.7U10Y0805

C4.7U10Y0805

HT_CLKIN_H19

HT_CLKIN_L19

VCC_1V2

C C

B B

A A

HT_CLKIN_H09

HT_CLKIN_L09

R125 51R1%0402R125 51R1%0402
R127 51R1%0402R127 51R1%0402

HT_CTLIN_H09

HT_CTLIN_L09

HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8

HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3

HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0

N6

L0_CLKIN_H(1)

P6

L0_CLKIN_L(1)

N3

L0_CLKIN_H(0)

N2

L0_CLKIN_L(0)

V4

L0_CTLIN_H(1)

V5

L0_CTLIN_L(1)

U1

L0_CTLIN_H(0)

V1

L0_CTLIN_L(0)

U6

L0_CADIN_H(15)

V6

L0_CADIN_L(15)

T4

L0_CADIN_H(14)

T5

L0_CADIN_L(14)

R6

L0_CADIN_H(13)

T6

L0_CADIN_L(13)

P4

L0_CADIN_H(12)

P5

L0_CADIN_L(12)

M4

L0_CADIN_H(11)

M5

L0_CADIN_L(11)

L6

L0_CADIN_H(10)

M6

L0_CADIN_L(10)

K4

L0_CADIN_H(9)

K5

L0_CADIN_L(9)

J6

L0_CADIN_H(8)

K6

L0_CADIN_L(8)

U3

L0_CADIN_H(7)

U2

L0_CADIN_L(7)

R1

L0_CADIN_H(6)

T1

L0_CADIN_L(6)

R3

L0_CADIN_H(5)

R2

L0_CADIN_L(5)

N1

L0_CADIN_H(4)

P1

L0_CADIN_L(4)

L1

L0_CADIN_H(3)

M1

L0_CADIN_L(3)

L3

L0_CADIN_H(2)

L2

L0_CADIN_L(2)

J1

L0_CADIN_H(1)

K1

L0_CADIN_L(1)

J3

L0_CADIN_H(0)

J2

L0_CADIN_L(0)

ZIF-SOCKET940

ZIF-SOCKET940

LDT_STOP#10,13

LDT_STOP#

5

5

4

3

2

1

MEM_MA_DQS_L[8..0]7

MEM_MA_DQS_H[8..0]7

MEM_MA_DM[8..0]7

D D

CPU1B

CPU1B

MEMORY INTERFACE A

MEM_MA0_CLK_H27,8
MEM_MA0_CLK_L27,8
MEM_MA0_CLK_H17,8

MEM_MA0_CLK_H07,8
MEM_MA0_CLK_L07,8

MEM_MA0_CLK_L17,8

MEM_MA0_CS_L17,8
MEM_MA0_CS_L07,8

MEM_MA0_ODT07,8

MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0

MEM_MA0_CS_L1
MEM_MA0_CS_L0

MEM_MA0_ODT0

remove MEM_MA1_CS_L0,L1, MA1_ODT0,MA_CKE1

C C

MEM_MA_ADD[15..0]7,8

B B

A A

MEM_MA_CAS_L7,8
MEM_MA_WE_L7,8
MEM_MA_RAS_L7,8

MEM_MA_BANK27,8
MEM_MA_BANK17,8
MEM_MA_BANK07,8

MEM_MA_CKE07,8

5

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CKE0
MEM_MA_ADD15

MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0

AG21
AG20

AC25
AA24

AC28
AE20

AE19

AD27
AA25

AC27

AB25
AB27
AA26

AA27

AC26

AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28

AF15
AF19

AJ25

AH29

G19
H19
U27
U26

G20
G21
V27
W27

N25
Y27

M25
M27

N24
N26

P25
Y25
N27
R24
P27
R25
R26
R27

U25
W24

D29
C29
C25
D25
E19

G15

B29
E24
E18
H15

L27

T25
T27

F19
F15

MEMORY INTERFACE A

MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)

MA0_CS_L(1)
MA0_CS_L(0)

MA0_ODT(0)
MA1_CLK_H(2)

MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)

MA1_CS_L(1)
MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L
MA_WE_L
MA_RAS_L

MA_BANK(2)
MA_BANK(1)
MA_BANK(0)

MA_CKE(1)
MA_CKE(0)

MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)

MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)

MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)

ZIF-SOCKET940

ZIF-SOCKET940

MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)

MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)

4

MEM_MA_DATA63

AE14

MEM_MA_DATA62

AG14

MEM_MA_DATA61

AG16

MEM_MA_DATA60

AD17

MEM_MA_DATA59

AD13

MEM_MA_DATA58

AE13

MEM_MA_DATA57

AG15

MEM_MA_DATA56

AE16

MEM_MA_DATA55

AG17

MEM_MA_DATA54

AE18

MEM_MA_DATA53

AD21

MEM_MA_DATA52

AG22

MEM_MA_DATA51

AE17

MEM_MA_DATA50

AF17

MEM_MA_DATA49

AF21

MEM_MA_DATA48

AE21

MEM_MA_DATA47

AF23

MEM_MA_DATA46

AE23

MEM_MA_DATA45

AJ26

MEM_MA_DATA44

AG26

MEM_MA_DATA43

AE22

MEM_MA_DATA42

AG23

MEM_MA_DATA41

AH25

MEM_MA_DATA40

AF25

MEM_MA_DATA39

AJ28

MEM_MA_DATA38

AJ29

MEM_MA_DATA37

AF29

MEM_MA_DATA36

AE26

MEM_MA_DATA35

AJ27

MEM_MA_DATA34

AH27

MEM_MA_DATA33

AG29

MEM_MA_DATA32

AF27

MEM_MA_DATA31

E29

MEM_MA_DATA30

E28

MEM_MA_DATA29

D27

MEM_MA_DATA28

C27

MEM_MA_DATA27

G26

MEM_MA_DATA26

F27

MEM_MA_DATA25

C28

MEM_MA_DATA24

E27

MEM_MA_DATA23

F25

MEM_MA_DATA22

E25

MEM_MA_DATA21

E23

MEM_MA_DATA20

D23

MEM_MA_DATA19

E26

MEM_MA_DATA18

C26

MEM_MA_DATA17

G23

MEM_MA_DATA16

F23

MEM_MA_DATA15

E22

MEM_MA_DATA14

E21

MEM_MA_DATA13

F17

MEM_MA_DATA12

G17

MEM_MA_DATA11

G22

MEM_MA_DATA10

F21

MEM_MA_DATA9

G18

MEM_MA_DATA8

E17

MEM_MA_DATA7

G16

MEM_MA_DATA6

E15

MEM_MA_DATA5

G13

MEM_MA_DATA4

H13

MEM_MA_DATA3

H17

MEM_MA_DATA2

E16

MEM_MA_DATA1

E14

MEM_MA_DATA0

G14

MEM_MA_DQS_H8

J28

MEM_MA_DQS_L8

J27

MEM_MA_DM8

J25

DDRA_CB7

K25

DDRA_CB6

J26

DDRA_CB5

G28

DDRA_CB4

G27

DDRA_CB3

L24

DDRA_CB2

K27

DDRA_CB1

H29

DDRA_CB0

H27

DDRA_CB[7:0] 7

MEM_MA_DATA[63..0] 7

MEM_MB0_CLK_H07,8
MEM_MB0_CLK_L07,8

remove MEM_MB1_CS_L0,L1,MB1_ODT0,MB_CKE1

MEM_MB_ADD[15..0]7,8

3

MEM_MB_DQS_L[8..0]7

MEM_MB_DQS_H[8..0]7

MEM_MB_DM[8..0]7

CPU1C

CPU1C

MEMORY INTERFACE B

MEM_MB0_CLK_H27,8
MEM_MB0_CLK_L27,8
MEM_MB0_CLK_H17,8
MEM_MB0_CLK_L17,8

MEM_MB0_CS_L17,8
MEM_MB0_CS_L07,8

MEM_MB0_ODT07,8

MEM_MB_CAS_L7,8
MEM_MB_WE_L7,8
MEM_MB_RAS_L7,8

MEM_MB_BANK27,8
MEM_MB_BANK17,8
MEM_MB_BANK07,8

MEM_MB_CKE07,8

MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0

MEM_MB0_CS_L1
MEM_MB0_CS_L0

MEM_MB0_ODT0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CKE0
MEM_MB_ADD15

MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0

AJ19
AK19

AE30
AC31

AD29
AL19

AL18

W29
W28

AE29
AB31

AD31

AC29
AC30
AB29

AA31
AA28

M31
M29

AE31

AA29

AA30
AK13

AJ13
AK17
AJ17
AK23
AL23
AL28
AL29

AJ14
AH17
AJ23
AK29

A18
A19
U31
U30

C19
D19

N31

N28
N29

N30
P29

P31
R29
R28
R31
R30
T31
T29
U29
U28

D31
C31
C24
C23
D17
C17
C14
C13

C30
A23
B17
B13

MEMORY INTERFACE B

MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)

MB0_CS_L(1)
MB0_CS_L(0)

MB0_ODT(0)
MB1_CLK_H(2)

MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)

MB1_CS_L(1)
MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L
MB_WE_L
MB_RAS_L

MB_BANK(2)
MB_BANK(1)
MB_BANK(0)

MB_CKE(1)
MB_CKE(0)

MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)

MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)

MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)

ZIF-SOCKET940

ZIF-SOCKET940

2

MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)

MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)

AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13

MEM_MB_DQS_H8

J31

MEM_MB_DQS_L8

J30

MEM_MB_DM8

J29
K29

K31
G30
G29
L29
L28
H31
G31

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20

MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10

MEM_MB_DATA9

MEM_MB_DATA8

MEM_MB_DATA7

MEM_MB_DATA6

MEM_MB_DATA5

MEM_MB_DATA4

MEM_MB_DATA3

MEM_MB_DATA2

MEM_MB_DATA1

MEM_MB_DATA0

DDRB_CB7

DDRB_CB6

DDRB_CB5

DDRB_CB4

DDRB_CB3

DDRB_CB2

DDRB_CB1

DDRB_CB0

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

M2 DDR MEMORY I/F

M2 DDR MEMORY I/F

M2 DDR MEMORY I/F

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

DDRB_CB[7:0] 7

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

MEM_MB_DATA[63..0] 7

Friday, February 22, 2008

Friday, February 22, 2008

Friday, February 22, 2008

of

of

of

534

534

534

Rev

Rev

Rev

0A

0A

0A

5

VCCP

CPU1F

CPU1F

VDD1

VDD1

A4

VDD1

A6

VDD2

AA8

VDD3

AA10

VDD4

AA12

VDD5

AA14

VDD6

AA16

VDD7

AA18

VDD8

AB7

VDD9

D D

C C

B B

AB11

AC10

AE10

AB9
AC4

AC5
AC8

AD2
AD3
AD7
AD9

AF7
AF9
AG4
AG5
AG7
AH2
AH3

E10

G10
G12

H11
H23

K11
K13
K15
K17
K19
K21
K23

Y17
Y19

B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8

F5
F7
F9

F11

G6
G8

H7

J8
J12
J14
J16
J18
J20
J22
J24

K7
K9

L4
L5

L8
L10
L12

VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151

ZIF-SOCKET940

ZIF-SOCKET940

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

VSS240
VSS241

A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16

VCCP

L14

VDD1

L16

VDD2

L18

VDD3

M2

VDD4

M3

VDD5

M7

VDD6

M9

VDD7

M11

VDD8

M13

VDD9

M15

VDD10

M17

VDD11

M19

VDD12

N8

VDD13

N10

VDD14

N12

VDD15

N14

VDD16

N16

VDD17

N18

VDD18

P7

VDD19

P9

VDD20

P11

VDD21

P13

VDD22

P15

VDD23

P17

VDD24

P19

VDD25

R4

VDD26

R5

VDD27

R8

VDD28

R10

VDD29

R12

VDD30

R14

VDD31

R16

VDD32

R18

VDD33

R20

VDD34

T2

VDD35

T3

VDD36

T7

VDD37

T9

VDD38

T11

VDD39

T13

VDD40

T15

VDD41

T17

VDD42

T19

VDD43

T21

VDD44

U8

VDD45

U10

VDD46

U12

VDD47

U14

VDD48

U16

VDD49

U18

VDD50

U20

VDD51

V9

VDD52

V11

VDD53

V13

VDD54

V15

VDD55

V17

VDD56

V19

VDD57

V21

VDD58

W4

VDD59

W5

VDD60

W8

VDD61

W10

VDD62

W12

VDD63

W14

VDD64

W16

VDD65

W18

VDD66

W20

VDD67

Y2

VDD68

Y3

VDD69

Y7

VDD70

Y9

VDD71

Y11

VDD72

Y13

VDD73

Y15

VDD74

Y21

VDD75

ZIF-SOCKET940

ZIF-SOCKET940

VDD2

VDD2

CPU1G

CPU1G

4

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75

AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18

0.8375~1.6V / 65A

VCCP

AA20

VDD1

AA22

VDD2

AB13

VDD3

AB15

VDD4

AB17

VDD5

AB19

VDD6

AB21

VDD7

AB23

VDD8

AC12

VDD9

AC14

VDD10

AC16

VDD11

AC18

VDD12

AC20

VDD13

AC22

VDD14

AD11

VDD15

AD23

VDD16

AE12

VDD17

AF11

VDD18

L20

VDD19

L22

VDD20

M21

VDD21

M23

VDD22

N20

VDD23

N22

VDD24

P21

VDD25

P23

VDD26

R22

VDD27

T23

VDD28

U22

VDD29

V23

VDD30

W22

VDD31

Y23

VDD32

5

NC1

6

NC2

7

NC3

8

NC4

1

GND

2

GND

3

GND

ZIF-SOCKET940

ZIF-SOCKET940

CPU1H

CPU1H

VDD3

VDD3

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VCCP

22u_6V_0805

22u_6V_0805

C423

C423

N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22

3

22u_6V_0805

22u_6V_0805

C443

C443

500mA

VCC_DDR

0.22u_10V_0402

0.22u_10V_0402

22u_6V_0805

22u_6V_0805

C408

C408

1.75A

VCC_1V2

VTT_DDR

3.6A

VCCP

C468

C468

22u_6V_0805

22u_6V_0805

C407

C407

0.22u_10V_0402

0.22u_10V_0402

22u_6V_0805

22u_6V_0805

C431

C431

AJ4
AJ3
AJ2
AJ1

D12
C12
B12
A12

AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30

M24
M26
M28
M30
P24
P26
P28
P30

T24
T26
T28

T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29

ZIF-SOCKET940

ZIF-SOCKET940

C466

C466

0.22u_10V_0402

0.22u_10V_0402

22u_6V_0805

22u_6V_0805

C424

C424

VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4

VTT1
VTT2
VTT3
VTT4

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29

C451

C451

CPU1I

CPU1I

VDDIO

VDDIO

22u_6V_0805

22u_6V_0805

VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4

H6
H5
H2
H1

AK12

VTT5

AJ12

VTT6

AH12

VTT7

AG12

VTT8

AL12

VTT9

K24

VSS1

K26

VSS2

K28

VSS3

K30

VSS4

L7

VSS5

L9

VSS6

L11

VSS7

L13

VSS8

L15

VSS9

L17

VSS10

L19

VSS11

L21

VSS12

L23

VSS13

M8

VSS14

M10

VSS15

M12

VSS16

M14

VSS17

M16

VSS18

M18

VSS19

M20

VSS20

M22

VSS21

N4

VSS22

N5

VSS23

N7

VSS24

N9

VSS25

N11

VSS26

N13

VSS27

N15

VSS28

C445

C445

0.01u_16V_0402

0.01u_16V_0402

22u_6V_0805

22u_6V_0805

C458

C458

2

VLDT_RUN_B

VTT_DDR

C398

C398
180P

180P

C432

C432

C4.7U10Y0805

C4.7U10Y0805

22u_6V_0805

22u_6V_0805

C456

C456

C138

C138

22u_6V_0805

22u_6V_0805

C400

C400

22u_6V_0805

22u_6V_0805

C444

C444

22u_6V_0805

22u_6V_0805

C402

C402

22u_6V_0805

22u_6V_0805

C409

C409

1

22u_6V_0805

22u_6V_0805

C401

C401

22u_6V_0805

22u_6V_0805

C461

C461

180p 0402 X41000p 0402 X40.22u 0402 X4 4.7u 0805 X4

VTT_DDR

C144

C144

C145

180p

180p

C242

C242

C145

180p

180p

C241

C241

180p

180p

4

C124

C127

C127

C258

C258

0.22u

0.22u

0.22u_10V_0402

0.22u_10V_0402

A A

VTT_DDR

C133

C133

0.22u_10V_0402

0.22u_10V_0402

C263

C263

0.22u

0.22u

C259

C259
C4.7U10Y0805

C4.7U10Y0805

C4.7U10Y0805

C4.7U10Y0805

C260

C260
C4.7U10Y0805

C4.7U10Y0805

C4.7U10Y0805

C4.7U10Y0805

5

C124

C125

C125

1000P

1000P

C126

C126
1000P

1000P

C134

C134

C257

C257

1000P

1000P

C264

C264
1000P

1000P

180p

180p

between CPU and DIMM

CPU Bottom

22u_6V_0805

22u_6V_0805

180p

180p

C470

C470

C426

C426

0.22u_10V_0402

0.22u_10V_0402

VCC_DDR

C433

C433

22u_6V_0805

22u_6V_0805

C452

C452

3

C410

C410

180p

180p

22u_6V_0805

22u_6V_0805

C427

C427

0.22u_10V_0402

0.22u_10V_0402
C460

C460

0.22u_10V_0402

0.22u_10V_0402
C421

C421

VCC_DDRVCC_DDR

C4.7U10Y0805

C4.7U10Y0805

0.01u_16V_0402

0.01u_16V_0402

C459

C459

C465

C465
180P

180P

C430

C430

C403

C403

C4.7U10Y0805

C4.7U10Y0805

C406

C406
180p

180p

C475

C475

C4.7U10Y0805

C4.7U10Y0805

C447

C447

2

C4.7U10Y0805

C4.7U10Y0805

VCC_DDR

C453

C453

0.22u

0.22u

C405

C405
180p

180p

C439

C439

0.22u

0.22u

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

AM2 PWR & GND

AM2 PWR & GND

AM2 PWR & GND

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

C471

C471
180p

180p

MS-9826

MS-9826

MS-9826

1

Last Revision Date:

Last Revision Date:

Last Revision Date:

Thursday, February 21, 2008

Thursday, February 21, 2008

Thursday, February 21, 2008

Sheet

Sheet

Sheet

634

634

634

Rev

Rev

Rev

0A

0A

0A

of

of

of

A

B

C

D

E

DDRB_CB5

DDRB_CB6

162

167

CB5

CB6

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

A10_AP

A16/BA2

CAS#
RAS#

ODT0
ODT1

CKE0
CKE1

CS0#
CS1#

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

VREF

VSS

VSS

VSS

234

237

DDRB_CB7

168

CB7

7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45

188

A0

183

A1

63

A2

182

A3

61

A4

60

A5

180

A6

58

A7

179

A8

177

A9

70
57

A11

176

A12

196

A13

174

A14

173

A15

54
190

BA1

71

BA0

73

WE#

74
192

125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165

195
77

52
171

193
76

185
186
137
138
220
221

120

SCL

119

SDA

1

239

SA0

240

SA1

101

SA2

DDRII-240_blue

DDRII-240_blue

MEM_MB_DQS_L[8..0]5

MEM_MB_DQS_H[8..0]5

MEM_MB_DM[8..0]5

MEM_MB_ADD[15..0]5,8

MEM_MB_BANK[2..0]5,8

MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H8
MEM_MB_DQS_L8

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MB_RAS_L

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8

MEM_MB0_ODT0

MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2

SCL
SDA

VCC3

PLACE CLOSE TO DIMM PIN

ADDRESS: 001
0xA2

DIMM_VREF_B

DDRB_CB[7:0] 5DDRA_CB[7:0] 5

IN
IN
IN

MEM_MB0_ODT0 5,8

MEM_MB_CKE0 5,8

MEM_MB0_CS_L0 5,8
MEM_MB0_CS_L1 5,8

MEM_MB0_CLK_H0 5,8
MEM_MB0_CLK_L0 5,8
MEM_MB0_CLK_H1 5,8
MEM_MB0_CLK_L1 5,8
MEM_MB0_CLK_H2 5,8
MEM_MB0_CLK_L2 5,8

C45

C45
C0.1U10X0402

C0.1U10X0402

MEM_MB_WE_L 5,8
MEM_MB_CAS_L 5,8
MEM_MB_RAS_L 5,8

194

181

VDD6

VSS

139

142

175

170

VDD7

VDD8

VDDQ0

VSS

VSS

VSS

145

148

151

MEM_MB_DATA[63..0] 5

197

172

187

VDDQ153VDDQ259VDDQ364VDDQ4

VDDQ5

VDDQ469VDDQ7

VSS

VSS

VSS

VSS

VSS

VSS

154

157

160

163

166

169

VDDQ6

VSS

184

198

178

VDDQ7

VSS

201

DDRB_CB0

DDRB_CB1

DDRB_CB2

DDRB_CB3

DDRB_CB4

161

238

189

67

CB042CB143CB248CB349CB4

VDDQ8

VDDQ9

VDDSPD

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

CK1#(CK0#)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

204

207

210

213

216

219

222

225

228

231

MEM_MA_DATA[63..0] 5

MEM_MA_BANK[2..0]5,8

DDRA_CB5

DDRA_CB6

162

CB5
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#

A10_AP

A16/BA2

CK0(DU)

CK2(DU)

VSS

234

167

CB6

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

WE#
CAS#
RAS#

ODT0
ODT1

CKE0
CKE1

CS0#

CS1#

VREF

VSS

237

DDRA_CB7

168

CB7

7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45

188

A0

183

A1

63

A2

182

A3

61

A4

60

A5

180

A6

58

A7

179

A8

177

A9

70
57

A11

176

A12

196

A13

174

A14

173

A15

54
190

BA1

71

BA0

73
74
192

125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165

195
77

52
171

193
76

185
186
137
138
220
221

120

SCL

119

SDA

1

239

SA0

240

SA1

101

SA2

DDRII-240_blue

DDRII-240_blue

MEM_MA_ADD[15..0]5,8

MEM_MA_DQS_L[8..0]5

MEM_MA_DQS_H[8..0]5

MEM_MA_DM[8..0]5

MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H8
MEM_MA_DQS_L8

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_RAS_L

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8

MEM_MA0_ODT0

MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2

SCL
SDA

DIMM_VREF_A

PLACE CLOSE TO DIMM PIN

ADDRESS: 000
0xA0

IN

MEM_MA_WE_L 5,8

IN

MEM_MA_CAS_L 5,8

IN

MEM_MA_RAS_L 5,8

C65

C65
C0.1U10X0402

C0.1U10X0402

MEM_MA0_ODT0 5,8

MEM_MA_CKE0 5,8

MEM_MA0_CS_L0 5,8
MEM_MA0_CS_L1 5,8

MEM_MA0_CLK_H0 5,8
MEM_MA0_CLK_L0 5,8
MEM_MA0_CLK_H1 5,8
MEM_MA0_CLK_L1 5,8
MEM_MA0_CLK_H2 5,8
MEM_MA0_CLK_L2 5,8

Layout note: Place capacitors between and
near DDR connector if possible.

VCC_DDR

+

+

C217

C217
C0.1U10X0402

C0.1U10X0402

VCC_DDR

C215

C215
C0.1U10X0402

C0.1U10X0402

12

EC4

EC4
C330U2.5POS-1

C330U2.5POS-1

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

DIMM2

DIMM2

10
122
123
128
129

12

13

21

22
131
132
140
141

24

25

30

31
143
144
149
150

33

34

39

40
152
153
158
159

80

81

86

87
199
200
205
206

89

90

95

96
208
209
214
215

98

99
107
108
217
218
226
227
110
111
116
117
229
230
235
236

11

14

17

20

23

26

29

32

35

38

41

44

47

50

65

66

79

82

85

88

91

94

97

55

68

19

102

NC

3

RC118RC0

DQ0

4

DQ1

9

2
5
8

DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NC/TEST

VSS

VSS

VSS

VSS

100

103

106

109

112

NC

VDD051VDD156VDD262VDD372VDD478VDD5

VSS

VSS

VSS

VSS

115

118

121

191

75

VDD3

VSS

VSS

VSS

VSS

VSS

124

127

130

133

136

VCC_DDR

4 4

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33

3 3

MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

2 2

DIMM1

DIMM1

10
122
123
128
129

12

13

21

22
131
132
140
141

24

25

30

31
143
144
149
150

33

34

39

40
152
153
158
159

80

81

86

87
199
200
205
206

89

90

95

96
208
209
214
215

98

99
107
108
217
218
226
227
110
111
116
117
229
230
235
236

11

14

17

20

23

26

29

32

35

38

41

44

47

50

65

66

79

82

85

88

91

94

97

55

102

68

19

NC

3

RC118RC0

DQ0

4

DQ1

9

NC/TEST

DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

2

VSS

5

VSS

8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS

100

103

106

109

112

NC

VDD051VDD156VDD262VDD372VDD478VDD5

VSS

VSS

VSS

VSS

115

118

121

191

194

181

175

75

170

VDD6

VDD7

VDD8

VDD3

VDDQ0

VDDQ153VDDQ259VDDQ364VDDQ4

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

124

127

130

133

136

139

142

145

148

151

154

VCC3 VCC_DDR VCC3

DDRA_CB3

DDRA_CB4

DDRA_CB1

DDRA_CB2

DDRA_CB0

161

172

187

184

178

VDDQ5

VDDQ6

VDDQ7

VDDQ469VDDQ7

VSS

VSS

VSS

VSS

VSS

166

169

198

201

189

204

VDDQ8

VSS

67

207

VDDQ9

VSS

238

CB042CB143CB248CB349CB4

VDDSPD

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2#(DU)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

210

213

216

219

222

225

228

231

197

VSS

VSS

VSS

157

160

163

SDA12,14

VCC_DDR

R38 49.9R1%0402R38 49.9R1%0402

1 1

SCL12,14

DIMM_VREF_A

R37

R37

49.9R1%0402

49.9R1%0402

A

SDA
SCL

DDR2 DIMM1

Layout note: Place capacitors between and
near DDR connector if possible.

VCC_DDR

+

+

12

B

change DIP to SMD, EC39,EC40 (1214)

EC20

EC20
C330U2.5POS-1

C330U2.5POS-1

AMD design guide just need
the caps in page 6, ADD SOME
BULK, DECOUPLE CAP, NEED
POWER TEAM CONFIRM

C173

C173
C2.2U6.3X5

C2.2U6.3X5

C227

C227

C223

C223

C2.2U6.3X5

C2.2U6.3X5

C2.2U6.3X5

C2.2U6.3X5

Reserve for EMI

C

C174

C174
C2.2U6.3X5

C2.2U6.3X5

VCC_DDR

C0.1U10X0402

C0.1U10X0402

C177

C177

C0.1U10X0402

C0.1U10X0402

C234

C234

C0.1U10X0402

C0.1U10X0402

C176

C176

VCC_DDR

R23 49.9R1%0402R23 49.9R1%0402

R381,382,385,386 CHANGE TO 49.9R (1217)

D

DIMM_VREF_B

R22

R22

49.9R1%0402

49.9R1%0402

DDR2 DIMM2

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

MS-9826

MS-9826

MS-9826

E

Last Revision Date:

Last Revision Date:

Last Revision Date:

Friday, February 22, 2008

Friday, February 22, 2008

Friday, February 22, 2008

Sheet

Sheet

Sheet

734

734

734

Rev

Rev

Rev

0A

0A

0A

of

of

of

5

MEM_MA_ADD[15..0]5,7

D D

MEM_MA_BANK[2..0]5,7

C C

MEM_MB_ADD[15..0]5,7

B B

A A

MEM_MB_BANK[2..0]5,7

MEM_MA_ADD[15..0]

MEM_MA_BANK[2..0]

MEM_MA_CAS_L5,7
MEM_MA_WE_L5,7
MEM_MA_RAS_L5,7

MEM_MA0_CS_L05,7
MEM_MA0_CS_L15,7

MEM_MA0_ODT05,7

MEM_MA_CKE05,7

MEM_MB_ADD[15..0]

MEM_MB_BANK[2..0]

MEM_MB_CAS_L5,7
MEM_MB_WE_L5,7
MEM_MB_RAS_L5,7

MEM_MB0_CS_L05,7
MEM_MB0_CS_L15,7

MEM_MB0_ODT05,7

MEM_MB_CKE05,7

4

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA0_CS_L0
MEM_MA0_CS_L1

MEM_MA0_ODT0

MEM_MA_CKE0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB0_CS_L0
MEM_MB0_CS_L1

MEM_MB0_ODT0

MEM_MB_CKE0

MEM_MA_ADD15
MEM_MB_BANK2
MEM_MA_ADD14
MEM_MB_ADD2

MEM_MA_ADD1
MEM_MA_ADD5
MEM_MA_ADD2
MEM_MA0_CS_L0
MEM_MB_WE_L
MEM_MB0_CS_L0
MEM_MA_WE_L

MEM_MB0_ODT0
MEM_MA0_ODT0
MEM_MB_ADD13

MEM_MB0_CS_L1
MEM_MB_ADD12

MEM_MB_ADD11
MEM_MA_ADD11
MEM_MB_ADD9
MEM_MB_ADD7
MEM_MA_ADD8
MEM_MA_ADD6
MEM_MB_ADD8

MEM_MA_ADD10

MEM_MA_ADD0
MEM_MA_RAS_L

MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_RAS_L

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MA_ADD4
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MA_ADD3

MEM_MA_CKE0
MEM_MA_BANK2

MEM_MB_CKE0
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MA_ADD7
MEM_MB_ADD4

MEM_MA_BANK1
MEM_MA_BANK0

MEM_MB_ADD0
MEM_MB_ADD10
MEM_MB_CAS_L
MEM_MA_CAS_L
MEM_MA0_CS_L1
MEM_MA_ADD13

8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402

8P4R-47_RN0402
8P4R-47_RN0402

8P4R-47_RN0402

3

VTT_DDR

C170 0.1u_10V_0402C170 0.1u_10V_0402

RN6

RN6

1

2

3

4
6
8
2
4
6
8
2
4
6
8
2
4
6
8

2
4
6
8
2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8
2
4
6
8

2
4
6
8
2
4
6
8

2
4
6
8
2
4
6
8

RN12

RN12

RN16

RN16

RN18

RN18

RN8

RN8

RN9

RN9

RN13

RN13

RN15

RN15

VTT_DDR

RN7

RN7

RN11

RN11

RN5

RN5

RN10

RN10

RN14

RN14

RN17

RN17

C180 0.1u_10V_0402C180 0.1u_10V_0402
C203 0.1u_10V_0402C203 0.1u_10V_0402
C178 0.1u_10V_0402C178 0.1u_10V_0402
C226 0.1u_10V_0402C226 0.1u_10V_0402
C224 0.1u_10V_0402C224 0.1u_10V_0402
C199 0.1u_10V_0402C199 0.1u_10V_0402
C182 0.1u_10V_0402C182 0.1u_10V_0402

C208 0.1u_10V_0402C208 0.1u_10V_0402
C216 0.1u_10V_0402C216 0.1u_10V_0402
C218 0.1u_10V_0402C218 0.1u_10V_0402
C195 0.1u_10V_0402C195 0.1u_10V_0402

C188 0.1u_10V_0402C188 0.1u_10V_0402

C261 0.1u_10V_0402C261 0.1u_10V_0402
C168 0.1u_10V_0402C168 0.1u_10V_0402

C228 0.1u_10V_0402C228 0.1u_10V_0402

C214 0.1u_10V_0402C214 0.1u_10V_0402
C186 0.1u_10V_0402C186 0.1u_10V_0402
C235 0.1u_10V_0402C235 0.1u_10V_0402
C239 0.1u_10V_0402C239 0.1u_10V_0402
C238 0.1u_10V_0402C238 0.1u_10V_0402
C190 0.1u_10V_0402C190 0.1u_10V_0402
C181 0.1u_10V_0402C181 0.1u_10V_0402
C206 0.1u_10V_0402C206 0.1u_10V_0402

C192 0.1u_10V_0402C192 0.1u_10V_0402
C243 0.1u_10V_0402C243 0.1u_10V_0402
C240 0.1u_10V_0402C240 0.1u_10V_0402
C201 0.1u_10V_0402C201 0.1u_10V_0402

C252 0.1u_10V_0402C252 0.1u_10V_0402

C236 0.1u_10V_0402C236 0.1u_10V_0402
C184 0.1u_10V_0402C184 0.1u_10V_0402

C213 0.1u_10V_0402C213 0.1u_10V_0402

5
7
1
3
5
7
1
3
5
7
1
3
5
7

1
3
5
7
1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7
1
3
5
7

1
3
5
7
1
3
5
7

1
3
5
7
1
3
5
7

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

after swap (1214)

2

add for DIMM(1218)

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD11
MEM_MB_BANK2
MEM_MB_ADD9
MEM_MB_ADD12
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_RAS_L
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MB_ADD13

MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD1

MEM_MB_ADD2

MEM_MA_ADD1
MEM_MA_ADD2

MEM_MB_ADD5

MEM_MB_ADD6
MEM_MA_BANK0

MEM_MA_BANK1
MEM_MA_ADD10
MEM_MA_ADD0
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD13
MEM_MA_CAS_L
MEM_MA_WE_L

MEM_MA_RAS_L

MEM_MA_ADD12
MEM_MA_ADD14
MEM_MA_BANK2
MEM_MA_ADD15
MEM_MA_ADD8

MEM_MA_ADD7
MEM_MA_ADD11
MEM_MA_ADD9

MEM_MA0_CLK_H25,7

MEM_MA0_CLK_L25,7

MEM_MA0_CLK_H15,7

MEM_MA0_CLK_L15,7

MEM_MA0_CLK_H05,7

MEM_MA0_CLK_L05,7

MEM_MB0_CLK_H25,7

MEM_MB0_CLK_L25,7

MEM_MB0_CLK_H15,7

MEM_MB0_CLK_L15,7

MEM_MB0_CLK_H05,7

MEM_MB0_CLK_L05,7

CN3 8P4C-22P50N3CN3 8P4C-22P50N3

1

2

3

4

5

6

CN5 8P4C-22P50N3CN5 8P4C-22P50N3

7

8

1

2

3

4

5

6

CN11 8P4C-22P50N3CN11 8P4C-22P50N3

7

8

1

2

3

4

5

6

CN13 8P4C-22P50N3CN13 8P4C-22P50N3

7

8

1

2

3

4

5

6

7

8

CN9 8P4C-22P50N3CN9 8P4C-22P50N3

1

2

3

4

5

6

7

CN7 8P4C-22P50N3CN7 8P4C-22P50N3

CN4 8P4C-22P50N3CN4 8P4C-22P50N3

8

1

2

3

4

5

6

7

8

CN10 8P4C-22P50N3CN10 8P4C-22P50N3

1

2

3

4

5

6

CN8 8P4C-22P50N3CN8 8P4C-22P50N3

7

8

1

2

3

4

5

6

CN12 8P4C-22P50N3CN12 8P4C-22P50N3

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

CN6 8P4C-22P50N3CN6 8P4C-22P50N3

6

7

8

1

2

3

4

5

6

7

8

1

MEM_MA0_CLK_H2

MEM_MA0_CLK_L2

MEM_MA0_CLK_H1

MEM_MA0_CLK_L1

MEM_MA0_CLK_H3

MEM_MA0_CLK_L3

MEM_MB0_CLK_H2

MEM_MB0_CLK_L2

MEM_MB0_CLK_H1

MEM_MB0_CLK_L1

MEM_MB0_CLK_H3

MEM_MB0_CLK_L3

VCC_DDR

C249

C249
C1.5P/4

C1.5P/4

C136

C136
C1.5P/4

C1.5P/4

C197

C197
C1.5P/4

C1.5P/4

C250

C250
C1.5P/4

C1.5P/4

C137

C137
C1.5P/4

C1.5P/4

C196

C196
C1.5P/4

C1.5P/4

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

DDR Terminatior

DDR Terminatior

DDR Terminatior

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

5

4

3

2

http://www.msi.com.tw

MS-9826

MS-9826

MS-9826

1

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

Wednesday, February 20, 2008

Wednesday, February 20, 2008

Wednesday, February 20, 2008

834

834

834

Rev

Rev

Rev

0A

0A

0A

of

of

of

5

HT_CADIN_H[15..0]4

HT_CADIN_L[15..0]4

HT_CADOUT_H[15..0]4

HT_CADOUT_L[15..0]4

HT_CADOUT_H15
HT_CADOUT_L15

D D

C C

VDDHT_PKG

HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

HT_CLKOUT_H14
HT_CLKOUT_L14

HT_CLKOUT_H04
HT_CLKOUT_L04

HT_CTLOUT_H04
HT_CTLOUT_L04

R63 49.9/4R63 49.9/4
R73 49.9/4R73 49.9/4

HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]

R19
R18
R21
R22
U22
U21
U18

U19
W19
W20

AC21
AB22
AB20
AA20
AA19

Y19

T24
R25
U25
U24
V23
U23
V24
V25

AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25

W21
W22

Y24

W25

P24
P25

HT_RXCALN

A24

HT_RXCALP

C24

U7A

U7A

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

HT_RXCLK1P
HT_RXCLK1N

HT_RXCLK0P
HT_RXCLK0N

HT_RXCTLP
HT_RXCTLN

HT_RXCALP
HT_RXCALN

ATI-216TQA6AVA12FG-A12-RH

ATI-216TQA6AVA12FG-A12-RH

PART 1 OF 6

PART 1 OF 6

HYPER TRANSPORT CPU

HYPER TRANSPORT CPU

I/F

I/F

4

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HT_TXCTLP

HT_TXCTLN
HT_TXCALP

HT_TXCALN

P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25

L21
L22

J24
J25

N23
P23

C25
D24

HT_TXCALP
HT_TXCALN

HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8

HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0

R74 100/4/1R74 100/4/1

HT_CLKIN_H1 4
HT_CLKIN_L1 4

HT_CLKIN_H0 4
HT_CLKIN_L0 4

HT_CTLIN_H0 4
HT_CTLIN_L0 4

3

2

1

U7B

U7B

G5
G4

J8
J7
J4

B B

A_RX2P13
A_RX2N13

A_RX3P13
A_RX3N13

GPP_RX0P18
GPP_RX0N18

GPP_RX1P19
GPP_RX1N19

A_RX0P13

A A

A_RX0N13
A_RX1P13
A_RX1N13

A_RX2P
A_RX2N

A_RX3P
A_RX3N

GPP_RX0P
GPP_RX0N

GPP_RX1P
GPP_RX1N

5

J5
L8
L7
L4

L5
M8
M7
M4
M5

P8

P7

Y4

Y5
W4

W5

P4

P5
R4

R5
R7

R8
U4

U5

AB7
AB6

V9
W9

AC4
AD4

ATI-216TQA6AVA12FG-A12-RH

ATI-216TQA6AVA12FG-A12-RH

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N

SB_RX2P
SB_RX2N

SB_RX3P
SB_RX3N

GPP_RX2P
GPP_RX2N

GPP_RX3P
GPP_RX3N

GPP_RX0P
GPP_RX0N

GPP_RX1P
GPP_RX1N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N

NC1
NC2

PART 2 OF 6

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRN

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N

SB_TX2P
SB_TX2N

SB_TX3P

SB_TX3N

GPP_TX2P
GPP_TX2N

GPP_TX3P
GPP_TX3N

GPP_TX0P
GPP_TX0N

GPP_TX1P
GPP_TX1N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N

PCE_CALRP

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2

AA1
AA2

Y2
Y3

U2
U1

V2
V1

V3
W3

W1
W2

AC1
AC2
AB1
AB2

R97 562R1%0402R97 562R1%0402

AE4

R96 2KR1%0402R96 2KR1%0402

AE3

4

A_TX2P_C
A_TX2N_C

A_TX3P_C
A_TX3N_C

GPP_TX0P_C
GPP_TX0N_C

GPP_TX1P_C
GPP_TX1N_C

A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C

*
*

REMOVE HDMI

C135 0.1u/16V/4C135 0.1u/16V/4
C146 0.1u/16V/4C146 0.1u/16V/4

C130 0.1u/16V/4C130 0.1u/16V/4
C132 0.1u/16V/4C132 0.1u/16V/4

C120 0.1u/16V/4C120 0.1u/16V/4
C122 0.1u/16V/4C122 0.1u/16V/4

C123 0.1u/16V/4C123 0.1u/16V/4
C129 0.1u/16V/4C129 0.1u/16V/4

C148 0.1u/16V/4C148 0.1u/16V/4
C150 0.1u/16V/4C150 0.1u/16V/4
C147 0.1u/16V/4C147 0.1u/16V/4
C149 0.1u/16V/4C149 0.1u/16V/4

VDDA12_PKG2

A_TX2P 13
A_TX2N 13

A_TX3P 13
A_TX3N 13

GPP_TX0P 18
GPP_TX0N 18

GPP_TX1P 19
GPP_TX1N 19

A_TX0P 13
A_TX0N 13
A_TX1P 13
A_TX1N 13

3

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

2

http://www.msi.com.tw

RS690T-HT LINK/PCIE/HDMI

RS690T-HT LINK/PCIE/HDMI

RS690T-HT LINK/PCIE/HDMI

MS-9826

MS-9826

MS-9826

Last Revision Date:

Last Revision Date:

Last Revision Date:

Wednesday, February 20, 2008

Wednesday, February 20, 2008

Wednesday, February 20, 2008

Sheet

Sheet

Sheet

934

934

1

934

Rev

Rev

Rev

0A

0A

0A

of

of

of