MSI MS-9620 Schematics
5
4
http://adf.ly/3o8pJ
Title Page
3
2
1
Cover Sheet 1
D D
Block Diagram
MS-9620-0A
2
3POWER DELIVER
4 - 7CPU 0 940 PIN
System Memory
/ DDR Terminations
8-11
CPU1 940 PIN 12-15
CK8-04 PRO
PCI1 & CPUCLOCK BUFFER
C C
PCI-Express *16 and *1
PCIE-*4 SLOT
PCI-Express *8 and NV-SLI
Rear USB Port
BCM 5705 GbLAN
FAN
B B
88E1111CAA LAN
Front USB Port
AC97 ACL850
16-21
22
23
24
24
26
27
28
29
30
31
ATX connector / Front Panel
SYSTEM CLOCK BLOCK DIAGRAM
SYSTEM RESET BLOCK DIAGRAM
A A
SYSTEM SMBUS BLOCK DIAGRAM
DDR ROUTING BLOCK DIAGRAM
GENERAL SPEC
5
39
40
41
42
43
44
4
W627THF LPC I/O / BIOS
VIA 6306 1394
IDE CONNECTOR
MS-6 ACPI Controller & MS-6+
VRM1 ISL 6566
VRM0 ISL 6566
3
KB/MS/LPT/COM Port
32
33
34
35
36
37
38
2
Micro Star R estricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien , Taiwan
http:/ /www.msi.com.tw
Cover Sheet
MS-9620
Last Revision Date:
Sheet
1
Tuesday, January 25, 2005
144
of
Rev
0A
5
Block Diagram
4
3
2
1
http://adf.ly/3o8pJ
AMD K8 Socket 940
D D
HT(8GB/s)
AMD K8 Socket 940
CPU 0CPU 1
HT(8GB/s)
PCIE_X8
DDR * 6
PCIE_X8
PCIE_X4
DDR400
C C
1 PCI Slots
PCI-33
PCIE_X20LANE
Dual ATA
100/133
IDE Slot
==>ATA66,100,133 *2
B B
AC97 => S/W Audio
ALC850 8 CHANEL
Giga Bit LAN
BCM5705
A A
5
VIA 6306
1394-->2 PORT
4
SERIAL ATA *4
AC97
CK8-04
USB
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *6,
Back-Port *4
3
RGMII
LPC BUS
SUPER I/O
W83627HF
2
FWH
88E1111
PHY GIGA
BIT LAN
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 6 9, Li-De St, Jung -He City,
Taip ei Hsien, Taiwan
http://www.msi.com.tw
1
Block Diagram
MS-9620
Last Revision Date:
Sheet
Rev
0A
Wed nesday, February 02, 2005
of
244
5
HT0 is for SH0 & Golem connection
VDD_12_A
K10
VLDT_1(1)
R2035
X_1K
R2034
X_100K
closed to F22 pinclosed to AF22 pin
VCC_DDR
J11
H10
H8
K14
J15
K16
J16
J9
E14
E13
C15
D15
E16
E15
C17
D17
C19
D19
E20
E19
C21
D21
E22
E21
C14
B14
A16
A15
C16
B16
A18
A17
A20
A19
C20
B20
A22
A21
C22
B22
E18
E17
C18
B18
A14
A13
C13
D13
R2027
X_1K
R2026
X_100K
C2094
0.1u
1
2
VLDT_1(2)
VLDT_1(3)
VLDT_1(4)
VLDT_1(5)
VLDT_1(6)
VLDT_1(7)
VLDT_1(8)
VLDT_1(9)
L1_CADIN_H(15)
L1_CADIN_L(15)
L1_CADIN_H(14)
L1_CADIN_L(14)
L1_CADIN_H(13)
L1_CADIN_L(13)
L1_CADIN_H(12)
L1_CADIN_L(12)
L1_CADIN_H(11)
L1_CADIN_L(11)
L1_CADIN_H(10)
L1_CADIN_L(10)
L1_CADIN_H(9)
L1_CADIN_L(9)
L1_CADIN_H(8)
L1_CADIN_L(8)
L1_CADIN_H(7)
L1_CADIN_L(7)
L1_CADIN_H(6)
L1_CADIN_L(6)
L1_CADIN_H(5)
L1_CADIN_L(5)
L1_CADIN_H(4)
L1_CADIN_L(4)
L1_CADIN_H(3)
L1_CADIN_L(3)
L1_CADIN_H(2)
L1_CADIN_L(2)
L1_CADIN_H(1)
L1_CADIN_L(1)
L1_CADIN_H(0)
L1_CADIN_L(0)
L1_CLKIN_H(1)
L1_CLKIN_L(1)
L1_CLKIN_H(0)
L1_CLKIN_L(0)
L1_CTLIN_H(0)
L1_CTLIN_L(0)
L1_RSVD1
L1_RSVD2
H0_VREF0_DDR
U2005
A
B
GND3Y
X_SN7X_4LVC1G08DCKR,SC-70
D D
C C
B B
A A
VCC_DDR
5
C2554
0.22u/16V/ X7R
SOLDER SIDE
C2175
R2078
100RST
0.1u
C2174
R2077
100RST
0.1u
MEM_GPIO1<17>
FROM CPU TO DIMM
MEM_GPIO2<17>
C2545
1000P/50V/X7R
TP2000
TP2001
C2176
1000P/50V/X7R
R2028 X_0
H0_MEM RESET1_L
VCC_DDR
R2455
X_0
4
U2006E
L1_CADOUT_H(15)
L1_CADOUT_L(15)
L1_CADOUT_H(14)
L1_CADOUT_L(14)
L1_CADOUT_H(13)
L1_CADOUT_L(13)
L1_CADOUT_H(12)
L1_CADOUT_L(12)
L1_CADOUT_H(11)
L1_CADOUT_L(11)
L1_CADOUT_H(10)
L1_CADOUT_L(10)
L1_CADOUT_H(9)
L1_CADOUT_L(9)
L1_CADOUT_H(8)
L1_CADOUT_L(8)
L1_CADOUT_H(7)
L1_CADOUT_L(7)
L1_CADOUT_H(6)
L1_CADOUT_L(6)
L1_CADOUT_H(5)
L1_CADOUT_L(5)
L1_CADOUT_H(4)
L1_CADOUT_L(4)
L1_CADOUT_H(3)
L1_CADOUT_L(3)
L1_CADOUT_H(2)
L1_CADOUT_L(2)
L1_CADOUT_H(1)
L1_CADOUT_L(1)
L1_CADOUT_H(0)
L1_CADOUT_L(0)
L1_CLKOUT_H(1)
L1_CLKOUT_L(1)
L1_CLKOUT_H(0)
L1_CLKOUT_L(0)
L1_CTLOUT_H(0)
L1_CTLOUT_L(0)
SledgeHammer
C2095
1000P/50V/X7R
VCC_DDR
5
VCC
4
H0_MEM RESET1_L H0_MEMRESET _L
4
D11
C11
E9
E10
D9
C9
E7
E8
E5
E6
D5
C5
E3
E4
D3
C3
A11
A12
B10
C10
A9
A10
B8
C8
B6
C6
A5
A6
B4
C4
A3
A4
D7
C7
A7
A8
B12
C12
E11
L1_RSVD3
E12
L1_RSVD4
U2003
1
A
VCC
2
B
GND3Y
X_SN74LVC1G32DBVR
R2456 0
VCC_DDR
5
4
TP2002
TP2003
H0_MEMRESET _L <8,9,10>
modified on 1/30
C2542
0.22u/16V/ X7R
SOLDER SIDE
3
3
C2560
1000P/50V/X7R
VCC_DDR
H0_VREF0_DDR
H0_VREF0_DDR
H0_MD [127..64]<11>
VTT_DDR
http://adf.ly/3o8pJ
C2052
4.7u/0805
H0_MDQS35<11>
H0_MDQS34<11>
H0_MDQS33<11>
H0_MDQS32<11>
H0_MDQS31<11>
H0_MDQS30<11>
H0_MDQS29<11>
H0_MDQS28<11>
H0_MDQS27<11>
H0_MDQS26<11>
H0_MDQS25<11>
H0_MDQS24<11>
H0_MDQS23<11>
H0_MDQS22<11>
H0_MDQS21<11>
H0_MDQS20<11>
H0_MDQS19<11>
H0_MDQS18<11>
H0_MDQS17<11>
H0_MDQS16<11>
H0_MDQS15<11>
H0_MDQS14<11>
H0_MDQS13<11>
H0_MDQS12<11>
H0_MDQS11<11>
H0_MDQS10<11>
H0_MDQS9<11>
H0_MDQS8<11>
H0_MDQS7<11>
H0_MDQS6<11>
H0_MDQS5<11>
H0_MDQS4<11>
H0_MDQS3<11>
H0_MDQS2<11>
H0_MDQS1<11>
H0_MDQS0<11>
VTT_DDR
R2089
X_51
VTT_DDR
R2083 42.2RST
R2082 42.2RST
H0_MD127
H0_MD126
H0_MD125
H0_MD124
H0_MD123
H0_MD122
H0_MD121
H0_MD120
H0_MD119
H0_MD118
H0_MD117
H0_MD116
H0_MD115
H0_MD114
H0_MD113
H0_MD112
H0_MD111
H0_MD110
H0_MD109
H0_MD108
H0_MD107
H0_MD106
H0_MD105
H0_MD104
H0_MD103
H0_MD102
H0_MD101
H0_MD100
H0_MD99
H0_MD98
H0_MD97
H0_MD96
H0_MD95
H0_MD94
H0_MD93
H0_MD92
H0_MD91
H0_MD90
H0_MD89
H0_MD88
H0_MD87
H0_MD86
H0_MD85
H0_MD84
H0_MD83
H0_MD82
H0_MD81
H0_MD80
H0_MD79
H0_MD78
H0_MD77
H0_MD76
H0_MD75
H0_MD74
H0_MD73
H0_MD72
H0_MD71
H0_MD70
H0_MD69
H0_MD68
H0_MD67
H0_MD66
H0_MD65
H0_MD64
H0_MDQS35
H0_MDQS34
H0_MDQS33
H0_MDQS32
H0_MDQS31
H0_MDQS30
H0_MDQS29
H0_MDQS28
H0_MDQS27
H0_MDQS26
H0_MDQS25
H0_MDQS24
H0_MDQS23
H0_MDQS22
H0_MDQS21
H0_MDQS20
H0_MDQS19
H0_MDQS18
H0_MDQS17
H0_MDQS16
H0_MDQS15
H0_MDQS14
H0_MDQS13
H0_MDQS12
H0_MDQS11
H0_MDQS10
H0_MDQS9
H0_MDQS8
H0_MDQS7
H0_MDQS6
H0_MDQS5
H0_MDQS4
H0_MDQS3
H0_MDQS2
H0_MDQS1
H0_MDQS0
AC19
AE19
AE18
AC18
AF18
AF19
AF17
AE16
AF22
AG24
AH25
AG26
AH27
AF23
AH24
AF25
AJ26
AG27
AF26
AF28
AE29
AJ29
AH29
AE27
AD26
AD27
AC26
AA26
AA28
AD28
AC27
AB29
AA27
W27
AG25
AF27
AB27
W29
AF24
AG28
AC28
AJ25
AJ30
AD29
AA31
AL25
AL29
AE31
J19
H19
F20
G19
F21
F22
Y27
Y28
V28
U26
Y26
V27
U27
P28
N29
M26
L28
P27
P26
M27
L27
K29
K27
H28
G29
L26
J28
H27
H26
F27
F26
D29
D27
G27
F28
E27
C27
C26
E25
D24
F23
E26
F25
E24
G23
R27
N27
J27
E29
F24
R28
V26
M28
J26
E28
D25
U31
M30
H30
C30
B25
T31
Y29
M29
H29
C29
C25
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT_SENSE
MEMZN
MEMZP
MEMVREF0
MEMVREF1
MEMDATA(127)
MEMDATA(126)
MEMDATA(125)
MEMDATA(124)
MEMDATA(123)
MEMDATA(122)
MEMDATA(121)
MEMDATA(120)
MEMDATA(119)
MEMDATA(118)
MEMDATA(117)
MEMDATA(116)
MEMDATA(115)
MEMDATA(114)
MEMDATA(113)
MEMDATA(112)
MEMDATA(111)
MEMDATA(110)
MEMDATA(109)
MEMDATA(108)
MEMDATA(107)
MEMDATA(106)
MEMDATA(105)
MEMDATA(104)
MEMDATA(103)
MEMDATA(102)
MEMDATA(101)
MEMDATA(100)
MEMDATA(99)
MEMDATA(98)
MEMDATA(97)
MEMDATA(96)
MEMDATA(95)
MEMDATA(94)
MEMDATA(93)
MEMDATA(92)
MEMDATA(91)
MEMDATA(90)
MEMDATA(89)
MEMDATA(88)
MEMDATA(87)
MEMDATA(86)
MEMDATA(85)
MEMDATA(84)
MEMDATA(83)
MEMDATA(82)
MEMDATA(81)
MEMDATA(80)
MEMDATA(79)
MEMDATA(78)
MEMDATA(77)
MEMDATA(76)
MEMDATA(75)
MEMDATA(74)
MEMDATA(73)
MEMDATA(72)
MEMDATA(71)
MEMDATA(70)
MEMDATA(69)
MEMDATA(68)
MEMDATA(67)
MEMDATA(66)
MEMDATA(65)
MEMDATA(64)
MEMDQS(35)
MEMDQS(34)
MEMDQS(33)
MEMDQS(32)
MEMDQS(31)
MEMDQS(30)
MEMDQS(29)
MEMDQS(28)
MEMDQS(27)
MEMDQS(26)
MEMDQS(25)
MEMDQS(24)
MEMDQS(23)
MEMDQS(22)
MEMDQS(21)
MEMDQS(20)
MEMDQS(19)
MEMDQS(18)
MEMDQS(17)
MEMDQS(16)
MEMDQS(15)
MEMDQS(14)
MEMDQS(13)
MEMDQS(12)
MEMDQS(11)
MEMDQS(10)
MEMDQS(9)
MEMDQS(8)
MEMDQS(7)
MEMDQS(6)
MEMDQS(5)
MEMDQS(4)
MEMDQS(3)
MEMDQS(2)
MEMDQS(1)
MEMDQS(0)
U2006B
MEMCLK_UP_H(3)
MEMCLK_UP_L(3)
MEMCLK_UP_H(2)
MEMCLK_UP_L(2)
MEMCLK_UP_H(1)
MEMCLK_UP_L(1)
MEMCLK_UP_H(0)
MEMCLK_UP_L(0)
MEMCLK_LO_H(3)
MEMCLK_LO_L(3)
MEMCLK_LO_H(2)
MEMCLK_LO_L(2)
MEMCLK_LO_H(1)
MEMCLK_LO_L(1)
MEMCLK_LO_H(0)
MEMCLK_LO_L(0)
MEMCHECK(15)
MEMCHECK(14)
MEMCHECK(13)
MEMCHECK(12)
MEMCHECK(11)
MEMCHECK(10)
MEMCHECK(9)
MEMCHECK(8)
MEMCHECK(7)
MEMCHECK(6)
MEMCHECK(5)
MEMCHECK(4)
MEMCHECK(3)
MEMCHECK(2)
MEMCHECK(1)
MEMCHECK(0)
SledgeHammer
2
MEMCKE_UP
MEMCKE_LO
RSVD_MA(15)
RSVD_MA(14)
MEMADD(13)
MEMADD(12)
MEMADD(11)
MEMADD(10)
MEMADD(9)
MEMADD(8)
MEMADD(7)
MEMADD(6)
MEMADD(5)
MEMADD(4)
MEMADD(3)
MEMADD(2)
MEMADD(1)
MEMADD(0)
MEMDATA(63)
MEMDATA(62)
MEMDATA(61)
MEMDATA(60)
MEMDATA(59)
MEMDATA(58)
MEMDATA(57)
MEMDATA(56)
MEMDATA(55)
MEMDATA(54)
MEMDATA(53)
MEMDATA(52)
MEMDATA(51)
MEMDATA(50)
MEMDATA(49)
MEMDATA(48)
MEMDATA(47)
MEMDATA(46)
MEMDATA(45)
MEMDATA(44)
MEMDATA(43)
MEMDATA(42)
MEMDATA(41)
MEMDATA(40)
MEMDATA(39)
MEMDATA(38)
MEMDATA(37)
MEMDATA(36)
MEMDATA(35)
MEMDATA(34)
MEMDATA(33)
MEMDATA(32)
MEMDATA(31)
MEMDATA(30)
MEMDATA(29)
MEMDATA(28)
MEMDATA(27)
MEMDATA(26)
MEMDATA(25)
MEMDATA(24)
MEMDATA(23)
MEMDATA(22)
MEMDATA(21)
MEMDATA(20)
MEMDATA(19)
MEMDATA(18)
MEMDATA(17)
MEMDATA(16)
MEMDATA(15)
MEMDATA(14)
MEMDATA(13)
MEMDATA(12)
MEMDATA(11)
MEMDATA(10)
MEMDATA(9)
MEMDATA(8)
MEMDATA(7)
MEMDATA(6)
MEMDATA(5)
MEMDATA(4)
MEMDATA(3)
MEMDATA(2)
MEMDATA(1)
MEMDATA(0)
MEMRESET_L
MEMBANK(1)
MEMBANK(0)
MEMRAS_L
MEMCAS_L
MEMWE_L
MEMCS_L(7)
MEMCS_L(6)
MEMCS_L(5)
MEMCS_L(4)
MEMCS_L(3)
MEMCS_L(2)
MEMCS_L(1)
MEMCS_L(0)
2
G20
G21
H0_ME MCLK_H5
AE21
H0_M EMCLK_L5
AE20
H0_ME MCLK_H3
L24
H0_M EMCLK_L3
L25
H0_ME MCLK_H2
R23
H0_M EMCLK_L2
T23
H23
J23
H0_ME MCLK_H4
AD21
H0_M EMCLK_L4
AD20
H0_ME MCLK_H1
Y23
H0_M EMCLK_L1
AA23
H0_ME MCLK_H0
U25
H0_M EMCLK_L0
U24
H0_MCKEUP
H24
H0_MC KELO
H25
V23
M23
H0_MAA13
AE23
H0_MAA12
J24
H0_MAA11
J25
H0_MAA10
V24
H0_MAA9
K23
H0_MAA8
L23
H0_MAA7
K25
H0_MAA6
M25
H0_MAA5
M24
H0_MAA4
N25
H0_MAA3
N23
H0_MAA2
P23
H0_MAA1
T25
H0_MAA0
V25
H0_MD63
AJ24
H0_MD62
AK25
H0_MD61
AK27
H0_MD60
AJ27
H0_MD59
AL24
H0_MD58
AK24
H0_MD57
AL26
H0_MD56
AL27
H0_MD55
AJ28
H0_MD54
AK30
H0_MD53
AJ31
H0_MD52
AG29
H0_MD51
AL28
H0_MD50
AK28
H0_MD49
AH31
H0_MD48
AG30
H0_MD47
AG31
H0_MD46
AF30
H0_MD45
AD31
H0_MD44
AC30
H0_MD43
AF29
H0_MD42
AF31
H0_MD41
AD30
H0_MD40
AC29
H0_MD39
AB31
H0_MD38
AA29
H0_MD37
Y31
H0_MD36
W31
H0_MD35
AC31
H0_MD34
AA30
H0_MD33
Y30
H0_MD32
V29
H0_MD31
P31
H0_MD30
M31
H0_MD29
L30
H0_MD28
L29
H0_MD27
P29
H0_MD26
N31
H0_MD25
L31
H0_MD24
K31
H0_MD23
J30
H0_MD22
J29
H0_MD21
G31
H0_MD20
F29
H0_MD19
J31
H0_MD18
H31
H0_MD17
F31
H0_MD16
F30
H0_MD15
D31
H0_MD14
C31
H0_MD13
B30
H0_MD12
C28
H0_MD11
E31
H0_MD10
E30
H0_MD9
A29
H0_MD8
B28
H0_MD7
B27
H0_MD6
A26
H0_MD5
C24
H0_MD4
A24
H0_MD3
A28
H0_MD2
A27
H0_MD1
A25
H0_MD0
B24
H0_MEMRESET1_L
G25
W25
W23
H0_-MSRASA
Y25
H0_-MSCASA
AA25
Y24
H0_MEMCHECK15
U28
H0_MEMCHECK14
T29
H0_MEMCHECK13
P24
H0_MEMCHECK12
P25
H0_MEMCHECK11
T27
H0_MEMCHECK10
R26
H0_MEMCHECK9
R25
H0_MEMCHECK8
R24
H0_MEMCHECK7
V30
H0_MEMCHECK6
U29
H0_MEMCHECK5
R30
H0_MEMCHECK4
P30
H0_MEMCHECK3
V31
H0_MEMCHECK2
U30
H0_MEMCHECK1
R29
H0_MEMCHECK0
R31
AD23
AE25
H0_-MCS5
AD24
H0_-MCS4
AD25
H0_-MCS3
AC24
H0_-MCS2
AC25
H0_-MCS1
AB25
H0_-MCS0
AA24
H0_ME MCLK_H5 <10>
H0_MEM CLK_L5 <10>
H0_ME MCLK_H3 <9>
H0_MEM CLK_L3 <9>
H0_ME MCLK_H2 <8>
H0_MEM CLK_L2 <8>
H0_ME MCLK_H4 <10>
H0_MEM CLK_L4 <10>
H0_ME MCLK_H1 <9>
H0_MEM CLK_L1 <9>
H0_ME MCLK_H0 <8>
H0_MEM CLK_L0 <8>
H0_MCKEUP <11>
H0_MC KELO <11>
H0_MAA13 <11>
H0_MAA12 <11>
H0_MAA11 <11>
H0_MAA10 <11>
H0_MAA9 <11>
H0_MAA8 <11>
H0_MAA7 <11>
H0_MAA6 <11>
H0_MAA5 <11>
H0_MAA4 <11>
H0_MAA3 <11>
H0_MAA2 <11>
H0_MAA1 <11>
H0_MAA0 <11>
H0_MD[63..0] <11>
H0_MEMBAKA1 <11>
H0_MEMBAKA0 <11>
H0_-MSRASA <11>
H0_-MSCASA <11>
H0_-MSWEA <11>
H0_ME MCHECK15 <11>
H0_ MEMC HECK1 4 <11>
H0_ MEMC HECK1 3 <11>
H0_ MEMC HECK1 2 <11>
H0_ MEMC HECK1 1 <11>
H0_ MEMC HECK1 0 <11>
H0_ME MCHECK9 <11>
H0_ME MCHECK8 <11>
H0_ME MCHECK7 <11>
H0_ME MCHECK6 <11>
H0_ME MCHECK5 <11>
H0_ME MCHECK4 <11>
H0_ME MCHECK3 <11>
H0_ME MCHECK2 <11>
H0_ME MCHECK1 <11>
H0_ME MCHECK0 <11>
H0_-MCS5 <11>
H0_-MCS4 <11>
H0_-MCS3 <11>
H0_-MCS2 <11>
H0_-MCS1 <11>
H0_-MCS0 <11>
H0_ME MCLK_H3
H0_M EMCLK_L3
H0_ME MCLK_H2
H0_M EMCLK_L2
H0_ME MCLK_H1
H0_M EMCLK_L1
H0_ME MCLK_H0
H0_M EMCLK_L0
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http:// www.msi.com.tw
R2063
(BOT)120RST
R2067
(BOT)120RST
R2072
(BOT)120RST
R2073
(BOT)120RST
H0_ME MCLK_H5
H0_M EMCLK_L5
H0_ME MCLK_H4
H0_M EMCLK_L4
Micro S tar Restricted Secret
CPU0_K8 DDR & HT
1
MS-9620
1
R985
(BOT)120RST
R986
(BOT)120RST
Last Revision Date:
Tuesd ay, Feb ruary 15, 2005
Sheet
444
Rev
0A
of
5
VDDA25
C2077
4.7u/0805
D D
C C
B B
A A
C2070
1000P/50V/X7R
Routed differentially
with a 20/5/5/5/20.
C2089
3300p/50V/X7R
VDD_12_A
0.22u/16V
VERY CLOSE TO CPU
CLKIN0_H
R2422
(BOT)169RST
CLKIN0_L
HT_STOP#
VCC2_5
VCC2_5
PS_ON#A
CPU_PWRGD<13,16>
VCC2_5
R2493 680
R2494 680
5
CPU_RST#<13,16>
HT_STOP#<13,16>
R2041 680
PS_ON#A<39>
C2088
CPU_RST#
HT_STOP#
CT2003
100u/10V
VCC2_5
C2073 0.1u
COREFB0_H<37>
COREFB0_L<37>
CPUCLK0_H<22>
CPUCLK0_L<22>
R2062 680
Q2007
2N7002S
FB2000 180nH/1210
R2060 43.2RST
R2059 43.2RST
R2057 0
R2058 0
C2083
C2084
H0_TMS
H0_TCK
H0_TRST_L
VCC2_5
C2068
33P
VCC2_5
R2495 680
3900P/50V/X7R
C2092
33P
VDDA25
TP2006
3900P/50V/X7R
TP2008
TP2007
TP2017
TP2018
TP2019
TP2005
TP2020
TP2012
TP2013
TP2009
CPU_T HEMTRIP#
4
LAYOUT:
Route VDDA trace approx. 50 mils wide
(use 2x25 mil traces to exit ball) and
500 mils long.
C1
VDDA1
D2
VDDA2
C2
VDDA3
E1
L0_REF1
D1
L0_REF0
L7
COREFB_H
L6
COREFB_L
K7
CORESENSE_H
CLKIN0_H
G16
H16
G14
H14
AE6
AE7
AD7
AF7
AE10
AE11
AF11
AE13
AE12
AF13
AF15
AE14
G12
F12
AG1
AH2
AJ2
AA6
AC6
J7
T3
T4
L8
K8
J6
H9
N6
CLKIN_H
CLKIN_L
BYPASSCLK_H
BYPASSCLK_L
TMS
TCK
TRST_L
TDI
DBREQ_L
SCANCLK1
SCANCLK2
SCANEN
SCANSHIFTEN
SCANSHIFTENB
SCANIN_H
SCANIN_L
SINGLECHAIN
PLLCHRZ_H
PLLCHRZ_L
DCLKTWO
BURNIN_L
RESET_L
LDTSTOP_L
PWROK
FREE7
FREE11
FREE15
FREE12
FREE21
FREE1
FREE3
SledgeHammer
CLKIN0_L
H0_N C_G14
H0_NC_H14
H0_TDI
H0_D BREQ_L
H0_SCANCLK1
H0_SCANCLK2
H0_SCANEN
H0_SS ENA
H0_SS ENB
H0_NC_T3
H0_NC_T4
H0_NC_AF13
H0_NC _AE14
4
3
http://adf.ly/3o8pJ
U2006C
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
BP(3)
BP(2)
BP(1)
BP(0)
TDO
DBRDY
TSTOUT
ANALOG3
ANALOG2
ANALOG1
ANALOG0
AE15
AJ1
AH1
G9
F9
G10
H11
G11
H13
G6
F7
H12
H0_FBC LKOUT_H
G18
H18
H0_FBCLKOUT_L
AE8
H0_DBRDY
G8
V5
U5
H7
U1_T7
T7
U1_W6
W6
U1_R6
R6
U1_U6
U6
AF9
AE9
3
THER MDA_CPU1 <33>
VTIN_G ND <13,33>
R2049 0
R2048 0
R2050 0
R2051 0
R2044 0
H0_BP3
H0_BP2
H0_BP1
H0_BP0
R2421
80.6RST
LAYOUT:
Route FBCLKOUT_H/L differentially
with 20/5/5/5/20 for 1.5" to escape the BGA.
TP2014
TP2011
TP2010
TP2004
U1_U6
U1_T7
U1_W6
TP2016
TP2015
THERMTRIP_L
THERMDA
THERMDC
FBCLKOUT_H
FBCLKOUT_L
SCANOUT_H
SCANOUT_L
RSVD_SMBUSC
RSVD_SMBUSD
2
Routed
differentially.
VID 4 <38>
VID3 <32,38>
VID2 <32,38>
VID1 <32,38>
VID0 <32,38>
This termination
resistor should
be placed as
close to
Processor as
possible.
U1_R6 H0_NC_T3
680_8P4R
R2457 680
RN2026
12
34
56
78
modified on 1/30
CPU_T HEMTRIP# <13,16>
R2458
49.9RST
2
H0_TRST_L
H0_TCK
R2463 1K
R2462 1K
H0_TMS
H0_TDI
STRAPPINGS
H0_N C_G14
H0_N C_AE14
H0_NC_AF13
H0_D BREQ_L
H0_DBRDY
H0_NC_H14
H0_SCANEN
H0_SCANCLK1
H0_SCANCLK2
H0_SS ENA
H0_SS ENB
H0_BP3
H0_BP2
H0_BP1
H0_BP0
H0_NC_T4
R2461 1K
R2079 1K
R2043 820
R2088 680
R2087 680
R2052 1K
R2042 820
R2085 680
R2080 680
R2084 680
R2086 680
R2081 680
R2056 X_680
R2053 X_680
R2054 680
R2055 680
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li- De St, Jung-He City,
Taipe i Hsien, Taiwan
http://www.m si.com.tw
1
VCC2_5
R2047 1K
VDD_12_A
R2070 49.9RST
R2068
X_49.9RST
CPU0_K8 HDT & MISC
MS-9620
Last Revision Date:
Tuesday, February 15, 2005
Sheet
544
1
Rev
0A
of
5
4
3
2
1
http://adf.ly/3o8pJ
VDD_12_A
N7
VLDT_0(1)
R7
VLDT_0(2)
U7
D D
H0_CADIN[15..0]<12>
H0_CADIN#[15..0]<12>
C C
H0_CLKIN1<12>
H0_CLKIN#1<12>
H0_CLKIN0<12>
H0_CLKIN#0<12>
B B
H0_CTLIN0<12>
H0_CTLIN#0<12>
CT2007
100u/10V
C2132
0.22u /16V/X7R
H0_CADIN15
H0_CADIN#15
H0_CADIN14
H0_CADIN#14
H0_CADIN13
H0_CADIN#13
H0_CADIN12
H0_CADIN#12
H0_CADIN11
H0_CADIN#11
H0_CADIN10
H0_CADIN#10
H0_CADIN9
H0_CADIN#9
H0_CADIN8
H0_CADIN#8
H0_CADIN7
H0_CADIN#7
H0_CADIN6
H0_CADIN#6
H0_CADIN5
H0_CADIN#5
H0_CADIN4
H0_CADIN#4
H0_CADIN3
H0_CADIN#3
H0_CADIN2
H0_CADIN#2
H0_CADIN1
H0_CADIN#1
H0_CADIN0
H0_CADIN#0
H0_CLKIN1
H0_CLKIN#1
H0_CLKIN0
H0_CLKIN#0
H0_CTLIN0
H0_CTLIN#0
VDD_12_A
0.22u /16V/X7R
C2080
103P
C2146
W7
M8
P8
AA7
V8
Y8
R5
T5
P3
P4
N5
P5
M3
M4
K3
K4
J5
K5
H3
H4
G5
H5
R3
R2
N1
P1
N3
N2
L1
M1
J1
K1
J3
J2
G1
H1
G3
G2
L5
M5
L3
L2
R1
T1
C2079
C2093
1000P/50V/X7R
0.22u /16V/X7R
VLDT_0(3)
VLDT_0(4)
VLDT_0(5)
VLDT_0(6)
VLDT_0(7)
VLDT_0(8)
VLDT_0(9)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
SledgeHammer
C2163
1000P/50V/X7R
U2006A
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
CT2006
100u/10V
H0_CADOUT15
V4
H0_CADOUT#15 VDD_12_A
V3
H0_CADOUT14
Y5
H0_CADOUT#14
W5
H0_CADOUT13
Y4
H0_CADOUT#13
Y3
H0_CADOUT12
AB5
H0_CADOUT#12
AA5
H0_CADOUT11
AD5
H0_CADOUT#11
AC5
H0_CADOUT10
AD4
H0_CADOUT#10
AD3
H0_CADOUT9
AF5
H0_CADOUT#9
AE5
H0_CADOUT8
AF4
H0_CADOUT#8
AF3
H0_CADOUT7
V1
H0_CADOUT#7
U1
H0_CADOUT6
W2
H0_CADOUT#6
W3
H0_CADOUT5
Y1
H0_CADOUT#5
W1
H0_CADOUT4
AA2
H0_CADOUT#4
AA3
H0_CADOUT3
AC2
H0_CADOUT#3
AC3
H0_CADOUT2
AD1
H0_CADOUT#2
AC1
H0_CADOUT1
AE2
H0_CADOUT#1
AE3
H0_CADOUT0
AF1
H0_CADOUT#0
AE1
H0_CL KOUT1
AB4
H0_CL KOUT#1
AB3
H0_CL KOUT0
AB1
H0_CL KOUT#0
AA1
H0_CT LOUT0
U2
H0_CT LOUT#0
U3
H0_C ADOUT[15 ..0] <12>
H0_CA DOUT#[15 ..0] <12>
H0_CL KOUT1 <12>
H0_CL KOUT#1 <12>
H0_CL KOUT0 <12>
H0_CL KOUT#0 <12>
H0_CT LOUT0 <12>
H0_CT LOUT#0 <12>
C2141
0.22u /16V/X7R
4.7u/1206
L0_CADIN[15..0]<16>
L0_CADIN#[15..0]<16>
<16>
L0_CLKIN#1<16>
L0_CLKIN#0<16>
<16>
L0_CTLIN#0
L0_CLKIN1<16>
L0_CLKIN0<16>
L0_CTLIN0
C2164
C2123
103P
L0_CADIN15
L0_CADIN#15
L0_CADIN14
L0_CADIN#14
L0_CADIN13
L0_CADIN#13
L0_CADIN12
L0_CADIN#12
L0_CADIN11
L0_CADIN#11
L0_CADIN10
L0_CADIN#10
L0_CADIN9
L0_CADIN#9
L0_CADIN8
L0_CADIN#8
L0_CADIN7
L0_CADIN#7
L0_CADIN6
L0_CADIN#6
L0_CADIN5
L0_CADIN#5
L0_CADIN4
L0_CADIN#4
L0_CADIN3
L0_CADIN#3
L0_CADIN2
L0_CADIN#2
L0_CADIN1
L0_CADIN#1
L0_CADIN0
L0_CADIN#0
L0_CLKIN1
L0_CLKIN#1
L0_CLKIN0
L0_CLKIN#0
L0_CTLIN0
L0_CTLIN#0
AB10
AC11
AD10
AB14
AC15
AB16
AC16
AG11
AG12
AJ10
AH10
AG10
AJ11
AK11
AL10
AL11
AL12
AJ12
AH12
AD8
AC9
AG9
AJ8
AH8
AJ6
AH6
AG5
AG6
AJ4
AH4
AG3
AG4
AL9
AJ9
AK9
AL7
AL8
AL5
AL6
AJ5
AK5
AL3
AL4
AJ3
AK3
AG7
AG8
AJ7
AK7
VLDT_2(1)
VLDT_2(2)
VLDT_2(3)
VLDT_2(4)
VLDT_2(5)
VLDT_2(6)
VLDT_2(7)
VLDT_2(8)
VLDT_2(9)
L2_CADIN_H(15)
L2_CADIN_L(15)
L2_CADIN_H(14)
L2_CADIN_L(14)
L2_CADIN_H(13)
L2_CADIN_L(13)
L2_CADIN_H(12)
L2_CADIN_L(12)
L2_CADIN_H(11)
L2_CADIN_L(11)
L2_CADIN_H(10)
L2_CADIN_L(10)
L2_CADIN_H(9)
L2_CADIN_L(9)
L2_CADIN_H(8)
L2_CADIN_L(8)
L2_CADIN_H(7)
L2_CADIN_L(7)
L2_CADIN_H(6)
L2_CADIN_L(6)
L2_CADIN_H(5)
L2_CADIN_L(5)
L2_CADIN_H(4)
L2_CADIN_L(4)
L2_CADIN_H(3)
L2_CADIN_L(3)
L2_CADIN_H(2)
L2_CADIN_L(2)
L2_CADIN_H(1)
L2_CADIN_L(1)
L2_CADIN_H(0)
L2_CADIN_L(0)
L2_CLKIN_H(1)
L2_CLKIN_L(1)
L2_CLKIN_H(0)
L2_CLKIN_L(0)
L2_CTLIN_H(0)
L2_CTLIN_L(0)
L2_RSVD1
L2_RSVD2
SledgeHammer
U2006F
L2_CADOUT_H(15)
L2_CADOUT_L(15)
L2_CADOUT_H(14)
L2_CADOUT_L(14)
L2_CADOUT_H(13)
L2_CADOUT_L(13)
L2_CADOUT_H(12)
L2_CADOUT_L(12)
L2_CADOUT_H(11)
L2_CADOUT_L(11)
L2_CADOUT_H(10)
L2_CADOUT_L(10)
L2_CADOUT_H(9)
L2_CADOUT_L(9)
L2_CADOUT_H(8)
L2_CADOUT_L(8)
L2_CADOUT_H(7)
L2_CADOUT_L(7)
L2_CADOUT_H(6)
L2_CADOUT_L(6)
L2_CADOUT_H(5)
L2_CADOUT_L(5)
L2_CADOUT_H(4)
L2_CADOUT_L(4)
L2_CADOUT_H(3)
L2_CADOUT_L(3)
L2_CADOUT_H(2)
L2_CADOUT_L(2)
L2_CADOUT_H(1)
L2_CADOUT_L(1)
L2_CADOUT_H(0)
L2_CADOUT_L(0)
L2_CLKOUT_H(1)
L2_CLKOUT_L(1)
L2_CLKOUT_H(0)
L2_CLKOUT_L(0)
L2_CTLOUT_H(0)
L2_CTLOUT_L(0)
L2_RSVD3
L2_RSVD4
AH14
AJ14
AG16
AG15
AH16
AJ16
AG18
AG17
AG20
AG19
AH20
AJ20
AG22
AG21
AH22
AJ22
AL14
AL13
AK15
AJ15
AL16
AL15
AK17
AJ17
AK19
AJ19
AL20
AL19
AK21
AJ21
AL22
AL21
AH18
AJ18
AL18
AL17
AK13
AJ13
AG13
AG14
L0_CADOUT15
L0_CADOUT#15
L0_CADOUT14
L0_CADOUT#14
L0_CADOUT13
L0_CADOUT#13
L0_CADOUT12
L0_CADOUT#12
L0_CADOUT11
L0_CADOUT#11
L0_CADOUT10
L0_CADOUT#10
L0_CADOUT9
L0_CADOUT#9
L0_CADOUT8
L0_CADOUT#8
L0_CADOUT7
L0_CADOUT#7
L0_CADOUT6
L0_CADOUT#6
L0_CADOUT5
L0_CADOUT#5
L0_CADOUT4
L0_CADOUT#4
L0_CADOUT3
L0_CADOUT#3
L0_CADOUT2
L0_CADOUT#2
L0_CADOUT1
L0_CADOUT#1
L0_CADOUT0
L0_CADOUT#0
L0_CLKOUT1
L0_CLKOUT#1
L0_CLKOUT0
L0_CLKOUT#0
L0_CTLOUT0
L0_CTLOUT#0
L0_CADOUT[15..0] <16>
L0_CADOUT#[15..0] <16>
L0_CLKOUT1 <16>
L0_CLKOUT#1 <16>
L0_CLKOUT0 <16>
L0_CLKOUT#0 <16>
L0_CTLOUT0 <16>
L0_CTLOUT#0 <16>
A A
5
4
3
2
Micro S tar Res tricte d Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69 , Li-De St, Jung-He City,
Taipei Hs ien, Taiwan
http://www.msi.com.tw
CPU0_K8 HT0 & HT2
MS-9620
1
Last Revision Date:
Thurs day, Februa ry 17, 2005
Sheet
644
Rev
0A
of
5
4
3
2
1
http://adf.ly/3o8pJ
D D
EMI
LAYOUT:
LAYOUT: Place solder side of processor.
VCCP0
C2605
X_(BOT)SP-CAP,220u/2V
C2557
X_(BOT)SP-CAP,220u/2V
4.7u/1206
VCCP0
C2547
C2606
4.7u/1206
LAYOUT: Place clolse to socket.
C C
4.7u/1206
C2085
C2087
4.7u/1206
4.7u/1206
C2166
C2167
C2104
C2139
4.7u/1206
4.7u/1206
4.7u/1206
4.7u/1206
C2127
BULK / Decopuling
Place on CPU Solder side
VCCP0
C2551
C2550
0.22u/16V/X7R
C2552
0.22u/16V/X7R
0.22u/16V/X7R
Buck-decoupling Mid-Freq. decoupling Cap. ( 7 * 4.7uF / 1206 X7R )
VCCP0
C2086
4.7u/1206
C2137
4.7u/1206
Place 1 capacitor every 1-1.5" along VDD_CORE perimiter.
VCCP0
C2102
6.8p /50V/NPO
C2162
6.8p /50V/NPO
C2151
6.8p /50V/NPO
C2184
C2133
C2161
C2075
6.8p /50V/NPO
6.8p /50V/NPO
6.8p /50V/NPO
6.8p /50V/NPO
LAYOUT:
Place 1000pF capacitors between VRM & CPU.
VCCP0VCCP0
C2142
1000P/50V/X7R
C2049
1000P/50V/X7R
C2117
1000P/50V/X7R
C2058
1000P/50V/X7R
C2129
6.8p /50V/NPO
C2135
6.8p /50V/NPO
C2125
6.8p /50V/NPO
C2120
C2113
6.8p /50V/NPO
6.8p /50V/NPO
Buck-decoupling Mid-Freq. decoupling Cap. ( 7 * 4.7uF / 1206 X7R )
VCCP0
C2116
4.7u/1206
PLEASE THESE PARTS UNDER SOLDER SIDE OF U27
AD22
VDDIO48
VSS47M9VSS48P9VSS50
AB13
VCCP0
U19
W19
D20
AE4
M20
P20
T20
V20
Y20
AK20
B21
AH21
AK4
AH5
AB6
AF6
AB8
AK8
K18
AA9
AB18
AH9
W13
M10
P10
T10
V10
Y10
AB12
AF10
F11
L11
N11
R11
U11
W11
AA11
AD2
D12
M12
P12
T12
V12
Y12
AC13
AK12
B13
L13
N13
R13
U13
AA13
AH13
J13
M14
P14
T14
V14
Y14
AD14
AF14
F15
L15
N15
R15
U15
W15
AA15
D16
F18
AA4
T18
V18
Y18
F19
N19
AF20
AC23
AB23
VDDIOFB_L
VDDIOFB_H
VDDIO_SENSE
VSS51Y9VSS52
VSS53
VSS49
T9
D10
AB9
AD9
AC22
R19
AD12
K12
VDD1H2VDD2
VDD3
VDD4
VDD5
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23B5VDD24
VDD25K6VDD26P6VDD27T8VDD28
VDD29
VDD30M2VDD31F6VDD32D8VDD33G7VDD34
VDD35
VDD36B9VDD37
VDD38L9VDD39N9VDD40R9VDD41T2VDD42U9VDD43W9VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52Y2VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74D4VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84J4VDD85
VDD117V6VDD118
VDD119
VSS54
VSS55
VSS97
VSS56
VSS57
VSS58
VSS59
VSS60T6VSS61
VSS62
VSS63
VSS64
VSS98
VSS65
VSS66J8VSS67
VSS68
VSS69
VSS70
VSS71
VSS99
VSS72
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS101
VSS90
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS100
VSS81
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS182
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS183
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS184
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
J10
L10
L14
T11
B11
K11
P11
V11
N10
R10
U10
AA10
AD13
AC10
Y11
H15
N14
N16
M11
AK10
AF12
AA12
J12
F13
F10
K13
U14
N12
R12
U12
G15
AD15
R14
G13
M13
W12
W14
AB11
AA14
AD11
AH11
AC14
AH15
J14
L16
T15
B15
K15
B23
P15
V15
Y15
D14
H17
R16
U16
G24
M15
AK14
3
W18
AB15
AA16
AC17
VSS134
F16
T17
K17
P17
V17
Y17
N24
D18
M17
AF16
AB17
AD17
VDD86
VSS135
VSS185
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS186
J18
L18
B19
K19
N18
R18
U18
G30
W24
W10
AA18
AE17
AK18
M16
P16
T16
V16
Y16
AD16
AK16
B17
L17
N17
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
VDD93
VDD94
VDD95N4VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106U4VDD107
VDD108
VDD109
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS187
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS188
VSS163
VSS164
J20
L20
T19
V19
Y19
N20
R20
M19
W30
AB19
AH19
VSS165
T21
K21
P21
V21
U20
M21
W20
AF21
AA20
AB24
AC20
2
Sled geHammer
R17
U17
W17
AA17
AH17
M18
P18
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS189
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
J22
L22
Y21
B26
D22
N22
R22
U22
G22
W22
AB21
AA22
AE22
AK22
AE24
AK26
P13
W16
AG2
E2
D23
AH23
VSS5
VSS91
VSS203
VSS202
VSS200
VSS201
VSS190
VSS181
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS1
VSS2V9VSS3
VSS4
L12
T24
T30
B29
K24
K30
D30
AH7
AK23
AE30
AK29
AB30
AH30
AC12
Micro Star Restricted Secret
Title
Docume nt Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taip ei Hs ien, Taiwan
http://www.msi.com .tw
1
CPU0 _K8 POWER & GND
MS-9 620
Last Revision Date:
Sheet
Rev
Tues day, Febr uary 15, 2005
of
744
0A
VCC_DDR
AB22
AJ23
AA19
C23
E23
K26
T26
AE28
G26
N26
W26
AE26
AG23
K20
D28
K28
T28
AB28
AH28
AH26
G28
N28
W28
AB26
AB20
L21
N21
R21
U21
H22
D26
K22
A23
U23
AL23
L19
W21
AA21
J21
M22
P22
T22
V22
B B
U2006D
A A
5
Y22
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VSS6
VSS7
VSS8
VSS9F1VSS10F2VSS11K2VSS12P2VSS92
VSS13V2VSS14
VSS15
VSS16
VSS17B3VSS18
VSS19G4VSS20L4VSS21R4VSS93
VSS22W4VSS23
VSS24F5VSS25D6VSS26H6VSS27M7VSS28
VSS29Y6VSS30
VSS94
VSS31
VSS32B7VSS33
VSS34P7VSS35V7VSS36Y7VSS37M6VSS95
F17
T13
P19
N30
AF2
AB2
AK2
AH3
J17
V13
F14
AB7
AK6
AC4
AD6
AC21
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO47
VSS38N8VSS39R8VSS40U8VSS41W8VSS42
VSS43
VSS44F8VSS45
VSS46K9VSS96
Y13
AF8
G17
AA8
4
5
Registered DDR333 SDRAM Sockets
4
3
2
1
http://adf.ly/3o8pJ
D D
DDR _VREF
1000P/50V/X7R
VCC_DDR
C2032
H0_DR_MD0
H0_DR_MD1
H0_DR_MD2
H0_DR_MD3
H0_DR_MD4
H0_DR_MD5
H0_DR_MD6
H0_DR_MD7
H0_DR_MD8
H0_DR_MD9
H0_DR_MD10
H0_DR_MD11
H0_DR_MD12
H0_DR_MD13
H0_DR_MD14
H0_DR_MD15
H0_DR_MD16
H0_DR_MD17
H0_DR_MD18
H0_DR_MD19
H0_DR_MD20
H0_DR_MD21
H0_DR_MD22
H0_DR_MD23
H0_DR_MD24
H0_DR_MD25
H0_DR_MD26
H0_DR_MD27
H0_DR_MD28
H0_DR_MD29
H0_DR_MD30
H0_DR_MD31
H0_DR_MD32
H0_DR_MD33
H0_DR_MD34
H0_DR_MD35
H0_DR_MD36
H0_DR_MD37
H0_DR_MD38
H0_DR_MD39
H0_DR_MD40
H0_DR_MD41
H0_DR_MD42
H0_DR_MD43
H0_DR_MD44
H0_DR_MD45
H0_DR_MD46
H0_DR_MD47
H0_DR_MD48
H0_DR_MD49
H0_DR_MD50
H0_DR_MD51
H0_DR_MD52
H0_DR_MD53
H0_DR_MD54
H0_DR_MD55
H0_DR_MD56
H0_DR_MD57
H0_DR_MD58
H0_DR_MD59
H0_DR_MD60
H0_DR_MD61
H0_DR_MD62
H0_DR_MD63
H0_DR_MD[63..0]<9,10,11>
C C
B B
H0_DR_-MSWEA<9,10,11>
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
C2016
101
102
1000P/50V/X7R
VCC_DDR
2
DQ0
4
DQ1
6
DQ2
8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
1
VREF
9
NC2
NC3
NC4
VDD07VDD138VDD246VDD370VDD485VDD5
Channel A
108
120
148
168
104
112
128
136
143
156
164
172
180
15
VDD6
VDD7
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
PIN
184
DDR DIMM
SOCKET
NC(RESET#)
SLAVE ADDRESS = 1010000B
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
116
124
132
139
145
152
160
176
82
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
CKE0
CKE1
CAS#
RAS#
VSS21
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DDR2000
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
SMB_MEM_CLK
SMB_MEM_DATA
H0_DR_-MCS0 <11>
H0_DR_-MCS1 <11>
H0_DR _MDQS0 <9,10,11>
H0_DR _MDQS1 <9,10,11>
H0_DR _MDQS2 <9,10,11>
H0_DR _MDQS3 <9,10,11>
H0_DR _MDQS4 <9,10,11>
H0_DR _MDQS5 <9,10,11>
H0_DR _MDQS6 <9,10,11>
H0_DR _MDQS7 <9,10,11>
H0_DR _MDQS8 <9,10,11>
H0_DR _MAA13 <9 ,10,11>
H0_DR _MAA0 < 9,10,11>
H0_DR _MAA1 < 9,10,11>
H0_DR _MAA2 < 9,10,11>
H0_DR _MAA3 < 9,10,11>
H0_DR _MAA4 < 9,10,11>
H0_DR _MAA5 < 9,10,11>
H0_DR _MAA6 < 9,10,11>
H0_DR _MAA7 < 9,10,11>
H0_DR _MAA8 < 9,10,11>
H0_DR _MAA9 < 9,10,11>
H0_DR _MAA10 <9 ,10,11>
H0_DR _MAA11 <9 ,10,11>
H0_DR _MAA12 <9 ,10,11>
H0_DR _MEMBAKA0 < 9,10,11>
H0_DR _MEMBAKA1 < 9,10,11>
SMB_MEM_CLK <9,10,17>
SMB_MEM_DATA <9,10,17>
H0_DR_MEMCHECK0 <9,10,11>
H0_DR_MEMCHECK1 <9,10,11>
H0_DR_MEMCHECK2 <9,10,11>
H0_DR_MEMCHECK3 <9,10,11>
H0_DR_MEMCHECK4 <9,10,11>
H0_DR_MEMCHECK5 <9,10,11>
H0_DR_MEMCHECK6 <9,10,11>
H0_DR_MEMCHECK7 <9,10,11>
H0_ME MCLK_H0 <4>
H0_MEM CLK_L0 <4>
H0_MEMRESET _L <4,9,10>
H0_DR _MCKELO <9,10,11>
H0_DR _MCKEUP <9 ,10,11>
H0_DR _-MSCASA <9,10,11>
H0_DR _-MSRASA <9,10,11>
H0_DR _MDQS9 <9,10,11>
H0_DR _MDQS10 <9,10,11>
H0_DR _MDQS11 <9,10,11>
H0_DR _MDQS12 <9,10,11>
H0_DR _MDQS13 <9,10,11>
H0_DR _MDQS14 <9,10,11>
H0_DR _MDQS15 <9,10,11>
H0_DR _MDQS16 <9,10,11>
H0_DR _MDQS17 <9,10,11>
VCC_DDR
VDD07VDD138VDD246VDD370VDD485VDD5
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
DDR _VREF
1000P/50V/X7R
H0_DR_MD64
H0_DR_MD65
H0_DR_MD66
H0_DR_MD67
H0_DR_MD68
H0_DR_MD69
H0_DR_MD70
H0_DR_MD71
H0_DR_MD72
H0_DR_MD73
H0_DR_MD74
H0_DR_MD75
H0_DR_MD76
H0_DR_MD77
H0_DR_MD78
H0_DR_MD79
H0_DR_MD80
H0_DR_MD81
H0_DR_MD82
H0_DR_MD83
H0_DR_MD84
H0_DR_MD85
H0_DR_MD86
H0_DR_MD87
H0_DR_MD88
H0_DR_MD89
H0_DR_MD90
H0_DR_MD91
H0_DR_MD92
H0_DR_MD93
H0_DR_MD94
H0_DR_MD95
H0_DR_MD96
H0_DR_MD97
H0_DR_MD98
H0_DR_MD99
H0_DR_MD100
H0_DR_MD101
H0_DR_MD102
H0_DR_MD103
H0_DR_MD104
H0_DR_MD105
H0_DR_MD106
H0_DR_MD107
H0_DR_MD108
H0_DR_MD109
H0_DR_MD110
H0_DR_MD111
H0_DR_MD112
H0_DR_MD113
H0_DR_MD114
H0_DR_MD115
H0_DR_MD116
H0_DR_MD117
H0_DR_MD118
H0_DR_MD119
H0_DR_MD120
H0_DR_MD121
H0_DR_MD122
H0_DR_MD123
H0_DR_MD124
H0_DR_MD125
H0_DR_MD126
H0_DR_MD127
H0_DR_-MSWEA
C2034
VCC_DDR
C2042
1000P/50V/X7R
H0_DR _MD[127.. 64]<9,10,11>
Channel B
108
120
148
168
VDD6
VDD7
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
DDR DIMM
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
DDR2001
104
112
128
136
143
156
164
172
180
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
184
SOCKET
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
100
116
124
132
139
145
152
160
15
VDDQ14
VDDQ15
PIN
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
82
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
CK0(DU)
CK2(DU)
CKE0
CKE1
CAS#
RAS#
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
H0_DR_MCKELO
21
H0_DR_MCKEUP
111
65
154
97
107
119
129
149
159
169
177
140
H0_DR_-MCS0 <11>
H0_DR_-MCS1 <11>
H0_DR _MDQS18 <9,10,11>
H0_DR _MDQS19 <9,10,11>
H0_DR _MDQS20 <9,10,11>
H0_DR _MDQS21 <9,10,11>
H0_DR _MDQS22 <9,10,11>
H0_DR _MDQS23 <9,10,11>
H0_DR _MDQS24 <9,10,11>
H0_DR _MDQS25 <9,10,11>
H0_DR _MDQS26 <9,10,11>
H0_DR _MAA13 <9 ,10,11>
H0_DR _MAA0 < 9,10,11>
H0_DR _MAA1 < 9,10,11>
H0_DR _MAA2 < 9,10,11>
H0_DR _MAA3 < 9,10,11>
H0_DR _MAA4 < 9,10,11>
H0_DR _MAA5 < 9,10,11>
H0_DR _MAA6 < 9,10,11>
H0_DR _MAA7 < 9,10,11>
H0_DR _MAA8 < 9,10,11>
H0_DR _MAA9 < 9,10,11>
H0_DR _MAA10 <9 ,10,11>
H0_DR _MAA11 <9 ,10,11>
H0_DR _MAA12 <9 ,10,11>
H0_DR _MEMBAKA0 < 9,10,11>
H0_DR _MEMBAKA1 < 9,10,11>
SMB_MEM_CLK
SMB_MEM_DATA
VCC_DDR
H0_DR_MEMCHECK8 <9,10,11>
H0_DR_MEMCHECK9 <9,10,11>
H0_DR_MEMCHECK10 <9,10,11>
H0_DR_MEMCHECK11 <9,10,11>
H0_DR_MEMCHECK12 <9,10,11>
H0_DR_MEMCHECK13 <9,10,11>
H0_DR_MEMCHECK14 <9,10,11>
H0_DR_MEMCHECK15 <9,10,11>
H0_MEMCLK_H2 <4>
H0_MEM CLK_L2 <4>
H0_MEMRESET _L <4,9,10>
H0_DR _-MSCASA <9,10,11>
H0_DR _-MSRASA <9,10,11>
H0_DR _MDQS27 <9,10,11>
H0_DR _MDQS28 <9,10,11>
H0_DR _MDQS29 <9,10,11>
H0_DR _MDQS30 <9,10,11>
H0_DR _MDQS31 <9,10,11>
H0_DR _MDQS32 <9,10,11>
H0_DR _MDQS33 <9,10,11>
H0_DR _MDQS34 <9,10,11>
H0_DR _MDQS35 <9,10,11>
DDR_VREFVCC_DDR
C2033
R2013
100RST
0.1u
C2014
A A
5
4
R2007
100RST
C2015
1000P/50V/X7R
0.1u
Micro S tar Restricted Secret
Title
CPU0 Register DDR DIMM1 & 2
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
3
2
http:// www.msi.com.tw
MS-9620
1
Last Revision Date:
Tuesd ay, Feb ruary 15, 2005
Sheet
Rev
0A
of
844
5
4
3
2
1
Registered DDR333 SDRAM Sockets
Channel A
VCC_DDR
D D
H0_D R_MD[63..0]<8,10,11>
C C
B B
H0_DR _-MSWEA<8,10,11>
DDR_VREF
H0_DR_MD0
H0_DR_MD1
H0_DR_MD2
H0_DR_MD3
H0_DR_MD4
H0_DR_MD5
H0_DR_MD6
H0_DR_MD7
H0_DR_MD8
H0_DR_MD9
H0_DR _MD10
H0_DR _MD11
H0_DR _MD12
H0_DR _MD13
H0_DR _MD14
H0_DR _MD15
H0_DR _MD16
H0_DR _MD17
H0_DR _MD18
H0_DR _MD19
H0_DR _MD20
H0_DR _MD21
H0_DR _MD22
H0_DR _MD23
H0_DR _MD24
H0_DR _MD25
H0_DR _MD26
H0_DR _MD27
H0_DR _MD28
H0_DR _MD29
H0_DR _MD30
H0_DR _MD31
H0_DR _MD32
H0_DR _MD33
H0_DR _MD34
H0_DR _MD35
H0_DR _MD36
H0_DR _MD37
H0_DR _MD38
H0_DR _MD39
H0_DR _MD40
H0_DR _MD41
H0_DR _MD42
H0_DR _MD43
H0_DR _MD44
H0_DR _MD45
H0_DR _MD46
H0_DR _MD47
H0_DR _MD48
H0_DR _MD49
H0_DR _MD50
H0_DR _MD51
H0_DR _MD52
H0_DR _MD53
H0_DR _MD54
H0_DR _MD55
H0_DR _MD56
H0_DR _MD57
H0_DR _MD58
H0_DR _MD59
H0_DR _MD60
H0_DR _MD61
H0_DR _MD62
H0_DR _MD63
C2036
1000P/50V/X7R
VCC_DDR VCC_DDR
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
C2025
101
102
1000P/50V/X7R
2
4
6
8
1
9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
NC4
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
SLAVE ADDRESS = 1010010B
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
143
104
112
128
136
VDDQ7
VDDQ8
VDDQ9
184 PIN
DDR DIMM
SOCKET
VSS14
VSS15
100
116
124
132
156
164
172
180
15
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
CK1#(CK0#)
NC(RESET#)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
139
145
152
160
176
82
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DDR2002
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
SMB_MEM_CLK
SMB_MEM_DATA
http://adf.ly/3o8pJ
H0_DR _-MCS2 <11>
H0_DR _MDQS0 <8,10,11>
H0_DR _MDQS1 <8,10,11>
H0_DR _MDQS2 <8,10,11>
H0_DR _MDQS3 <8,10,11>
H0_DR _MDQS4 <8,10,11>
H0_DR _MDQS5 <8,10,11>
H0_DR _MDQS6 <8,10,11>
H0_DR _MDQS7 <8,10,11>
H0_DR _MDQS8 <8,10,11>
H0_DR_MAA13 <8,10,11>
H0_DR_MAA0 <8,10,11>
H0_DR_MAA1 <8,10,11>
H0_DR_MAA2 <8,10,11>
H0_DR_MAA3 <8,10,11>
H0_DR_MAA4 <8,10,11>
H0_DR_MAA5 <8,10,11>
H0_DR_MAA6 <8,10,11>
H0_DR_MAA7 <8,10,11>
H0_DR_MAA8 <8,10,11>
H0_DR_MAA9 <8,10,11>
H0_DR_MAA10 <8,10,11>
H0_DR_MAA11 <8,10,11>
H0_DR_MAA12 <8,10,11>
H0_DR_MEMBAKA0 <8,10,11>
H0_DR_MEMBAKA1 <8,10,11>
VCC_DDR
H0_DR _MEMCHECK0 < 8,10,11>
H0_DR _MEMCHECK1 < 8,10,11>
H0_DR _MEMCHECK2 < 8,10,11>
H0_DR _MEMCHECK3 < 8,10,11>
H0_DR _MEMCHECK4 < 8,10,11>
H0_DR _MEMCHECK5 < 8,10,11>
H0_DR _MEMCHECK6 < 8,10,11>
H0_DR _MEMCHECK7 < 8,10,11>
H0_MEMCLK_H1 <4>
H0_MEMCLK_L1 <4>
H0_MEMRESET_L <4 ,8,10>
H0_DR _MCKELO <8,1 0,11>
H0_DR _MCKEUP <8 ,10,11>
H0_DR _-MSCASA <8,10 ,11>
H0_DR _-MSRASA <8,10 ,11>
H0_DR _MDQS9 <8,10,11>
H0_DR _MDQS10 <8,10,11>
H0_DR _MDQS11 <8,10,11>
H0_DR _MDQS12 <8,10,11>
H0_DR _MDQS13 <8,10,11>
H0_DR _MDQS14 <8,10,11>
H0_DR _MDQS15 <8,10,11>
H0_DR _MDQS16 <8,10,11>
H0_DR _MDQS17 <8,10,11>
H0_DR_MD[127..64]<8,10,11>
H0_DR _-MSWEA<8,10,11>
DDR_VREF
1000P/50V/X7R
DDR_VREF
H0_DR _MD64
H0_DR _MD65
H0_DR _MD66
H0_DR _MD67
H0_DR _MD68
H0_DR _MD69
H0_DR _MD70
H0_DR _MD71
H0_DR _MD72
H0_DR _MD73
H0_DR _MD74
H0_DR _MD75
H0_DR _MD76
H0_DR _MD77
H0_DR _MD78
H0_DR _MD79
H0_DR _MD80
H0_DR _MD81
H0_DR _MD82
H0_DR _MD83
H0_DR _MD84
H0_DR _MD85
H0_DR _MD86
H0_DR _MD87
H0_DR _MD88
H0_DR _MD89
H0_DR _MD90
H0_DR _MD91
H0_DR _MD92
H0_DR _MD93
H0_DR _MD94
H0_DR _MD95
H0_DR _MD96
H0_DR _MD97
H0_DR _MD98
H0_DR _MD99
H0_DR _MD100
H0_DR _MD101
H0_DR _MD102
H0_DR _MD103
H0_DR _MD104
H0_DR _MD105
H0_DR _MD106
H0_DR _MD107
H0_DR _MD108
H0_DR _MD109
H0_DR _MD110
H0_DR _MD111
H0_DR _MD112
H0_DR _MD113
H0_DR _MD114
H0_DR _MD115
H0_DR _MD116
H0_DR _MD117
H0_DR _MD118
H0_DR _MD119
H0_DR _MD120
H0_DR _MD121
H0_DR _MD122
H0_DR _MD123
H0_DR _MD124
H0_DR _MD125
H0_DR _MD126
H0_DR _MD127
C2035
VCC_DDR
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
C2047
101
102
1000P/50V/X7R
Channel B
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
1
VREF
9
NC2
NC3
SLAVE ADDRESS = 1010011B
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
DDR DIMM
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
143
156
164
172
104
112
180
128
136
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
184 PIN
SOCKET
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
100
116
124
132
139
145
152
160
15
82
VDDQ14
VDDQ15
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
DDR2003
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
H0_DR _MCKELO
21
H0_DR _MCKEUP
111
65
154
97
107
119
129
149
159
169
177
140
SMB_MEM_CLK
SMB_MEM_DATA
H0_DR _-MCS2 <11>
H0_DR _-MCS3 <11>H0_DR _-MCS3 <11>
H0_DR _MDQS18 <8,10 ,11>
H0_DR _MDQS19 <8,10 ,11>
H0_DR _MDQS20 <8,10 ,11>
H0_DR _MDQS21 <8,10 ,11>
H0_DR _MDQS22 <8,10 ,11>
H0_DR _MDQS23 <8,10 ,11>
H0_DR _MDQS24 <8,10 ,11>
H0_DR _MDQS25 <8,10 ,11>
H0_DR _MDQS26 <8,10 ,11>
H0_DR _MAA13 <8,10,11>
H0_DR_MAA0 <8,10,11>
H0_DR_MAA1 <8,10,11>
H0_DR_MAA2 <8,10,11>
H0_DR_MAA3 <8,10,11>
H0_DR_MAA4 <8,10,11>
H0_DR_MAA5 <8,10,11>
H0_DR_MAA6 <8,10,11>
H0_DR_MAA7 <8,10,11>
H0_DR_MAA8 <8,10,11>
H0_DR_MAA9 <8,10,11>
H0_DR _MAA10 <8,10,11>
H0_DR _MAA11 <8,10,11>
H0_DR _MAA12 <8,10,11>
H0_DR_MEMBAKA0 <8,10,11>
H0_DR_MEMBAKA1 <8,10,11>
SMB_MEM_CLK <8,10 ,17>
SMB_MEM_DATA <8,10,17>
VCC_DDR
H0_DR _MEMCHECK8 < 8,10,11>
H0_DR _MEMCHECK9 < 8,10,11>
H0_DR _MEMCHECK10 < 8,10,11>
H0_DR _MEMCHECK11 < 8,10,11>
H0_DR _MEMCHECK12 < 8,10,11>
H0_DR _MEMCHECK13 < 8,10,11>
H0_DR _MEMCHECK14 < 8,10,11>
H0_DR _MEMCHECK15 < 8,10,11>
H0_MEMCLK_H3 <4>
H0_MEMCLK_L3 <4>
H0_MEMRESET_L < 4,8,10>
H0_DR _-MSCASA <8,1 0,11>
H0_DR _-MSRASA <8,1 0,11>
H0_DR _MDQS27 <8,10 ,11>
H0_DR _MDQS28 <8,10 ,11>
H0_DR _MDQS29 <8,10 ,11>
H0_DR _MDQS30 <8,10 ,11>
H0_DR _MDQS31 <8,10 ,11>
H0_DR _MDQS32 <8,10 ,11>
H0_DR _MDQS33 <8,10 ,11>
H0_DR _MDQS34 <8,10 ,11>
H0_DR _MDQS35 <8,10 ,11>
A A
5
4
C2038
0.1u
3
C2030
1000P/50V/X7R
Micro Star R estric ted Se cret
Title
Document Number
2
CPU0 Register DDR DIMM3,4
MS- 9620
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http:/ /www.msi.com.tw
Last Revision Date:
Sheet
1
Tuesday, F ebruary 15, 2005
944
Rev
0A
of
5
4
3
2
1
Registered DDR333 SDRAM Sockets
Channel A
VCC_DDR
D D
H0_D R_MD[63..0]<8,9 ,11>
C C
B B
H0_DR _-MSWEA<8,9,11>
DDR_VREF
H0_DR_MD0
H0_DR_MD1
H0_DR_MD2
H0_DR_MD3
H0_DR_MD4
H0_DR_MD5
H0_DR_MD6
H0_DR_MD7
H0_DR_MD8
H0_DR_MD9
H0_DR _MD10
H0_DR _MD11
H0_DR _MD12
H0_DR _MD13
H0_DR _MD14
H0_DR _MD15
H0_DR _MD16
H0_DR _MD17
H0_DR _MD18
H0_DR _MD19
H0_DR _MD20
H0_DR _MD21
H0_DR _MD22
H0_DR _MD23
H0_DR _MD24
H0_DR _MD25
H0_DR _MD26
H0_DR _MD27
H0_DR _MD28
H0_DR _MD29
H0_DR _MD30
H0_DR _MD31
H0_DR _MD32
H0_DR _MD33
H0_DR _MD34
H0_DR _MD35
H0_DR _MD36
H0_DR _MD37
H0_DR _MD38
H0_DR _MD39
H0_DR _MD40
H0_DR _MD41
H0_DR _MD42
H0_DR _MD43
H0_DR _MD44
H0_DR _MD45
H0_DR _MD46
H0_DR _MD47
H0_DR _MD48
H0_DR _MD49
H0_DR _MD50
H0_DR _MD51
H0_DR _MD52
H0_DR _MD53
H0_DR _MD54
H0_DR _MD55
H0_DR _MD56
H0_DR _MD57
H0_DR _MD58
H0_DR _MD59
H0_DR _MD60
H0_DR _MD61
H0_DR _MD62
H0_DR _MD63
C1049
1000P/50V/X7R
VCC_DDR VCC_DDR
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
C1050
101
102
1000P/50V/X7R
2
4
6
8
1
9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
NC4
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
SLAVE ADDRESS = 1010100B
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
143
104
112
128
136
VDDQ7
VDDQ8
VDDQ9
184 PIN
DDR DIMM
SOCKET
VSS14
VSS15
100
116
124
132
156
164
172
180
15
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
CK1#(CK0#)
NC(RESET#)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
139
145
152
160
176
82
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DDR5
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
H0_DR _-MCS4
H0_DR _-MCS5
SMB_MEM_CLK
SMB_MEM_DATA
H0_MEMCLK_H4
H0_MEMCLK_L4
http://adf.ly/3o8pJ
Channel B
VCC_DDR
DDR6
143
156
164
172
180
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
SLAVE ADDRESS = 1010101B
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
C1051
1000P/50V/X7R
H0_DR _MD64
H0_DR _MD65
H0_DR _MD66
H0_DR _MD67
H0_DR _MD68
H0_DR _MD69
H0_DR _MD70
H0_DR _MD71
H0_DR _MD72
H0_DR _MD73
H0_DR _MD74
H0_DR _MD75
H0_DR _MD76
H0_DR _MD77
H0_DR _MD78
H0_DR _MD79
H0_DR _MD80
H0_DR _MD81
H0_DR _MD82
H0_DR _MD83
H0_DR _MD84
H0_DR _MD85
H0_DR _MD86
H0_DR _MD87
H0_DR _MD88
H0_DR _MD89
H0_DR _MD90
H0_DR _MD91
H0_DR _MD92
H0_DR _MD93
H0_DR _MD94
H0_DR _MD95
H0_DR _MD96
H0_DR _MD97
H0_DR _MD98
H0_DR _MD99
H0_DR _MD100
H0_DR _MD101
H0_DR _MD102
H0_DR _MD103
H0_DR _MD104
H0_DR _MD105
H0_DR _MD106
H0_DR _MD107
H0_DR _MD108
H0_DR _MD109
H0_DR _MD110
H0_DR _MD111
H0_DR _MD112
H0_DR _MD113
H0_DR _MD114
H0_DR _MD115
H0_DR _MD116
H0_DR _MD117
H0_DR _MD118
H0_DR _MD119
H0_DR _MD120
H0_DR _MD121
H0_DR _MD122
H0_DR _MD123
H0_DR _MD124
H0_DR _MD125
H0_DR _MD126
H0_DR _MD127
H0_DR _-MCS4 <11>
H0_DR _-MCS5 <11>
H0_DR _MDQS0 <8,9,11>
H0_DR _MDQS1 <8,9,11>
H0_DR _MDQS2 <8,9,11>
H0_DR _MDQS3 <8,9,11>
H0_DR _MDQS4 <8,9,11>
H0_DR _MDQS5 <8,9,11>
H0_DR _MDQS6 <8,9,11>
H0_DR _MDQS7 <8,9,11>
H0_DR _MDQS8 <8,9,11>
H0_DR_MAA13 <8,9,11>
H0_DR_MAA0 <8,9,11>
H0_DR_MAA1 <8,9,11>
H0_DR_MAA2 <8,9,11>
H0_DR_MAA3 <8,9,11>
H0_DR_MAA4 <8,9,11>
H0_DR_MAA5 <8,9,11>
H0_DR_MAA6 <8,9,11>
H0_DR_MAA7 <8,9,11>
H0_DR_MAA8 <8,9,11>
H0_DR_MAA9 <8,9,11>
H0_DR_MAA10 <8,9,11>
H0_DR_MAA11 <8,9,11>
H0_DR_MAA12 <8,9,11>
H0_DR_MEMBAKA0 <8,9,11>
H0_DR_MEMBAKA1 <8,9,11>
SMB_MEM_CLK <8,9, 17>
SMB_MEM_DATA <8,9,17>
VCC_DDR VCC_DDR
H0_DR _MEMCHECK0 < 8,9,11>
H0_DR _MEMCHECK1 < 8,9,11>
H0_DR _MEMCHECK2 < 8,9,11>
H0_DR _MEMCHECK3 < 8,9,11>
H0_DR _MEMCHECK4 < 8,9,11>
H0_DR _MEMCHECK5 < 8,9,11>
H0_DR _MEMCHECK6 < 8,9,11>
H0_DR _MEMCHECK7 < 8,9,11>
H0_MEMCLK_H4 <4>
H0_MEMCLK_L4 <4>
H0_MEMRESET_L <4 ,8,9>
H0_DR _MCKELO <8,9 ,11>
H0_DR _MCKEUP <8 ,9,11>
H0_DR _-MSCASA <8,9, 11>
H0_DR _-MSRASA <8,9, 11>
H0_DR _MDQS9 <8,9,11>
H0_DR _MDQS10 <8,9,11>
H0_DR _MDQS11 <8,9,11>
H0_DR _MDQS12 <8,9,11>
H0_DR _MDQS13 <8,9,11>
H0_DR _MDQS14 <8,9,11>
H0_DR _MDQS15 <8,9,11>
H0_DR _MDQS16 <8,9,11>
H0_DR _MDQS17 <8,9,11>
H0_DR_MD[127..64]<8,9,11>
H0_DR _-MSWEA<8,9,11>
DDR_VREF
DDR_VREF
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
C1052
101
102
1000P/50V/X7R
2
DQ0
4
DQ1
6
DQ2
8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
1
VREF
9
NC2
NC3
NC4
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
104
112
128
VDDQ7
184 PIN
DDR DIMM
SOCKET
100
116
15
136
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
CK1#(CK0#)
NC(RESET#)
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
124
132
139
145
152
160
176
82
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
DDRDIMM_184
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
H0_DR _MCKELO
21
H0_DR _MCKEUP
111
65
154
97
107
119
129
149
159
169
177
140
H0_DR _-MCS4
H0_DR _-MCS5
SMB_MEM_CLK
SMB_MEM_DATA
H0_MEMCLK_H5
H0_MEMCLK_L5
H0_DR _-MCS4 <11>
H0_DR _-MCS5 <11>
H0_DR _MDQS18 <8,9, 11>
H0_DR _MDQS19 <8,9, 11>
H0_DR _MDQS20 <8,9, 11>
H0_DR _MDQS21 <8,9, 11>
H0_DR _MDQS22 <8,9, 11>
H0_DR _MDQS23 <8,9, 11>
H0_DR _MDQS24 <8,9, 11>
H0_DR _MDQS25 <8,9, 11>
H0_DR _MDQS26 <8,9, 11>
H0_DR _MAA13 <8,9,11>
H0_DR_MAA0 <8,9,11>
H0_DR_MAA1 <8,9,11>
H0_DR_MAA2 <8,9,11>
H0_DR_MAA3 <8,9,11>
H0_DR_MAA4 <8,9,11>
H0_DR_MAA5 <8,9,11>
H0_DR_MAA6 <8,9,11>
H0_DR_MAA7 <8,9,11>
H0_DR_MAA8 <8,9,11>
H0_DR_MAA9 <8,9,11>
H0_DR _MAA10 <8,9,11>
H0_DR _MAA11 <8,9,11>
H0_DR _MAA12 <8,9,11>
H0_DR_MEMBAKA0 <8,9,11>
H0_DR_MEMBAKA1 <8,9,11>
SMB_MEM_CLK <8,9 ,17>
SMB_MEM_DATA <8,9,17>
VCC_DDR
H0_DR _MEMCHECK8 < 8,9,11>
H0_DR _MEMCHECK9 < 8,9,11>
H0_DR _MEMCHECK10 < 8,9,11>
H0_DR _MEMCHECK11 < 8,9,11>
H0_DR _MEMCHECK12 < 8,9,11>
H0_DR _MEMCHECK13 < 8,9,11>
H0_DR _MEMCHECK14 < 8,9,11>
H0_DR _MEMCHECK15 < 8,9,11>
H0_MEMCLK_H5 <4>
H0_MEMCLK_L5 <4>
H0_MEMRESET_L < 4,8,9>
H0_DR _-MSCASA <8,9 ,11>
H0_DR _-MSRASA <8,9 ,11>
H0_DR _MDQS27 <8,9, 11>
H0_DR _MDQS28 <8,9, 11>
H0_DR _MDQS29 <8,9, 11>
H0_DR _MDQS30 <8,9, 11>
H0_DR _MDQS31 <8,9, 11>
H0_DR _MDQS32 <8,9, 11>
H0_DR _MDQS33 <8,9, 11>
H0_DR _MDQS34 <8,9, 11>
H0_DR _MDQS35 <8,9, 11>
A A
5
4
C1053
0.1u
3
C1054
1000P/50V/X7R
Micro Star R estric ted Se cret
Title
Document Number
2
CPU0 Register DDR DIMM3,4
MS- 9620
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http:/ /www.msi.com.tw
Last Revision Date:
Sheet
1
Tuesday, F ebruary 15, 2005
10 44
Rev
0A
of
5
DDR Terminations
RN2002 22_8P4R
H0_MD4
H0_MD0
H0_MD5
H0_MD1
RN2005 10_8P4R
H0_MDQS9
H0_MDQS0
D D
H0_MD6
H0_MD2
RN2007 10_8P4R
H0_MD7
H0_MD3
H0_MD8
H0_MD12
RN2009 10_8P4R
H0_MD9
H0_MD13
H0_MDQS1
H0_MDQS10
RN2012 10_8P4R
H0_MD14
H0_MD10
H0_MD11
RN2015 10_8P4R
H0_M CKEUP
H0_MCKELO
H0_MD20
H0_MD16
RN2017 10_8P4R
H0_MD17
H0_MD21
H0_MDQS2
H0_MDQS11
RN2019 10_8P4R
H0_MAA12
H0_MAA11
H0_MAA9
H0_MAA7
RN2021 10_8P4R
H0_MD18
H0_MD22
H0_MD23
H0_MD19
RN2028 10_8P4R
H0_MD24
H0_MD28
H0_MD29
H0_MD25
RN2030 10_8P4R
H0_MDQS3
H0_MDQS12
H0_MD30
H0_MD26
C C
B B
H0_MAA3
H0_MAA2
H0_MAA1
H0_MD27
H0_MD31
H0_M EMCHECK4
H0_M EMCHECK5
H0_M EMCHECK0
H0_M EMCHECK1
H0_MDQS8
H0_MDQS17
H0_M EMCHECK2
H0_M EMCHECK6
H0_M EMCHECK3
H0_M EMCHECK7
H0_MD32
H0_MD36
H0_MD37
H0_MD33
H0_MDQS4
H0_MDQS13
H0_MD34
H0_MD38
H0_MD39
H0_MD35
H0_MD44
H0_MD40
H0_MD45
H0_MD41
H0_MDQS14
H0_MDQS5
H0_MD42
H0_MD46
H0_MD43
H0_MD47
H0_-MCS1
H0_-MCS2
H0_-MCS3
H0_MAA13
H0_MD48
H0_MD52
H0_MD49
H0_MD53
H0_MDQS15
H0_MD54
H0_MDQS6
H0_MD55
H0_MD50
H0_MD51
H0_MD60
H0_MD61
H0_MD56
H0_MD57
H0_MDQS16
H0_MD62
H0_MDQS7
H0_MD63
H0_MD58
H0_MD59
RN2032 10_8P4R
RN2034 10_8P4R
RN2036 10_8P4R
RN2037 10_8P4R
RN2039 10_8P4R
RN2042 10_8P4R
RN2044 10_8P4R
RN2048 10_8P4R
RN2051 10_8P4R
RN2049 10_8P4R
RN2053 10_8P4R
RN2055 10_8P4R
RN2057 10_8P4R
RN2059 10_8P4R
RN2061 10_8P4R
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
H0_DR_MD4
H0_DR_MD0
H0_DR_MD5
H0_DR_MD1
H0_DR_MDQS9
H0_DR_MDQS0
H0_DR_MD6
H0_DR_MD2
H0_DR_MD7
H0_DR_MD3
H0_DR_MD8
H0_DR_MD12
H0_DR_MD9
H0_DR_MD13
H0_DR_MDQS1
H0_DR_MDQS10
H0_DR_MD14
H0_DR_MD15H0_MD15
H0_DR_MD10
H0_DR_MD11
H0_DR_MCKEUP
H0_DR_MCKELO
H0_DR_MD20
H0_DR_MD16
H0_DR_MD17
H0_DR_MD21
H0_DR_MDQS2
H0_DR_MDQS11
H0_DR_MAA12
H0_DR_MAA11
H0_D R_MAA9
H0_D R_MAA7
H0_DR_MD18
H0_DR_MD22
H0_DR_MD23
H0_DR_MD19
H0_DR_MD24
H0_DR_MD28
H0_DR_MD29
H0_DR_MD25
H0_DR_MDQS3
H0_DR_MDQS12
H0_DR_MD30
H0_DR_MD26
H0_D R_MAA3
H0_D R_MAA2
H0_D R_MAA1
H0_DR_MD27
H0_DR_MD31
H0_DR_MEMCHECK4
H0_DR_MEMCHECK5
H0_DR_MEMCHECK0
H0_DR_MEMCHECK1
H0_DR_MDQS8
H0_DR_MDQS17
H0_DR_MEMCHECK2
H0_DR_MEMCHECK6
H0_DR_MEMCHECK3
H0_DR_MEMCHECK7
H0_DR_MD32
H0_DR_MD36
H0_DR_MD37
H0_DR_MD33
H0_DR_MDQS4
H0_DR_MDQS13
H0_DR_MD34
H0_DR_MD38
H0_DR_MD39
H0_DR_MD35
H0_DR_MD44
H0_DR_MD40
H0_DR_MD45
H0_DR_MD41
H0_DR_MDQS14
H0_DR_MDQS5
H0_DR_MD42
H0_DR_MD46
H0_DR_MD43
H0_DR_MD47
H0_DR_-MCS1
H0_DR_-MCS2
H0_DR_-MCS3
H0_DR_MAA13
H0_DR_MD48
H0_DR_MD52
H0_DR_MD49
H0_DR_MD53
H0_DR_MDQS15
H0_DR_MD54
H0_DR_MDQS6
H0_DR_MD55
H0_DR_MD50
H0_DR_MD51
H0_DR_MD60
H0_DR_MD61
H0_DR_MD56
H0_DR_MD57
H0_DR_MDQS16
H0_DR_MD62
H0_DR_MDQS7
H0_DR_MD63
H0_DR_MD58
H0_DR_MD59
H0_DR_MD4
H0_DR_MD0
H0_DR_MD5
H0_DR_MD1
H0_DR_MDQS9
H0_DR_MDQS0
H0_DR_MD6
H0_DR_MD2
H0_DR_MD7
H0_DR_MD3
H0_DR_MD8
H0_DR_MD12
H0_DR_MD9
H0_DR_MD13
H0_DR_MDQS1
H0_DR_MDQS10
H0_DR_MD14
H0_DR_MD15
H0_DR_MD10
H0_DR_MCKEUP
H0_DR_MD11
H0_DR_MCKELO
H0_DR_MD20
H0_DR_MAA12
H0_DR_MD16
H0_DR_MD17
H0_DR_MD21
H0_DR_MDQS2
H0_DR_MAA11
H0_D R_MAA9
H0_DR_MDQS11
H0_DR_MD18
H0_DR_MD22
H0_D R_MAA8
H0_DR_MD23
H0_DR_MD19
H0_DR_MD24
H0_DR_MD28
H0_DR_MD29
H0_DR_MD25
H0_DR_MDQS3
H0_DR_MDQS12
H0_D R_MAA3
H0_DR_MD30
H0_DR_MD26
H0_DR_MD27
H0_D R_MAA2
H0_DR_MD31
H0_DR_MEMCHECK4
H0_DR_MEMCHECK5
H0_D R_MAA1
H0_DR_MEMCHECK0
H0_DR_MEMCHECK1
H0_DR_MDQS8
H0_D R_MAA0
H0_DR_MDQS17
H0_DR_MAA10
H0_DR_MEMCHECK2
H0_DR_MEMCHECK6
H0_DR_MEMCHECK3
H0_D R_MEMBAKA1
H0_DR_MEMCHECK7
H0_DR_MD32
H0_DR_MD36
H0_DR_MD37
H0_DR_MD33
H0_DR_MDQS4
H0_DR_MDQS13
H0_DR_MD34
H0_DR_MD38
H0_DR_MD39
H0_D R_MEMBAKA0
H0_DR_MD35
H0_DR_MD44
H0_DR_MD40
H0_DR_MD45
H0_DR_MD41
H0_DR_MDQS14
H0_DR_MDQS5
H0_DR_MD42
H0_DR_MD46
H0_DR_MD43
H0_DR_MD47
H0_DR_MD48
H0_DR_MD52
H0_DR_MD49
H0_DR_MD53
H0_DR_MAA13
H0_DR_MDQS15
H0_DR_MD54
H0_DR_MDQS6
H0_DR_MD55
H0_DR_MD50
H0_DR_MD51
H0_DR_MD60
H0_DR_MD61
H0_DR_MD56
H0_DR_MD57
H0_DR_MDQS16
H0_DR_MD62
H0_DR_MDQS7
H0_DR_MD63
H0_DR_MD58
H0_DR_MD59
RN2001 47_8P4R
RN2003 47_8P4R
RN2006 47_8P4R
RN2008 47_8P4R
RN2011 47_8P4R
RN2014 47_8P4R
RN2016 47_8P4R
RN2018 47_8P4R
RN2020 47_8P4R
RN2023 47_8P4R
RN2027 47_8P4R
RN2029 47_8P4R
RN2031 47_8P4R
RN2033 47_8P4R
RN2035 47_8P4R
RN2038 47_8P4R
RN2041 47_8P4R
RN2043 47_8P4R
RN2045 47_8P4R
RN2047 47_8P4R
RN2050 47_8P4R
RN2052 47_8P4R
RN2054 47_8P4R
RN2056 47_8P4R
RN2058 47_8P4R
RN2060 47_8P4R
VTT_DDR VTT_DDR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
H0_-MCS4<4>
H0_-MCS5<4>
4
RN2108 (BOT)10_8P4R
H0_MD68
H0_MD69
H0_MD65
RN2110 (BOT)10_8P4R
H0_MDQS27
H0_MDQS18
H0_MD70
H0_MD66
RN2112 (BOT)10_8P4R
H0_MD71
H0_MD67
H0_MD72
H0_MD76
RN2114 (BOT)10_8P4R
H0_MD73
H0_MD77
H0_MDQS19
H0_MDQS28
RN2116 (BOT)10_8P4R
H0_MD78
H0_MD79
H0_MD74
H0_MD75
RN2118 (BOT)10_8P4R
H0_MD84
H0_MD85
RN2120 (BOT)10_8P4R
H0_MDQS20
H0_MDQS29
H0_MD82
H0_MD86
RN2024 (BOT)10_8P4R
H0_MAA8
H0_MAA5
H0_MAA6
H0_MAA4
RN2122 (BOT)10_8P4R
H0_MD83
H0_MD87
H0_MD88
H0_MD92
RN2124 (BOT)10_8P4R
H0_MD93
H0_MD89
H0_MDQS21
H0_MDQS30
RN2126 (BOT)10_8P4R
H0_MD94
H0_MD90
H0_MD95
RN2128 (BOT)10_8P4R
H0_M EMCHECK12
H0_M EMCHECK8
H0_M EMCHECK9
RN2130 (BOT)10_8P4R
H0_MDQS35
H0_MDQS26
H0_M EMCHECK10
H0_M EMCHECK11
RN2132 (BOT)10_8P4R
H0_MAA0
H0_MAA10 H0_DR_MAA10
H0_MEMBAKA1
RN2134 (BOT)10_8P4R
H0_M EMCHECK14
H0_M EMCHECK15
H0_MD100 H0_ DR_MD100
RN2135 (BOT)10_8P4R
H0_MD101
H0_MD97
H0_MDQS22 H0_DR_MDQS22
RN2137 (BOT)10_8P4R
H0_MDQS31
H0_MD102
H0_MD99
RN2139 (BOT)10_8P4R
H0_MD108
H0_MD104
H0_MD109
H0_MD105
RN2046 (BOT)10_8P4R
H0_-MSRASA H0_DR_-MSRASA
H0_-MSWEA
H0_-MSCASA
H0_-MCS0
H0_MD106 H0_D R_MD106
H0_MDQS23 H0_DR_MDQS23
H0_MDQS32 H0_DR_MDQS32
RN2142 (BOT)10_8P4R
H0_MD111 H0_D R_MD111
H0_MD107 H0_D R_MD107
H0_MD110 H0_D R_MD110
RN2144
H0_MD112
H0_MD113 H0_D R_MD113
H0_MD116 H0_D R_MD116
H0_MD117 H0_ DR_MD117
RN2146 (BOT)10_8P4R
H0_MDQS33 H0_DR_MDQS33
H0_MD118
H0_MDQS24 H0_DR_MDQS24
H0_MD119
RN2148
H0_MD114 H0_ DR_MD114
H0_MD115 H0_ DR_MD115
H0_MD124 H0_ DR_MD124
H0_MD125
RN2150
H0_MD120 H0_ DR_MD120
H0_MD121
H0_MDQS34
H0_MD126
RN2152
H0_MDQS25
H0_MD127 H0_ DR_MD127
H0_MD122 H0_ DR_MD122
H0_MD123
RN2154
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
H0_DR_MD68
H0_DR_MD64H0_MD64
H0_DR_MD69
H0_DR_MD65
H0_DR_MDQS27
H0_DR_MDQS18
H0_DR_MD70
H0_DR_MD66
H0_DR_MD71
H0_DR_MD67
H0_DR_MD72
H0_DR_MD76
H0_DR_MD73
H0_DR_MD77
H0_DR_MDQS19
H0_DR_MDQS28
H0_DR_MD78
H0_DR_MD79
H0_DR_MD74
H0_DR_MD75
H0_DR_MD84
H0_DR_MD80H0_MD80
H0_DR_MD81H0_MD81
H0_DR_MD85
H0_DR_MDQS20
H0_DR_MDQS29
H0_DR_MD82
H0_DR_MD86
H0_D R_MAA8
H0_D R_MAA5
H0_D R_MAA6
H0_D R_MAA4
H0_DR_MD83
H0_DR_MD87
H0_DR_MD88
H0_DR_MD92
H0_DR_MD93
H0_DR_MD89
H0_DR_MDQS21
H0_DR_MDQS30
H0_DR_MD94
H0_DR_MD90
H0_DR_MD91H0_MD91
H0_DR_MD95
H0_DR_MEMCHECK12
H0_DR_MEMCHECK13H0_M EMCHECK13
H0_DR_MEMCHECK8
H0_DR_MEMCHECK9
H0_DR_MDQS35
H0_DR_MDQS26
H0_DR_MEMCHECK10
H0_DR_MEMCHECK11
H0_D R_MAA0
H0_D R_MEMBAKA1
H0_D R_MEMBAKA0H0_MEMBAKA0
H0_DR_MEMCHECK14
H0_DR_MEMCHECK15
H0_DR_MD96H0_MD96
H0_D R_MD101
H0_DR_MD97
H0_DR_MD98H0_MD98
H0_DR_MDQS31
H0_D R_MD102
H0_D R_MD103H0_MD103
H0_DR_MD99
H0_D R_MD108
H0_D R_MD104
H0_D R_MD109
H0_D R_MD105
H0_DR_-MSWEA
H0_DR_-MSCASA
H0_DR_-MCS0
H0_D R_MD112
(BOT)10_8P4R
H0_D R_MD118
H0_D R_MD119
(BOT)10_8P4R
H0_D R_MD125
(BOT)10_8P4R
H0_D R_MD121
H0_DR_MDQS34
H0_D R_MD126
(BOT)10_8P4R
H0_DR_MDQS25
H0_D R_MD123
H0_DR_-MCS4 <10>
H0_DR_-MCS5 <10>
(BOT)10_8P4R
H0_DR_MD68
H0_DR_MD64
H0_DR_MD69
H0_DR_MD65
H0_DR_MDQS27
H0_DR_MDQS18
H0_DR_MD70
H0_DR_MD66
H0_DR_MD71
H0_DR_MD67
H0_DR_MD72
H0_DR_MD76
H0_DR_MD73
H0_DR_MD77
H0_DR_MDQS19
H0_DR_MDQS28
H0_DR_MD78
H0_DR_MD79
H0_DR_MD74
H0_DR_MD75
H0_DR_MD84
H0_DR_MD80
H0_DR_MD81
H0_DR_MD85
H0_DR_MDQS20
H0_DR_MDQS29
H0_DR_MD82
H0_DR_MD86
H0_D R_MAA7
H0_DR_MD83
H0_DR_MD87
H0_D R_MAA5
H0_DR_MD88
H0_D R_MAA6
H0_DR_MD92
H0_DR_MD93
H0_DR_MD89
H0_DR_MDQS21
H0_DR_MDQS30
H0_D R_MAA4
H0_DR_MD94
H0_DR_MD90
H0_DR_MD91
H0_DR_MD95
H0_DR_MEMCHECK12
H0_DR_MEMCHECK13
H0_DR_MEMCHECK8
H0_DR_MEMCHECK9
H0_DR_MDQS35
H0_DR_MDQS26
H0_DR_MEMCHECK10
H0_DR_MEMCHECK11
H0_DR_MEMCHECK14
H0_DR_MEMCHECK15
H0_DR_MD96
H0_D R_MD100
H0_D R_MD101
H0_DR_MD97
H0_DR_MDQS22
H0_DR_MD98
H0_DR_MDQS31
H0_D R_MD102
H0_D R_MD103
H0_DR_MD99
H0_D R_MD108
H0_D R_MD104
H0_DR_-MSRASA
H0_D R_MD109
H0_DR_-MSWEA
H0_D R_MD105
H0_DR_-MCS0
H0_DR_-MSCASA
H0_DR_-MCS2
H0_DR_-MCS3
H0_DR_-MCS1
H0_DR_MDQS32
H0_DR_MDQS23
H0_D R_MD106
H0_D R_MD110
H0_D R_MD107
H0_D R_MD111
H0_D R_MD112
H0_D R_MD113
H0_D R_MD116
H0_D R_MD117
H0_DR_MDQS33
H0_D R_MD118
H0_DR_MDQS24
H0_D R_MD119
H0_D R_MD114
H0_D R_MD115
H0_D R_MD124
H0_D R_MD125
H0_D R_MD120
H0_D R_MD121
H0_DR_MDQS34
H0_D R_MD126
H0_DR_MDQS25
H0_D R_MD127
H0_D R_MD122
H0_D R_MD123
3
http://adf.ly/3o8pJ
RN2107 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2109 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2111 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2113 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2115 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2117 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2119 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2121 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2123 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2125 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2127 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2129 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2131 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2133 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2136 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2138 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2140 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2141 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2143 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2145 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2147 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2149 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2151 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2153 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2155 (BOT)47_8P4R
7 8
5 6
3 4
1 2
RN2156 (BOT)47_8P4R
7 8
5 6
3 4
1 2
LAYOUT:
Place alternating caps to GND and VDD_25_SUS
in a single line along VTT island.
VTT_DDR
VTT_DDR
VTT_DDR
VTT_DDR
VCC_DDR
VCC_DDR
VCC_DDR
C2006
0.22u/16V/X7R
VTT_DDR
VCC_DDR
VCC_DDR
C2207
0.1u
C2149
0.1u
C2096
0.1u
0.22u/16V/X7R
C2114
4.7u/0805
VCC_DDR
C2260
0.1u
C2153
0.1u
C2140
0.1u
C2008
0.22u/16V/X7R
C2156
C2067
0.1u
C2221
0.1u
C2187
0.1u
C2050
0.1u
C2130
0.1u
C2112
0.22u/16V/X7R
C2296
4.7u/0805
C2059
0.1u
C2183
0.1u
C2134
0.1u
C2054
0.22u/16V/X7R
Put close to dimm
socket
0.22u/16V/X7R
C2252
4.7u/0805
C2013
0.1u
LAYOUT:
Locate c lose to Sledgehammer
socket.
C2119
0.1u
C2165
C2177
0.1u
0.1u
C2172
C2160
0.1u
0.1u
C2081
C2072
0.1u
0.1u
C2124
C2090
C2131
C2193
C2138
0.1u
0.1u
0.1u
0.1u
0.1u
C2148
C2159
C2152
C2257
C2154
0.1u
0.1u
0.1u
0.1u
0.1u
C2189
C2199
C2180
0.1u
C2126
0.1u
C2206
C2185
0.1u
0.1u
0.1u
0.1u
C2121
C2060
C2055
C2115
0.1u
0.1u
0.1u
0.1u
AROUND VTT POWER RAIL BETWEEN DIMM AND CPU
C2232
C2262
C2204
0.22u/16V/X7R
0.22u/16V/X7R
C2069
0.22u/16V/X7R
C2271
4.7u/0805
C2017
0.1u
These caps are at both
ends of dimm
C2043
0.22u/16V/X7R
0.22u/16V/X7R
C2110
C2111
C2157
0.22u/16V/X7R
0.22u/16V/X7R
C2144
C2203
4.7u/0805
4.7u/0805
C2211
C2026
C2212
0.1u
0.1u
0.1u
2
VTT_DDR VTT_DDR
CT2008
C2098
0.1u
C2253
0.1u
C2208
0.1u
C2028
0.1u
100u/10V
C2100
0.1u
C2235
0.1u
C2218
0.1u
C2261
0.1u
C2168
0.22u/16V/X7R
C2062
0.1u
C2213
0.1u
C2230
0.1u
C2099
0.1u
C2128
0.1u
C2106
0.1u
C2242
0.1u
C2103
0.1u
C2046
0.22u/16V/X7R
C2201
C2078
0.1u
0.1u
C2143
C2108
0.1u
0.1u
C2258
C2256
0.1u
0.1u
C2107
C2145
0.1u
0.1u
C2057
0.22u/16V/X7R
LAYOUT:
Place alternating caps to GND and VDD_25_SUS
in a single line along VTT island.
VCC_DDR
VTT_DDR
VCC_DDR
VTT_DDR
VTT_DDR
VTT_DDR
PLEASE ON SOLDER SIDE
VTT_DDR
VTT_DDR
CT2000
4.7u/0805
C2592
(BOT)0.1u
C2541
(BOT)0.1u
C2583
(BOT)0.1u
C2171
1000P/50V/X7R
C2532
C2572
(BOT)0.1u
(BOT)0.1u
C2553
C2586
C2584
C2590
(BOT)0.1u
(BOT)0.1u
(BOT)0.1u
(BOT)0.1u
C2535
C2533
C2539
(BOT)0.1u
(BOT)0.1u
(BOT)0.1u
C2577
C2571
C2581
C2575
(BOT)0.1u
(BOT)0.1u
(BOT)0.1u
(BOT)0.1u
VTT_DDR
C2269
4.7u /6.3V/X5R-0805
VTT_DDR
C2267
CT2012
0.22u/16V/X7R
4.7u/0805
These caps are along the path from
regulator to CPU
C2173
4.7u /6.3V/X5R-0805
0.22u/16V/X7R
C2570
(BOT)0.1u
C2538
(BOT)0.1u
C2529
(BOT)0.1u
C2566
(BOT)0.1u
C2065
C2565
C2567
(BOT)0.1u
(BOT)0.1u
C2526
C2528
(BOT)0.1u
(BOT)0.1u
C2589
C2579
(BOT)0.1u
(BOT)0.1u
C2555
C2564
(BOT)0.1u
(BOT)0.1u
C2018
4.7u /6.3V/X5R-0805
C2191
0.22u/16V/X7R
C2563
(BOT)0.1u
C2582
(BOT)0.1u
C2573
(BOT)0.1u
C2544
(BOT)0.1u
C2041
4.7u /6.3V/X5R-0805
C2254
0.22u/16V/X7R
???
VCC_DDR
C2044
C2027
C2158
0.22u/16V/X7R
0.22u/16V
C2266
0.22u/16V
0.22u/16V
0.22u/16V
C2039
C2076
0.22u/16V
EMI components
C2315
C2064
C2071
4.7u/0805
C2181
4.7u/0805
4.7u/0805
4.7u/0805
5/14
C2210
C2270
0.1u
0.1u
VCC_DDR
4.7u/35V-1206
C2272
VCC_DDR VCC_DDR
C2287
C2179
0.22u/16V
0.22u/16V
1
LAYOUT:
Locate c lose to Cla whammer socket.
CT2002
100u/10V
C2540
C2543
(BOT)0.1u
(BOT)0.1u
C2576
C2530
(BOT)0.1u
(BOT)0.1u
C2531
C2537
(BOT)0.1u
(BOT)0.1u
C2569
C2597
(BOT)0.1u
(BOT)0.1u
C2216
C2192
4.7u /6.3V/X5R-0805
4.7u /6.3V/X5R-0805
C2002
0.22u/16V/X7R
C2536
(BOT)0.1u
C2588
(BOT)0.1u
C2527
(BOT)0.1u
C2595
(BOT)0.1u
0.22u/16V/X7R
C2534
C2561
(BOT)0.1u
(BOT)0.1u
C2548
C2578
(BOT)0.1u
(BOT)0.1u
C2525
C2523
(BOT)0.1u
(BOT)0.1u
C2591
C2593
(BOT)0.1u
(BOT)0.1u
C2040
4.7u /6.3V/X5R-0805
C2004
C2556
(BOT)0.1u
C2580
(BOT)0.1u
C2549
(BOT)0.1u
C2559
(BOT)0.1u
VTT_DDR
C2214
C2190
C2225
0.22u/16V
0.22u/16V
0.22u/16V
EC2008
EC2017
1200u/4V
1200u/4V
C2596
(BOT)0.1u
C2574
(BOT)0.1u
C2524
(BOT)0.1u
C2587
(BOT)0.1u
0.22u/16V/X7R
solder side
C2066
0.22u/16V
EC2016
+
100 0U/6.3V
C2607
C2594
(BOT)0.1u
C2568
(BOT)0.1u
C2562
(BOT)0.1u
C2585
(BOT)0.1u
Co-layoutCo-layout
C2194
0.22u/16V
EC2007
+
1000U/6.3V
H0_M DQS [35..0]
H0_M DQS [35..0]<4>
H0_M D[1 27..0]
H0_M D[1 27..0]<4>
H0_MEMCHECK[15..0]<4>
A A
5
H0_MEMCHECK[15..0]
H0_M AA[ 13..0]
H0_M AA[ 13..0]<4>
H0_- MCS [3..0]
H0_- MCS [3..0]<4>
H0_MCKELO<4> H0_DR_MCKELO<8,9,10>
H0_M CKEUP
H0_M CKEUP<4>
H0_MEMBAKA0
H0_MEMBAKA0<4>
H0_MEMBAKA1
H0_MEMBAKA1<4>
H0_-MSRASA
H0_-MSRASA<4>
H0_-MSCASA
H0_-MSCASA<4>
H0_-MSWEA
H0_-MSWEA<4>
4
H0_DR_MDQS[35..0]<8,9,10>
H0_DR_MEMCHECK[15..0]<8,9,10>
H0_D R_MEMBAKA0<8,9,10>
H0_D R_MEMBAKA1<8,9,10>
H0_DR_MDQS[35..0]
H0_DR_MD[127..0]
H0_DR_MD[127..0]<8,9,10>
H0_DR_MEMCHECK[15..0]
H0_DR_MAA[13..0]
H0_DR_MAA[13..0]<8,9,10>
H0_DR_-MCS[3..0]
H0_DR_-MCS[3..0]<8,9>
H0_DR_MCKELOH0_MCKELO
H0_DR_MCKEUP
H0_DR_MCKEUP<8,9,10>
H0_D R_MEMBAKA0
H0_D R_MEMBAKA1
H0_DR_-MSRASA
H0_DR_-MSRASA<8,9,10>
H0_DR_-MSCASA
H0_DR_-MSCASA<8,9,10>
H0_DR_-MSWEA
H0_DR_-MSWEA<8,9,10>
3
2
Micro Star Restricted Secret
Title
CPU DDR ( termination)
Docume nt Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taip ei Hs ien, Taiwan
http://www.msi.com .tw
1
MS-9 620
Last Revision Date:
Tues day, Febr uary 15, 2005
Sheet
11 44
Rev
0A
of
5
VDD_12_A
K10
VLDT_1(1)
J11
VLDT_1(2)
H10
VLDT_1(3)
H8
VLDT_1(4)
K14
VLDT_1(5)
J15
VLDT_1(6)
K16
VLDT_1(7)
H0_CLKOUT1
H0_CLKOUT#1
H0_CLKOUT0
H0_CLKOUT#0
H0_CTLOUT0
H0_CTLOUT#0
C2251
0.1u
C2250
0.1u
J16
VLDT_1(8)
J9
VLDT_1(9)
E14
L1_CADIN_H(15)
E13
L1_CADIN_L(15)
C15
L1_CADIN_H(14)
D15
L1_CADIN_L(14)
E16
L1_CADIN_H(13)
E15
L1_CADIN_L(13)
C17
L1_CADIN_H(12)
D17
L1_CADIN_L(12)
C19
L1_CADIN_H(11)
D19
L1_CADIN_L(11)
E20
L1_CADIN_H(10)
E19
L1_CADIN_L(10)
C21
L1_CADIN_H(9)
D21
L1_CADIN_L(9)
E22
L1_CADIN_H(8)
E21
L1_CADIN_L(8)
C14
L1_CADIN_H(7)
B14
L1_CADIN_L(7)
A16
L1_CADIN_H(6)
A15
L1_CADIN_L(6)
C16
L1_CADIN_H(5)
B16
L1_CADIN_L(5)
A18
L1_CADIN_H(4)
A17
L1_CADIN_L(4)
A20
L1_CADIN_H(3)
A19
L1_CADIN_L(3)
C20
L1_CADIN_H(2)
B20
L1_CADIN_L(2)
A22
L1_CADIN_H(1)
A21
L1_CADIN_L(1)
C22
L1_CADIN_H(0)
B22
L1_CADIN_L(0)
E18
L1_CLKIN_H(1)
E17
L1_CLKIN_L(1)
C18
L1_CLKIN_H(0)
B18
L1_CLKIN_L(0)
A14
L1_CTLIN_H(0)
A13
L1_CTLIN_L(0)
C13
L1_RSVD1
D13
L1_RSVD2
C2248
1000P/50V/X7R
C2249
1000P/50V/X7R
C2268
1000P/50V/X7R
D D
H0_CADOUT[15..0]<6>
H0_CADOUT#[15..0]<6>
H0_CLKOUT1<6>
C C
B B
A A
H0_CLKOUT#1<6>
H0_CLKOUT0<6>
H0_CLKOUT#0<6>
H0_CTLOUT0<6>
H0_CTLOUT#0<6>
0.22u/16V/ X7R
SOLDER SIDE
VDD_12_A
C2603
VCC_DDR
5
H0_CADOUT15
H0_CADOUT#15
H0_CADOUT14
H0_CADOUT#14
H0_CADOUT13
H0_CADOUT#13
H0_CADOUT12
H0_CADOUT#12
H0_CADOUT11
H0_CADOUT#11
H0_CADOUT10
H0_CADOUT#10
H0_CADOUT9
H0_CADOUT#9
H0_CADOUT8
H0_CADOUT#8
H0_CADOUT7
H0_CADOUT#7
H0_CADOUT6
H0_CADOUT#6
H0_CADOUT5
H0_CADOUT#5
H0_CADOUT4
H0_CADOUT#4
H0_CADOUT3
H0_CADOUT#3
H0_CADOUT2
H0_CADOUT#2
H0_CADOUT1
H0_CADOUT#1
H0_CADOUT0
H0_CADOUT#0
C2604
0.22u/16V/ X7R
R2120
100RST
R2121
100RST
U2013E
SledgeHammer
C2337
1000P/50V/X7R
L1_CADOUT_H(15)
L1_CADOUT_L(15)
L1_CADOUT_H(14)
L1_CADOUT_L(14)
L1_CADOUT_H(13)
L1_CADOUT_L(13)
L1_CADOUT_H(12)
L1_CADOUT_L(12)
L1_CADOUT_H(11)
L1_CADOUT_L(11)
L1_CADOUT_H(10)
L1_CADOUT_L(10)
L1_CADOUT_H(9)
L1_CADOUT_L(9)
L1_CADOUT_H(8)
L1_CADOUT_L(8)
L1_CADOUT_H(7)
L1_CADOUT_L(7)
L1_CADOUT_H(6)
L1_CADOUT_L(6)
L1_CADOUT_H(5)
L1_CADOUT_L(5)
L1_CADOUT_H(4)
L1_CADOUT_L(4)
L1_CADOUT_H(3)
L1_CADOUT_L(3)
L1_CADOUT_H(2)
L1_CADOUT_L(2)
L1_CADOUT_H(1)
L1_CADOUT_L(1)
L1_CADOUT_H(0)
L1_CADOUT_L(0)
L1_CLKOUT_H(1)
L1_CLKOUT_L(1)
L1_CLKOUT_H(0)
L1_CLKOUT_L(0)
L1_CTLOUT_H(0)
L1_CTLOUT_L(0)
C2334
1000P/50V/X7R
L1_RSVD3
L1_RSVD4
C2280
1000P/50V/X7R
H1_VREF1_DDR
C2338
0.1u
4
H0_CADIN 15
D11
H0_CADIN#15
C11
H0_CADIN 14
E9
E10
H0_CADIN 13
D9
C9
H0_CADIN 12
E7
E8
H0_CADIN 11
E5
E6
H0_CADIN 10
D5
C5
H0_CADIN 9
E3
E4
H0_CADIN 8
D3
C3
H0_CADIN 7
A11
A12
H0_CADIN 6
B10
C10
H0_CADIN 5
A9
A10
H0_CADIN 4
B8
C8
H0_CADIN 3
B6
C6
H0_CADIN 2
A5
A6
H0_CADIN 1
B4
H0_CADIN #1
C4
H0_CADIN 0
A3
H0_CADIN #0
A4
D7
C7
A7
A8
B12
C12
E11
E12
C2233
4.7u/ 6.3V/X5R-0805
C2339
1000P/50V/X7R
closed to F22 PINclosed to AF22 PIN
4
H0_CADIN#14
H0_CADIN#13
H0_CADIN#12
H0_CADIN#11
H0_CADIN#10
H0_CADIN #9
H0_CADIN #8
H0_CADIN #7
H0_CADIN #6
H0_CADIN #5
H0_CADIN #4
H0_CADIN #3
H0_CADIN #2
H0_CLKIN1
H0_CLKIN#1
H0_CLKIN0
H0_CLKIN#0
H0_CTLIN0
H0_CTLIN#0
CT2011
100u/10V
VTT_DDR
H0_CADIN[15..0] <6>
H0_CADIN#[15..0] <6>
H0_CLKIN1 <6>
H0_CLKIN#1 <6>
H0_CLKIN0 <6>
H0_CLKIN#0 <6>
H0_CTLIN0 <6>
H0_CTLIN#0 <6>
3
http://adf.ly/3o8pJ
C2236
0.1u
C2222
0.1u
C2223
0.1u
C2224
0.1u
3
VTT_DDR
VCC_DDR
H1_VREF1_DDR
H1_VREF1_DDR
R21 22 X_51
R2182 42.2RST
R2184 42.2RST
VTT_DDR
AC19
AE19
AE18
AC18
AF18
AF19
AF17
AE16
AF22
AG24
AH25
AG26
AH27
AF23
AH24
AF25
AG27
AF26
AF28
AE29
AH29
AE27
AD26
AD27
AC26
AA26
AA28
AD28
AC27
AB29
AA27
AG25
AF27
AB27
AF24
AG28
AC28
AD29
AA31
AE31
AJ26
AJ29
W27
W29
AJ25
AJ30
AL25
AL29
J19
H19
F20
G19
F21
F22
Y27
Y28
V28
U26
Y26
V27
U27
P28
N29
M26
L28
P27
P26
M27
L27
K29
K27
H28
G29
L26
J28
H27
H26
F27
F26
D29
D27
G27
F28
E27
C27
C26
E25
D24
F23
E26
F25
E24
G23
R27
N27
J27
E29
F24
R28
V26
M28
J26
E28
D25
U31
M30
H30
C30
B25
T31
Y29
M29
H29
C29
C25
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT_SENSE
MEMZN
MEMZP
MEMVREF0
MEMVREF1
MEMDATA(127)
MEMDATA(126)
MEMDATA(125)
MEMDATA(124)
MEMDATA(123)
MEMDATA(122)
MEMDATA(121)
MEMDATA(120)
MEMDATA(119)
MEMDATA(118)
MEMDATA(117)
MEMDATA(116)
MEMDATA(115)
MEMDATA(114)
MEMDATA(113)
MEMDATA(112)
MEMDATA(111)
MEMDATA(110)
MEMDATA(109)
MEMDATA(108)
MEMDATA(107)
MEMDATA(106)
MEMDATA(105)
MEMDATA(104)
MEMDATA(103)
MEMDATA(102)
MEMDATA(101)
MEMDATA(100)
MEMDATA(99)
MEMDATA(98)
MEMDATA(97)
MEMDATA(96)
MEMDATA(95)
MEMDATA(94)
MEMDATA(93)
MEMDATA(92)
MEMDATA(91)
MEMDATA(90)
MEMDATA(89)
MEMDATA(88)
MEMDATA(87)
MEMDATA(86)
MEMDATA(85)
MEMDATA(84)
MEMDATA(83)
MEMDATA(82)
MEMDATA(81)
MEMDATA(80)
MEMDATA(79)
MEMDATA(78)
MEMDATA(77)
MEMDATA(76)
MEMDATA(75)
MEMDATA(74)
MEMDATA(73)
MEMDATA(72)
MEMDATA(71)
MEMDATA(70)
MEMDATA(69)
MEMDATA(68)
MEMDATA(67)
MEMDATA(66)
MEMDATA(65)
MEMDATA(64)
MEMDQS(35)
MEMDQS(34)
MEMDQS(33)
MEMDQS(32)
MEMDQS(31)
MEMDQS(30)
MEMDQS(29)
MEMDQS(28)
MEMDQS(27)
MEMDQS(26)
MEMDQS(25)
MEMDQS(24)
MEMDQS(23)
MEMDQS(22)
MEMDQS(21)
MEMDQS(20)
MEMDQS(19)
MEMDQS(18)
MEMDQS(17)
MEMDQS(16)
MEMDQS(15)
MEMDQS(14)
MEMDQS(13)
MEMDQS(12)
MEMDQS(11)
MEMDQS(10)
MEMDQS(9)
MEMDQS(8)
MEMDQS(7)
MEMDQS(6)
MEMDQS(5)
MEMDQS(4)
MEMDQS(3)
MEMDQS(2)
MEMDQS(1)
MEMDQS(0)
2
U2013B
MEMCLK_UP_H(3)
MEMCLK_UP_L(3)
MEMCLK_UP_H(2)
MEMCLK_UP_L(2)
MEMCLK_UP_H(1)
MEMCLK_UP_L(1)
MEMCLK_UP_H(0)
MEMCLK_UP_L(0)
MEMCLK_LO_H(3)
MEMCLK_LO_L(3)
MEMCLK_LO_H(2)
MEMCLK_LO_L(2)
MEMCLK_LO_H(1)
MEMCLK_LO_L(1)
MEMCLK_LO_H(0)
MEMCLK_LO_L(0)
SledgeHammer
2
MEMCKE_UP
MEMCKE_LO
RSVD_MA(15)
RSVD_MA(14)
MEMADD(13)
MEMADD(12)
MEMADD(11)
MEMADD(10)
MEMADD(9)
MEMADD(8)
MEMADD(7)
MEMADD(6)
MEMADD(5)
MEMADD(4)
MEMADD(3)
MEMADD(2)
MEMADD(1)
MEMADD(0)
MEMDATA(63)
MEMDATA(62)
MEMDATA(61)
MEMDATA(60)
MEMDATA(59)
MEMDATA(58)
MEMDATA(57)
MEMDATA(56)
MEMDATA(55)
MEMDATA(54)
MEMDATA(53)
MEMDATA(52)
MEMDATA(51)
MEMDATA(50)
MEMDATA(49)
MEMDATA(48)
MEMDATA(47)
MEMDATA(46)
MEMDATA(45)
MEMDATA(44)
MEMDATA(43)
MEMDATA(42)
MEMDATA(41)
MEMDATA(40)
MEMDATA(39)
MEMDATA(38)
MEMDATA(37)
MEMDATA(36)
MEMDATA(35)
MEMDATA(34)
MEMDATA(33)
MEMDATA(32)
MEMDATA(31)
MEMDATA(30)
MEMDATA(29)
MEMDATA(28)
MEMDATA(27)
MEMDATA(26)
MEMDATA(25)
MEMDATA(24)
MEMDATA(23)
MEMDATA(22)
MEMDATA(21)
MEMDATA(20)
MEMDATA(19)
MEMDATA(18)
MEMDATA(17)
MEMDATA(16)
MEMDATA(15)
MEMDATA(14)
MEMDATA(13)
MEMDATA(12)
MEMDATA(11)
MEMDATA(10)
MEMDATA(9)
MEMDATA(8)
MEMDATA(7)
MEMDATA(6)
MEMDATA(5)
MEMDATA(4)
MEMDATA(3)
MEMDATA(2)
MEMDATA(1)
MEMDATA(0)
MEMRESET_L
MEMBANK(1)
MEMBANK(0)
MEMRAS_L
MEMCAS_L
MEMWE_L
MEMCHECK(15)
MEMCHECK(14)
MEMCHECK(13)
MEMCHECK(12)
MEMCHECK(11)
MEMCHECK(10)
MEMCHECK(9)
MEMCHECK(8)
MEMCHECK(7)
MEMCHECK(6)
MEMCHECK(5)
MEMCHECK(4)
MEMCHECK(3)
MEMCHECK(2)
MEMCHECK(1)
MEMCHECK(0)
MEMCS_L(7)
MEMCS_L(6)
MEMCS_L(5)
MEMCS_L(4)
MEMCS_L(3)
MEMCS_L(2)
MEMCS_L(1)
MEMCS_L(0)
G20
G21
AE21
AE20
L24
L25
R23
T23
H23
J23
AD21
AD20
Y23
AA23
U25
U24
H24
H25
V23
M23
AE23
J24
J25
V24
K23
L23
K25
M25
M24
N25
N23
P23
T25
V25
AJ24
AK25
AK27
AJ27
AL24
AK24
AL26
AL27
AJ28
AK30
AJ31
AG29
AL28
AK28
AH31
AG30
AG31
AF30
AD31
AC30
AF29
AF31
AD30
AC29
AB31
AA29
Y31
W31
AC31
AA30
Y30
V29
P31
M31
L30
L29
P29
N31
L31
K31
J30
J29
G31
F29
J31
H31
F31
F30
D31
C31
B30
C28
E31
E30
A29
B28
B27
A26
C24
A24
A28
A27
A25
B24
H1_MEMRESET1_L
G25
W25
W23
Y25
AA25
Y24
U28
T29
P24
P25
T27
R26
R25
R24
V30
U29
R30
P30
V31
U30
R29
R31
AD23
AE25
AD24
AD25
AC24
AC25
AB25
AA24
Micro S tar Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http:// www.msi.com.tw
CPU1_K8 DDR & HT
1
MS-9620
1
Last Revision Date:
Tuesd ay, Feb ruary 15, 2005
Sheet
12 44
Rev
0A
of
5
4
3
2
1
H1_VDDA25
C2229
C2234
D D
C C
B B
4.7u/6 .3V/X5R-0805
CLKIN1_H
R2424
(BOT)169RST
CLKIN1_L
C2245
3300p/50V/X7R
1000P/50V/X7R
C2246
0.22u /16V
COREFB1_H<38>
COREFB1_L<38>
CPUCLK1_H<22>
CPUCLK1_L<22>
CPU_PWRGD<5,16>
CT2010
100u/10V
VCC2_5
VDD_12_A
CPU_RST#<5,16>
HT_STOP#<5,16>
LAYOUT:
Route VDDA trace approx. 50 mils wide
(use 2x25 mil traces to exit ball) and
500 mils long.
H1_VDDA25
FB2001 180nH/1210
R2128 43.2RST
R2127 43.2RST
R2144 0
R2137 0
TP2023
C2237
C2238
3900P/50V/X7R
3900P/50V/X7R
TP2025
TP2024
TP2033
CLKIN1_H
CLKIN1_L
H1_N C_G14
H1_NC_H14
H1_TMS
H1_TCK
H1_TRST_L
H1_TDI
H1_D BREQ_L
H1_SCANCLK1
H1_SCANCLK2
H1_SCANEN
H1_SS ENA
H1_SS ENB
H1_NC_T3
H1_NC_T4
H1_NC_AF13
H1_NC _AE14
G16
H16
G14
H14
AE6
AE7
AD7
AF7
AE10
AE11
AF11
AE13
AE12
AF13
AF15
AE14
G12
F12
C1
D2
C2
E1
D1
L7
L6
K7
J7
T3
T4
L8
K8
J6
VDDA1
VDDA2
VDDA3
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORESENSE_H
CLKIN_H
CLKIN_L
BYPASSCLK_H
BYPASSCLK_L
TMS
TCK
TRST_L
TDI
DBREQ_L
SCANCLK1
SCANCLK2
SCANEN
SCANSHIFTEN
SCANSHIFTENB
SCANIN_H
SCANIN_L
SINGLECHAIN
PLLCHRZ_H
PLLCHRZ_L
DCLKTWO
BURNIN_L
RESET_L
LDTSTOP_L
PWROK
http://adf.ly/3o8pJ
U2013C
CPU_T HEMTRIP#
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
BP(3)
BP(2)
BP(1)
BP(0)
TDO
DBRDY
TSTOUT
ANALOG3
ANALOG2
ANALOG1
ANALOG0
AE15
AJ1
AH1
G9
F9
G10
H11
G11
H13
G6
F7
H12
H1_FBC LKOUT_H
G18
H18
H1_FBCLKOUT_L
AE8
H1_DBRDY
G8
V5
U5
H7
U2_T7
T7
U2_W6
W6
U2_R6
R6
U2_U6
U6
AF9
AE9
H1_BP3
H1_BP2
H1_BP1
H1_BP0
THER MDA_CPU2 <33>
VTIN_G ND <5,33>
R2133 0
R2118 0
R2134 0
R2117 0
R2119 0
R2423
80.6RST
TP2037
TP2028
TP2027
TP2021
U2_T7
U2_W6
U2_U6
TP2032
TP2031
THERMTRIP_L
THERMDA
THERMDC
FBCLKOUT_H
FBCLKOUT_L
SCANOUT_H
SCANOUT_L
RSVD_SMBUSC
RSVD_SMBUSD
CPU_THEMTRIP# <5,16>
H1_V ID4 <32,37>
H1_V ID3 <32,37>
H1_V ID2 <32,37>
H1_V ID1 <32,37>
H1_V ID0 <32,37>
U2_R6 H1_NC_T3
RN2062
510_8P4R
modified on 1/30
R2459 680
12
34
56
78
LAYOUT:
Route FBCLKOUT_H/L differentially with
20/8/5/8/20 spacing and trace width.
R2460
49.9RST
H1_TDI
H1_TMS
H1_TRST_L
H1_TCK
STRAPPINGS
H1_N C_G14
H1_N C_AE14
H1_NC_AF13
H1_D BREQ_L
H1_DBRDY
H1_NC_H14
H1_SCANEN
H1_SCANCLK1
H1_SCANCLK2
H1_SS ENA
H1_SS ENB
H1_BP0
H1_BP1
H1_BP2
H1_BP3
VCC2_5
R2464 1K
R2465 1K
R2466 1K
R2467 1K
VCC2_5
R2149 820
R2181 680
R2180 680
R2148 1K
R2131 1K
R2126 820
R2198 680
R2177 680
R2178 680
R2199 680
R2179 680
R2114 680
R2129 680
R2130 X_680
R2115 X_680
2
VDD_12_A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li- De St, Jung-He City,
Taipe i Hsien, Taiwan
http://www.m si.com.tw
CPU1_K8 HDT 7 MISC
MS-9620
Last Revision Date:
Tuesday, February 15, 2005
Sheet
13 44
1
Rev
0A
of
TP2034
TP2035
TP2022
TP2036
TP2029
TP2030
TP2026
A A
5
AG1
FREE7
AH2
FREE11
H9
FREE15
AJ2
FREE12
AA6
FREE21
AC6
FREE1
N6
FREE3
SledgeHammer
4
3
H1_NC_T4
R2138 49.9RST
R2145
X_49.9RST
Loading...