MSI MS-91A4 Schematic 0C

A B C

D

REVISIONS

1

2

3

SUB=NP Always no-pop

BOM options

1 = Adds 1U Parts
2 = Adds 2U Parts
5 = STMicro TPM (ROW)

6 = Winbond TPM (ST TPM is base/pop 0)
7 = Plug In Module TPM (ROW-PIM)
8 = Development/Debug (ST parts)
9 = Development/Debug (non-ST parts)

BOM Instructions

In order to build a proper BOM, you must run a combo build
Parts without subs appear on all builds (i.e., Build 0 is not needed)

BRINGUP/UT/PT
2U: 2,5,8,9

1U: 1,5,8,9

SYSTEM TEST
2U: 2,5,8

1U: 1,5,8

PRODUCTION
2U: 2,5 (Must be in Combined Build Field)

1U: 1,5 (Must be in Combined Build Field)

Bluefish Thidwick

PWA: KP259
ASSY: DU071
PWB: YN967
SCH: NT247

THIDWICK PLANAR

1U DPNs2U DPNs
PWA: FN855

ASSY: UU671
PWB: PK460
SCH: RR154

P15_JR_DT17255: remove change build5 to STMicro TPM

P15_JR_DT17120: New build option for onboard TPM

Bluefish/Thidwick 8 Layers Stackup

SolderMask: 0.5 mils, ER = 3.7

Layer 1: TOP, 2.1 mils, 1.5 oz

Prepreg: 4 mils, ER = 4

Layer 2: GND, 1.3 mils, 1.0 oz

Core: 4 mils, ER = 4

Layer 3: INNER1, 1.3 mils, 1.0 oz

Prepreg: 20 mils, ER = 4.3

Layer 4: VCC, 2.6 mils, 2.0 oz

Core: 10 mils, ER = 4

Layer 5: VC2, 2.6 mils, 2.0 oz

Prepreg: 20 mils, ER = 4.3

Layer 6: INNER2, 1.3 mils, 1.0 oz

Core: 4 mils, ER = 4

Layer 7: GD2, 1.3 mils, 1.0 oz

Prepreg: 4 mils, ER = 4

Layer 8: BOTTOM, 2.1 mils, 1.5 oz

SolderMask: 0.5 mils, ER = 3.7

REV

X00 Initial Prototype Release
X01 Unit Test (UT) Release

Layout Issue, schematics same as X01X02
X03 Product Test (PT) Release
X04
X05

Product Test (PT) Release with Memory Route Updates

System Test (ST1) Release

DESCRIPTIONECO DATE

TABLE OF CONTENTS

Page 1.
Page 2-10.
Page 11.
Page 12-18.
Page 19-28.
Page 29-35.
Page 36-45.
Page 46.
Page 47.
Page 48-49
Page 50.
Page 51-61.
Page 62-71.
Page 72.
Page 73.
Page 74.
Page 75.
Page 76.
Page 77-80.
Page 81-84.
Page 85.
Page 86-87.
Page 88.
Page 89.
Page 90.
Page 91.
Page 92.
Page 93.
Page 94-97. CPLD
Page 98.
Page 99.
Page 100.
Page 101.
Page 102-110.
Page 111.
Page 112.
Page 113.
Page 114.
Page 115.
Page 116-118.
Page 119-121.
Page 122.
Page 123.
Page 124.
Page 125-126.
Page 127-128.
Page 129.
Page 130.
Page 131.
Page 132.
Page 133. VR: ICH9 1.05V
Page 134.
Page 135.
Page 136. VR: System 1.2V AUX and 1.8V AUX
Page 137.
Page 138.
Page 139.
Page 140.
Page 141. VR: Voltage Margining
Page 142.
Page 143.
Page 144.
Page 145.

TOC

BLOCK DIAGRAMS

CPU TOC

CPU 1
CPU 1 DIMMs (6)
CPU 2
CPU 2 DIMMs (6)

CPU XDP
Clock Generator: CK410B+
Clock Buffer: DB1200
Clock Buffer: CK-MNG
Tylersburg IOH
ICH9
PCIE Wake
Super I/O
TPM and Jumpers
Firmware Hub
Coin Cell Battery
LOM1 Broadcom 5709C
LOM2 Broadcom 5709C
LOM 1&2 Shared Circuitry
Risers (Left, Center)
Control Panel and Backplane Connectors
SATA Connectors
USB Connectors and Buttons
COM port
PCIe Midbus
Debug

Intrusion Detect and Power Good
Rear ID, Cyclops
Fan Connectors and Tach

iBMC TOC

iBMC
Video Riser
Video Redrive
Video Switch
Power Connectors
VR: CPU 1&2 1.8V
VR: CPU 1 VCore
VR: CPU 2 VCore
VR: CPU 1 Vtt
VR: CPU 2 Vtt
VR: Memory 1 & 2 Vtt 0.75V
VR: Memory 1 1.5V
VR: Memory 2 1.5V
VR: System 8V
VR: IOH 1.8V & 0.9V
VR: ICH9 5V AUX
VR: 3.3V AUX

VR: LOM 1.0V
VR: LOM 1.0V AUX

VR: System 5V
VR: System 3.3V
VR: System 1.5V
VR: System 1.1V

Ground Clips, Mounting Holes and Mechanical Adds
Impedance Coupons
PAUX LED & Voltage Props
Spare Parts

APPROVED

1

2

3

4

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

THIDWICK

UNIQUE PAGE

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY
OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN
WHOLE OR IN PART AND MUST BE RETURNED TO DELL INC.
UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE
OF THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED
FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE
LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DRAWN

DESIGNED

CHECKED

APPROVED

APPROVED

APPROVED

APPROVED

RELEASED

11G Team
11G Team

TJ Thompson

Mark Reinke

04/11/2008
04/11/2008
04/11/2008
04/11/2008

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO
ECO

TITLE

SCHEM,PLN,SV,R610

DWG NO.

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

INC.

ROUND ROCK,TEXAS

RR154

DATE

SHEET

4

REV.

X05

1 OF 14511/6/2008

DCBA

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

SCHEM,PLN,SV,R610

RR154

DCBA

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

2 OF 14511/6/2008

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

SCHEM,PLN,SV,R610

RR154

DCBA

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

3 OF 14511/6/2008

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

11/6/2008 4 OF 145

DCBA

4

X05

A B C

I2C Bluefish Address Table & Segments

D

1

1

2

2

3

3

Location of these docs: R:\Schematic_Projects\PowerEdge\11G\Bluefish\System_Documentation\Block_Diagrams\I2C

P21_DTnone_BT: Updated I2C Table

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

11/6/2008 5 OF 145

DCBA

4

X05

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

11/6/2008 6 OF 145

DCBA

4

X05

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

11/6/2008 7 OF 145

DCBA

4

X05

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

SCHEM,PLN,SV,R610

RR154

DCBA

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

8 OF 14511/6/2008

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

11/6/2008 9 OF 145

DCBA

4

X05

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 10 OF 145

DCBA

4

A B C

D

1

1

2

2

3

3

4

P22_JLP_added chart

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 11 OF 145

DCBA

4

A B C

J_CPU1

D

1

CSI_CK_CPU1_IOH_DN

51

CSI_CK_CPU1_IOH_DP

51

CSI_CK_IOH_CPU1_DN

51

CSI_CK_IOH_CPU1_DP

51

MOD_CPU_CSI_CPU1_COMP_0

16

CSI_CPU1_IOH_19_DP

51

CSI_CPU1_IOH_18_DN

51

CSI_CPU1_IOH_17_DP

51

CSI_CPU1_IOH_16_DN

51

CSI_CPU1_IOH_15_DP

51

CSI_CPU1_IOH_14_DN

51

CSI_CPU1_IOH_13_DN

51

CSI_CPU1_IOH_12_DN

51

CSI_CPU1_IOH_11_DN

51

CSI_CPU1_IOH_10_DN

51

CSI_CPU1_IOH_09_DN

51

CSI_CPU1_IOH_08_DP

51

CSI_CPU1_IOH_07_DP

51

CSI_CPU1_IOH_06_DN

51

CSI_CPU1_IOH_05_DP

51

CSI_CPU1_IOH_04_DP

51

CSI_CPU1_IOH_03_DP

51

CSI_CPU1_IOH_02_DP

51

CSI_CPU1_IOH_01_DP

51

CSI_CPU1_IOH_00_DN

51

AG42

CSI0_CLKTX_DP

AF42

CSI0_CLKTX_DN

AR41

CSI0_CLKRX_DP

AR42

CSI0_CLKRX_DN

AL43

CSI0_COMP

AE40

CSI0_DTX_DP_19

AD38

CSI0_DTX_DP_18

AB39

CSI0_DTX_DP_17

AC39

CSI0_DTX_DP_16

AC41

CSI0_DTX_DP_15

AD40

CSI0_DTX_DP_14

AC43

CSI0_DTX_DP_13

AD42

CSI0_DTX_DP_12

AE42

CSI0_DTX_DP_11

AF43

CSI0_DTX_DP_10

AG40

CSI0_DTX_DP_9

AJ43

CSI0_DTX_DP_8

AK42

CSI0_DTX_DP_7

AH41

CSI0_DTX_DP_6

AK40

CSI0_DTX_DP_5

AH40

CSI0_DTX_DP_4

AJ38

CSI0_DTX_DP_3

AK37

CSI0_DTX_DP_2

AF39

CSI0_DTX_DP_1

AG38

CSI0_DTX_DP_0

CSI1_CLKTX_DP
CSI1_CLKTX_DN
CSI1_CLKRX_DP
CSI1_CLKRX_DN

CSI1_COMP

CSI1_DTX_DP_19
CSI1_DTX_DP_18
CSI1_DTX_DP_17
CSI1_DTX_DP_16
CSI1_DTX_DP_15
CSI1_DTX_DP_14
CSI1_DTX_DP_13
CSI1_DTX_DP_12
CSI1_DTX_DP_11
CSI1_DTX_DP_10

CSI1_DTX_DP_9
CSI1_DTX_DP_8
CSI1_DTX_DP_7
CSI1_DTX_DP_6
CSI1_DTX_DP_5
CSI1_DTX_DP_4
CSI1_DTX_DP_3
CSI1_DTX_DP_2
CSI1_DTX_DP_1
CSI1_DTX_DP_0

AF6
AE6
AT6
AR6
AL6

AC8
AD5
AD6
AB6
AC4
AE3
AC3
AD2
AE1
AF2
AH2
AH3
AK1
AJ3
AG7
AJ4
AK6
AH6
AJ8
AG8

CSI_CK_CPU1_CPU2_DP
CSI_CK_CPU1_CPU2_DN
CSI_CK_CPU2_CPU1_DP
CSI_CK_CPU2_CPU1_DN

MOD_CPU_CSI_CPU1_COMP_1

CSI_CPU1_CPU2_19_DP
CSI_CPU1_CPU2_18_DP
CSI_CPU1_CPU2_17_DP
CSI_CPU1_CPU2_16_DP
CSI_CPU1_CPU2_15_DP
CSI_CPU1_CPU2_14_DP
CSI_CPU1_CPU2_13_DP
CSI_CPU1_CPU2_12_DP
CSI_CPU1_CPU2_11_DP
CSI_CPU1_CPU2_10_DP
CSI_CPU1_CPU2_09_DP
CSI_CPU1_CPU2_08_DP
CSI_CPU1_CPU2_07_DP
CSI_CPU1_CPU2_06_DP
CSI_CPU1_CPU2_05_DP
CSI_CPU1_CPU2_04_DP
CSI_CPU1_CPU2_03_DP
CSI_CPU1_CPU2_02_DP
CSI_CPU1_CPU2_01_DP
CSI_CPU1_CPU2_00_DP

29
29
29
29
16

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

1

To CPU2

Port 1 Port 1

2

Port 0

CSI_CPU1_IOH_19_DN

51

CSI_CPU1_IOH_18_DP

51

CSI_CPU1_IOH_17_DN

51

CSI_CPU1_IOH_16_DP

51

CSI_CPU1_IOH_15_DN

51

CSI_CPU1_IOH_14_DP

51

CSI_CPU1_IOH_13_DP

51

CSI_CPU1_IOH_12_DP

51

CSI_CPU1_IOH_11_DP

51

CSI_CPU1_IOH_10_DP

51

CSI_CPU1_IOH_09_DP

51

CSI_CPU1_IOH_08_DN

51

CSI_CPU1_IOH_07_DN

51

CSI_CPU1_IOH_06_DP

51

CSI_CPU1_IOH_05_DN

51

CSI_CPU1_IOH_04_DN

51

CSI_CPU1_IOH_03_DN

51

CSI_CPU1_IOH_02_DN

51

CSI_CPU1_IOH_01_DN

51

CSI_CPU1_IOH_00_DP

51

AF40

CSI0_DTX_DN_19

AE38

CSI0_DTX_DN_18

AB38

CSI0_DTX_DN_17

AC38

CSI0_DTX_DN_16

AC40

CSI0_DTX_DN_15

AD39

CSI0_DTX_DN_14

AB43

CSI0_DTX_DN_13

AC42

CSI0_DTX_DN_12

AE41

CSI0_DTX_DN_11

AE43

CSI0_DTX_DN_10

AG41

CSI0_DTX_DN_9

AH43

CSI0_DTX_DN_8

AJ42

CSI0_DTX_DN_7

AH42

CSI0_DTX_DN_6

AK41

CSI0_DTX_DN_5

AJ40

CSI0_DTX_DN_4

AJ39

CSI0_DTX_DN_3

AK38

CSI0_DTX_DN_2

AG39

CSI0_DTX_DN_1

AH38

CSI0_DTX_DN_0

CSI1_DTX_DN_19
CSI1_DTX_DN_18
CSI1_DTX_DN_17
CSI1_DTX_DN_16
CSI1_DTX_DN_15
CSI1_DTX_DN_14
CSI1_DTX_DN_13
CSI1_DTX_DN_12
CSI1_DTX_DN_11
CSI1_DTX_DN_10

CSI1_DTX_DN_9
CSI1_DTX_DN_8
CSI1_DTX_DN_7
CSI1_DTX_DN_6
CSI1_DTX_DN_5
CSI1_DTX_DN_4
CSI1_DTX_DN_3
CSI1_DTX_DN_2
CSI1_DTX_DN_1
CSI1_DTX_DN_0

AD8
AE5
AD7
AC6
AD4
AE4
AB3
AD3
AD1
AF3
AG2
AH4
AJ1
AJ2
AG6
AK4
AK5
AJ6
AJ7
AH8

CSI_CPU1_CPU2_19_DN
CSI_CPU1_CPU2_18_DN
CSI_CPU1_CPU2_17_DN
CSI_CPU1_CPU2_16_DN
CSI_CPU1_CPU2_15_DN
CSI_CPU1_CPU2_14_DN
CSI_CPU1_CPU2_13_DN
CSI_CPU1_CPU2_12_DN
CSI_CPU1_CPU2_11_DN
CSI_CPU1_CPU2_10_DN
CSI_CPU1_CPU2_09_DN
CSI_CPU1_CPU2_08_DN
CSI_CPU1_CPU2_07_DN
CSI_CPU1_CPU2_06_DN
CSI_CPU1_CPU2_05_DN
CSI_CPU1_CPU2_04_DN
CSI_CPU1_CPU2_03_DN
CSI_CPU1_CPU2_02_DN
CSI_CPU1_CPU2_01_DN
CSI_CPU1_CPU2_00_DN

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

2

3

CSI_IOH_CPU1_19_DN

51

CSI_IOH_CPU1_18_DN

51

CSI_IOH_CPU1_17_DN

51

CSI_IOH_CPU1_16_DN

51

CSI_IOH_CPU1_15_DN

51

CSI_IOH_CPU1_14_DP

51

CSI_IOH_CPU1_13_DP

51

CSI_IOH_CPU1_12_DN

51

CSI_IOH_CPU1_11_DN

51

CSI_IOH_CPU1_10_DP

51

CSI_IOH_CPU1_09_DN

51

CSI_IOH_CPU1_08_DN

51

CSI_IOH_CPU1_07_DN

51

CSI_IOH_CPU1_06_DN

51

CSI_IOH_CPU1_05_DN

51

CSI_IOH_CPU1_04_DN

51

CSI_IOH_CPU1_03_DN

51

CSI_IOH_CPU1_02_DN

51

CSI_IOH_CPU1_01_DP

51

CSI_IOH_CPU1_00_DN

51

AP38

CSI0_DRX_DP_19

AN39

CSI0_DRX_DP_18

AP41

CSI0_DRX_DP_17

AM42

CSI0_DRX_DP_16

AN40

CSI0_DRX_DP_15

AN43

CSI0_DRX_DP_14

AP42

CSI0_DRX_DP_13

AT40

CSI0_DRX_DP_12

AT43

CSI0_DRX_DP_11

AU42

CSI0_DRX_DP_10

AU40

CSI0_DRX_DP_9

AW40

CSI0_DRX_DP_8

AU39

CSI0_DRX_DP_7

BA38

CSI0_DRX_DP_6

AW37

CSI0_DRX_DP_5

BA36

CSI0_DRX_DP_4

AW36

CSI0_DRX_DP_3

AV36

CSI0_DRX_DP_2

AU38

CSI0_DRX_DP_1

AT37

CSI0_DRX_DP_0

CSI1_DRX_DP_19
CSI1_DRX_DP_18
CSI1_DRX_DP_17
CSI1_DRX_DP_16
CSI1_DRX_DP_15
CSI1_DRX_DP_14
CSI1_DRX_DP_13
CSI1_DRX_DP_12
CSI1_DRX_DP_11
CSI1_DRX_DP_10

CSI1_DRX_DP_9
CSI1_DRX_DP_8
CSI1_DRX_DP_7
CSI1_DRX_DP_6
CSI1_DRX_DP_5
CSI1_DRX_DP_4
CSI1_DRX_DP_3
CSI1_DRX_DP_2
CSI1_DRX_DP_1
CSI1_DRX_DP_0

AM8
AM6
AN5
AM4
AP3
AM2
AN1
AP2
AR4
AT1
AT3
AU4
AW4
AU7
AY6
BA7
AV5
AY8
AV7
AU8

CSI_CPU2_CPU1_19_DP
CSI_CPU2_CPU1_18_DP
CSI_CPU2_CPU1_17_DP
CSI_CPU2_CPU1_16_DP
CSI_CPU2_CPU1_15_DP
CSI_CPU2_CPU1_14_DP
CSI_CPU2_CPU1_13_DP
CSI_CPU2_CPU1_12_DP
CSI_CPU2_CPU1_11_DP
CSI_CPU2_CPU1_10_DP
CSI_CPU2_CPU1_09_DP
CSI_CPU2_CPU1_08_DP
CSI_CPU2_CPU1_07_DP
CSI_CPU2_CPU1_06_DP
CSI_CPU2_CPU1_05_DP
CSI_CPU2_CPU1_04_DP
CSI_CPU2_CPU1_03_DP
CSI_CPU2_CPU1_02_DP
CSI_CPU2_CPU1_01_DP
CSI_CPU2_CPU1_00_DP

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

From CPU2

3

4

CSI_IOH_CPU1_19_DP

51

CSI_IOH_CPU1_18_DP

51

CSI_IOH_CPU1_17_DP

51

CSI_IOH_CPU1_16_DP

51

CSI_IOH_CPU1_15_DP

51

DEBUG: Mirror port default is port 0.

Port 0

From IOH To IOH

Note: P/N is intentionally swizzled for layout

CSI_IOH_CPU1_14_DN

51

CSI_IOH_CPU1_13_DN

51

CSI_IOH_CPU1_12_DP

51

CSI_IOH_CPU1_11_DP

51

CSI_IOH_CPU1_10_DN

51

CSI_IOH_CPU1_09_DP

51

CSI_IOH_CPU1_08_DP

51

CSI_IOH_CPU1_07_DP

51

CSI_IOH_CPU1_06_DP

51

CSI_IOH_CPU1_05_DP

51

CSI_IOH_CPU1_04_DP

51

CSI_IOH_CPU1_03_DP

51

CSI_IOH_CPU1_02_DP

51

CSI_IOH_CPU1_01_DN

51

CSI_IOH_CPU1_00_DP

51

ADD*_FN258_ILM

AR38

CSI0_DRX_DN_19

AP39

CSI0_DRX_DN_18

AP40

CSI0_DRX_DN_17

AM41

CSI0_DRX_DN_16

AM40

CSI0_DRX_DN_15

AM43

CSI0_DRX_DN_14

AN42

CSI0_DRX_DN_13

AR40

CSI0_DRX_DN_12

AR43

CSI0_DRX_DN_11

AT42

CSI0_DRX_DN_10

AU41

CSI0_DRX_DN_9

AV40

CSI0_DRX_DN_8

AT39

CSI0_DRX_DN_7

AY38

CSI0_DRX_DN_6

AW38

CSI0_DRX_DN_5

BA37

CSI0_DRX_DN_4

AY36

CSI0_DRX_DN_3

AV37

CSI0_DRX_DN_2

AV38

CSI0_DRX_DN_1

AU37

CSI0_DRX_DN_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 1 OF 10

CSI1_DRX_DN_19
CSI1_DRX_DN_18
CSI1_DRX_DN_17
CSI1_DRX_DN_16
CSI1_DRX_DN_15
CSI1_DRX_DN_14
CSI1_DRX_DN_13
CSI1_DRX_DN_12
CSI1_DRX_DN_11
CSI1_DRX_DN_10

CSI1_DRX_DN_9
CSI1_DRX_DN_8
CSI1_DRX_DN_7
CSI1_DRX_DN_6
CSI1_DRX_DN_5
CSI1_DRX_DN_4
CSI1_DRX_DN_3
CSI1_DRX_DN_2
CSI1_DRX_DN_1
CSI1_DRX_DN_0

AL8
AM7
AN6
AN4
AP4
AM3
AM1
AN2
AR5
AR1
AT2
AU3
AW3
AU6
AY5
BA6
AW5
BA8
AW7
AV8

CSI_CPU2_CPU1_19_DN
CSI_CPU2_CPU1_18_DN
CSI_CPU2_CPU1_17_DN
CSI_CPU2_CPU1_16_DN
CSI_CPU2_CPU1_15_DN
CSI_CPU2_CPU1_14_DN
CSI_CPU2_CPU1_13_DN
CSI_CPU2_CPU1_12_DN
CSI_CPU2_CPU1_11_DN
CSI_CPU2_CPU1_10_DN
CSI_CPU2_CPU1_09_DN
CSI_CPU2_CPU1_08_DN
CSI_CPU2_CPU1_07_DN
CSI_CPU2_CPU1_06_DN
CSI_CPU2_CPU1_05_DN
CSI_CPU2_CPU1_04_DN
CSI_CPU2_CPU1_03_DN
CSI_CPU2_CPU1_02_DN
CSI_CPU2_CPU1_01_DN
CSI_CPU2_CPU1_00_DN

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

Note: P/N is intentionally swizzled for layout

MODULE:
DESC:
REV: OF

CPU1

INC.

TITLE

ROUND ROCK,TEXAS

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ADD*_Y080J_ILM_COVER
ADD*_D994J_LABEL

P21_SCH_17608 added ilm cover and label

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

SCHEM,PLN,SV,R610

RR154

DCBA

REV.

X05

SHEET

12 OF 14511/6/2008

A B C

J_CPU1

J_CPU1

D

1

2

3

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20,21
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20,21
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20,21

21
20

CPU1_M_CH0_DQ63
CPU1_M_CH0_DQ62
CPU1_M_CH0_DQ61
CPU1_M_CH0_DQ60
CPU1_M_CH0_DQ59
CPU1_M_CH0_DQ58
CPU1_M_CH0_DQ57
CPU1_M_CH0_DQ56
CPU1_M_CH0_DQ55
CPU1_M_CH0_DQ54
CPU1_M_CH0_DQ53
CPU1_M_CH0_DQ52
CPU1_M_CH0_DQ51
CPU1_M_CH0_DQ50
CPU1_M_CH0_DQ49
CPU1_M_CH0_DQ48
CPU1_M_CH0_DQ47
CPU1_M_CH0_DQ46
CPU1_M_CH0_DQ45
CPU1_M_CH0_DQ44
CPU1_M_CH0_DQ43
CPU1_M_CH0_DQ42
CPU1_M_CH0_DQ41
CPU1_M_CH0_DQ40
CPU1_M_CH0_DQ39
CPU1_M_CH0_DQ38
CPU1_M_CH0_DQ37
CPU1_M_CH0_DQ36
CPU1_M_CH0_DQ35
CPU1_M_CH0_DQ34
CPU1_M_CH0_DQ33
CPU1_M_CH0_DQ32
CPU1_M_CH0_DQ31
CPU1_M_CH0_DQ30
CPU1_M_CH0_DQ29
CPU1_M_CH0_DQ28
CPU1_M_CH0_DQ27
CPU1_M_CH0_DQ26
CPU1_M_CH0_DQ25
CPU1_M_CH0_DQ24
CPU1_M_CH0_DQ23
CPU1_M_CH0_DQ22
CPU1_M_CH0_DQ21
CPU1_M_CH0_DQ20
CPU1_M_CH0_DQ19
CPU1_M_CH0_DQ18
CPU1_M_CH0_DQ17
CPU1_M_CH0_DQ16
CPU1_M_CH0_DQ15
CPU1_M_CH0_DQ14
CPU1_M_CH0_DQ13
CPU1_M_CH0_DQ12
CPU1_M_CH0_DQ11
CPU1_M_CH0_DQ10
CPU1_M_CH0_DQ09
CPU1_M_CH0_DQ08
CPU1_M_CH0_DQ07
CPU1_M_CH0_DQ06
CPU1_M_CH0_DQ05
CPU1_M_CH0_DQ04
CPU1_M_CH0_DQ03
CPU1_M_CH0_DQ02
CPU1_M_CH0_DQ01
CPU1_M_CH0_DQ00

CPU1_M_CH0_ECC_7
CPU1_M_CH0_ECC_6
CPU1_M_CH0_ECC_5
CPU1_M_CH0_ECC_4
CPU1_M_CH0_ECC_3
CPU1_M_CH0_ECC_2
CPU1_M_CH0_ECC_1
CPU1_M_CH0_ECC_0

CPU1_M_CH0_MA_PAR

NC_SCR_CPU1_M_CH0_PERR_2_N
CPU1_M_CH0_PERR_1_N
CPU1_M_CH0_PERR_0_N

W4

DDR0_DQ_63

V4

DDR0_DQ_62

U3

DDR0_DQ_61

U1

DDR0_DQ_60

Y3

DDR0_DQ_59

Y2

DDR0_DQ_58

V1

DDR0_DQ_57

U4

DDR0_DQ_56

T3

DDR0_DQ_55

R4

DDR0_DQ_54

N3

DDR0_DQ_53

M3

DDR0_DQ_52

T2

DDR0_DQ_51

T1

DDR0_DQ_50

N2

DDR0_DQ_49

N1

DDR0_DQ_48

L2

DDR0_DQ_47

L3

DDR0_DQ_46

H3

DDR0_DQ_45

G1

DDR0_DQ_44

M1

DDR0_DQ_43

L1

DDR0_DQ_42

H1

DDR0_DQ_41

H2

DDR0_DQ_40

F2

DDR0_DQ_39

F3

DDR0_DQ_38

C6

DDR0_DQ_37

B6

DDR0_DQ_36

G3

DDR0_DQ_35

F1

DDR0_DQ_34

C4

DDR0_DQ_33

B5

DDR0_DQ_32

B38

DDR0_DQ_31

C38

DDR0_DQ_30

D42

DDR0_DQ_29

D41

DDR0_DQ_28

D37

DDR0_DQ_27

A38

DDR0_DQ_26

C41

DDR0_DQ_25

D40

DDR0_DQ_24

F42

DDR0_DQ_23

F43

DDR0_DQ_22

J41

DDR0_DQ_21

J42

DDR0_DQ_20

E43

DDR0_DQ_19

E42

DDR0_DQ_18

H43

DDR0_DQ_17

H41

DDR0_DQ_16

L42

DDR0_DQ_15

L43

DDR0_DQ_14

P41

DDR0_DQ_13

P42

DDR0_DQ_12

K43

DDR0_DQ_11

K42

DDR0_DQ_10

N43

DDR0_DQ_9

N41

DDR0_DQ_8

T42

DDR0_DQ_7

U41

DDR0_DQ_6

W42

DDR0_DQ_5

W40

DDR0_DQ_4

R42

DDR0_DQ_3

R43

DDR0_DQ_2

V41

DDR0_DQ_1

W41

DDR0_DQ_0

C34

DDR0_ECC_7

B34

DDR0_ECC_6

A37

DDR0_ECC_5

C37

DDR0_ECC_4

C33

DDR0_ECC_3

F32

DDR0_ECC_2

A36

DDR0_ECC_1

C36

DDR0_ECC_0

B20

DDR0_MA_PAR

A27

DDR0_PAR_ERR_N_2

B28

DDR0_PAR_ERR_N_1

D25

DDR0_PAR_ERR_N_0

DDR0_DQS_P_17
DDR0_DQS_P_16
DDR0_DQS_P_15
DDR0_DQS_P_14
DDR0_DQS_P_13
DDR0_DQS_P_12
DDR0_DQS_P_11
DDR0_DQS_P_10

DDR0_DQS_P_9
DDR0_DQS_P_8
DDR0_DQS_P_7
DDR0_DQS_P_6
DDR0_DQS_P_5
DDR0_DQS_P_4
DDR0_DQS_P_3
DDR0_DQS_P_2
DDR0_DQS_P_1
DDR0_DQS_P_0

DDR0_DQS_N_17
DDR0_DQS_N_16
DDR0_DQS_N_15
DDR0_DQS_N_14
DDR0_DQS_N_13
DDR0_DQS_N_12
DDR0_DQS_N_11
DDR0_DQS_N_10

DDR0_DQS_N_9
DDR0_DQS_N_8
DDR0_DQS_N_7
DDR0_DQS_N_6
DDR0_DQS_N_5
DDR0_DQS_N_4
DDR0_DQS_N_3
DDR0_DQS_N_2
DDR0_DQS_N_1
DDR0_DQS_N_0

DDR0_MA_15
DDR0_MA_14
DDR0_MA_13
DDR0_MA_12
DDR0_MA_11
DDR0_MA_10

DDR0_MA_9
DDR0_MA_8
DDR0_MA_7
DDR0_MA_6
DDR0_MA_5
DDR0_MA_4
DDR0_MA_3
DDR0_MA_2
DDR0_MA_1
DDR0_MA_0

DDR0_BA_2
DDR0_BA_1
DDR0_BA_0

DDR0_CLK_P_3
DDR0_CLK_P_2
DDR0_CLK_P_1
DDR0_CLK_P_0

DDR0_CLK_N_3
DDR0_CLK_N_2
DDR0_CLK_N_1
DDR0_CLK_N_0

DDR0_CS_N_7/DDR0_ODT_5
DDR0_CS_N_6/DDR0_ODT_4

DDR0_CS_N_5
DDR0_CS_N_4
DDR0_CS_N_3
DDR0_CS_N_2
DDR0_CS_N_1
DDR0_CS_N_0

B36
V2
P2
J2
D5
D39
H42
N42
V43
D34
W2
R2
K2
E3
B39
F41
L41
T43

B35
V3
P1
J1
D4
C39
G43
M43
V42
D35
W1
R3
K3
E4
B40
G41
M41
U43

B29
A28
A10
B26
A26
B19
C26
B25
A25
C24
B24
B23
D24
C23
B21
A20

C28
A16
B16

E20
F18
D19
J19

E19
E18
C19
K19

B8
C11
A7
B15
B9
C13
B10
G15

CPU1_M_CH0_DQS_17_DP
CPU1_M_CH0_DQS_16_DP
CPU1_M_CH0_DQS_15_DP
CPU1_M_CH0_DQS_14_DP
CPU1_M_CH0_DQS_13_DP
CPU1_M_CH0_DQS_12_DP
CPU1_M_CH0_DQS_11_DP
CPU1_M_CH0_DQS_10_DP
CPU1_M_CH0_DQS_09_DP
CPU1_M_CH0_DQS_08_DP
CPU1_M_CH0_DQS_07_DP
CPU1_M_CH0_DQS_06_DP
CPU1_M_CH0_DQS_05_DP
CPU1_M_CH0_DQS_04_DP
CPU1_M_CH0_DQS_03_DP
CPU1_M_CH0_DQS_02_DP
CPU1_M_CH0_DQS_01_DP
CPU1_M_CH0_DQS_00_DP

CPU1_M_CH0_DQS_17_DN
CPU1_M_CH0_DQS_16_DN
CPU1_M_CH0_DQS_15_DN
CPU1_M_CH0_DQS_14_DN
CPU1_M_CH0_DQS_13_DN
CPU1_M_CH0_DQS_12_DN
CPU1_M_CH0_DQS_11_DN
CPU1_M_CH0_DQS_10_DN
CPU1_M_CH0_DQS_09_DN
CPU1_M_CH0_DQS_08_DN
CPU1_M_CH0_DQS_07_DN
CPU1_M_CH0_DQS_06_DN
CPU1_M_CH0_DQS_05_DN
CPU1_M_CH0_DQS_04_DN
CPU1_M_CH0_DQS_03_DN
CPU1_M_CH0_DQS_02_DN
CPU1_M_CH0_DQS_01_DN
CPU1_M_CH0_DQS_00_DN

CPU1_M_CH0_MA_15
CPU1_M_CH0_MA_14
CPU1_M_CH0_MA_13
CPU1_M_CH0_MA_12
CPU1_M_CH0_MA_11
CPU1_M_CH0_MA_10
CPU1_M_CH0_MA_09
CPU1_M_CH0_MA_08
CPU1_M_CH0_MA_07
CPU1_M_CH0_MA_06
CPU1_M_CH0_MA_05
CPU1_M_CH0_MA_04
CPU1_M_CH0_MA_03
CPU1_M_CH0_MA_02
CPU1_M_CH0_MA_01
CPU1_M_CH0_MA_00

CPU1_M_CH0_BA_2
CPU1_M_CH0_BA_1
CPU1_M_CH0_BA_0

CPU1_M_CH0_CK_3_DP
CPU1_M_CH0_CK_2_DP
CPU1_M_CH0_CK_1_DP
CPU1_M_CH0_CK_0_DP

CPU1_M_CH0_CK_3_DN
CPU1_M_CH0_CK_2_DN
CPU1_M_CH0_CK_1_DN
CPU1_M_CH0_CK_0_DN

CPU1_M_CH0_CS_7_N
CPU1_M_CH0_CS_6_N
CPU1_M_CH0_CS_5_N
CPU1_M_CH0_CS_4_N
CPU1_M_CH0_CS_3_N
CPU1_M_CH0_CS_2_N
CPU1_M_CH0_CS_1_N
CPU1_M_CH0_CS_0_N

20,21
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20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21

20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21

20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21
20,21

20,21
20,21
20,21

21
20
21
20

21
20
21
20

21
21
21
21
20
20
20
20

23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24

23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24

23,24

24
23

CPU1_M_CH1_DQ63
CPU1_M_CH1_DQ62
CPU1_M_CH1_DQ61
CPU1_M_CH1_DQ60
CPU1_M_CH1_DQ59
CPU1_M_CH1_DQ58
CPU1_M_CH1_DQ57
CPU1_M_CH1_DQ56
CPU1_M_CH1_DQ55
CPU1_M_CH1_DQ54
CPU1_M_CH1_DQ53
CPU1_M_CH1_DQ52
CPU1_M_CH1_DQ51
CPU1_M_CH1_DQ50
CPU1_M_CH1_DQ49
CPU1_M_CH1_DQ48
CPU1_M_CH1_DQ47
CPU1_M_CH1_DQ46
CPU1_M_CH1_DQ45
CPU1_M_CH1_DQ44
CPU1_M_CH1_DQ43
CPU1_M_CH1_DQ42
CPU1_M_CH1_DQ41
CPU1_M_CH1_DQ40
CPU1_M_CH1_DQ39
CPU1_M_CH1_DQ38
CPU1_M_CH1_DQ37
CPU1_M_CH1_DQ36
CPU1_M_CH1_DQ35
CPU1_M_CH1_DQ34
CPU1_M_CH1_DQ33
CPU1_M_CH1_DQ32
CPU1_M_CH1_DQ31
CPU1_M_CH1_DQ30
CPU1_M_CH1_DQ29
CPU1_M_CH1_DQ28
CPU1_M_CH1_DQ27
CPU1_M_CH1_DQ26
CPU1_M_CH1_DQ25
CPU1_M_CH1_DQ24
CPU1_M_CH1_DQ23
CPU1_M_CH1_DQ22
CPU1_M_CH1_DQ21
CPU1_M_CH1_DQ20
CPU1_M_CH1_DQ19
CPU1_M_CH1_DQ18
CPU1_M_CH1_DQ17
CPU1_M_CH1_DQ16
CPU1_M_CH1_DQ15
CPU1_M_CH1_DQ14
CPU1_M_CH1_DQ13
CPU1_M_CH1_DQ12
CPU1_M_CH1_DQ11
CPU1_M_CH1_DQ10
CPU1_M_CH1_DQ09
CPU1_M_CH1_DQ08
CPU1_M_CH1_DQ07
CPU1_M_CH1_DQ06
CPU1_M_CH1_DQ05
CPU1_M_CH1_DQ04
CPU1_M_CH1_DQ03
CPU1_M_CH1_DQ02
CPU1_M_CH1_DQ01
CPU1_M_CH1_DQ00

CPU1_M_CH1_ECC_7
CPU1_M_CH1_ECC_6
CPU1_M_CH1_ECC_5
CPU1_M_CH1_ECC_4
CPU1_M_CH1_ECC_3
CPU1_M_CH1_ECC_2
CPU1_M_CH1_ECC_1
CPU1_M_CH1_ECC_0

CPU1_M_CH1_MA_PAR

NC_SCR_CPU1_M_CH1_PERR_2_N
CPU1_M_CH1_PERR_1_N
CPU1_M_CH1_PERR_0_N

W9

DDR1_DQ_63

AA7

DDR1_DQ_62

W5

DDR1_DQ_61

V9

DDR1_DQ_60

W10

DDR1_DQ_59

Y10

DDR1_DQ_58

W7

DDR1_DQ_57

W6

DDR1_DQ_56

R7

DDR1_DQ_55

R8

DDR1_DQ_54

M6

DDR1_DQ_53

J4

DDR1_DQ_52

T5

DDR1_DQ_51

R5

DDR1_DQ_50

K5

DDR1_DQ_49

K4

DDR1_DQ_48

J5

DDR1_DQ_47

G5

DDR1_DQ_46

H9

DDR1_DQ_45

G9

DDR1_DQ_44

H4

DDR1_DQ_43

G4

DDR1_DQ_42

J6

DDR1_DQ_41

H8

DDR1_DQ_40

F6

DDR1_DQ_39

D6

DDR1_DQ_38

G8

DDR1_DQ_37

F10

DDR1_DQ_36

F5

DDR1_DQ_35

E5

DDR1_DQ_34

E8

DDR1_DQ_33

E9

DDR1_DQ_32

K30

DDR1_DQ_31

L32

DDR1_DQ_30

H34

DDR1_DQ_29

J34

DDR1_DQ_28

J32

DDR1_DQ_27

K32

DDR1_DQ_26

L33

DDR1_DQ_25

H33

DDR1_DQ_24

H36

DDR1_DQ_23

J36

DDR1_DQ_22

M36

DDR1_DQ_21

N34

DDR1_DQ_20

J35

DDR1_DQ_19

K35

DDR1_DQ_18

M34

DDR1_DQ_17

M35

DDR1_DQ_16

N38

DDR1_DQ_15

N37

DDR1_DQ_14

R35

DDR1_DQ_13

R34

DDR1_DQ_12

N39

DDR1_DQ_11

P39

DDR1_DQ_10

P35

DDR1_DQ_9

P34

DDR1_DQ_8

Y39

DDR1_DQ_7

Y40

DDR1_DQ_6

AB36

DDR1_DQ_5

AA35

DDR1_DQ_4

Y34

DDR1_DQ_3

Y35

DDR1_DQ_2

AA36

DDR1_DQ_1

AA37

DDR1_DQ_0

G35

DDR1_ECC_7

E34

DDR1_ECC_6

F37

DDR1_ECC_5

E37

DDR1_ECC_4

G36

DDR1_ECC_3

E33

DDR1_ECC_2

F36

DDR1_ECC_1

D36

DDR1_ECC_0

D20

DDR1_MA_PAR

F25

DDR1_PAR_ERR_N_2

E25

DDR1_PAR_ERR_N_1

C22

DDR1_PAR_ERR_N_0

DDR1_DQS_P_17
DDR1_DQS_P_16
DDR1_DQS_P_15
DDR1_DQS_P_14
DDR1_DQS_P_13
DDR1_DQS_P_12
DDR1_DQS_P_11
DDR1_DQS_P_10

DDR1_DQS_P_9
DDR1_DQS_P_8
DDR1_DQS_P_7
DDR1_DQS_P_6
DDR1_DQS_P_5
DDR1_DQS_P_4
DDR1_DQS_P_3
DDR1_DQS_P_2
DDR1_DQS_P_1
DDR1_DQS_P_0

DDR1_DQS_N_17
DDR1_DQS_N_16
DDR1_DQS_N_15
DDR1_DQS_N_14
DDR1_DQS_N_13
DDR1_DQS_N_12
DDR1_DQS_N_11
DDR1_DQS_N_10

DDR1_DQS_N_9
DDR1_DQS_N_8
DDR1_DQS_N_7
DDR1_DQS_N_6
DDR1_DQS_N_5
DDR1_DQS_N_4
DDR1_DQS_N_3
DDR1_DQS_N_2
DDR1_DQS_N_1
DDR1_DQS_N_0

DDR1_MA_15
DDR1_MA_14
DDR1_MA_13
DDR1_MA_12
DDR1_MA_11
DDR1_MA_10

DDR1_MA_9
DDR1_MA_8
DDR1_MA_7
DDR1_MA_6
DDR1_MA_5
DDR1_MA_4
DDR1_MA_3
DDR1_MA_2
DDR1_MA_1
DDR1_MA_0

DDR1_BA_2
DDR1_BA_1
DDR1_BA_0

DDR1_CLK_P_3
DDR1_CLK_P_2
DDR1_CLK_P_1
DDR1_CLK_P_0

DDR1_CLK_N_3
DDR1_CLK_N_2
DDR1_CLK_N_1
DDR1_CLK_N_0

DDR1_CS_N_7/DDR1_ODT_5
DDR1_CS_N_6/DDR1_ODT_4

DDR1_CS_N_5
DDR1_CS_N_4
DDR1_CS_N_3
DDR1_CS_N_2
DDR1_CS_N_1
DDR1_CS_N_0

F35
Y4
M5
H7
F8
K34
L37
P36
AA40
G33
Y8
L6
H6
E7
L30
L35
R38
Y38

E35
Y5
M4
J7
F7
K33
K37
P37
AA41
G34
Y9
L5
G6
D7
L31
L36
R37
Y37

F26
H26
B14
E24
E23
H14
G24
E22
D22
J27
F22
K28
L28
J17
J16
J14

H27
K13
C18

H18
K18
G19
C21

H19
L18
G20
D21

E12
C14
E10
C17
E13
E15
A8
D12

CPU1_M_CH1_DQS_17_DP
CPU1_M_CH1_DQS_16_DP
CPU1_M_CH1_DQS_15_DP
CPU1_M_CH1_DQS_14_DP
CPU1_M_CH1_DQS_13_DP
CPU1_M_CH1_DQS_12_DP
CPU1_M_CH1_DQS_11_DP
CPU1_M_CH1_DQS_10_DP
CPU1_M_CH1_DQS_09_DP
CPU1_M_CH1_DQS_08_DP
CPU1_M_CH1_DQS_07_DP
CPU1_M_CH1_DQS_06_DP
CPU1_M_CH1_DQS_05_DP
CPU1_M_CH1_DQS_04_DP
CPU1_M_CH1_DQS_03_DP
CPU1_M_CH1_DQS_02_DP
CPU1_M_CH1_DQS_01_DP
CPU1_M_CH1_DQS_00_DP

CPU1_M_CH1_DQS_17_DN
CPU1_M_CH1_DQS_16_DN
CPU1_M_CH1_DQS_15_DN
CPU1_M_CH1_DQS_14_DN
CPU1_M_CH1_DQS_13_DN
CPU1_M_CH1_DQS_12_DN
CPU1_M_CH1_DQS_11_DN
CPU1_M_CH1_DQS_10_DN
CPU1_M_CH1_DQS_09_DN
CPU1_M_CH1_DQS_08_DN
CPU1_M_CH1_DQS_07_DN
CPU1_M_CH1_DQS_06_DN
CPU1_M_CH1_DQS_05_DN
CPU1_M_CH1_DQS_04_DN
CPU1_M_CH1_DQS_03_DN
CPU1_M_CH1_DQS_02_DN
CPU1_M_CH1_DQS_01_DN
CPU1_M_CH1_DQS_00_DN

CPU1_M_CH1_MA_15
CPU1_M_CH1_MA_14
CPU1_M_CH1_MA_13
CPU1_M_CH1_MA_12
CPU1_M_CH1_MA_11
CPU1_M_CH1_MA_10
CPU1_M_CH1_MA_09
CPU1_M_CH1_MA_08
CPU1_M_CH1_MA_07
CPU1_M_CH1_MA_06
CPU1_M_CH1_MA_05
CPU1_M_CH1_MA_04
CPU1_M_CH1_MA_03
CPU1_M_CH1_MA_02
CPU1_M_CH1_MA_01
CPU1_M_CH1_MA_00

CPU1_M_CH1_BA_2
CPU1_M_CH1_BA_1
CPU1_M_CH1_BA_0

CPU1_M_CH1_CK_3_DP
CPU1_M_CH1_CK_2_DP
CPU1_M_CH1_CK_1_DP
CPU1_M_CH1_CK_0_DP

CPU1_M_CH1_CK_3_DN
CPU1_M_CH1_CK_2_DN
CPU1_M_CH1_CK_1_DN
CPU1_M_CH1_CK_0_DN

CPU1_M_CH1_CS_7_N
CPU1_M_CH1_CS_6_N
CPU1_M_CH1_CS_5_N
CPU1_M_CH1_CS_4_N
CPU1_M_CH1_CS_3_N
CPU1_M_CH1_CS_2_N
CPU1_M_CH1_CS_1_N
CPU1_M_CH1_CS_0_N

23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24

23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24

23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24
23,24

23,24
23,24
23,24

24
23
24
23

24
23
24
23

24
24
24
24
23
23
23
23

1

2

3

4

CPU1_M_CH0_ODT_3

21

CPU1_M_CH0_ODT_2

21

CPU1_M_CH0_ODT_1

20

CPU1_M_CH0_ODT_0

20

C7

DDR0_ODT_3

B11

DDR0_ODT_2

C9

DDR0_ODT_1

F12

DDR0_ODT_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 2 OF 10

DDR0_CKE_3
DDR0_CKE_2
DDR0_CKE_1
DDR0_CKE_0

DDR0_WE_N
DDR0_RAS_N
DDR0_CAS_N

DDR0_RESET_N

B31
B30
A30
C29

B13
A15
C12

D32

CPU1_M_CH0_CKE_3
CPU1_M_CH0_CKE_2
CPU1_M_CH0_CKE_1
CPU1_M_CH0_CKE_0

CPU1_M_CH0_WE_N
CPU1_M_CH0_RAS_N
CPU1_M_CH0_CAS_N

CPU1_M_CH0_RST_N

21
20
21
20

CPU1_M_CH1_ODT_3

24
20,21
20,21
20,21

20,21

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

CPU1_M_CH1_ODT_2

24

CPU1_M_CH1_ODT_1

23

CPU1_M_CH1_ODT_0

23

F11

DDR1_ODT_3

D14

DDR1_ODT_2

C8

DDR1_ODT_1

D11

DDR1_ODT_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 3 OF 10

DDR1_CKE_3
DDR1_CKE_2
DDR1_CKE_1
DDR1_CKE_0

DDR1_WE_N
DDR1_RAS_N
DDR1_CAS_N

DDR1_RESET_N

C27
D27
E27
H28

G13
G14
E14

D29

CPU1_M_CH1_CKE_3
CPU1_M_CH1_CKE_2
CPU1_M_CH1_CKE_1
CPU1_M_CH1_CKE_0

CPU1_M_CH1_WE_N
CPU1_M_CH1_RAS_N
CPU1_M_CH1_CAS_N

CPU1_M_CH1_RST_N

TITLE

CPU1

DWG NO.

DATE

24
23
24
23

23,24
23,24
23,24

MODULE:
DESC:

23,24

REV: OF

INC.

SCHEM,PLN,SV,R610

RR154

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

13 OF 14511/6/2008

DCBA

1

2

3

26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27

26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27

26,27

27
26

A B C

J_CPU1

CPU1_M_CH2_DQ63
CPU1_M_CH2_DQ62
CPU1_M_CH2_DQ61
CPU1_M_CH2_DQ60
CPU1_M_CH2_DQ59
CPU1_M_CH2_DQ58
CPU1_M_CH2_DQ57
CPU1_M_CH2_DQ56
CPU1_M_CH2_DQ55
CPU1_M_CH2_DQ54
CPU1_M_CH2_DQ53
CPU1_M_CH2_DQ52
CPU1_M_CH2_DQ51
CPU1_M_CH2_DQ50
CPU1_M_CH2_DQ49
CPU1_M_CH2_DQ48
CPU1_M_CH2_DQ47
CPU1_M_CH2_DQ46
CPU1_M_CH2_DQ45
CPU1_M_CH2_DQ44
CPU1_M_CH2_DQ43
CPU1_M_CH2_DQ42
CPU1_M_CH2_DQ41
CPU1_M_CH2_DQ40
CPU1_M_CH2_DQ39
CPU1_M_CH2_DQ38
CPU1_M_CH2_DQ37
CPU1_M_CH2_DQ36
CPU1_M_CH2_DQ35
CPU1_M_CH2_DQ34
CPU1_M_CH2_DQ33
CPU1_M_CH2_DQ32
CPU1_M_CH2_DQ31
CPU1_M_CH2_DQ30
CPU1_M_CH2_DQ29
CPU1_M_CH2_DQ28
CPU1_M_CH2_DQ27
CPU1_M_CH2_DQ26
CPU1_M_CH2_DQ25
CPU1_M_CH2_DQ24
CPU1_M_CH2_DQ23
CPU1_M_CH2_DQ22
CPU1_M_CH2_DQ21
CPU1_M_CH2_DQ20
CPU1_M_CH2_DQ19
CPU1_M_CH2_DQ18
CPU1_M_CH2_DQ17
CPU1_M_CH2_DQ16
CPU1_M_CH2_DQ15
CPU1_M_CH2_DQ14
CPU1_M_CH2_DQ13
CPU1_M_CH2_DQ12
CPU1_M_CH2_DQ11
CPU1_M_CH2_DQ10
CPU1_M_CH2_DQ09
CPU1_M_CH2_DQ08
CPU1_M_CH2_DQ07
CPU1_M_CH2_DQ06
CPU1_M_CH2_DQ05
CPU1_M_CH2_DQ04
CPU1_M_CH2_DQ03
CPU1_M_CH2_DQ02
CPU1_M_CH2_DQ01
CPU1_M_CH2_DQ00

CPU1_M_CH2_ECC_7
CPU1_M_CH2_ECC_6
CPU1_M_CH2_ECC_5
CPU1_M_CH2_ECC_4
CPU1_M_CH2_ECC_3
CPU1_M_CH2_ECC_2
CPU1_M_CH2_ECC_1
CPU1_M_CH2_ECC_0

CPU1_M_CH2_MA_PAR

NC_SCR_CPU1_M_CH2_PERR_2_N
CPU1_M_CH2_PERR_1_N
CPU1_M_CH2_PERR_0_N

U9

DDR2_DQ_63

V8

DDR2_DQ_62

T7

DDR2_DQ_61

T6

DDR2_DQ_60

U10

DDR2_DQ_59

T10

DDR2_DQ_58

U6

DDR2_DQ_57

U5

DDR2_DQ_56

R9

DDR2_DQ_55

R10

DDR2_DQ_54

N7

DDR2_DQ_53

N8

DDR2_DQ_52

P10

DDR2_DQ_51

P9

DDR2_DQ_50

N6

DDR2_DQ_49

P7

DDR2_DQ_48

M8

DDR2_DQ_47

L8

DDR2_DQ_46

M10

DDR2_DQ_45

L11

DDR2_DQ_44

N9

DDR2_DQ_43

M9

DDR2_DQ_42

K10

DDR2_DQ_41

L10

DDR2_DQ_40

L12

DDR2_DQ_39

H12

DDR2_DQ_38

G10

DDR2_DQ_37

G11

DDR2_DQ_36

L13

DDR2_DQ_35

H13

DDR2_DQ_34

J12

DDR2_DQ_33

K12

DDR2_DQ_32

E38

DDR2_DQ_31

F38

DDR2_DQ_30

G39

DDR2_DQ_29

H39

DDR2_DQ_28

H37

DDR2_DQ_27

J37

DDR2_DQ_26

F40

DDR2_DQ_25

G40

DDR2_DQ_24

K38

DDR2_DQ_23

L40

DDR2_DQ_22

N36

DDR2_DQ_21

P40

DDR2_DQ_20

J39

DDR2_DQ_19

J40

DDR2_DQ_18

M40

DDR2_DQ_17

M39

DDR2_DQ_16

R40

DDR2_DQ_15

T41

DDR2_DQ_14

V39

DDR2_DQ_13

W39

DDR2_DQ_12

T36

DDR2_DQ_11

R39

DDR2_DQ_10

U39

DDR2_DQ_9

U38

DDR2_DQ_8

V38

DDR2_DQ_7

V37

DDR2_DQ_6

V34

DDR2_DQ_5

U34

DDR2_DQ_4

U36

DDR2_DQ_3

V36

DDR2_DQ_2

W35

DDR2_DQ_1

W34

DDR2_DQ_0

F30

DDR2_ECC_7

F31

DDR2_ECC_6

J30

DDR2_ECC_5

J31

DDR2_ECC_4

E30

DDR2_ECC_3

E29

DDR2_ECC_2

F33

DDR2_ECC_1

H32

DDR2_ECC_0

B18

DDR2_MA_PAR

F23

DDR2_PAR_ERR_N_2

J25

DDR2_PAR_ERR_N_1

F21

DDR2_PAR_ERR_N_0

DDR2_DQS_P_17
DDR2_DQS_P_16
DDR2_DQS_P_15
DDR2_DQS_P_14
DDR2_DQS_P_13
DDR2_DQS_P_12
DDR2_DQS_P_11
DDR2_DQS_P_10

DDR2_DQS_P_9
DDR2_DQS_P_8
DDR2_DQS_P_7
DDR2_DQS_P_6
DDR2_DQS_P_5
DDR2_DQS_P_4
DDR2_DQS_P_3
DDR2_DQS_P_2
DDR2_DQS_P_1
DDR2_DQS_P_0

DDR2_DQS_N_17
DDR2_DQS_N_16
DDR2_DQS_N_15
DDR2_DQS_N_14
DDR2_DQS_N_13
DDR2_DQS_N_12
DDR2_DQS_N_11
DDR2_DQS_N_10

DDR2_DQS_N_9
DDR2_DQS_N_8
DDR2_DQS_N_7
DDR2_DQS_N_6
DDR2_DQS_N_5
DDR2_DQS_N_4
DDR2_DQS_N_3
DDR2_DQS_N_2
DDR2_DQS_N_1
DDR2_DQS_N_0

DDR2_MA_15
DDR2_MA_14
DDR2_MA_13
DDR2_MA_12
DDR2_MA_11
DDR2_MA_10

DDR2_MA_9
DDR2_MA_8
DDR2_MA_7
DDR2_MA_6
DDR2_MA_5
DDR2_MA_4
DDR2_MA_3
DDR2_MA_2
DDR2_MA_1
DDR2_MA_0

DDR2_BA_2
DDR2_BA_1
DDR2_BA_0

DDR2_CLK_P_3
DDR2_CLK_P_2
DDR2_CLK_P_1
DDR2_CLK_P_0

DDR2_CLK_N_3
DDR2_CLK_N_2
DDR2_CLK_N_1
DDR2_CLK_N_0

DDR2_CS_N_7/DDR2_ODT_5
DDR2_CS_N_6/DDR2_ODT_4

DDR2_CS_N_5
DDR2_CS_N_4
DDR2_CS_N_3
DDR2_CS_N_2
DDR2_CS_N_1
DDR2_CS_N_0

H31
V6
N4
K9
H11
H38
M38
U40
U35
G29
U8
P6
L7
J10
E39
K40
T37
W37

G31
V7
P4
K8
J11
G38
L38
T40
T35
G30
T8
P5
K7
J9
E40
K39
T38
W36

G25
H24
F15
G23
H23
H17
H22
L25
J24
K22
K23
F20
J20
G18
K17
A18

L26
F17
A17

L22
H21
L20
J22

L21
G21
K20
J21

J15
L17
D9
E17
H16
D16
K14
G16

CPU1_M_CH2_DQS_17_DP
CPU1_M_CH2_DQS_16_DP
CPU1_M_CH2_DQS_15_DP
CPU1_M_CH2_DQS_14_DP
CPU1_M_CH2_DQS_13_DP
CPU1_M_CH2_DQS_12_DP
CPU1_M_CH2_DQS_11_DP
CPU1_M_CH2_DQS_10_DP
CPU1_M_CH2_DQS_09_DP
CPU1_M_CH2_DQS_08_DP
CPU1_M_CH2_DQS_07_DP
CPU1_M_CH2_DQS_06_DP
CPU1_M_CH2_DQS_05_DP
CPU1_M_CH2_DQS_04_DP
CPU1_M_CH2_DQS_03_DP
CPU1_M_CH2_DQS_02_DP
CPU1_M_CH2_DQS_01_DP
CPU1_M_CH2_DQS_00_DP

CPU1_M_CH2_DQS_17_DN
CPU1_M_CH2_DQS_16_DN
CPU1_M_CH2_DQS_15_DN
CPU1_M_CH2_DQS_14_DN
CPU1_M_CH2_DQS_13_DN
CPU1_M_CH2_DQS_12_DN
CPU1_M_CH2_DQS_11_DN
CPU1_M_CH2_DQS_10_DN
CPU1_M_CH2_DQS_09_DN
CPU1_M_CH2_DQS_08_DN
CPU1_M_CH2_DQS_07_DN
CPU1_M_CH2_DQS_06_DN
CPU1_M_CH2_DQS_05_DN
CPU1_M_CH2_DQS_04_DN
CPU1_M_CH2_DQS_03_DN
CPU1_M_CH2_DQS_02_DN
CPU1_M_CH2_DQS_01_DN
CPU1_M_CH2_DQS_00_DN

CPU1_M_CH2_MA_15
CPU1_M_CH2_MA_14
CPU1_M_CH2_MA_13
CPU1_M_CH2_MA_12
CPU1_M_CH2_MA_11
CPU1_M_CH2_MA_10
CPU1_M_CH2_MA_09
CPU1_M_CH2_MA_08
CPU1_M_CH2_MA_07
CPU1_M_CH2_MA_06
CPU1_M_CH2_MA_05
CPU1_M_CH2_MA_04
CPU1_M_CH2_MA_03
CPU1_M_CH2_MA_02
CPU1_M_CH2_MA_01
CPU1_M_CH2_MA_00

CPU1_M_CH2_BA_2
CPU1_M_CH2_BA_1
CPU1_M_CH2_BA_0

CPU1_M_CH2_CK_3_DP
CPU1_M_CH2_CK_2_DP
CPU1_M_CH2_CK_1_DP
CPU1_M_CH2_CK_0_DP

CPU1_M_CH2_CK_3_DN
CPU1_M_CH2_CK_2_DN
CPU1_M_CH2_CK_1_DN
CPU1_M_CH2_CK_0_DN

CPU1_M_CH2_CS_7_N
CPU1_M_CH2_CS_6_N
CPU1_M_CH2_CS_5_N
CPU1_M_CH2_CS_4_N
CPU1_M_CH2_CS_3_N
CPU1_M_CH2_CS_2_N
CPU1_M_CH2_CS_1_N
CPU1_M_CH2_CS_0_N

26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27

26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27

26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27
26,27

26,27
26,27
26,27

27
26
27
26

27
26
27
26

27
27
27
27
26
26
26
26

IN to CPU

OUT to XDP

DBR not used with XDP

16,31,33,46,52

16,94
16,94

16
16,94
94,95

16

16
16
16

31,33

16

47

47

46

46

16
16,94
16,94

16,116

16

16

116

17

17

122
122

46

46

46

46

46

46

46

46

46

46

31,46
31,46
31,46

46

46

CPU_RST_N
CPU1_CAT_ERR_N
CPU1_THERMTRIP_N
CPU1_PROCHOT_N
CPU1_PRES_N

CPU1_CPLD_EVENT_N

MOD_CPU_CPU1_COMP_SOUTH_0

MOD_CPU_CPU1_M_DDR_COMP_2
MOD_CPU_CPU1_M_DDR_COMP_1
MOD_CPU_CPU1_M_DDR_COMP_0

PECI_CPU
MOD_CPU_PECI_CPU1_ID_N

CK_133M_CPU1_DP
CK_133M_CPU1_DN
MOD_CPU_CK_133M_CPU1_ITP_DP
MOD_CPU_CK_133M_CPU1_ITP_DN

MOD_CPU_VCORE_CPU1_GTL_PG
MEM_CPU1_GTL_PG
VTT_CPU1_GTL_PG

MOD_CPU_VCORE_CPU1_VID_7

16

MOD_CPU_VCORE_CPU1_VID_6

16

MOD_CPU_VCORE_CPU1_VID_5

16

MOD_CPU_VCORE_CPU1_VID_4

16

MOD_CPU_VCORE_CPU1_VID_3

16

VCORE_CPU1_VID_2

16

VCORE_CPU1_VID_1

16

VCORE_CPU1_VID_0

16

VTT_CPU1_VID_2

122

VTT_CPU1_VID_1

122

VTT_CPU1_VID_0

122

MOD_CPU_CPU1_PSI_N

MOD_CPU_CPU1_DDR3_VREF

MOD_CPU_CPU1_GTL_VREF

CPU1_ISENSE

MOD_CPU_VCORE_CPU1_SENSE_P
MOD_CPU_VCORE_CPU1_SENSE_N

VTT_CPU1_SENSE_P
VTT_CPU1_SENSE_N

TP_MOD_CPU_DBR_CPU1_N
MOD_CPU_XDP_CPU1_PRDY_N
MOD_CPU_XDP_CPU1_PREQ_N

MOD_CPU_XDP_CPU1_BPM_7_N
MOD_CPU_XDP_CPU1_BPM_6_N
MOD_CPU_XDP_CPU1_BPM_5_N
MOD_CPU_XDP_CPU1_BPM_4_N
MOD_CPU_XDP_CPU1_BPM_3_N
MOD_CPU_XDP_CPU1_BPM_2_N
MOD_CPU_XDP_CPU1_BPM_1_N
MOD_CPU_XDP_CPU1_BPM_0_N

MOD_CPU_JTAG_CPU_TRST_N
MOD_CPU_JTAG_CPU_TCK
MOD_CPU_JTAG_CPU_TMS
MOD_CPU_JTAG_CPU1_TDI
MOD_CPU_JTAG_CPU1_TDO

AL39

RESET_N

AC37

CAT_ERR_N

AG37

THERMTRIP_N

AG35

PROCHOT_N

AG36

SKTOCC_N

AB5

DDR_THERM_N

AB41

COMP0

AC1

DDR_COMP_2

Y7

DDR_COMP_1

AA8

DDR_COMP_0

AH36

PECI

AK35

PECI_ID_N/ODT

AJ35

BCLK_DP

AH35

BCLK_DN

AA5

BCLK_ITP_DP

AA4

BCLK_ITP_DN

AR7

VCCPWRGOOD

AA6

VDDPWRGOOD

AB35

VTTPWRGOOD

AN8

VID_7

AP8

VID_6

AP9

VID5_CSC_2

AN10

VID4_CSC_1

AM10

VID3_CSC_0

AN9

VID2_MSID_2

AL9

VID1_MSID_1

AL10

VID0_MSID_0

AV6

VTT_VID_4

AF7

VTT_VID_3

AV3

VTT_VID_2

AP7

PSI_N

L23

DDR_VREF

AJ37

GTLREF

AK8

ISENSE

AR9

VCC_SENSE

AR8

VSS_SENSE

AE36

VTTD_SENSE

AE37

VSS_SENSE_VTTD

AF10

DBR_N

B41

PRDY_N

C42

PREQ_N

E2

BPM_N_7

D2

BPM_N_6

C3

BPM_N_5

D1

BPM_N_4

B4

BPM_N_3

C2

BPM_N_2

A5

BPM_N_1

B3

BPM_N_0

AH9

TRST_N

AH10

TCK

AG10

TMS

AJ9

TDI

AJ10

TDO

GAINESTOWN_WESTMERE REV 2.0

J_CPU1

Ball L23 is DDR_VREF in Intel CRB

DDR_THERM2_N

TAPPWRGOOD

HETERO 5 OF 10

RSVD_66
RSVD_65
RSVD_64
RSVD_63
RSVD_62
RSVD_61
RSVD_60
RSVD_59
RSVD_58
RSVD_57
RSVD_56
RSVD_55
RSVD_54
RSVD_53
RSVD_52
RSVD_51
RSVD_50
RSVD_49
RSVD_48
RSVD_47
RSVD_46
RSVD_45
RSVD_44
RSVD_43
RSVD_42
RSVD_41
RSVD_40
RSVD_39
RSVD_38
RSVD_37
RSVD_36
RSVD_35
RSVD_34

RSVD_32
RSVD_31
RSVD_30
RSVD_29
RSVD_28
RSVD_27
RSVD_26
RSVD_25
RSVD_24
RSVD_23
RSVD_22
RSVD_21
RSVD_20
RSVD_19

RSVD_15
RSVD_14

RSVD_12
RSVD_11
RSVD_10

RSVD_9
RSVD_8
RSVD_7
RSVD_6
RSVD_5

RSVD_3
RSVD_2
RSVD_1
RSVD_0

D

B33
F27
K25
K27
D30
K29
J29
G28
H29
E28
F28
A31
C32
C31
D31
AL3
AL38
AG1
AF1
AK7
AT5
AT4
V11
U11
A40
AL4
AL5
AL41
AL40
K24
AK36
K15
L15

AU2
BA40
AY40
AW41
AY41
AW42
AV43
AV42
AV1
AY3
AW2
AV2
AY4
BA4

AF4

NOTE: not implementing THERM2 method for Westmere, using PECI interface

AG4
AG5
AH5
AK2
AM36
AM38
AN36
AN38
AR36
AR37
AT36

AV35
AW39
AY35
AY39

NC_J_CPU1_B33
NC_J_CPU1_F27
NC_J_CPU1_K25
NC_J_CPU1_K27
NC_J_CPU1_D30
NC_J_CPU1_K29
NC_J_CPU1_J29
NC_J_CPU1_G28
NC_J_CPU1_H29
NC_J_CPU1_E28
NC_J_CPU1_F28
NC_J_CPU1_A31
NC_J_CPU1_C32
NC_J_CPU1_C31
NC_J_CPU1_D31
NC_J_CPU1_AL3

NC_J_CPU1_AL38

NC_J_CPU1_AG1
NC_J_CPU1_AF1
NC_J_CPU1_AK7
NC_J_CPU1_AT5
NC_J_CPU1_AT4
NC_J_CPU1_V11
NC_J_CPU1_U11
NC_J_CPU1_A40
NC_J_CPU1_AL4

NC_J_CPU1_AL5
NC_J_CPU1_AL41
NC_J_CPU1_AL40

NC_J_CPU1_K24
NC_J_CPU1_AK36

NC_J_CPU1_K15

NC_J_CPU1_L15

NC_J_CPU1_AU2
NC_J_CPU1_BA40
NC_J_CPU1_AY40
NC_J_CPU1_AW41
NC_J_CPU1_AY41
NC_J_CPU1_AW42
NC_J_CPU1_AV43
NC_J_CPU1_AV42

NC_J_CPU1_AV1

NC_J_CPU1_AY3

NC_J_CPU1_AW2

NC_J_CPU1_AV2

NC_J_CPU1_AY4

NC_J_CPU1_BA4

J_CPU1_TESTHI_AF4

NC_J_CPU1_AG4

NC_J_CPU1_AG5
CPU_TAPPWRGOOD

NC_J_CPU1_AK2
NC_J_CPU1_AM36
NC_J_CPU1_AM38
NC_J_CPU1_AN36
NC_J_CPU1_AN38
NC_J_CPU1_AR36
NC_J_CPU1_AR37
NC_J_CPU1_AT36

NC_J_CPU1_AV35
NC_J_CPU1_AW39
NC_J_CPU1_AY35
NC_J_CPU1_AY39

1

2

16

31,46

3

4

27
27
26
26

CPU1_M_CH2_ODT_3
CPU1_M_CH2_ODT_2
CPU1_M_CH2_ODT_1
CPU1_M_CH2_ODT_0

D10

DDR2_ODT_3

D15

DDR2_ODT_2

F13

DDR2_ODT_1

L16

DDR2_ODT_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 4 OF 10

DDR2_CKE_3
DDR2_CKE_2
DDR2_CKE_1
DDR2_CKE_0

DDR2_WE_N
DDR2_RAS_N
DDR2_CAS_N

DDR2_RESET_N

L27
D26
G26
J26

C16
D17
F16

E32

CPU1_M_CH2_CKE_3
CPU1_M_CH2_CKE_2
CPU1_M_CH2_CKE_1
CPU1_M_CH2_CKE_0

CPU1_M_CH2_WE_N
CPU1_M_CH2_RAS_N
CPU1_M_CH2_CAS_N

CPU1_M_CH2_RST_N

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

27
26
27
26

26,27
26,27
26,27

26,27

CPU1

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

RR154

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

14 OF 14511/6/2008

DCBA

A B C

D

CPU1

1

2

3

+MEM_CPU1

A14
A19
A24
A29

A9
B12
B17
B22
B27
B32

B7
C10
C15
C20
C25
C30
D13
D18
D23
D28
E11
E16
E21
E26
E31
F14
F19
F24
G17
G22
G27
H15
H20
H25
J18
J23
J28
K16
K21
K26
L14
L19
L24
M17

V_1V8_CPU1

18,115,141,144

NET_PHYSICAL_TYPE=PWR_PNG

M27

U33
V33
W33

VDDQ_44
VDDQ_43
VDDQ_42
VDDQ_41
VDDQ_40
VDDQ_39
VDDQ_38
VDDQ_37
VDDQ_36
VDDQ_35
VDDQ_34
VDDQ_33
VDDQ_32
VDDQ_31
VDDQ_30
VDDQ_29
VDDQ_28
VDDQ_27
VDDQ_26
VDDQ_25
VDDQ_24
VDDQ_23
VDDQ_22
VDDQ_21
VDDQ_20
VDDQ_19
VDDQ_18
VDDQ_17
VDDQ_16
VDDQ_15
VDDQ_14
VDDQ_13
VDDQ_12
VDDQ_11
VDDQ_10
VDDQ_9
VDDQ_8
VDDQ_7
VDDQ_6
VDDQ_5
VDDQ_4
VDDQ_3
VDDQ_2
VDDQ_1
VDDQ_0

VCCPLL_2
VCCPLL_1
VCCPLL_0

GAINESTOWN_WESTMERE REV 2.0

J_CPU1

HETERO 6 OF 10

VTTD_25
VTTD_24
VTTD_23
VTTD_22
VTTD_21
VTTD_20
VTTD_19
VTTD_18
VTTD_17
VTTD_16
VTTD_15
VTTD_14
VTTD_13
VTTD_12
VTTD_11
VTTD_10

VTTD_9
VTTD_8
VTTD_7
VTTD_6
VTTD_5
VTTD_4
VTTD_3
VTTD_2
VTTD_1
VTTD_0

VTTA_7
VTTA_6
VTTA_5
VTTA_4
VTTA_3
VTTA_2
VTTA_1
VTTA_0

AF37
AA10
AA11
AA33
AB10
AB11
AB33
AB34
AB8
AB9
AC10
AC11
AC33
AC34
AC35
AD34
AD35
AD36
AD9
AE34
AE35
AE8
AE9
AF36
AF8
AF9

AG34
AF34
AF33
AF11
AE33
AE11
AE10
AD10

+VTT_CPU1

J_CPU1

AH11

VCC_209

AH33

VCC_208

AJ11

VCC_207

AJ33

VCC_206

AK11

VCC_205

AK12

VCC_204

AK13

VCC_203

AK15

VCC_202

AK16

VCC_201

AK18

VCC_200

AK19

VCC_199

AK21

VCC_198

AK24

VCC_197

AK25

VCC_196

AK27

VCC_195

AK28

VCC_194

AK30

VCC_193

AK31

VCC_192

AK33

VCC_191

AL12

VCC_190

AL13

VCC_189

AL15

VCC_188

AL16

VCC_187

AL18

VCC_186

AL19

VCC_185

AL21

VCC_184

AL24

VCC_183

AL25

VCC_182

AL27

VCC_181

AL28

VCC_180

AL30

VCC_179

AL31

VCC_178

AL33

VCC_177

AL34

VCC_176

AM12

VCC_175

AM13

VCC_174

AM15

VCC_173

AM16

VCC_172

AM18

VCC_171

AM19

VCC_170

AM21

VCC_169

AM24

VCC_168

AM25

VCC_167

AM27

VCC_166

AM28

VCC_165

AM30

VCC_164

AM31

VCC_163

AM33

VCC_162

AM34

VCC_161

AN12

VCC_160

AN13

VCC_159

AN15

VCC_158

AN16

VCC_157

GAINESTOWN_WESTMERE REV 2.0

HETERO 7 OF 10

VCC_156
VCC_155
VCC_154
VCC_153
VCC_152
VCC_151
VCC_150
VCC_149
VCC_148
VCC_147
VCC_146
VCC_145
VCC_144
VCC_143
VCC_142
VCC_141
VCC_140
VCC_139
VCC_138
VCC_137
VCC_136
VCC_135
VCC_134
VCC_133
VCC_132
VCC_131
VCC_130
VCC_129
VCC_128
VCC_127
VCC_126
VCC_125
VCC_124
VCC_123
VCC_122
VCC_121
VCC_120
VCC_119
VCC_118
VCC_117
VCC_116
VCC_115
VCC_114
VCC_113
VCC_112
VCC_111
VCC_110
VCC_109
VCC_108
VCC_107
VCC_106
VCC_105
VCC_104

AN18
AN19
AN21
AN24
AN25
AN27
AN28
AN30
AN31
AN33
AN34
AP12
AP13
AP15
AP16
AP18
AP19
AP21
AP24
AP25
AP27
AP28
AP30
AP31
AP33
AP34
AR10
AR12
AR13
AR15
AR16
AR18
AR19
AR21
AR24
AR25
AR27
AR28
AR30
AR31
AR33
AR34
AT10
AT12
AT13
AT15
AT16
AT18
AT19
AT21
AT24
AT25
AT27

J_CPU1

Y6

VSS_309

Y41

VSS_308

Y36

VSS_307

Y33

VSS_306

Y11

VSS_305

Y1

+VCORE_CPU1 +VCORE_CPU1+VCORE_CPU1 +VCORE_CPU1

J_CPU1

AT28
AT30
AT31
AT33
AT34

AT9
AU10
AU12
AU13
AU15
AU16
AU18
AU19
AU21
AU24
AU25
AU27
AU28
AU30
AU31
AU33
AU34

AU9
AV10
AV12
AV13
AV15
AV16
AV18
AV19
AV21
AV24
AV25
AV27
AV28
AV30
AV31
AV33
AV34

AV9
AW10
AW12
AW13
AW15
AW16
AW18
AW19
AW21
AW24
AW25
AW27
AW28

VCC_103
VCC_102
VCC_101
VCC_100
VCC_99
VCC_98
VCC_97
VCC_96
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_89
VCC_88
VCC_87
VCC_86
VCC_85
VCC_84
VCC_83
VCC_82
VCC_81
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_63
VCC_62
VCC_61
VCC_60
VCC_59
VCC_58
VCC_57
VCC_56
VCC_55
VCC_54
VCC_53
VCC_52

GAINESTOWN_WESTMERE REV 2.0

HETERO 8 OF 10

VCC_51
VCC_50
VCC_49
VCC_48
VCC_47
VCC_46
VCC_45
VCC_44
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_35
VCC_34
VCC_33
VCC_32
VCC_31
VCC_30
VCC_29
VCC_28
VCC_27
VCC_26
VCC_25
VCC_24
VCC_23
VCC_22
VCC_21
VCC_20
VCC_19
VCC_18
VCC_17
VCC_16
VCC_15
VCC_14
VCC_13
VCC_12
VCC_11
VCC_10

VCC_9
VCC_8
VCC_7
VCC_6
VCC_5
VCC_4
VCC_3
VCC_2
VCC_1
VCC_0

AW30
AW31
AW33
AW34
AW9
AY10
AY12
AY13
AY15
AY16
AY18
AY19
AY21
AY24
AY25
AY27
AY28
AY30
AY31
AY33
AY34
AY9
BA10
BA12
BA13
BA15
BA16
BA18
BA19
BA24
BA25
BA27
BA28
BA30
BA9
M11
M13
M15
M19
M21
M23
M25
M29
M31
M33
N11
N33
R11
R33
T11
T33
W11

W8
W43
W38

W3

V5
V40
V35
V10

U7
U42
U37

U2

T9

T4
T39
T34

R6
R41
R36

R1

P8
P43
P38
P33

P3
P11

N5
N40
N35
N10

M7
M42
M37
M32
M30
M28
M26
M24
M22
M20

M2
M18
M16
M14
M12

L9

L4
L39
L34
L29

K6
K41
K36
K31
K11

K1

J8
J43
J38
J33

J3
J13

H5
H40
H35
H30
H10

G7
G42
G37
G32

G2
G12

VSS_304
VSS_303
VSS_302
VSS_301
VSS_300
VSS_299
VSS_298
VSS_297
VSS_296
VSS_295
VSS_294
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231

GAINESTOWN_WESTMERE REV 2.0

HETERO 9 OF 10

VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_195
VSS_194
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_188
VSS_187
VSS_186
VSS_185
VSS_184
VSS_183
VSS_182
VSS_181
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153

F9
F4
F39
F34
F29
E6
E41
E36
E1
D8
D43
D38
D33
D3
C5
C43
C40
C35
BA5
BA39
BA35
BA3
BA29
BA26
BA20
BA17
BA14
BA11
B42
B37
B2
AY7
AY42
AY37
AY32
AY29
AY26
AY23
AY22
AY20
AY2
AY17
AY14
AY11
AW8
AW6
AW35
AW32
AW29
AW26
AW23
AW22
AW20
AW17
AW14
AW11
AW1
AV41
AV4
AV39
AV32
AV29
AV26
AV23
AV22
AV20
AV17
AV14
AV11
AU5
AU43
AU36
AU35
AU32
AU29
AU26
AU23
AU22

AU20
AU17
AU14
AU11

AU1
AT8

AT7
AT41
AT38
AT35
AT32
AT29
AT26
AT23
AT22
AT20
AT17
AT14
AT11
AR39
AR35
AR32

AR3
AR29
AR26
AR23
AR22
AR20

AR2
AR17
AR14
AR11

AP6

AP5
AP43
AP37
AP36
AP35
AP32
AP29
AP26
AP23
AP22
AP20
AP17
AP14
AP11
AP10

AP1

AN7
AN41
AN37
AN35
AN32

AN3
AN29
AN26
AN23
AN22
AN20
AN17
AN14
AN11

AM9

AM5
AM39
AM37
AM35
AM32
AM29
AM26
AM23
AM22
AM20
AM17
AM14
AM11

AL7

VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_99
VSS_98
VSS_97
VSS_96
VSS_95
VSS_94
VSS_93
VSS_92
VSS_91
VSS_90
VSS_89
VSS_88
VSS_87
VSS_86
VSS_85
VSS_84
VSS_83
VSS_82
VSS_81
VSS_80
VSS_79
VSS_78
VSS_77
VSS_76
VSS_75

GAINESTOWN_WESTMERE REV 2.0

J_CPU1

HETERO 10 OF 10

MODULE:
DESC:
REV: OF

VSS_74
VSS_73
VSS_72
VSS_71
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_65
VSS_64
VSS_63
VSS_62
VSS_61
VSS_60
VSS_59
VSS_58
VSS_57
VSS_56
VSS_55
VSS_54
VSS_53
VSS_52
VSS_51
VSS_50
VSS_49
VSS_48
VSS_47
VSS_46
VSS_45
VSS_44
VSS_43
VSS_42
VSS_41
VSS_40
VSS_39
VSS_38
VSS_37
VSS_36
VSS_35
VSS_34
VSS_33
VSS_32
VSS_31
VSS_30
VSS_29
VSS_28
VSS_27
VSS_26
VSS_25
VSS_24
VSS_23
VSS_22
VSS_21
VSS_20
VSS_19
VSS_18
VSS_17
VSS_16
VSS_15
VSS_14
VSS_13
VSS_12
VSS_11
VSS_10

VSS_9
VSS_8
VSS_7
VSS_6
VSS_5
VSS_4
VSS_3
VSS_2
VSS_1
VSS_0

AL42
AL37
AL36
AL35
AL32
AL29
AL26
AL23
AL22
AL20
AL2
AL17
AL14
AL11
AL1
AK9
AK43
AK39
AK34
AK32
AK3
AK29
AK26
AK23
AK22
AK20
AK17
AK14
AK10
AJ5
AJ41
AJ36
AJ34
AH7
AH39
AH37
AH34
AH1
AG9
AG43
AG33
AG3
AG11
AF5
AF41
AF38
AF35
AE7
AE39
AE2
AD43
AD41
AD37
AD33
AD11
AC9
AC7
AC5
AC36
AC2
AB7
AB42
AB40
AB4
AB37
AA9
AA39
AA38
AA34
AA3
A6
A41
A4
A39
A35

1

2

3

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

SCHEM,PLN,SV,R610

RR154

DCBA

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

15 OF 14511/6/2008

1

A B C

NOTE: VTT_CPU1_GTL_PG - We know 1k is differnt from PDG's 100ohm.

Note: Placed close to CPU1

14,31,33,46,52

14,94

14,94

14,94

14

Different circuit implementation. Intel confirmed no rise time requirement See DT16314

+VTT_CPU1

R2856

MEM_CPU1_GTL_PG

VTT_CPU1_GTL_PG

J_CPU1_TESTHI_AF4

1 2

1K-1%

R2857

1 2

1K-1%

R7400

21

Rev 0.8 PDG has 75ohm PUs at each CPU and tied together.
Confirmed w/ Intel that we can seperate to determine who
created the CAT_ERR, as long as we forward the CAT_ERR to all CPUs.
Using 1x75ohm PU for CAT_ERR instead of 2x75ohm as these are for

termination, not current source

CPU_RST_N

CPU1_CAT_ERR_N

DT14599_rt_P00_change_resistor

+VTT_CPU1

R141

NP

1 2

49.9-1%

1 2

301-1%

X

R143

C466

ROOM=CPU1

21

.1uF

16V-10%

14,16

14,94

14,16

CPU1_PROCHOT_N

CPU1_THERMTRIP_N

CPU1_PROCHOT_N

D

R144

1 2

301-1%

R2019

1 2

1K-1%

R7630

1 2

22.6-1%

+VTT_CPU1

CPU1_CPLD_PROCHOT_N

CPU1

1

94

2

33,46,63

CPU_VCCP_PG

1K-1%

R1505

1 2

0-5%

MOD_CPU_VCORE_CPU1_GTL_PG

14

MOD_CPU_CSI_CPU1_COMP_1

12

MOD_CPU_CSI_CPU1_COMP_0

12

MOD_CPU_CPU1_COMP_SOUTH_0

14

MOD_CPU_CPU1_M_DDR_COMP_2

14

R1395

21.0-1%

R539

1 2

21

R1394

21.0-1%

R142

1 2

49.9-1%

21

2

3

MOD_CPU_VCORE_CPU1_VID_7

14

VID[7] : PD = VRM 11

NP

21

R543

X

21

R54421R546

1K-1%

+VTT_CPU1

21

R545

1K-1%

NP

21

R548

1K-1%

X

21

R547

1K-1%1K-1%

NP

21

R549

1K-1%

X

1K-1%

R3556

1 2

0-5%

MOD_CPU_CPU1_M_DDR_COMP_1

14

MOD_CPU_CPU1_M_DDR_COMP_0

14

VCORE_CPU1_VID_R_7

116

+MEM_CPU1

NP

R283

X

1 2

NP

R282

X

1 2

130-1%

R284

1 2

100-1%

100-1%

100-1%

R1365

1 2

24.9-1%

Gainestown processor is designed with
an internal VREF but external VREF
circuit is recommended as a backup.

MOD_CPU_CPU1_DDR3_VREF

NP

21

C468

X

.1uF

16V-10%

14,94

CPU1_PRES_N

14

+3.3VAUX

R1175

1 2

4.75K-1%

+VTT_CPU1

R1768

1 2

MOD_CPU_CPU1_PSI_N

NP

R1769

X

p23_17745_ws: change PSI PD to PU per MOW 40.

1K-1% 1K-1%

1 2

14,116

3

p21_17637_ws: Changed Cpu1 &CPu2 CSC to 95w max proc

MOD_CPU_VCORE_CPU1_VID_6

14

VID[6] : RSVD function - Pull Low.

MOD_CPU_VCORE_CPU1_VID_5

14

MOD_CPU_VCORE_CPU1_VID_4

14

MOD_CPU_VCORE_CPU1_VID_3

14

VID[5:3] : CSC

VCORE_CPU1_VID_2

14

VCORE_CPU1_VID_1

14

VCORE_CPU1_VID_0

14

VID[2:0] : MSID

R3552

1 2

0-5%

R3555

1 2

0-5%

R3554

1 2

0-5%

R3553

1 2

0-5%

NP

21

NP

21

NP

21

NP

21

R3551

1 2

0-5%

R3550

1 2

0-5%

R3549

1 2

0-5%

VCORE_CPU1_VID_R_6

VCORE_CPU1_VID_R_5

VCORE_CPU1_VID_R_4

VCORE_CPU1_VID_R_3

VCORE_CPU1_VID_R_2

VCORE_CPU1_VID_R_1

VCORE_CPU1_VID_R_0

116

116

116

116

116

116

116

+VTT_CPU1

NP

R280

X

1 2

NP

R281

X

1 2

Gainestown processor is designed with
an internal VREF but external VREF
circuit is recommended as a backup.

MOD_CPU_CPU1_GTL_VREF

NP

21

100-1% 100-1%

C467

X

.1uF

16V-10%

14

+VTT_CPU1

NP

R146

X

12

MOD_CPU_PECI_CPU1_ID_N

49.9-1%49.9-1%

R145

12

MODULE:
DESC:
REV: OF

SEC

14

CPU1

CPUS,CSI,XDP0,XDP1

4

R552

R551

1K-1% 1K-1%

X

R550

1K-1%

X

1K-1%

R3542

X

1 2

1K-1%

R3543

1 2

R3544

X

1 2

1K-1%

R1922

1 2

R553

1K-1%

1K-1%

CPU1 Misc Connections

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 16 OF 145

DCBA

4

A B C

CPU1 Vcore Decoupling Caps

D

CPU1

1

14

14

116

MOD_CPU_VCORE_CPU1_SENSE_P

VSENSE_VR_CPU1_P

R1506

1 2

0-5%

R1507

1 2

0-5%

R1419

10-1%

CAD NOTE:

THESE 2 WIRES MUST CONNECT TO
THE PLANES ONLY AT PINS OF MOST
CENTRALLY LOCATED 10UF CAP UNDER THE PROCESSOR

R1713

VSENSE_CPU1_SKT_DP

VSENSE_CPU1_SKT_DNMOD_CPU_VCORE_CPU1_SENSE_N

CAD NOTE:

21

THESE 2 RES MUST BE PLACED
CLOSE TO CPU NEAR A CAP

1 2

100-1%

R1732

1 2

100-1%

NP

21

C1654

X

NP

21

C1653

X

10uF 6.3V

NP

21

C1652

X

10uF 6.3V

+VCORE_CPU1

NP

21

C1651

X

10uF 6.3V

NP

21

C1655

X

10uF 6.3V

NP

21

C1656

X

10uF 6.3V

10uF 6.3V

NP

21

C1658

X

NP

21

C1659

X

10uF 6.3V

21

C1648

10uF 6.3V

21

C1649

10uF 6.3V

+VCORE_CPU1

NP

21

C1650

X

10uF 6.3V

1

10uF 6.3V

2

116

VSENSE_VR_CPU1_N

+VCORE_CPU1

21

C1642

10uF 6.3V

NP

21

C1600

X

R1420

1 2

10-1%

21

C1626

10uF 6.3V

NP

21

C1625

X

10uF 6.3V

21

C1643

10uF 6.3V

NP

21

C1644

X

10uF 6.3V

NP

21

C1645

X

10uF 6.3V

21

C1646

10uF 6.3V

21

C1647

10uF 6.3V

2V-20%

+

330uF

21

C1620

10uF 6.3V

2V-20%

330uF

C1957

21

C1621

10uF 6.3V

NP

+

X

21

21

NP

2V-20%

+

330uF

C1958

X

21

C1622

10uF 6.3V

2V-20%

330uF

C1959

21

C1619

10uF 6.3V

+

21

21

10uF 6.3V

2V-20%

C1960

NP

+

330uF

X

21

C1623

2V-20%

330uF

C1961

21

C1633

10uF 6.3V

+

21

21

10uF 6.3V

2V-20%

C1962

NP

+

330uF

21

C1618

X

2V-20%

330uF

C1963

21

NP

C1612

10uF 6.3V

+

21

X

2V-20%

C1964

21

10uF 6.3V

+

330uF

C1608

C1965

21

21

10uF 6.3V

2V-20%

+

330uF

C1606

C1966

21

21

10uF 6.3V

2

3

+VCORE_CPU1

C1632

1 2

C1629

22uF 4V

1 2

ROOM = CPU1_CAVITY

+VCORE_CPU1

C1628

22uF 4V

1 2

C1627

22uF 4V

C1605

1 2

22uF 4V

room=cpu_cavity

1 2

C1601

22uF 4V

1 2

22uF 4V

C1630

3

1 2

C1641

1 2

22uF 4V22uF 4V

C1640

1 2

22uF 4V

C1639

1 2

22uF 4V

C1636

1 2

22uF 4V

C1637

1 2

22uF 4V

C1638

1 2

22uF 4V

C1635

1 2

22uF 4V

C1631

1 2

22uF 4V

C1634

1 2

22uF 4V

C7395

1 2

22uF 4V

C7394

1 2

22uF 4V

C7393

1 2

22uF 4V

C7391

1 2

22uF 4V

C7392

1 2

22uF 4V

4

C1607

1 2

C1624

22uF 4V

1 2

22uF 4V

ROOM = CPU1_CAVITY_BOT

C1602

1 2

C1613

22uF 4V

room=cpu_cavity_bot

1 2

22uF 4V

C1616

1 2

22uF 4V 22uF 4V

C1617

C1603

1 2

1 2

22uF 4V

C1657

1 2

22uF 4V

C1604

1 2

22uF 4V

C1609

1 2

22uF 4V

C1614

1 2

22uF 4V

C1615

1 2

22uF 4V

C1610

1 2

22uF 4V

C1611

1 2

22uF 4V

C7396

1 2

22uF 4V

C7397

1 2

22uF 4V

C7398

1 2

22uF 4V

C7399

1 2

22uF 4V

C7400

1 2

22uF 4V

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

CPU

211

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

INC.

TITLE

SCHEM,PLN,SV,R610

DWG NO.

RR154

DATE

11/6/2008 17 OF 145

ROUND ROCK,TEXAS

REV.

X05

SHEET

DCBA

A B C

CPU1 VTT/MEM Decoupling Caps

D

CPU1

1

CAD NOTE:

Diff Route these traces 0.025" MIN Width

125

VR Team suggests 10 ohm

125

VSENSE_MEM_CPU1_DP

NET_PHYSICAL_TYPE =PWR_PNG

VSENSE_MEM_CPU1_DN

NET_PHYSICAL_TYPE =PWR_PNG

R1508

1 2

0-5%

R1509

1 2

0-5%

21

C1489

10uF

6.3V-20%

21

C1487

10uF

6.3V-20%

21

C1484

10uF

6.3V-20%

21

C1486

10uF 6.3V

C1485

21

10uF 6.3V

21

C1482

10uF 6.3V

C1483

21

10uF 6.3V

+MEM_CPU1

21

C1488

1

10uF

6.3V-20%

2

+MEM_CPU1

V_1V8_CPU1

15,115,141,144

21

C453

10uF 4V

CAD NOTE:

These two resistors must be placed near central cap under DIMMs

+VTT_CPU1

21

C1279

21

C1278

10uF 6.3V

C1281

1 2

10uF 6.3V10uF 6.3V

22uF 4V

C1280

1 2

22uF 4V

C1038

21

47uF

4V-20%

21

C1040

47uF

4V-20%

+MEM_CPU1

C1492

1 2

22uF 4V22uF 4V

C1491

2

C1490

1 2

1 2

22uF 4V22uF 4V

3

21

C447

21

C446

10uF 6.3V

10uF

C7493

6.3V-20%

ROOM = CPU1_CAVITY

21

10uF

1 2

C452

6.3V-20%

10uF

21

C451

6.3V-20%

10uF

6.3V-20%

room=cpu_cavity

+MEM_CPU1+VTT_CPU1

3

21

C1037

10uF 6.3V

C448

1 2

C449

1 2

22uF 4V 22uF 4V

C450

1 2

C1274

ROOM = CPU1_CAVITY_BOT

21

10uF 6.3V

21

C1275

21

C1277

21

C1276

10uF 6.3V

room=cpu_cavity_bot

10uF 6.3V

21

C1039

10uF 6.3V

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

RR154

DCBA

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

18 OF 14511/6/2008

A B C

CPU Control Signal Connections

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 19 OF 145

DCBA

4

A B C

D

1

2

3

4

+3.3V

20,21,23,24,26,27,109

20,21,23,24,26,27,109

I2C_CPU1_GP0_SCL

49.9-1%

R7666

21

2 1

49.9-1%

I2C_CPU1_GP0_SCL_CH0_R1

13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21

13,21
13,21

I2C_CPU1_GP0_SDA

13,21

R7665

CPU1_M_CH0_BA_2
CPU1_M_CH0_BA_1
CPU1_M_CH0_BA_0
CPU1_M_CH0_MA_15
CPU1_M_CH0_MA_14
CPU1_M_CH0_MA_13
CPU1_M_CH0_MA_12
CPU1_M_CH0_MA_11
CPU1_M_CH0_MA_10
CPU1_M_CH0_MA_09
CPU1_M_CH0_MA_08
CPU1_M_CH0_MA_07
CPU1_M_CH0_MA_06
CPU1_M_CH0_MA_05
CPU1_M_CH0_MA_04
CPU1_M_CH0_MA_03
CPU1_M_CH0_MA_02
CPU1_M_CH0_MA_01
CPU1_M_CH0_MA_00

CPU1_M_CH0_CS_3_N

13

CPU1_M_CH0_CS_2_N

13

CPU1_M_CH0_CS_1_N

13

CPU1_M_CH0_CS_0_N

13

CPU1_M_CH0_RAS_N
CPU1_M_CH0_CAS_N
CPU1_M_CH0_WE_N
CPU1_M_CH0_CK_2_DP

13

CPU1_M_CH0_CK_2_DN

13

CPU1_M_CH0_CK_0_DN

13

CPU1_M_CH0_CK_0_DP

13

CPU1_M_CH0_CKE_2

13

CPU1_M_CH0_CKE_0

13

I2C_CPU1_GP0_SDA_CH0_R1

20,21,23,24,26,27
20,21,23,24,26,27
20,21,23,24,26,27

20,21
20,21

13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21

13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21

13,21

CPU1_DIMM_PD
CPU1_DIMM_PD
CPU1_DIMM_PD

CPU1_M_CH0_CA_VREF
CPU1_M_CH0_DQ_VREF
CPU1_M_CH0_ODT_1

13

CPU1_M_CH0_ODT_0

13

CPU1_M_CH0_ECC_7
CPU1_M_CH0_ECC_6
CPU1_M_CH0_ECC_5
CPU1_M_CH0_ECC_4
CPU1_M_CH0_ECC_3
CPU1_M_CH0_ECC_2
CPU1_M_CH0_ECC_1
CPU1_M_CH0_ECC_0

CPU1_M_CH0_DQS_17_DN
CPU1_M_CH0_DQS_17_DP
CPU1_M_CH0_DQS_16_DN
CPU1_M_CH0_DQS_16_DP
CPU1_M_CH0_DQS_15_DN
CPU1_M_CH0_DQS_15_DP
CPU1_M_CH0_DQS_14_DN
CPU1_M_CH0_DQS_14_DP
CPU1_M_CH0_DQS_13_DN
CPU1_M_CH0_DQS_13_DP
CPU1_M_CH0_DQS_12_DN
CPU1_M_CH0_DQS_12_DP
CPU1_M_CH0_DQS_11_DN
CPU1_M_CH0_DQS_11_DP
CPU1_M_CH0_DQS_10_DN
CPU1_M_CH0_DQS_10_DP
CPU1_M_CH0_DQS_09_DN
CPU1_M_CH0_DQS_09_DP
CPU1_M_CH0_DQS_08_DN
CPU1_M_CH0_DQS_08_DP
CPU1_M_CH0_DQS_07_DN
CPU1_M_CH0_DQS_07_DP
CPU1_M_CH0_DQS_06_DN
CPU1_M_CH0_DQS_06_DP
CPU1_M_CH0_DQS_05_DN
CPU1_M_CH0_DQS_05_DP
CPU1_M_CH0_DQS_04_DN
CPU1_M_CH0_DQS_04_DP
CPU1_M_CH0_DQS_03_DN
CPU1_M_CH0_DQS_03_DP
CPU1_M_CH0_DQS_02_DN
CPU1_M_CH0_DQS_02_DP
CPU1_M_CH0_DQS_01_DN
CPU1_M_CH0_DQS_01_DP
CPU1_M_CH0_DQS_00_DN
CPU1_M_CH0_DQS_00_DP

CPU1_M_CH0_PERR_0_N

13

CPU1_M_CH0_MA_PAR

NC_J_CPU1_CH0_DIMM1_P167

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

J_CPU1_CH0_DIMM1

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH0_DQ63
CPU1_M_CH0_DQ62
CPU1_M_CH0_DQ61
CPU1_M_CH0_DQ60
CPU1_M_CH0_DQ59
CPU1_M_CH0_DQ58
CPU1_M_CH0_DQ57
CPU1_M_CH0_DQ56
CPU1_M_CH0_DQ55
CPU1_M_CH0_DQ54
CPU1_M_CH0_DQ53
CPU1_M_CH0_DQ52
CPU1_M_CH0_DQ51
CPU1_M_CH0_DQ50
CPU1_M_CH0_DQ49
CPU1_M_CH0_DQ48
CPU1_M_CH0_DQ47
CPU1_M_CH0_DQ46
CPU1_M_CH0_DQ45
CPU1_M_CH0_DQ44
CPU1_M_CH0_DQ43
CPU1_M_CH0_DQ42
CPU1_M_CH0_DQ41
CPU1_M_CH0_DQ40
CPU1_M_CH0_DQ39
CPU1_M_CH0_DQ38
CPU1_M_CH0_DQ37
CPU1_M_CH0_DQ36
CPU1_M_CH0_DQ35
CPU1_M_CH0_DQ34
CPU1_M_CH0_DQ33
CPU1_M_CH0_DQ32
CPU1_M_CH0_DQ31
CPU1_M_CH0_DQ30
CPU1_M_CH0_DQ29
CPU1_M_CH0_DQ28
CPU1_M_CH0_DQ27
CPU1_M_CH0_DQ26
CPU1_M_CH0_DQ25
CPU1_M_CH0_DQ24
CPU1_M_CH0_DQ23
CPU1_M_CH0_DQ22
CPU1_M_CH0_DQ21
CPU1_M_CH0_DQ20
CPU1_M_CH0_DQ19
CPU1_M_CH0_DQ18
CPU1_M_CH0_DQ17
CPU1_M_CH0_DQ16
CPU1_M_CH0_DQ15
CPU1_M_CH0_DQ14
CPU1_M_CH0_DQ13
CPU1_M_CH0_DQ12
CPU1_M_CH0_DQ11
CPU1_M_CH0_DQ10
CPU1_M_CH0_DQ09
CPU1_M_CH0_DQ08
CPU1_M_CH0_DQ07
CPU1_M_CH0_DQ06
CPU1_M_CH0_DQ05
CPU1_M_CH0_DQ04
CPU1_M_CH0_DQ03
CPU1_M_CH0_DQ02
CPU1_M_CH0_DQ01
CPU1_M_CH0_DQ00

V_0P75_M_1_CH0_VTT

+MEM_CPU1

CPU1_M_CH0_EVENT_N

CPU1_M_CH0_RST_N

13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21
13,21

20,21,94
13,21

20,21,23,24,26,27,109
36,37,39,40,42,43,109

20,21,23,24,26,27,109
36,37,39,40,42,43,109

20,21,124,141,144

+MEM_CPU1

21

C2619

10uF 6.3V

C2620

CPU1 CH0 DIMM1

+3.3V

21

R2202

R2203

2.7K-5%

1 2

I2C_CPU1_GP0_SCL
I2C_CPU2_GP0_SCL

21,109
37,109

I2C_CPU1_GP1_SCL
I2C_CPU2_GP1_SCL

I2C_CPU1_GP0_SDA
I2C_CPU2_GP0_SDA

21,109
37,109

I2C_CPU1_GP1_SDA
I2C_CPU2_GP1_SDA

J_CPU1_CH0_DIMM1

2

VSS_2

5

VSS_5

8

VSS_8

11

VSS_11

14

VSS_14

17

VSS_17

20

VSS_20

23

VSS_23

26

VSS_26

29

VSS_29

32

VSS_32

35

VSS_35

38

VSS_38

41

VSS_41

44

VSS_44

47

VSS_47

80

VSS_80

83

VSS_83

86

VSS_86

89

VSS_89

92

VSS_92

95

VSS_95

98

VSS_98

101

VSS_101

104

VSS_104

107

VSS_107

110

VSS_110

113

VSS_113

116

VSS_116

121

VSS_121

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

(HETERO 2 OF 2)

21

10uF 6.3V

21

C2621

10uF 6.3V

C2622

21

R2204

4.75K-1%

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

21

10uF 6.3V

R2205

2.7K-5%

1 2

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

21

C2623

R2206

4.75K-1%

71,73
71,73

20,94

10uF 6.3V

21

R2207

2.7K-5%

1 2

4.75K-1%

GPO_I2C_MUX_SEL1
GPO_I2C_MUX_SEL0

ICH_SPD_MUX_EN_N

21

C2624

10uF 6.3V

21

R2208

R2209

2.7K-5%

1 2

4.75K-1%

1 2

C2771

10
11
12
13

6
5
4
3

2

14

15

1

+MEM_CPU1

4.7uF

6.3V-10%

U_ICH_SPD

PI3B3253QE

IB0
IB1
IB2
IB3

IA0
IA1
IA2
IA3

S1
S0

EB_N
EA_N

R290

1 2

R291

100-0.5% 100-0.5%

1 2

C7300

C501

1 2

YB

YA

GND
VCC

21

.1uF

4.7uF

6.3V-10%

+3.3V

R1999

21

CPU1_M_CH0_EVENT_N

20,21,94

1K-1%

+3.3V

R929

1 2

CPU1_DIMM_PU

21,23,24,26,27

220-5%

R928

1 2

CPU1_DIMM_PD

20,21,23,24,26,27

220-5%

Note: These 2 resistors for I2C address of CPU1 DIMMs

9

7

+3.3VAUX

8

16

CPU1_M_CH0_CA_VREF

16V-10%

V_0P75_M_1_CH0_VTT

21

C2789

.1uF

16V-10%

+3.3VAUX

21

C507

20,21,124,141,144

.1uF

20,21

I2C_ICH_SPD_VAUX_SCL

I2C_ICH_SPD_VAUX_SDA

16V-10%

71

71

+MEM_CPU1

NP

R293

X

1 2

NP

R292

X

1 2

TITLE

100-0.5%100-0.5%

21

C502

20,94

.1uF

16V-10%

SCHEM,PLN,SV,R610

+3.3VAUX

R3259

1 2

ICH_SPD_MUX_EN_N

CPU1_M_CH0_DQ_VREF

20,21

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

1

2

8.2K-5%

3

CPU1

4

I2C ID = A0

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

(HETERO 1 OF 2)

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

RR154

DCBA

REV.

X05

SHEET

20 OF 14511/6/2008

A B C

CPU1 CH0 DIMM2

D

1

2

3

4

+3.3V

13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20

13,20
13,20
13,20

I2C_CPU1_GP0_SDA_CH0_R2

21

I2C_CPU1_GP0_SCL_CH0_R2

21

20,21,23,24,26,27
20,21,23,24,26,27

20,23,24,26,27

20,21

13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20

13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20

13,20

CPU1_M_CH0_BA_2
CPU1_M_CH0_BA_1
CPU1_M_CH0_BA_0
CPU1_M_CH0_MA_15
CPU1_M_CH0_MA_14
CPU1_M_CH0_MA_13
CPU1_M_CH0_MA_12
CPU1_M_CH0_MA_11
CPU1_M_CH0_MA_10
CPU1_M_CH0_MA_09
CPU1_M_CH0_MA_08
CPU1_M_CH0_MA_07
CPU1_M_CH0_MA_06
CPU1_M_CH0_MA_05
CPU1_M_CH0_MA_04
CPU1_M_CH0_MA_03
CPU1_M_CH0_MA_02
CPU1_M_CH0_MA_01
CPU1_M_CH0_MA_00

CPU1_M_CH0_CS_7_N

13

CPU1_M_CH0_CS_6_N

13

CPU1_M_CH0_CS_5_N

13

CPU1_M_CH0_CS_4_N

13

CPU1_M_CH0_RAS_N
CPU1_M_CH0_CAS_N
CPU1_M_CH0_WE_N
CPU1_M_CH0_CK_3_DP

13

CPU1_M_CH0_CK_3_DN

13

CPU1_M_CH0_CK_1_DN

13

CPU1_M_CH0_CK_1_DP

13

CPU1_M_CH0_CKE_3

13

CPU1_M_CH0_CKE_1

13

CPU1_DIMM_PD
CPU1_DIMM_PD
CPU1_DIMM_PU

CPU1_M_CH0_CA_VREF

20

CPU1_M_CH0_DQ_VREF
CPU1_M_CH0_ODT_3

13

CPU1_M_CH0_ODT_2

13

CPU1_M_CH0_ECC_7
CPU1_M_CH0_ECC_6
CPU1_M_CH0_ECC_5
CPU1_M_CH0_ECC_4
CPU1_M_CH0_ECC_3
CPU1_M_CH0_ECC_2
CPU1_M_CH0_ECC_1
CPU1_M_CH0_ECC_0

CPU1_M_CH0_DQS_17_DN
CPU1_M_CH0_DQS_17_DP
CPU1_M_CH0_DQS_16_DN
CPU1_M_CH0_DQS_16_DP
CPU1_M_CH0_DQS_15_DN
CPU1_M_CH0_DQS_15_DP
CPU1_M_CH0_DQS_14_DN
CPU1_M_CH0_DQS_14_DP
CPU1_M_CH0_DQS_13_DN
CPU1_M_CH0_DQS_13_DP
CPU1_M_CH0_DQS_12_DN
CPU1_M_CH0_DQS_12_DP
CPU1_M_CH0_DQS_11_DN
CPU1_M_CH0_DQS_11_DP
CPU1_M_CH0_DQS_10_DN
CPU1_M_CH0_DQS_10_DP
CPU1_M_CH0_DQS_09_DN
CPU1_M_CH0_DQS_09_DP
CPU1_M_CH0_DQS_08_DN
CPU1_M_CH0_DQS_08_DP
CPU1_M_CH0_DQS_07_DN
CPU1_M_CH0_DQS_07_DP
CPU1_M_CH0_DQS_06_DN
CPU1_M_CH0_DQS_06_DP
CPU1_M_CH0_DQS_05_DN
CPU1_M_CH0_DQS_05_DP
CPU1_M_CH0_DQS_04_DN
CPU1_M_CH0_DQS_04_DP
CPU1_M_CH0_DQS_03_DN
CPU1_M_CH0_DQS_03_DP
CPU1_M_CH0_DQS_02_DN
CPU1_M_CH0_DQS_02_DP
CPU1_M_CH0_DQS_01_DN
CPU1_M_CH0_DQS_01_DP
CPU1_M_CH0_DQS_00_DN
CPU1_M_CH0_DQS_00_DP

CPU1_M_CH0_PERR_1_N

13

CPU1_M_CH0_MA_PAR

NC_J_CPU1_CH0_DIMM2_P167

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

J_CPU1_CH0_DIMM2

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH0_DQ63
CPU1_M_CH0_DQ62
CPU1_M_CH0_DQ61
CPU1_M_CH0_DQ60
CPU1_M_CH0_DQ59
CPU1_M_CH0_DQ58
CPU1_M_CH0_DQ57
CPU1_M_CH0_DQ56
CPU1_M_CH0_DQ55
CPU1_M_CH0_DQ54
CPU1_M_CH0_DQ53
CPU1_M_CH0_DQ52
CPU1_M_CH0_DQ51
CPU1_M_CH0_DQ50
CPU1_M_CH0_DQ49
CPU1_M_CH0_DQ48
CPU1_M_CH0_DQ47
CPU1_M_CH0_DQ46
CPU1_M_CH0_DQ45
CPU1_M_CH0_DQ44
CPU1_M_CH0_DQ43
CPU1_M_CH0_DQ42
CPU1_M_CH0_DQ41
CPU1_M_CH0_DQ40
CPU1_M_CH0_DQ39
CPU1_M_CH0_DQ38
CPU1_M_CH0_DQ37
CPU1_M_CH0_DQ36
CPU1_M_CH0_DQ35
CPU1_M_CH0_DQ34
CPU1_M_CH0_DQ33
CPU1_M_CH0_DQ32
CPU1_M_CH0_DQ31
CPU1_M_CH0_DQ30
CPU1_M_CH0_DQ29
CPU1_M_CH0_DQ28
CPU1_M_CH0_DQ27
CPU1_M_CH0_DQ26
CPU1_M_CH0_DQ25
CPU1_M_CH0_DQ24
CPU1_M_CH0_DQ23
CPU1_M_CH0_DQ22
CPU1_M_CH0_DQ21
CPU1_M_CH0_DQ20
CPU1_M_CH0_DQ19
CPU1_M_CH0_DQ18
CPU1_M_CH0_DQ17
CPU1_M_CH0_DQ16
CPU1_M_CH0_DQ15
CPU1_M_CH0_DQ14
CPU1_M_CH0_DQ13
CPU1_M_CH0_DQ12
CPU1_M_CH0_DQ11
CPU1_M_CH0_DQ10
CPU1_M_CH0_DQ09
CPU1_M_CH0_DQ08
CPU1_M_CH0_DQ07
CPU1_M_CH0_DQ06
CPU1_M_CH0_DQ05
CPU1_M_CH0_DQ04
CPU1_M_CH0_DQ03
CPU1_M_CH0_DQ02
CPU1_M_CH0_DQ01
CPU1_M_CH0_DQ00

V_0P75_M_1_CH0_VTT

+MEM_CPU1

CPU1_M_CH0_EVENT_N

CPU1_M_CH0_RST_N

13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20
13,20

+MEM_CPU1

21

C2627

10uF 6.3V

20,94
13,20

20,109
20,109

20,21,124,141,144

21

C2626

10uF 6.3V

Intel VREF Circuit - P20_BLR_DT17552 I2C Constraints - P20_BLR_DT17572

+MEM_CPU1

6

A

5

W

LM358A

7

R7834

1 2

12.1K-1%

C7481

1 2

8200pF

50V-10%

3dB = 7.7KHz @nominal

I2C_CPU1_GP1_SCL
I2C_CPU1_GP1_SDA

+3.3V

.1uF

1 2

C7483

21

C7484

16V-10%

.1uF

16V-10%

R7810

49.9-1%

+MEM_CPU1

1 2

C7485

21

.1uF

16V-10%

+3.3V

R7809

49.9-1%

U7268

1

VDD

21

3

SCL

4

SDA

2

GND

AD5247-SOT6

+3.3V

U7266

5

6

8

+

V

G

-

4

NC_CPU1_VREF_XTRA

I2C_CPU1_GP0_SDA_CH0_R2

21

I2C_CPU1_GP0_SCL_CH0_R2

21

2 1

20,23,24,26,27,109

20,23,24,26,27,109

21

C2625

10uF 6.3V

I2C_CPU1_GP0_SDA

I2C_CPU1_GP0_SCL

1 2

C2772

4.7uF

6.3V-10%

1 2

C7301

49.9-1%

R7667

2 1

49.9-1%

R7668

V_0P75_M_1_CH0_VTT

21

4.7uF

C2790

6.3V-10%

20,21,124,141,144

.1uF

16V-10%

R7814

1 2

Max Sat Current = 4.7mA

U7266

3

2

12.1K-1%

8

V

G

4

LM358A

1

21

C7482

220pF

50V-10%

+

-

J_CPU1_CH0_DIMM2
2
5
8

11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95

98
101
104
107
110
113
116
121

VSS_2
VSS_5
VSS_8
VSS_11
VSS_14
VSS_17
VSS_20
VSS_23
VSS_26
VSS_29
VSS_32
VSS_35
VSS_38
VSS_41
VSS_44
VSS_47
VSS_80
VSS_83
VSS_86
VSS_89
VSS_92
VSS_95
VSS_98
VSS_101
VSS_104
VSS_107
VSS_110
VSS_113
VSS_116
VSS_121

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

240 PIN DDR3 DIMM SKT

BLACK HOUSING, BLACK EJECTOR

(HETERO 2 OF 2)

R7808

649-1%

21

Q280

3904

1

TITLE

+MEM_CPU1+3.3V

R7831

1 2

0-5%

3

Short ckt max = 30mA

R7816

1 2

2

49.9-1%

R7817

49.9-1%

R7818

R7806

1 2

49.9-1%

1

49.9-1%

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

CPU1_M_CH0_DQ_VREF

21

CPU1_M_CH1_DQ_VREF

2

CPU1_M_CH2_DQ_VREF

CPUS,CSI,XDP0,XDP1

SEC

ROUND ROCK,TEXAS

1

20,21

23,24

26,27

2

3

CPU1

4

I2C ID = A2

240 PIN DDR3 DIMM SKT

BLACK HOUSING, BLACK EJECTOR

(HETERO 1 OF 2)

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

RR154

DCBA

REV.

X05

SHEET

21 OF 14511/6/2008

A B C

D

1

1

2

2

DIMM3 NOT PRESENT IN 1U DESIGN

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

THIDWICK

UNIQUE PAGE

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 22 OF 145

DCBA

CPU1

4

1

2

3

4

+3.3V

A B C

13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24

13
13
13

13
13,24
13,24
13,24

13

13

13

13

13

13

I2C_CPU1_GP0_SDA_CH1_R1

23

I2C_CPU1_GP0_SCL_CH1_R1

23

20,21,23,24,26,27

20,21,24,26,27

20,21,23,24,26,27

23,24

21,23,24

13

13

13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24

13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24

13
13,24

CPU1_M_CH1_BA_2
CPU1_M_CH1_BA_1
CPU1_M_CH1_BA_0
CPU1_M_CH1_MA_15
CPU1_M_CH1_MA_14
CPU1_M_CH1_MA_13
CPU1_M_CH1_MA_12
CPU1_M_CH1_MA_11
CPU1_M_CH1_MA_10
CPU1_M_CH1_MA_09
CPU1_M_CH1_MA_08
CPU1_M_CH1_MA_07
CPU1_M_CH1_MA_06
CPU1_M_CH1_MA_05
CPU1_M_CH1_MA_04
CPU1_M_CH1_MA_03
CPU1_M_CH1_MA_02
CPU1_M_CH1_MA_01
CPU1_M_CH1_MA_00

CPU1_M_CH1_CS_3_N
CPU1_M_CH1_CS_2_N
CPU1_M_CH1_CS_1_N
CPU1_M_CH1_CS_0_N
CPU1_M_CH1_RAS_N
CPU1_M_CH1_CAS_N
CPU1_M_CH1_WE_N
CPU1_M_CH1_CK_2_DP
CPU1_M_CH1_CK_2_DN
CPU1_M_CH1_CK_0_DN
CPU1_M_CH1_CK_0_DP
CPU1_M_CH1_CKE_2
CPU1_M_CH1_CKE_0

CPU1_DIMM_PD
CPU1_DIMM_PU
CPU1_DIMM_PD

CPU1_M_CH1_CA_VREF
CPU1_M_CH1_DQ_VREF
CPU1_M_CH1_ODT_1
CPU1_M_CH1_ODT_0

CPU1_M_CH1_ECC_7
CPU1_M_CH1_ECC_6
CPU1_M_CH1_ECC_5
CPU1_M_CH1_ECC_4
CPU1_M_CH1_ECC_3
CPU1_M_CH1_ECC_2
CPU1_M_CH1_ECC_1
CPU1_M_CH1_ECC_0

CPU1_M_CH1_DQS_17_DN
CPU1_M_CH1_DQS_17_DP
CPU1_M_CH1_DQS_16_DN
CPU1_M_CH1_DQS_16_DP
CPU1_M_CH1_DQS_15_DN
CPU1_M_CH1_DQS_15_DP
CPU1_M_CH1_DQS_14_DN
CPU1_M_CH1_DQS_14_DP
CPU1_M_CH1_DQS_13_DN
CPU1_M_CH1_DQS_13_DP
CPU1_M_CH1_DQS_12_DN
CPU1_M_CH1_DQS_12_DP
CPU1_M_CH1_DQS_11_DN
CPU1_M_CH1_DQS_11_DP
CPU1_M_CH1_DQS_10_DN
CPU1_M_CH1_DQS_10_DP
CPU1_M_CH1_DQS_09_DN
CPU1_M_CH1_DQS_09_DP
CPU1_M_CH1_DQS_08_DN
CPU1_M_CH1_DQS_08_DP
CPU1_M_CH1_DQS_07_DN
CPU1_M_CH1_DQS_07_DP
CPU1_M_CH1_DQS_06_DN
CPU1_M_CH1_DQS_06_DP
CPU1_M_CH1_DQS_05_DN
CPU1_M_CH1_DQS_05_DP
CPU1_M_CH1_DQS_04_DN
CPU1_M_CH1_DQS_04_DP
CPU1_M_CH1_DQS_03_DN
CPU1_M_CH1_DQS_03_DP
CPU1_M_CH1_DQS_02_DN
CPU1_M_CH1_DQS_02_DP
CPU1_M_CH1_DQS_01_DN
CPU1_M_CH1_DQS_01_DP
CPU1_M_CH1_DQS_00_DN
CPU1_M_CH1_DQS_00_DP

CPU1_M_CH1_PERR_0_N
CPU1_M_CH1_MA_PAR

NC_J_CPU1_CH1_DIMM1_P167

I2C ID = A4

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

J_CPU1_CH1_DIMM1

(HETERO 1 OF 2)

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH1_DQ63
CPU1_M_CH1_DQ62
CPU1_M_CH1_DQ61
CPU1_M_CH1_DQ60
CPU1_M_CH1_DQ59
CPU1_M_CH1_DQ58
CPU1_M_CH1_DQ57
CPU1_M_CH1_DQ56
CPU1_M_CH1_DQ55
CPU1_M_CH1_DQ54
CPU1_M_CH1_DQ53
CPU1_M_CH1_DQ52
CPU1_M_CH1_DQ51
CPU1_M_CH1_DQ50
CPU1_M_CH1_DQ49
CPU1_M_CH1_DQ48
CPU1_M_CH1_DQ47
CPU1_M_CH1_DQ46
CPU1_M_CH1_DQ45
CPU1_M_CH1_DQ44
CPU1_M_CH1_DQ43
CPU1_M_CH1_DQ42
CPU1_M_CH1_DQ41
CPU1_M_CH1_DQ40
CPU1_M_CH1_DQ39
CPU1_M_CH1_DQ38
CPU1_M_CH1_DQ37
CPU1_M_CH1_DQ36
CPU1_M_CH1_DQ35
CPU1_M_CH1_DQ34
CPU1_M_CH1_DQ33
CPU1_M_CH1_DQ32
CPU1_M_CH1_DQ31
CPU1_M_CH1_DQ30
CPU1_M_CH1_DQ29
CPU1_M_CH1_DQ28
CPU1_M_CH1_DQ27
CPU1_M_CH1_DQ26
CPU1_M_CH1_DQ25
CPU1_M_CH1_DQ24
CPU1_M_CH1_DQ23
CPU1_M_CH1_DQ22
CPU1_M_CH1_DQ21
CPU1_M_CH1_DQ20
CPU1_M_CH1_DQ19
CPU1_M_CH1_DQ18
CPU1_M_CH1_DQ17
CPU1_M_CH1_DQ16
CPU1_M_CH1_DQ15
CPU1_M_CH1_DQ14
CPU1_M_CH1_DQ13
CPU1_M_CH1_DQ12
CPU1_M_CH1_DQ11
CPU1_M_CH1_DQ10
CPU1_M_CH1_DQ09
CPU1_M_CH1_DQ08
CPU1_M_CH1_DQ07
CPU1_M_CH1_DQ06
CPU1_M_CH1_DQ05
CPU1_M_CH1_DQ04
CPU1_M_CH1_DQ03
CPU1_M_CH1_DQ02
CPU1_M_CH1_DQ01
CPU1_M_CH1_DQ00

V_0P75_M_1_CH1_VTT

+MEM_CPU1

CPU1_M_CH1_EVENT_N

CPU1_M_CH1_RST_N

13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24
13,24

+MEM_CPU1

C2633

23,24,94
13,24

CPU1 CH1 DIMM1

I2C_CPU1_GP0_SDA_CH1_R1

23

I2C_CPU1_GP0_SCL_CH1_R1

23

23,24,124,141,144

V_0P75_M_1_CH1_VTT

21

21

C2632

10uF 6.3V

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

10uF 6.3V

21

C2631

10uF 6.3V

1 2

C2774

4.7uF

6.3V-10%

1 2

C7302

4.7uF

C2792

6.3V-10%

21

.1uF

16V-10%

+3.3V

R297

1 2

R296

1 2

I2C_CPU1_GP0_SDA

2 1

49.9-1%

23,24,124,141,144

R7672

R2751

21

CPU1_M_CH1_EVENT_N

1K-1%

CPU1_M_CH1_CA_VREF

21

C504

100-0.5% 100-0.5%

.1uF

16V-10%

I2C_CPU1_GP0_SCL

2 1

49.9-1%

R7671

J_CPU1_CH1_DIMM1
2
5
8

11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95

98
101
104
107
110
113
116
121

VSS_2
VSS_5
VSS_8
VSS_11
VSS_14
VSS_17
VSS_20
VSS_23
VSS_26
VSS_29
VSS_32
VSS_35
VSS_38
VSS_41
VSS_44
VSS_47
VSS_80
VSS_83
VSS_86
VSS_89
VSS_92
VSS_95
VSS_98
VSS_101
VSS_104
VSS_107
VSS_110
VSS_113
VSS_116
VSS_121

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

(HETERO 2 OF 2)

23,24,94

23,24

20,21,24,26,27,109

20,21,24,26,27,109

+MEM_CPU1+MEM_CPU1

NP

NP

R295

X

1 2

R294

X

1 2

100-0.5%100-0.5%

21

C503

TITLE

DWG NO.

DATE

D

CPU1_M_CH1_DQ_VREF

.1uF

16V-10%

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

21,23,24

CPUS,CSI,XDP0,XDP1

SEC

ROUND ROCK,TEXAS

REV.

RR154

SHEET

11/6/2008 23 OF 145

1

2

3

CPU1

4

X05

DCBA

1

2

3

4

+3.3V

A B C

13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23

13,23
13,23
13,23

I2C_CPU1_GP0_SDA_CH1_R2

24

I2C_CPU1_GP0_SCL_CH1_R2

24

20,21,23,26,27
20,21,23,24,26,27
20,21,23,24,26,27

21,23

13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23

13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23

13,23

CPU1_M_CH1_BA_2
CPU1_M_CH1_BA_1
CPU1_M_CH1_BA_0
CPU1_M_CH1_MA_15
CPU1_M_CH1_MA_14
CPU1_M_CH1_MA_13
CPU1_M_CH1_MA_12
CPU1_M_CH1_MA_11
CPU1_M_CH1_MA_10
CPU1_M_CH1_MA_09
CPU1_M_CH1_MA_08
CPU1_M_CH1_MA_07
CPU1_M_CH1_MA_06
CPU1_M_CH1_MA_05
CPU1_M_CH1_MA_04
CPU1_M_CH1_MA_03
CPU1_M_CH1_MA_02
CPU1_M_CH1_MA_01
CPU1_M_CH1_MA_00

CPU1_M_CH1_CS_7_N

13

CPU1_M_CH1_CS_6_N

13

CPU1_M_CH1_CS_5_N

13

CPU1_M_CH1_CS_4_N

13

CPU1_M_CH1_RAS_N
CPU1_M_CH1_CAS_N
CPU1_M_CH1_WE_N
CPU1_M_CH1_CK_3_DP

13

CPU1_M_CH1_CK_3_DN

13

CPU1_M_CH1_CK_1_DN

13

CPU1_M_CH1_CK_1_DP

13

CPU1_M_CH1_CKE_3

13

CPU1_M_CH1_CKE_1

13

CPU1_DIMM_PD
CPU1_DIMM_PU
CPU1_DIMM_PU

CPU1_M_CH1_CA_VREF

23

CPU1_M_CH1_DQ_VREF
CPU1_M_CH1_ODT_3

13

CPU1_M_CH1_ODT_2

13

CPU1_M_CH1_ECC_7
CPU1_M_CH1_ECC_6
CPU1_M_CH1_ECC_5
CPU1_M_CH1_ECC_4
CPU1_M_CH1_ECC_3
CPU1_M_CH1_ECC_2
CPU1_M_CH1_ECC_1
CPU1_M_CH1_ECC_0

CPU1_M_CH1_DQS_17_DN
CPU1_M_CH1_DQS_17_DP
CPU1_M_CH1_DQS_16_DN
CPU1_M_CH1_DQS_16_DP
CPU1_M_CH1_DQS_15_DN
CPU1_M_CH1_DQS_15_DP
CPU1_M_CH1_DQS_14_DN
CPU1_M_CH1_DQS_14_DP
CPU1_M_CH1_DQS_13_DN
CPU1_M_CH1_DQS_13_DP
CPU1_M_CH1_DQS_12_DN
CPU1_M_CH1_DQS_12_DP
CPU1_M_CH1_DQS_11_DN
CPU1_M_CH1_DQS_11_DP
CPU1_M_CH1_DQS_10_DN
CPU1_M_CH1_DQS_10_DP
CPU1_M_CH1_DQS_09_DN
CPU1_M_CH1_DQS_09_DP
CPU1_M_CH1_DQS_08_DN
CPU1_M_CH1_DQS_08_DP
CPU1_M_CH1_DQS_07_DN
CPU1_M_CH1_DQS_07_DP
CPU1_M_CH1_DQS_06_DN
CPU1_M_CH1_DQS_06_DP
CPU1_M_CH1_DQS_05_DN
CPU1_M_CH1_DQS_05_DP
CPU1_M_CH1_DQS_04_DN
CPU1_M_CH1_DQS_04_DP
CPU1_M_CH1_DQS_03_DN
CPU1_M_CH1_DQS_03_DP
CPU1_M_CH1_DQS_02_DN
CPU1_M_CH1_DQS_02_DP
CPU1_M_CH1_DQS_01_DN
CPU1_M_CH1_DQS_01_DP
CPU1_M_CH1_DQS_00_DN
CPU1_M_CH1_DQS_00_DP

CPU1_M_CH1_PERR_1_N

13

CPU1_M_CH1_MA_PAR

I2C ID = A6

NC_J_CPU1_CH1_DIMM2_P167

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

240 PIN DDR3 DIMM SKT

BLACK HOUSING, BLACK EJECTOR

J_CPU1_CH1_DIMM2

(HETERO 1 OF 2)

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH1_DQ63
CPU1_M_CH1_DQ62
CPU1_M_CH1_DQ61
CPU1_M_CH1_DQ60
CPU1_M_CH1_DQ59
CPU1_M_CH1_DQ58
CPU1_M_CH1_DQ57
CPU1_M_CH1_DQ56
CPU1_M_CH1_DQ55
CPU1_M_CH1_DQ54
CPU1_M_CH1_DQ53
CPU1_M_CH1_DQ52
CPU1_M_CH1_DQ51
CPU1_M_CH1_DQ50
CPU1_M_CH1_DQ49
CPU1_M_CH1_DQ48
CPU1_M_CH1_DQ47
CPU1_M_CH1_DQ46
CPU1_M_CH1_DQ45
CPU1_M_CH1_DQ44
CPU1_M_CH1_DQ43
CPU1_M_CH1_DQ42
CPU1_M_CH1_DQ41
CPU1_M_CH1_DQ40
CPU1_M_CH1_DQ39
CPU1_M_CH1_DQ38
CPU1_M_CH1_DQ37
CPU1_M_CH1_DQ36
CPU1_M_CH1_DQ35
CPU1_M_CH1_DQ34
CPU1_M_CH1_DQ33
CPU1_M_CH1_DQ32
CPU1_M_CH1_DQ31
CPU1_M_CH1_DQ30
CPU1_M_CH1_DQ29
CPU1_M_CH1_DQ28
CPU1_M_CH1_DQ27
CPU1_M_CH1_DQ26
CPU1_M_CH1_DQ25
CPU1_M_CH1_DQ24
CPU1_M_CH1_DQ23
CPU1_M_CH1_DQ22
CPU1_M_CH1_DQ21
CPU1_M_CH1_DQ20
CPU1_M_CH1_DQ19
CPU1_M_CH1_DQ18
CPU1_M_CH1_DQ17
CPU1_M_CH1_DQ16
CPU1_M_CH1_DQ15
CPU1_M_CH1_DQ14
CPU1_M_CH1_DQ13
CPU1_M_CH1_DQ12
CPU1_M_CH1_DQ11
CPU1_M_CH1_DQ10
CPU1_M_CH1_DQ09
CPU1_M_CH1_DQ08
CPU1_M_CH1_DQ07
CPU1_M_CH1_DQ06
CPU1_M_CH1_DQ05
CPU1_M_CH1_DQ04
CPU1_M_CH1_DQ03
CPU1_M_CH1_DQ02
CPU1_M_CH1_DQ01
CPU1_M_CH1_DQ00

V_0P75_M_1_CH1_VTT

+MEM_CPU1

CPU1_M_CH1_EVENT_N

CPU1_M_CH1_RST_N

13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23
13,23

23,94
13,23

CPU1 CH1 DIMM2

I2C_CPU1_GP0_SDA_CH1_R2

49.9-1%

2 1

49.9-1%

20,21,23,26,27,109
20,21,23,26,27,109

23,24,124,141,144

I2C_CPU1_GP0_SDA
I2C_CPU1_GP0_SCL

+MEM_CPU1

V_0P75_M_1_CH1_VTT

21

C2636

10uF 6.3V

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

21

C2635

10uF 6.3V

C2634

21

10uF 6.3V

1 2

C2775

4.7uF

6.3V-10%

1 2

C7303

4.7uF

6.3V-10%

21

C2793

.1uF

R7673

16V-10%

I2C_CPU1_GP0_SCL_CH1_R2

2 1

R7674

23,24,124,141,144

24

24

J_CPU1_CH1_DIMM2
2
5
8

11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95

98
101
104
107
110
113
116
121

VSS_2
VSS_5
VSS_8
VSS_11
VSS_14
VSS_17
VSS_20
VSS_23
VSS_26
VSS_29
VSS_32
VSS_35
VSS_38
VSS_41
VSS_44
VSS_47
VSS_80
VSS_83
VSS_86
VSS_89
VSS_92
VSS_95
VSS_98
VSS_101
VSS_104
VSS_107
VSS_110
VSS_113
VSS_116
VSS_121

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

240 PIN DDR3 DIMM SKT

BLACK HOUSING, BLACK EJECTOR

(HETERO 2 OF 2)

TITLE

DWG NO.

DATE

D

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

RR154

1

2

3

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ROUND ROCK,TEXAS

REV.

X05

SHEET

24 OF 14511/6/2008

DCBA

A B C

D

1

1

2

2

DIMM3 NOT PRESENT IN 1U DESIGN

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

THIDWICK

UNIQUE PAGE

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 25 OF 145

DCBA

CPU1

4

1

2

3

4

+3.3V

A B C

14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27

14,27
14,27
14,27

I2C_CPU1_GP0_SDA_CH2_R1

26

I2C_CPU1_GP0_SCL_CH2_R1

26

20,21,23,24,27
20,21,23,24,26,27
20,21,23,24,26,27

26,27

21,26,27

14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27

14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27

14,27

CPU1_M_CH2_BA_2
CPU1_M_CH2_BA_1
CPU1_M_CH2_BA_0
CPU1_M_CH2_MA_15
CPU1_M_CH2_MA_14
CPU1_M_CH2_MA_13
CPU1_M_CH2_MA_12
CPU1_M_CH2_MA_11
CPU1_M_CH2_MA_10
CPU1_M_CH2_MA_09
CPU1_M_CH2_MA_08
CPU1_M_CH2_MA_07
CPU1_M_CH2_MA_06
CPU1_M_CH2_MA_05
CPU1_M_CH2_MA_04
CPU1_M_CH2_MA_03
CPU1_M_CH2_MA_02
CPU1_M_CH2_MA_01
CPU1_M_CH2_MA_00

CPU1_M_CH2_CS_3_N

14

CPU1_M_CH2_CS_2_N

14

CPU1_M_CH2_CS_1_N

14

CPU1_M_CH2_CS_0_N

14

CPU1_M_CH2_RAS_N
CPU1_M_CH2_CAS_N
CPU1_M_CH2_WE_N
CPU1_M_CH2_CK_2_DP

14

CPU1_M_CH2_CK_2_DN

14

CPU1_M_CH2_CK_0_DN

14

CPU1_M_CH2_CK_0_DP

14

CPU1_M_CH2_CKE_2

14

CPU1_M_CH2_CKE_0

14

CPU1_DIMM_PU
CPU1_DIMM_PD
CPU1_DIMM_PD

CPU1_M_CH2_CA_VREF
CPU1_M_CH2_DQ_VREF
CPU1_M_CH2_ODT_1

14

CPU1_M_CH2_ODT_0

14

CPU1_M_CH2_ECC_7
CPU1_M_CH2_ECC_6
CPU1_M_CH2_ECC_5
CPU1_M_CH2_ECC_4
CPU1_M_CH2_ECC_3
CPU1_M_CH2_ECC_2
CPU1_M_CH2_ECC_1
CPU1_M_CH2_ECC_0

CPU1_M_CH2_DQS_17_DN
CPU1_M_CH2_DQS_17_DP
CPU1_M_CH2_DQS_16_DN
CPU1_M_CH2_DQS_16_DP
CPU1_M_CH2_DQS_15_DN
CPU1_M_CH2_DQS_15_DP
CPU1_M_CH2_DQS_14_DN
CPU1_M_CH2_DQS_14_DP
CPU1_M_CH2_DQS_13_DN
CPU1_M_CH2_DQS_13_DP
CPU1_M_CH2_DQS_12_DN
CPU1_M_CH2_DQS_12_DP
CPU1_M_CH2_DQS_11_DN
CPU1_M_CH2_DQS_11_DP
CPU1_M_CH2_DQS_10_DN
CPU1_M_CH2_DQS_10_DP
CPU1_M_CH2_DQS_09_DN
CPU1_M_CH2_DQS_09_DP
CPU1_M_CH2_DQS_08_DN
CPU1_M_CH2_DQS_08_DP
CPU1_M_CH2_DQS_07_DN
CPU1_M_CH2_DQS_07_DP
CPU1_M_CH2_DQS_06_DN
CPU1_M_CH2_DQS_06_DP
CPU1_M_CH2_DQS_05_DN
CPU1_M_CH2_DQS_05_DP
CPU1_M_CH2_DQS_04_DN
CPU1_M_CH2_DQS_04_DP
CPU1_M_CH2_DQS_03_DN
CPU1_M_CH2_DQS_03_DP
CPU1_M_CH2_DQS_02_DN
CPU1_M_CH2_DQS_02_DP
CPU1_M_CH2_DQS_01_DN
CPU1_M_CH2_DQS_01_DP
CPU1_M_CH2_DQS_00_DN
CPU1_M_CH2_DQS_00_DP

CPU1_M_CH2_PERR_0_N

14

CPU1_M_CH2_MA_PAR

NC_J_CPU1_CH2_DIMM1_P167

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

J_CPU1_CH2_DIMM1

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH2_DQ63
CPU1_M_CH2_DQ62
CPU1_M_CH2_DQ61
CPU1_M_CH2_DQ60
CPU1_M_CH2_DQ59
CPU1_M_CH2_DQ58
CPU1_M_CH2_DQ57
CPU1_M_CH2_DQ56
CPU1_M_CH2_DQ55
CPU1_M_CH2_DQ54
CPU1_M_CH2_DQ53
CPU1_M_CH2_DQ52
CPU1_M_CH2_DQ51
CPU1_M_CH2_DQ50
CPU1_M_CH2_DQ49
CPU1_M_CH2_DQ48
CPU1_M_CH2_DQ47
CPU1_M_CH2_DQ46
CPU1_M_CH2_DQ45
CPU1_M_CH2_DQ44
CPU1_M_CH2_DQ43
CPU1_M_CH2_DQ42
CPU1_M_CH2_DQ41
CPU1_M_CH2_DQ40
CPU1_M_CH2_DQ39
CPU1_M_CH2_DQ38
CPU1_M_CH2_DQ37
CPU1_M_CH2_DQ36
CPU1_M_CH2_DQ35
CPU1_M_CH2_DQ34
CPU1_M_CH2_DQ33
CPU1_M_CH2_DQ32
CPU1_M_CH2_DQ31
CPU1_M_CH2_DQ30
CPU1_M_CH2_DQ29
CPU1_M_CH2_DQ28
CPU1_M_CH2_DQ27
CPU1_M_CH2_DQ26
CPU1_M_CH2_DQ25
CPU1_M_CH2_DQ24
CPU1_M_CH2_DQ23
CPU1_M_CH2_DQ22
CPU1_M_CH2_DQ21
CPU1_M_CH2_DQ20
CPU1_M_CH2_DQ19
CPU1_M_CH2_DQ18
CPU1_M_CH2_DQ17
CPU1_M_CH2_DQ16
CPU1_M_CH2_DQ15
CPU1_M_CH2_DQ14
CPU1_M_CH2_DQ13
CPU1_M_CH2_DQ12
CPU1_M_CH2_DQ11
CPU1_M_CH2_DQ10
CPU1_M_CH2_DQ09
CPU1_M_CH2_DQ08
CPU1_M_CH2_DQ07
CPU1_M_CH2_DQ06
CPU1_M_CH2_DQ05
CPU1_M_CH2_DQ04
CPU1_M_CH2_DQ03
CPU1_M_CH2_DQ02
CPU1_M_CH2_DQ01
CPU1_M_CH2_DQ00

V_0P75_M_1_CH2_VTT

+MEM_CPU1

CPU1_M_CH2_EVENT_N

CPU1_M_CH2_RST_N

14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27
14,27

26,27,94
14,27

CPU1 CH2 DIMM1

I2C_CPU1_GP0_SDA

I2C_CPU1_GP0_SCL

1 2

C7470

26,27,124,141,144

21

C7473

20,21,23,24,27,109

20,21,23,24,27,109

1 2

C7472

10uF 6.3V

10uF 6.3V

10uF 6.3V

C7471

1 2

10uF 6.3V

+MEM_CPU1

21

C2642

2 1

49.9-1%

C2641

10uF 6.3V

R301

1 2

R300

1 2

R7677

21

+3.3V

21

C506

100-0.5% 100-0.5%

2 1

49.9-1%

R7678

C2640

10uF 6.3V

.1uF

16V-10%

21

10uF 6.3V

R2752

21

1K-1%

CPU1_M_CH2_CA_VREF

I2C_CPU1_GP0_SDA_CH2_R1
I2C_CPU1_GP0_SCL_CH2_R1

2

VSS_2

5

VSS_5

8

VSS_8

11

VSS_11

14

VSS_14

17

VSS_17

20

VSS_20

23

VSS_23

26

VSS_26

29

VSS_29

32

VSS_32

35

VSS_35

38

VSS_38

41

VSS_41

44

VSS_44

47

VSS_47

80

VSS_80

83

VSS_83

86

VSS_86

89

VSS_89

92

VSS_92

95

VSS_95

98

VSS_98

101

VSS_101

104

VSS_104

107

VSS_107

110

VSS_110

113

VSS_113

116

VSS_116

121

VSS_121

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

CPU1_M_CH2_EVENT_N

26,27

J_CPU1_CH2_DIMM1

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

(HETERO 2 OF 2)

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

26,27,94

+MEM_CPU1+MEM_CPU1

NP

R299

X

1 2

NP

R298

X

1 2

100-0.5%100-0.5%

26
26

21

C505

1 2

C2777

.1uF

16V-10%

4.7uF

C7304

6.3V-10%

CPU1_M_CH2_DQ_VREF

V_0P75_M_1_CH2_VTT

21

4.7uF

1 2

C2795

6.3V-10%

TITLE

SCHEM,PLN,SV,R610

D

.1uF

16V-10%

21,26,27

26,27,124,141,144

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

1

2

3

CPU1

4

I2C ID = A8

240 PIN DDR3 DIMM SKT

BLACK HOUSING, IVORY EJECTOR

(HETERO 1 OF 2)

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

REV.

RR154

X05

SHEET

11/6/2008 26 OF 145

DCBA

1

2

3

4

+3.3V

A B C

14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26

14,26
14,26
14,26

I2C_CPU1_GP0_SDA_CH2_R2

27

I2C_CPU1_GP0_SCL_CH2_R2

27
20,21,23,24,26,27

20,21,23,24,26

20,21,23,24,26,27

21,26

14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26

14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26

14,26

CPU1_M_CH2_BA_2
CPU1_M_CH2_BA_1
CPU1_M_CH2_BA_0
CPU1_M_CH2_MA_15
CPU1_M_CH2_MA_14
CPU1_M_CH2_MA_13
CPU1_M_CH2_MA_12
CPU1_M_CH2_MA_11
CPU1_M_CH2_MA_10
CPU1_M_CH2_MA_09
CPU1_M_CH2_MA_08
CPU1_M_CH2_MA_07
CPU1_M_CH2_MA_06
CPU1_M_CH2_MA_05
CPU1_M_CH2_MA_04
CPU1_M_CH2_MA_03
CPU1_M_CH2_MA_02
CPU1_M_CH2_MA_01
CPU1_M_CH2_MA_00

CPU1_M_CH2_CS_7_N

14

CPU1_M_CH2_CS_6_N

14

CPU1_M_CH2_CS_5_N

14

CPU1_M_CH2_CS_4_N

14

CPU1_M_CH2_RAS_N
CPU1_M_CH2_CAS_N
CPU1_M_CH2_WE_N
CPU1_M_CH2_CK_3_DP

14

CPU1_M_CH2_CK_3_DN

14

CPU1_M_CH2_CK_1_DN

14

CPU1_M_CH2_CK_1_DP

14

CPU1_M_CH2_CKE_3

14

CPU1_M_CH2_CKE_1

14

CPU1_DIMM_PU
CPU1_DIMM_PD
CPU1_DIMM_PU

CPU1_M_CH2_CA_VREF

26

CPU1_M_CH2_DQ_VREF
CPU1_M_CH2_ODT_3

14

CPU1_M_CH2_ODT_2

14

CPU1_M_CH2_ECC_7
CPU1_M_CH2_ECC_6
CPU1_M_CH2_ECC_5
CPU1_M_CH2_ECC_4
CPU1_M_CH2_ECC_3
CPU1_M_CH2_ECC_2
CPU1_M_CH2_ECC_1
CPU1_M_CH2_ECC_0

CPU1_M_CH2_DQS_17_DN
CPU1_M_CH2_DQS_17_DP
CPU1_M_CH2_DQS_16_DN
CPU1_M_CH2_DQS_16_DP
CPU1_M_CH2_DQS_15_DN
CPU1_M_CH2_DQS_15_DP
CPU1_M_CH2_DQS_14_DN
CPU1_M_CH2_DQS_14_DP
CPU1_M_CH2_DQS_13_DN
CPU1_M_CH2_DQS_13_DP
CPU1_M_CH2_DQS_12_DN
CPU1_M_CH2_DQS_12_DP
CPU1_M_CH2_DQS_11_DN
CPU1_M_CH2_DQS_11_DP
CPU1_M_CH2_DQS_10_DN
CPU1_M_CH2_DQS_10_DP
CPU1_M_CH2_DQS_09_DN
CPU1_M_CH2_DQS_09_DP
CPU1_M_CH2_DQS_08_DN
CPU1_M_CH2_DQS_08_DP
CPU1_M_CH2_DQS_07_DN
CPU1_M_CH2_DQS_07_DP
CPU1_M_CH2_DQS_06_DN
CPU1_M_CH2_DQS_06_DP
CPU1_M_CH2_DQS_05_DN
CPU1_M_CH2_DQS_05_DP
CPU1_M_CH2_DQS_04_DN
CPU1_M_CH2_DQS_04_DP
CPU1_M_CH2_DQS_03_DN
CPU1_M_CH2_DQS_03_DP
CPU1_M_CH2_DQS_02_DN
CPU1_M_CH2_DQS_02_DP
CPU1_M_CH2_DQS_01_DN
CPU1_M_CH2_DQS_01_DP
CPU1_M_CH2_DQS_00_DN
CPU1_M_CH2_DQS_00_DP

CPU1_M_CH2_PERR_1_N

14

CPU1_M_CH2_MA_PAR

NC_J_CPU1_CH2_DIMM2_P167

52

BA2

190

BA1

71

BA0

171

A15/NC

172

A14

196

A13

174

A12/BC_N

55

A11

70

A10/AP

175

A9

177

A8

56

A7

178

A6

58

A5

59

A4

180

A3

61

A2

181

A1

188

A0

198

S3_N/NC

79

S2_N/NC

76

S1_N/NC

193

S0_N

192

RAS_N

74

CAS_N

73

WE_N

63

NC/CK1

64

NC/CK1_N

185

CK0_N

184

CK0

169

CKE1/NC

50

CKE0

238

SDA

118

SCL

119

SA2

237

SA1

117

SA0

236

VDDSPD

67

VREFCA

1

VREFDQ

77

ODT1/NC

195

ODT0

165

CB7/NC

164

CB6/NC

159

CB5/NC

158

CB4/NC

46

CB3/NC

45

CB2/NC

40

CB1/NC

39

CB0/NC

162

NC/DQS17_N/TDQS17_N

161

DM8/DQS17/TDQS17/NC

231

NC/DQS16_N/TDQS16_N

230

DM7/DQS16/TDQS16

222

NC/DQS15_N/TDQS15_N

221

DM6/DQS15/TDQS15

213

NC/DQS14_N/TDQS14_N

212

DM5/DQS14/TDQS14

204

NC/DQS13_N/TDQS13_N

203

DM4/DQS13/TDQS13

153

NC/DQS12_N/TDQS12_N

152

DM3/DQS12/TDQS12

144

NC/DQS11_N/TDQS11_N

143

DM2/DQS11/TDQS11

135

NC/DQS10_N/TDQS10_N

134

DM1/DQS10/TDQS10

126

NC/DQS9_N/TDQS9_N

125

DM0/DQS9/TDQS9

42

DQS8_N

43

DQS8

111

DQS7_N

112

DQS7

102

DQS6_N

103

DQS6

93

DQS5_N

94

DQS5

84

DQS4_N

85

DQS4

33

DQS3_N

34

DQS3

24

DQS2_N

25

DQS2

15

DQS1_N

16

DQS1

6

DQS0_N

7

DQS0

53

ERR_OUT_N/NC

68

PAR_IN/NC

167

NC/TEST

J_CPU1_CH2_DIMM2

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VTT_120

VTT_240
VTT_48/NC
VTT_49/NC

VDD_51
VDD_54
VDD_57
VDD_60
VDD_62
VDD_65
VDD_66
VDD_69
VDD_72
VDD_75

VDD_78
VDD_170
VDD_173
VDD_176
VDD_179
VDD_182
VDD_183
VDD_186
VDD_189
VDD_191
VDD_194
VDD_197

EVENT_N/NC

RESET_N

234
233
228
227
115
114
109
108
225
224
219
218
106
105
100
99
216
215
210
209
97
96
91
90
207
206
201
200
88
87
82
81
156
155
150
149
37
36
31
30
147
146
141
140
28
27
22
21
138
137
132
131
19
18
13
12
129
128
123
122
10
9
4
3

120
240
48
49
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197

187
168

CPU1_M_CH2_DQ63
CPU1_M_CH2_DQ62
CPU1_M_CH2_DQ61
CPU1_M_CH2_DQ60
CPU1_M_CH2_DQ59
CPU1_M_CH2_DQ58
CPU1_M_CH2_DQ57
CPU1_M_CH2_DQ56
CPU1_M_CH2_DQ55
CPU1_M_CH2_DQ54
CPU1_M_CH2_DQ53
CPU1_M_CH2_DQ52
CPU1_M_CH2_DQ51
CPU1_M_CH2_DQ50
CPU1_M_CH2_DQ49
CPU1_M_CH2_DQ48
CPU1_M_CH2_DQ47
CPU1_M_CH2_DQ46
CPU1_M_CH2_DQ45
CPU1_M_CH2_DQ44
CPU1_M_CH2_DQ43
CPU1_M_CH2_DQ42
CPU1_M_CH2_DQ41
CPU1_M_CH2_DQ40
CPU1_M_CH2_DQ39
CPU1_M_CH2_DQ38
CPU1_M_CH2_DQ37
CPU1_M_CH2_DQ36
CPU1_M_CH2_DQ35
CPU1_M_CH2_DQ34
CPU1_M_CH2_DQ33
CPU1_M_CH2_DQ32
CPU1_M_CH2_DQ31
CPU1_M_CH2_DQ30
CPU1_M_CH2_DQ29
CPU1_M_CH2_DQ28
CPU1_M_CH2_DQ27
CPU1_M_CH2_DQ26
CPU1_M_CH2_DQ25
CPU1_M_CH2_DQ24
CPU1_M_CH2_DQ23
CPU1_M_CH2_DQ22
CPU1_M_CH2_DQ21
CPU1_M_CH2_DQ20
CPU1_M_CH2_DQ19
CPU1_M_CH2_DQ18
CPU1_M_CH2_DQ17
CPU1_M_CH2_DQ16
CPU1_M_CH2_DQ15
CPU1_M_CH2_DQ14
CPU1_M_CH2_DQ13
CPU1_M_CH2_DQ12
CPU1_M_CH2_DQ11
CPU1_M_CH2_DQ10
CPU1_M_CH2_DQ09
CPU1_M_CH2_DQ08
CPU1_M_CH2_DQ07
CPU1_M_CH2_DQ06
CPU1_M_CH2_DQ05
CPU1_M_CH2_DQ04
CPU1_M_CH2_DQ03
CPU1_M_CH2_DQ02
CPU1_M_CH2_DQ01
CPU1_M_CH2_DQ00

V_0P75_M_1_CH2_VTT

+MEM_CPU1

CPU1_M_CH2_EVENT_N

CPU1_M_CH2_RST_N

14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26
14,26

26,94
14,26

26,27,124,141,144

CPU1 CH2 DIMM2

+MEM_CPU1

21

C2645

10uF 6.3V

C2644

21

10uF 6.3V

20,21,23,24,26,109
20,21,23,24,26,109

21

C2643

10uF 6.3V

I2C_CPU1_GP0_SDA
I2C_CPU1_GP0_SCL

4.7uF

1 2

C2778

C7305

6.3V-10%

1 2

4.7uF

6.3V-10%

2 1

49.9-1%

R7680

49.9-1%

V_0P75_M_1_CH2_VTT

21

C2796

.1uF

16V-10%

I2C_CPU1_GP0_SDA_CH2_R2
I2C_CPU1_GP0_SCL_CH2_R2

2 1

R7679

26,27,124,141,144

BLACK HOUSING, BLACK EJECTOR

27
27

J_CPU1_CH2_DIMM2
2
5
8

11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95

98
101
104
107
110
113
116
121

VSS_2
VSS_5
VSS_8
VSS_11
VSS_14
VSS_17
VSS_20
VSS_23
VSS_26
VSS_29
VSS_32
VSS_35
VSS_38
VSS_41
VSS_44
VSS_47
VSS_80
VSS_83
VSS_86
VSS_89
VSS_92
VSS_95
VSS_98
VSS_101
VSS_104
VSS_107
VSS_110
VSS_113
VSS_116
VSS_121

VSS_124
VSS_127
VSS_130
VSS_133
VSS_136
VSS_139
VSS_142
VSS_145
VSS_148
VSS_151
VSS_154
VSS_157
VSS_160
VSS_163
VSS_166
VSS_199
VSS_202
VSS_205
VSS_208
VSS_211
VSS_214
VSS_217
VSS_220
VSS_223
VSS_226
VSS_229
VSS_232
VSS_235
VSS_239

240 PIN DDR3 DIMM SKT

(HETERO 2 OF 2)

124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239

TITLE

D

MODULE:
DESC:
REV: OF

INC.

SCHEM,PLN,SV,R610

1

2

3

CPU1

CPUS,CSI,XDP0,XDP1

SEC

4

ROUND ROCK,TEXAS

I2C ID = AA

240 PIN DDR3 DIMM SKT

BLACK HOUSING, BLACK EJECTOR

(HETERO 1 OF 2)

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

RR154

DCBA

REV.

X05

SHEET

27 OF 14511/6/2008

A B C

D

1

1

2

2

DIMM3 NOT PRESENT IN 1U DESIGN

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

THIDWICK

UNIQUE PAGE

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

SHEET

X05

11/6/2008 28 OF 145

DCBA

CPU1

4

A B C

J_CPU2

D

1

12
12
12
12
33

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CSI_CK_CPU2_CPU1_DP
CSI_CK_CPU2_CPU1_DN
CSI_CK_CPU1_CPU2_DP
CSI_CK_CPU1_CPU2_DN
MOD_CPU_CSI_CPU2_COMP_0

CSI_CPU2_CPU1_19_DP
CSI_CPU2_CPU1_18_DP
CSI_CPU2_CPU1_17_DP
CSI_CPU2_CPU1_16_DP
CSI_CPU2_CPU1_15_DP
CSI_CPU2_CPU1_14_DP
CSI_CPU2_CPU1_13_DP
CSI_CPU2_CPU1_12_DP
CSI_CPU2_CPU1_11_DP
CSI_CPU2_CPU1_10_DP
CSI_CPU2_CPU1_09_DP
CSI_CPU2_CPU1_08_DP
CSI_CPU2_CPU1_07_DP
CSI_CPU2_CPU1_06_DP
CSI_CPU2_CPU1_05_DP
CSI_CPU2_CPU1_04_DP
CSI_CPU2_CPU1_03_DP
CSI_CPU2_CPU1_02_DP
CSI_CPU2_CPU1_01_DP
CSI_CPU2_CPU1_00_DP

AG42

CSI0_CLKTX_DP

AF42

CSI0_CLKTX_DN

AR41

CSI0_CLKRX_DP

AR42

CSI0_CLKRX_DN

AL43

CSI0_COMP

AE40

CSI0_DTX_DP_19

AD38

CSI0_DTX_DP_18

AB39

CSI0_DTX_DP_17

AC39

CSI0_DTX_DP_16

AC41

CSI0_DTX_DP_15

AD40

CSI0_DTX_DP_14

AC43

CSI0_DTX_DP_13

AD42

CSI0_DTX_DP_12

AE42

CSI0_DTX_DP_11

AF43

CSI0_DTX_DP_10

AG40

CSI0_DTX_DP_9

AJ43

CSI0_DTX_DP_8

AK42

CSI0_DTX_DP_7

AH41

CSI0_DTX_DP_6

AK40

CSI0_DTX_DP_5

AH40

CSI0_DTX_DP_4

AJ38

CSI0_DTX_DP_3

AK37

CSI0_DTX_DP_2

AF39

CSI0_DTX_DP_1

AG38

CSI0_DTX_DP_0

CSI1_CLKTX_DP
CSI1_CLKTX_DN
CSI1_CLKRX_DP
CSI1_CLKRX_DN

CSI1_COMP

CSI1_DTX_DP_19
CSI1_DTX_DP_18
CSI1_DTX_DP_17
CSI1_DTX_DP_16
CSI1_DTX_DP_15
CSI1_DTX_DP_14
CSI1_DTX_DP_13
CSI1_DTX_DP_12
CSI1_DTX_DP_11
CSI1_DTX_DP_10

CSI1_DTX_DP_9
CSI1_DTX_DP_8
CSI1_DTX_DP_7
CSI1_DTX_DP_6
CSI1_DTX_DP_5
CSI1_DTX_DP_4
CSI1_DTX_DP_3
CSI1_DTX_DP_2
CSI1_DTX_DP_1
CSI1_DTX_DP_0

AF6
AE6
AT6
AR6
AL6

AC8
AD5
AD6
AB6
AC4
AE3
AC3
AD2
AE1
AF2
AH2
AH3
AK1
AJ3
AG7
AJ4
AK6
AH6
AJ8
AG8

CSI_CK_CPU2_IOH_DP
CSI_CK_CPU2_IOH_DN
CSI_CK_IOH_CPU2_DP
CSI_CK_IOH_CPU2_DN

MOD_CPU_CSI_CPU2_COMP_1

CSI_CPU2_IOH_19_DP
CSI_CPU2_IOH_18_DP
CSI_CPU2_IOH_17_DP
CSI_CPU2_IOH_16_DP
CSI_CPU2_IOH_15_DP
CSI_CPU2_IOH_14_DP
CSI_CPU2_IOH_13_DP
CSI_CPU2_IOH_12_DP
CSI_CPU2_IOH_11_DP
CSI_CPU2_IOH_10_DP
CSI_CPU2_IOH_09_DP
CSI_CPU2_IOH_08_DP
CSI_CPU2_IOH_07_DP
CSI_CPU2_IOH_06_DP
CSI_CPU2_IOH_05_DP
CSI_CPU2_IOH_04_DP
CSI_CPU2_IOH_03_DP
CSI_CPU2_IOH_02_DP
CSI_CPU2_IOH_01_DP
CSI_CPU2_IOH_00_DP

51
51
51
51
33

51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51

To IOH

Port 1 Port 1

1

2

Port 0

To CPU1

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CSI_CPU2_CPU1_19_DN
CSI_CPU2_CPU1_18_DN
CSI_CPU2_CPU1_17_DN
CSI_CPU2_CPU1_16_DN
CSI_CPU2_CPU1_15_DN
CSI_CPU2_CPU1_14_DN
CSI_CPU2_CPU1_13_DN
CSI_CPU2_CPU1_12_DN
CSI_CPU2_CPU1_11_DN
CSI_CPU2_CPU1_10_DN
CSI_CPU2_CPU1_09_DN
CSI_CPU2_CPU1_08_DN
CSI_CPU2_CPU1_07_DN
CSI_CPU2_CPU1_06_DN
CSI_CPU2_CPU1_05_DN
CSI_CPU2_CPU1_04_DN
CSI_CPU2_CPU1_03_DN
CSI_CPU2_CPU1_02_DN
CSI_CPU2_CPU1_01_DN
CSI_CPU2_CPU1_00_DN

AF40

CSI0_DTX_DN_19

AE38

CSI0_DTX_DN_18

AB38

CSI0_DTX_DN_17

AC38

CSI0_DTX_DN_16

AC40

CSI0_DTX_DN_15

AD39

CSI0_DTX_DN_14

AB43

CSI0_DTX_DN_13

AC42

CSI0_DTX_DN_12

AE41

CSI0_DTX_DN_11

AE43

CSI0_DTX_DN_10

AG41

CSI0_DTX_DN_9

AH43

CSI0_DTX_DN_8

AJ42

CSI0_DTX_DN_7

AH42

CSI0_DTX_DN_6

AK41

CSI0_DTX_DN_5

AJ40

CSI0_DTX_DN_4

AJ39

CSI0_DTX_DN_3

AK38

CSI0_DTX_DN_2

AG39

CSI0_DTX_DN_1

AH38

CSI0_DTX_DN_0

CSI1_DTX_DN_19
CSI1_DTX_DN_18
CSI1_DTX_DN_17
CSI1_DTX_DN_16
CSI1_DTX_DN_15
CSI1_DTX_DN_14
CSI1_DTX_DN_13
CSI1_DTX_DN_12
CSI1_DTX_DN_11
CSI1_DTX_DN_10

CSI1_DTX_DN_9
CSI1_DTX_DN_8
CSI1_DTX_DN_7
CSI1_DTX_DN_6
CSI1_DTX_DN_5
CSI1_DTX_DN_4
CSI1_DTX_DN_3
CSI1_DTX_DN_2
CSI1_DTX_DN_1
CSI1_DTX_DN_0

AD8
AE5
AD7
AC6
AD4
AE4
AB3
AD3
AD1
AF3
AG2
AH4
AJ1
AJ2
AG6
AK4
AK5
AJ6
AJ7
AH8

CSI_CPU2_IOH_19_DN
CSI_CPU2_IOH_18_DN
CSI_CPU2_IOH_17_DN
CSI_CPU2_IOH_16_DN
CSI_CPU2_IOH_15_DN
CSI_CPU2_IOH_14_DN
CSI_CPU2_IOH_13_DN
CSI_CPU2_IOH_12_DN
CSI_CPU2_IOH_11_DN
CSI_CPU2_IOH_10_DN
CSI_CPU2_IOH_09_DN
CSI_CPU2_IOH_08_DN
CSI_CPU2_IOH_07_DN
CSI_CPU2_IOH_06_DN
CSI_CPU2_IOH_05_DN
CSI_CPU2_IOH_04_DN
CSI_CPU2_IOH_03_DN
CSI_CPU2_IOH_02_DN
CSI_CPU2_IOH_01_DN
CSI_CPU2_IOH_00_DN

51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51

2

3

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CSI_CPU1_CPU2_19_DP
CSI_CPU1_CPU2_18_DP
CSI_CPU1_CPU2_17_DP
CSI_CPU1_CPU2_16_DP
CSI_CPU1_CPU2_15_DP
CSI_CPU1_CPU2_14_DP
CSI_CPU1_CPU2_13_DP
CSI_CPU1_CPU2_12_DP
CSI_CPU1_CPU2_11_DP
CSI_CPU1_CPU2_10_DP
CSI_CPU1_CPU2_09_DP
CSI_CPU1_CPU2_08_DP
CSI_CPU1_CPU2_07_DP
CSI_CPU1_CPU2_06_DP
CSI_CPU1_CPU2_05_DP
CSI_CPU1_CPU2_04_DP
CSI_CPU1_CPU2_03_DP
CSI_CPU1_CPU2_02_DP
CSI_CPU1_CPU2_01_DP
CSI_CPU1_CPU2_00_DP

AP38

CSI0_DRX_DP_19

AN39

CSI0_DRX_DP_18

AP41

CSI0_DRX_DP_17

AM42

CSI0_DRX_DP_16

AN40

CSI0_DRX_DP_15

AN43

CSI0_DRX_DP_14

AP42

CSI0_DRX_DP_13

AT40

CSI0_DRX_DP_12

AT43

CSI0_DRX_DP_11

AU42

CSI0_DRX_DP_10

AU40

CSI0_DRX_DP_9

AW40

CSI0_DRX_DP_8

AU39

CSI0_DRX_DP_7

BA38

CSI0_DRX_DP_6

AW37

CSI0_DRX_DP_5

BA36

CSI0_DRX_DP_4

AW36

CSI0_DRX_DP_3

AV36

CSI0_DRX_DP_2

AU38

CSI0_DRX_DP_1

AT37

CSI0_DRX_DP_0

CSI1_DRX_DP_19
CSI1_DRX_DP_18
CSI1_DRX_DP_17
CSI1_DRX_DP_16
CSI1_DRX_DP_15
CSI1_DRX_DP_14
CSI1_DRX_DP_13
CSI1_DRX_DP_12
CSI1_DRX_DP_11
CSI1_DRX_DP_10

CSI1_DRX_DP_9
CSI1_DRX_DP_8
CSI1_DRX_DP_7
CSI1_DRX_DP_6
CSI1_DRX_DP_5
CSI1_DRX_DP_4
CSI1_DRX_DP_3
CSI1_DRX_DP_2
CSI1_DRX_DP_1
CSI1_DRX_DP_0

AM8
AM6
AN5
AM4
AP3
AM2
AN1
AP2
AR4
AT1
AT3
AU4
AW4
AU7
AY6
BA7
AV5
AY8
AV7
AU8

CSI_IOH_CPU2_19_DP
CSI_IOH_CPU2_18_DN
CSI_IOH_CPU2_17_DP
CSI_IOH_CPU2_16_DP
CSI_IOH_CPU2_15_DP
CSI_IOH_CPU2_14_DP
CSI_IOH_CPU2_13_DP
CSI_IOH_CPU2_12_DP
CSI_IOH_CPU2_11_DP
CSI_IOH_CPU2_10_DP
CSI_IOH_CPU2_09_DN
CSI_IOH_CPU2_08_DP
CSI_IOH_CPU2_07_DP
CSI_IOH_CPU2_06_DP
CSI_IOH_CPU2_05_DP
CSI_IOH_CPU2_04_DP
CSI_IOH_CPU2_03_DP
CSI_IOH_CPU2_02_DP
CSI_IOH_CPU2_01_DP
CSI_IOH_CPU2_00_DP

51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51

From IOH

3

4

12
12
12
12

Port 0

DEBUG: Mirror port default is port 0.

From CPU1

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

CSI_CPU1_CPU2_19_DN
CSI_CPU1_CPU2_18_DN
CSI_CPU1_CPU2_17_DN
CSI_CPU1_CPU2_16_DN
CSI_CPU1_CPU2_15_DN
CSI_CPU1_CPU2_14_DN
CSI_CPU1_CPU2_13_DN
CSI_CPU1_CPU2_12_DN
CSI_CPU1_CPU2_11_DN
CSI_CPU1_CPU2_10_DN
CSI_CPU1_CPU2_09_DN
CSI_CPU1_CPU2_08_DN
CSI_CPU1_CPU2_07_DN
CSI_CPU1_CPU2_06_DN
CSI_CPU1_CPU2_05_DN
CSI_CPU1_CPU2_04_DN
CSI_CPU1_CPU2_03_DN
CSI_CPU1_CPU2_02_DN
CSI_CPU1_CPU2_01_DN
CSI_CPU1_CPU2_00_DN

CPU2

AR38

CSI0_DRX_DN_19

AP39

CSI0_DRX_DN_18

AP40

CSI0_DRX_DN_17

AM41

CSI0_DRX_DN_16

AM40

CSI0_DRX_DN_15

AM43

CSI0_DRX_DN_14

AN42

CSI0_DRX_DN_13

AR40

CSI0_DRX_DN_12

AR43

CSI0_DRX_DN_11

AT42

CSI0_DRX_DN_10

AU41

CSI0_DRX_DN_9

AV40

CSI0_DRX_DN_8

AT39

CSI0_DRX_DN_7

AY38

CSI0_DRX_DN_6

AW38

CSI0_DRX_DN_5

BA37

CSI0_DRX_DN_4

AY36

CSI0_DRX_DN_3

AV37

CSI0_DRX_DN_2

AV38

CSI0_DRX_DN_1

AU37

CSI0_DRX_DN_0

ADD*_FN258_ILM

ADD*_Y080J_ILM_COVER
ADD*_D994J_LABEL

GAINESTOWN_WESTMERE REV 2.0

HETERO 1 OF 10

P21_SCH_17608 added ilm cover and label

CSI1_DRX_DN_19
CSI1_DRX_DN_18
CSI1_DRX_DN_17
CSI1_DRX_DN_16
CSI1_DRX_DN_15
CSI1_DRX_DN_14
CSI1_DRX_DN_13
CSI1_DRX_DN_12
CSI1_DRX_DN_11
CSI1_DRX_DN_10

CSI1_DRX_DN_9
CSI1_DRX_DN_8
CSI1_DRX_DN_7
CSI1_DRX_DN_6
CSI1_DRX_DN_5
CSI1_DRX_DN_4
CSI1_DRX_DN_3
CSI1_DRX_DN_2
CSI1_DRX_DN_1
CSI1_DRX_DN_0

AL8
AM7
AN6
AN4
AP4
AM3
AM1
AN2
AR5
AR1
AT2
AU3
AW3
AU6
AY5
BA6
AW5
BA8
AW7
AV8

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

CSI_IOH_CPU2_19_DN
CSI_IOH_CPU2_18_DP
CSI_IOH_CPU2_17_DN
CSI_IOH_CPU2_16_DN
CSI_IOH_CPU2_15_DN
CSI_IOH_CPU2_14_DN
CSI_IOH_CPU2_13_DN
CSI_IOH_CPU2_12_DN
CSI_IOH_CPU2_11_DN
CSI_IOH_CPU2_10_DN
CSI_IOH_CPU2_09_DP
CSI_IOH_CPU2_08_DN
CSI_IOH_CPU2_07_DN
CSI_IOH_CPU2_06_DN
CSI_IOH_CPU2_05_DN
CSI_IOH_CPU2_04_DN
CSI_IOH_CPU2_03_DN
CSI_IOH_CPU2_02_DN
CSI_IOH_CPU2_01_DN
CSI_IOH_CPU2_00_DN

51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM,PLN,SV,R610

REV.

RR154

X05

SHEET

11/6/2008 29 OF 145

CPU2

4

DCBA

A B C

J_CPU2

D

J_CPU2

1

2

3

36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37

36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37

36,37

37
36

CPU2_M_CH0_DQ63
CPU2_M_CH0_DQ62
CPU2_M_CH0_DQ61
CPU2_M_CH0_DQ60
CPU2_M_CH0_DQ59
CPU2_M_CH0_DQ58
CPU2_M_CH0_DQ57
CPU2_M_CH0_DQ56
CPU2_M_CH0_DQ55
CPU2_M_CH0_DQ54
CPU2_M_CH0_DQ53
CPU2_M_CH0_DQ52
CPU2_M_CH0_DQ51
CPU2_M_CH0_DQ50
CPU2_M_CH0_DQ49
CPU2_M_CH0_DQ48
CPU2_M_CH0_DQ47
CPU2_M_CH0_DQ46
CPU2_M_CH0_DQ45
CPU2_M_CH0_DQ44
CPU2_M_CH0_DQ43
CPU2_M_CH0_DQ42
CPU2_M_CH0_DQ41
CPU2_M_CH0_DQ40
CPU2_M_CH0_DQ39
CPU2_M_CH0_DQ38
CPU2_M_CH0_DQ37
CPU2_M_CH0_DQ36
CPU2_M_CH0_DQ35
CPU2_M_CH0_DQ34
CPU2_M_CH0_DQ33
CPU2_M_CH0_DQ32
CPU2_M_CH0_DQ31
CPU2_M_CH0_DQ30
CPU2_M_CH0_DQ29
CPU2_M_CH0_DQ28
CPU2_M_CH0_DQ27
CPU2_M_CH0_DQ26
CPU2_M_CH0_DQ25
CPU2_M_CH0_DQ24
CPU2_M_CH0_DQ23
CPU2_M_CH0_DQ22
CPU2_M_CH0_DQ21
CPU2_M_CH0_DQ20
CPU2_M_CH0_DQ19
CPU2_M_CH0_DQ18
CPU2_M_CH0_DQ17
CPU2_M_CH0_DQ16
CPU2_M_CH0_DQ15
CPU2_M_CH0_DQ14
CPU2_M_CH0_DQ13
CPU2_M_CH0_DQ12
CPU2_M_CH0_DQ11
CPU2_M_CH0_DQ10
CPU2_M_CH0_DQ09
CPU2_M_CH0_DQ08
CPU2_M_CH0_DQ07
CPU2_M_CH0_DQ06
CPU2_M_CH0_DQ05
CPU2_M_CH0_DQ04
CPU2_M_CH0_DQ03
CPU2_M_CH0_DQ02
CPU2_M_CH0_DQ01
CPU2_M_CH0_DQ00

CPU2_M_CH0_ECC_7
CPU2_M_CH0_ECC_6
CPU2_M_CH0_ECC_5
CPU2_M_CH0_ECC_4
CPU2_M_CH0_ECC_3
CPU2_M_CH0_ECC_2
CPU2_M_CH0_ECC_1
CPU2_M_CH0_ECC_0

CPU2_M_CH0_MA_PAR

NC_SCR_CPU2_M_CH0_PERR_2_N
CPU2_M_CH0_PERR_1_N
CPU2_M_CH0_PERR_0_N

W4

DDR0_DQ_63

V4

DDR0_DQ_62

U3

DDR0_DQ_61

U1

DDR0_DQ_60

Y3

DDR0_DQ_59

Y2

DDR0_DQ_58

V1

DDR0_DQ_57

U4

DDR0_DQ_56

T3

DDR0_DQ_55

R4

DDR0_DQ_54

N3

DDR0_DQ_53

M3

DDR0_DQ_52

T2

DDR0_DQ_51

T1

DDR0_DQ_50

N2

DDR0_DQ_49

N1

DDR0_DQ_48

L2

DDR0_DQ_47

L3

DDR0_DQ_46

H3

DDR0_DQ_45

G1

DDR0_DQ_44

M1

DDR0_DQ_43

L1

DDR0_DQ_42

H1

DDR0_DQ_41

H2

DDR0_DQ_40

F2

DDR0_DQ_39

F3

DDR0_DQ_38

C6

DDR0_DQ_37

B6

DDR0_DQ_36

G3

DDR0_DQ_35

F1

DDR0_DQ_34

C4

DDR0_DQ_33

B5

DDR0_DQ_32

B38

DDR0_DQ_31

C38

DDR0_DQ_30

D42

DDR0_DQ_29

D41

DDR0_DQ_28

D37

DDR0_DQ_27

A38

DDR0_DQ_26

C41

DDR0_DQ_25

D40

DDR0_DQ_24

F42

DDR0_DQ_23

F43

DDR0_DQ_22

J41

DDR0_DQ_21

J42

DDR0_DQ_20

E43

DDR0_DQ_19

E42

DDR0_DQ_18

H43

DDR0_DQ_17

H41

DDR0_DQ_16

L42

DDR0_DQ_15

L43

DDR0_DQ_14

P41

DDR0_DQ_13

P42

DDR0_DQ_12

K43

DDR0_DQ_11

K42

DDR0_DQ_10

N43

DDR0_DQ_9

N41

DDR0_DQ_8

T42

DDR0_DQ_7

U41

DDR0_DQ_6

W42

DDR0_DQ_5

W40

DDR0_DQ_4

R42

DDR0_DQ_3

R43

DDR0_DQ_2

V41

DDR0_DQ_1

W41

DDR0_DQ_0

C34

DDR0_ECC_7

B34

DDR0_ECC_6

A37

DDR0_ECC_5

C37

DDR0_ECC_4

C33

DDR0_ECC_3

F32

DDR0_ECC_2

A36

DDR0_ECC_1

C36

DDR0_ECC_0

B20

DDR0_MA_PAR

A27

DDR0_PAR_ERR_N_2

B28

DDR0_PAR_ERR_N_1

D25

DDR0_PAR_ERR_N_0

DDR0_DQS_P_17
DDR0_DQS_P_16
DDR0_DQS_P_15
DDR0_DQS_P_14
DDR0_DQS_P_13
DDR0_DQS_P_12
DDR0_DQS_P_11
DDR0_DQS_P_10

DDR0_DQS_P_9
DDR0_DQS_P_8
DDR0_DQS_P_7
DDR0_DQS_P_6
DDR0_DQS_P_5
DDR0_DQS_P_4
DDR0_DQS_P_3
DDR0_DQS_P_2
DDR0_DQS_P_1
DDR0_DQS_P_0

DDR0_DQS_N_17
DDR0_DQS_N_16
DDR0_DQS_N_15
DDR0_DQS_N_14
DDR0_DQS_N_13
DDR0_DQS_N_12
DDR0_DQS_N_11
DDR0_DQS_N_10

DDR0_DQS_N_9
DDR0_DQS_N_8
DDR0_DQS_N_7
DDR0_DQS_N_6
DDR0_DQS_N_5
DDR0_DQS_N_4
DDR0_DQS_N_3
DDR0_DQS_N_2
DDR0_DQS_N_1
DDR0_DQS_N_0

DDR0_MA_15
DDR0_MA_14
DDR0_MA_13
DDR0_MA_12
DDR0_MA_11
DDR0_MA_10

DDR0_MA_9
DDR0_MA_8
DDR0_MA_7
DDR0_MA_6
DDR0_MA_5
DDR0_MA_4
DDR0_MA_3
DDR0_MA_2
DDR0_MA_1
DDR0_MA_0

DDR0_BA_2
DDR0_BA_1
DDR0_BA_0

DDR0_CLK_P_3
DDR0_CLK_P_2
DDR0_CLK_P_1
DDR0_CLK_P_0

DDR0_CLK_N_3
DDR0_CLK_N_2
DDR0_CLK_N_1
DDR0_CLK_N_0

DDR0_CS_N_7/DDR0_ODT_5
DDR0_CS_N_6/DDR0_ODT_4

DDR0_CS_N_5
DDR0_CS_N_4
DDR0_CS_N_3
DDR0_CS_N_2
DDR0_CS_N_1
DDR0_CS_N_0

B36
V2
P2
J2
D5
D39
H42
N42
V43
D34
W2
R2
K2
E3
B39
F41
L41
T43

B35
V3
P1
J1
D4
C39
G43
M43
V42
D35
W1
R3
K3
E4
B40
G41
M41
U43

B29
A28
A10
B26
A26
B19
C26
B25
A25
C24
B24
B23
D24
C23
B21
A20

C28
A16
B16

E20
F18
D19
J19

E19
E18
C19
K19

B8
C11
A7
B15
B9
C13
B10
G15

CPU2_M_CH0_DQS_17_DP
CPU2_M_CH0_DQS_16_DP
CPU2_M_CH0_DQS_15_DP
CPU2_M_CH0_DQS_14_DP
CPU2_M_CH0_DQS_13_DP
CPU2_M_CH0_DQS_12_DP
CPU2_M_CH0_DQS_11_DP
CPU2_M_CH0_DQS_10_DP
CPU2_M_CH0_DQS_09_DP
CPU2_M_CH0_DQS_08_DP
CPU2_M_CH0_DQS_07_DP
CPU2_M_CH0_DQS_06_DP
CPU2_M_CH0_DQS_05_DP
CPU2_M_CH0_DQS_04_DP
CPU2_M_CH0_DQS_03_DP
CPU2_M_CH0_DQS_02_DP
CPU2_M_CH0_DQS_01_DP
CPU2_M_CH0_DQS_00_DP

CPU2_M_CH0_DQS_17_DN
CPU2_M_CH0_DQS_16_DN
CPU2_M_CH0_DQS_15_DN
CPU2_M_CH0_DQS_14_DN
CPU2_M_CH0_DQS_13_DN
CPU2_M_CH0_DQS_12_DN
CPU2_M_CH0_DQS_11_DN
CPU2_M_CH0_DQS_10_DN
CPU2_M_CH0_DQS_09_DN
CPU2_M_CH0_DQS_08_DN
CPU2_M_CH0_DQS_07_DN
CPU2_M_CH0_DQS_06_DN
CPU2_M_CH0_DQS_05_DN
CPU2_M_CH0_DQS_04_DN
CPU2_M_CH0_DQS_03_DN
CPU2_M_CH0_DQS_02_DN
CPU2_M_CH0_DQS_01_DN
CPU2_M_CH0_DQS_00_DN

CPU2_M_CH0_MA_15
CPU2_M_CH0_MA_14
CPU2_M_CH0_MA_13
CPU2_M_CH0_MA_12
CPU2_M_CH0_MA_11
CPU2_M_CH0_MA_10
CPU2_M_CH0_MA_09
CPU2_M_CH0_MA_08
CPU2_M_CH0_MA_07
CPU2_M_CH0_MA_06
CPU2_M_CH0_MA_05
CPU2_M_CH0_MA_04
CPU2_M_CH0_MA_03
CPU2_M_CH0_MA_02
CPU2_M_CH0_MA_01
CPU2_M_CH0_MA_00

CPU2_M_CH0_BA_2
CPU2_M_CH0_BA_1
CPU2_M_CH0_BA_0

CPU2_M_CH0_CK_3_DP
CPU2_M_CH0_CK_2_DP
CPU2_M_CH0_CK_1_DP
CPU2_M_CH0_CK_0_DP

CPU2_M_CH0_CK_3_DN
CPU2_M_CH0_CK_2_DN
CPU2_M_CH0_CK_1_DN
CPU2_M_CH0_CK_0_DN

CPU2_M_CH0_CS_7_N
CPU2_M_CH0_CS_6_N
CPU2_M_CH0_CS_5_N
CPU2_M_CH0_CS_4_N
CPU2_M_CH0_CS_3_N
CPU2_M_CH0_CS_2_N
CPU2_M_CH0_CS_1_N
CPU2_M_CH0_CS_0_N

36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37

36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37

36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37
36,37

36,37
36,37
36,37

37
36
37
36

37
36
37
36

37
37
37
37
36
36
36
36

39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40

39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40

39,40

40
39

CPU2_M_CH1_DQ63
CPU2_M_CH1_DQ62
CPU2_M_CH1_DQ61
CPU2_M_CH1_DQ60
CPU2_M_CH1_DQ59
CPU2_M_CH1_DQ58
CPU2_M_CH1_DQ57
CPU2_M_CH1_DQ56
CPU2_M_CH1_DQ55
CPU2_M_CH1_DQ54
CPU2_M_CH1_DQ53
CPU2_M_CH1_DQ52
CPU2_M_CH1_DQ51
CPU2_M_CH1_DQ50
CPU2_M_CH1_DQ49
CPU2_M_CH1_DQ48
CPU2_M_CH1_DQ47
CPU2_M_CH1_DQ46
CPU2_M_CH1_DQ45
CPU2_M_CH1_DQ44
CPU2_M_CH1_DQ43
CPU2_M_CH1_DQ42
CPU2_M_CH1_DQ41
CPU2_M_CH1_DQ40
CPU2_M_CH1_DQ39
CPU2_M_CH1_DQ38
CPU2_M_CH1_DQ37
CPU2_M_CH1_DQ36
CPU2_M_CH1_DQ35
CPU2_M_CH1_DQ34
CPU2_M_CH1_DQ33
CPU2_M_CH1_DQ32
CPU2_M_CH1_DQ31
CPU2_M_CH1_DQ30
CPU2_M_CH1_DQ29
CPU2_M_CH1_DQ28
CPU2_M_CH1_DQ27
CPU2_M_CH1_DQ26
CPU2_M_CH1_DQ25
CPU2_M_CH1_DQ24
CPU2_M_CH1_DQ23
CPU2_M_CH1_DQ22
CPU2_M_CH1_DQ21
CPU2_M_CH1_DQ20
CPU2_M_CH1_DQ19
CPU2_M_CH1_DQ18
CPU2_M_CH1_DQ17
CPU2_M_CH1_DQ16
CPU2_M_CH1_DQ15
CPU2_M_CH1_DQ14
CPU2_M_CH1_DQ13
CPU2_M_CH1_DQ12
CPU2_M_CH1_DQ11
CPU2_M_CH1_DQ10
CPU2_M_CH1_DQ09
CPU2_M_CH1_DQ08
CPU2_M_CH1_DQ07
CPU2_M_CH1_DQ06
CPU2_M_CH1_DQ05
CPU2_M_CH1_DQ04
CPU2_M_CH1_DQ03
CPU2_M_CH1_DQ02
CPU2_M_CH1_DQ01
CPU2_M_CH1_DQ00

CPU2_M_CH1_ECC_7
CPU2_M_CH1_ECC_6
CPU2_M_CH1_ECC_5
CPU2_M_CH1_ECC_4
CPU2_M_CH1_ECC_3
CPU2_M_CH1_ECC_2
CPU2_M_CH1_ECC_1
CPU2_M_CH1_ECC_0

CPU2_M_CH1_MA_PAR

NC_SCR_CPU2_M_CH1_PERR_2_N
CPU2_M_CH1_PERR_1_N
CPU2_M_CH1_PERR_0_N

W9

DDR1_DQ_63

AA7

DDR1_DQ_62

W5

DDR1_DQ_61

V9

DDR1_DQ_60

W10

DDR1_DQ_59

Y10

DDR1_DQ_58

W7

DDR1_DQ_57

W6

DDR1_DQ_56

R7

DDR1_DQ_55

R8

DDR1_DQ_54

M6

DDR1_DQ_53

J4

DDR1_DQ_52

T5

DDR1_DQ_51

R5

DDR1_DQ_50

K5

DDR1_DQ_49

K4

DDR1_DQ_48

J5

DDR1_DQ_47

G5

DDR1_DQ_46

H9

DDR1_DQ_45

G9

DDR1_DQ_44

H4

DDR1_DQ_43

G4

DDR1_DQ_42

J6

DDR1_DQ_41

H8

DDR1_DQ_40

F6

DDR1_DQ_39

D6

DDR1_DQ_38

G8

DDR1_DQ_37

F10

DDR1_DQ_36

F5

DDR1_DQ_35

E5

DDR1_DQ_34

E8

DDR1_DQ_33

E9

DDR1_DQ_32

K30

DDR1_DQ_31

L32

DDR1_DQ_30

H34

DDR1_DQ_29

J34

DDR1_DQ_28

J32

DDR1_DQ_27

K32

DDR1_DQ_26

L33

DDR1_DQ_25

H33

DDR1_DQ_24

H36

DDR1_DQ_23

J36

DDR1_DQ_22

M36

DDR1_DQ_21

N34

DDR1_DQ_20

J35

DDR1_DQ_19

K35

DDR1_DQ_18

M34

DDR1_DQ_17

M35

DDR1_DQ_16

N38

DDR1_DQ_15

N37

DDR1_DQ_14

R35

DDR1_DQ_13

R34

DDR1_DQ_12

N39

DDR1_DQ_11

P39

DDR1_DQ_10

P35

DDR1_DQ_9

P34

DDR1_DQ_8

Y39

DDR1_DQ_7

Y40

DDR1_DQ_6

AB36

DDR1_DQ_5

AA35

DDR1_DQ_4

Y34

DDR1_DQ_3

Y35

DDR1_DQ_2

AA36

DDR1_DQ_1

AA37

DDR1_DQ_0

G35

DDR1_ECC_7

E34

DDR1_ECC_6

F37

DDR1_ECC_5

E37

DDR1_ECC_4

G36

DDR1_ECC_3

E33

DDR1_ECC_2

F36

DDR1_ECC_1

D36

DDR1_ECC_0

D20

DDR1_MA_PAR

F25

DDR1_PAR_ERR_N_2

E25

DDR1_PAR_ERR_N_1

C22

DDR1_PAR_ERR_N_0

DDR1_DQS_P_17
DDR1_DQS_P_16
DDR1_DQS_P_15
DDR1_DQS_P_14
DDR1_DQS_P_13
DDR1_DQS_P_12
DDR1_DQS_P_11
DDR1_DQS_P_10

DDR1_DQS_P_9
DDR1_DQS_P_8
DDR1_DQS_P_7
DDR1_DQS_P_6
DDR1_DQS_P_5
DDR1_DQS_P_4
DDR1_DQS_P_3
DDR1_DQS_P_2
DDR1_DQS_P_1
DDR1_DQS_P_0

DDR1_DQS_N_17
DDR1_DQS_N_16
DDR1_DQS_N_15
DDR1_DQS_N_14
DDR1_DQS_N_13
DDR1_DQS_N_12
DDR1_DQS_N_11
DDR1_DQS_N_10

DDR1_DQS_N_9
DDR1_DQS_N_8
DDR1_DQS_N_7
DDR1_DQS_N_6
DDR1_DQS_N_5
DDR1_DQS_N_4
DDR1_DQS_N_3
DDR1_DQS_N_2
DDR1_DQS_N_1
DDR1_DQS_N_0

DDR1_MA_15
DDR1_MA_14
DDR1_MA_13
DDR1_MA_12
DDR1_MA_11
DDR1_MA_10

DDR1_MA_9
DDR1_MA_8
DDR1_MA_7
DDR1_MA_6
DDR1_MA_5
DDR1_MA_4
DDR1_MA_3
DDR1_MA_2
DDR1_MA_1
DDR1_MA_0

DDR1_BA_2
DDR1_BA_1
DDR1_BA_0

DDR1_CLK_P_3
DDR1_CLK_P_2
DDR1_CLK_P_1
DDR1_CLK_P_0

DDR1_CLK_N_3
DDR1_CLK_N_2
DDR1_CLK_N_1
DDR1_CLK_N_0

DDR1_CS_N_7/DDR1_ODT_5
DDR1_CS_N_6/DDR1_ODT_4

DDR1_CS_N_5
DDR1_CS_N_4
DDR1_CS_N_3
DDR1_CS_N_2
DDR1_CS_N_1
DDR1_CS_N_0

F35
Y4
M5
H7
F8
K34
L37
P36
AA40
G33
Y8
L6
H6
E7
L30
L35
R38
Y38

E35
Y5
M4
J7
F7
K33
K37
P37
AA41
G34
Y9
L5
G6
D7
L31
L36
R37
Y37

F26
H26
B14
E24
E23
H14
G24
E22
D22
J27
F22
K28
L28
J17
J16
J14

H27
K13
C18

H18
K18
G19
C21

H19
L18
G20
D21

E12
C14
E10
C17
E13
E15
A8
D12

CPU2_M_CH1_DQS_17_DP
CPU2_M_CH1_DQS_16_DP
CPU2_M_CH1_DQS_15_DP
CPU2_M_CH1_DQS_14_DP
CPU2_M_CH1_DQS_13_DP
CPU2_M_CH1_DQS_12_DP
CPU2_M_CH1_DQS_11_DP
CPU2_M_CH1_DQS_10_DP
CPU2_M_CH1_DQS_09_DP
CPU2_M_CH1_DQS_08_DP
CPU2_M_CH1_DQS_07_DP
CPU2_M_CH1_DQS_06_DP
CPU2_M_CH1_DQS_05_DP
CPU2_M_CH1_DQS_04_DP
CPU2_M_CH1_DQS_03_DP
CPU2_M_CH1_DQS_02_DP
CPU2_M_CH1_DQS_01_DP
CPU2_M_CH1_DQS_00_DP

CPU2_M_CH1_DQS_17_DN
CPU2_M_CH1_DQS_16_DN
CPU2_M_CH1_DQS_15_DN
CPU2_M_CH1_DQS_14_DN
CPU2_M_CH1_DQS_13_DN
CPU2_M_CH1_DQS_12_DN
CPU2_M_CH1_DQS_11_DN
CPU2_M_CH1_DQS_10_DN
CPU2_M_CH1_DQS_09_DN
CPU2_M_CH1_DQS_08_DN
CPU2_M_CH1_DQS_07_DN
CPU2_M_CH1_DQS_06_DN
CPU2_M_CH1_DQS_05_DN
CPU2_M_CH1_DQS_04_DN
CPU2_M_CH1_DQS_03_DN
CPU2_M_CH1_DQS_02_DN
CPU2_M_CH1_DQS_01_DN
CPU2_M_CH1_DQS_00_DN

CPU2_M_CH1_MA_15
CPU2_M_CH1_MA_14
CPU2_M_CH1_MA_13
CPU2_M_CH1_MA_12
CPU2_M_CH1_MA_11
CPU2_M_CH1_MA_10
CPU2_M_CH1_MA_09
CPU2_M_CH1_MA_08
CPU2_M_CH1_MA_07
CPU2_M_CH1_MA_06
CPU2_M_CH1_MA_05
CPU2_M_CH1_MA_04
CPU2_M_CH1_MA_03
CPU2_M_CH1_MA_02
CPU2_M_CH1_MA_01
CPU2_M_CH1_MA_00

CPU2_M_CH1_BA_2
CPU2_M_CH1_BA_1
CPU2_M_CH1_BA_0

CPU2_M_CH1_CK_3_DP
CPU2_M_CH1_CK_2_DP
CPU2_M_CH1_CK_1_DP
CPU2_M_CH1_CK_0_DP

CPU2_M_CH1_CK_3_DN
CPU2_M_CH1_CK_2_DN
CPU2_M_CH1_CK_1_DN
CPU2_M_CH1_CK_0_DN

CPU2_M_CH1_CS_7_N
CPU2_M_CH1_CS_6_N
CPU2_M_CH1_CS_5_N
CPU2_M_CH1_CS_4_N
CPU2_M_CH1_CS_3_N
CPU2_M_CH1_CS_2_N
CPU2_M_CH1_CS_1_N
CPU2_M_CH1_CS_0_N

39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40

39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40

39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40
39,40

39,40
39,40
39,40

40
39
40
39

40
39
40
39

40
40
40
40
39
39
39
39

1

2

3

4

CPU2_M_CH0_ODT_3

37

CPU2_M_CH0_ODT_2

37

CPU2_M_CH0_ODT_1

36

CPU2_M_CH0_ODT_0

36

CPU2

C7

DDR0_ODT_3

B11

DDR0_ODT_2

C9

DDR0_ODT_1

F12

DDR0_ODT_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 2 OF 10

DDR0_CKE_3
DDR0_CKE_2
DDR0_CKE_1
DDR0_CKE_0

DDR0_WE_N
DDR0_RAS_N
DDR0_CAS_N

DDR0_RESET_N

B31
B30
A30
C29

B13
A15
C12

D32

CPU2_M_CH0_CKE_3
CPU2_M_CH0_CKE_2
CPU2_M_CH0_CKE_1
CPU2_M_CH0_CKE_0

CPU2_M_CH0_WE_N
CPU2_M_CH0_RAS_N
CPU2_M_CH0_CAS_N

CPU2_M_CH0_RST_N

37
36
37
36

CPU2_M_CH1_ODT_3

40

CPU2_M_CH1_ODT_2

36,37
36,37
36,37

36,37

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

40

CPU2_M_CH1_ODT_1

39

CPU2_M_CH1_ODT_0

39

F11

DDR1_ODT_3

D14

DDR1_ODT_2

C8

DDR1_ODT_1

D11

DDR1_ODT_0

GAINESTOWN_WESTMERE REV 2.0

HETERO 3 OF 10

DDR1_CKE_3
DDR1_CKE_2
DDR1_CKE_1
DDR1_CKE_0

DDR1_WE_N
DDR1_RAS_N
DDR1_CAS_N

DDR1_RESET_N

C27
D27
E27
H28

G13
G14
E14

D29

CPU2_M_CH1_CKE_3
CPU2_M_CH1_CKE_2
CPU2_M_CH1_CKE_1
CPU2_M_CH1_CKE_0

CPU2_M_CH1_WE_N
CPU2_M_CH1_RAS_N
CPU2_M_CH1_CAS_N

CPU2_M_CH1_RST_N

TITLE

SCHEM,PLN,SV,R610

DWG NO.

RR154

DATE

40
39
40
39

39,40
39,40
39,40

39,40

MODULE:
DESC:
REV: OF

CPUS,CSI,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

REV.

X05

SHEET

30 OF 14511/6/2008

CPU2

4

DCBA