MSI MS-9184 9184_0A

5

4

3

2

1

MS-9184 AMD OptronII Socket F 4 ways DDRII System

001 COVER 002 Block Diagram 003 Main Power

D D

004 1.2V&1.5V&1.4V Power

Power

005 POWER CONNECTOR 006 Clock Synthesizer 007 CPU0_VT1115M 008 CPU0_VT1135S 009 CPU1_VT1115M 010 CPU1_VT1135S 011 CPU2_VT1115M

CPU 0

CPU 1

CPU 2

012 CPU2_VT1135S 013 CPU3_VT1115M

CPU 3

014 CPU3_VT1135S 015 CPU0 DDR POWER

C C

016 CPU0 DDR POWER 017 CPU0 DDR POWER 018 CPU3 DDR POWER

CPU 0 CPU 1 CPU 2 CPU 3

019 CPU0 HT Interface 020 CPU0 Memory Interface 021 CPU0 MISC/ POWER /GND 022 DDR2 Connector A1_P0 023 DDR2 Connector A2_P0

CPU 0

024 DDR2 Connector B1_P0 025 DDR2 Connector B2_P0 026 DDR2 Termination/Caps_ P0 027 CPU0 Decoupling CAP 028 CPU1 HT Interface

B B

029 CPU1 Memory Interface 030 CPU1 MISC/ POWER /GND 031 DDR2 Connector A1_P1 032 DDR2 Connector A2_P1

CPU 1

033 DDR2 Connector B1_P1 034 DDR2 Connector B2_P1 035 DDR2 Termination/Caps_ P1 036 CPU1 Decoupling CAP 037 CPU2 HT Interface 038 CPU2 Memory Interface 039 CPU2 MISC/ POWER /GND 040 DDR2 Connector A1_P2

A A

041 DDR2 Connector A2_P2

CPU 2

042 DDR2 Connector B1_P2 043 DDR2 Connector B2_P2 044 DDR2 Termination/Caps_ P2 045 CPU2 Decoupling CAP

5

046 CPU3 HT Interface 047 CPU3 Memory Interface 048 CPU3 MISC/ POWER /GND 049 DDR2 Connector A1_P3 050 DDR2 Connector A2_P3 051 DDR2 Connector B1_P3 052 DDR2 Connector B2_P3 053 DDR2 Termination/Caps_ P3 054 CPU3 Decoupling CAP 055 HDT_new 056 HT-LINK slot 057 MCP55-1/HT 058 MCP55-2/PWR&GND 059 MCP55-3/PCI,LPC 060 MCP55-4/PCI-E 061 MCP55-5/SATA,IDE 062 MCP55-6/USB,GPIO 063 MCP55-7/RGMII 064 LAN1 Marvell 88E1116 065 LAN2 Marvell 88E1116 066 PXH-V MISC 067 PXH-V PCIX-A 068 PXH-V PCI-X SLOT1-2 069 ATI RN50 PCI 070 ATI RN50 Memory 071 VGA Connector 072 PCI Slot 073 PCI-E 8X Slot &HTX Slot 074 PCI-E 8X Slot 075 Super IO W83627EHG,LPC 076 BIOS&Keyboard&Mouse&Print 077 USB&IDE 078 SMBUS Isolation 079 SSI connector+SPK+RESET+FP 080 BMC_H8S_2168 081 BMC_SDRAM 082 SYSTEM Logic 083 Haedware Monitor1 084 Haedware Monitor2 085 FAN 086 Misc Parts 087 SMBUS connection 088 SB/SIO GPIO 089 Power Map1 090 Power Map1

4

CPU 3

MCP55

LAN

PXH-V

VGA ATi RN50

H8_BMC

072 SIO-PC87417 GPIO 091 Clock Map 092 IO Map

3

Revision : 0A

Date : 2006/05/30

POWER DEFINITIONM P0_VCORE, P1_VCORE

P2_VCORE, P3_VCORE P0_P1V8, P1_P1V8

P2_P1V8, P3_P1V8 P0_VTT_0.9V, P1_VTT_0.9V

P2_VTT_0.9V, P3_VTT_0.9V +1.2V_HT +1.5V

CPU Voltage

DDR Dimm Voltage

DIMM Termination HT Voltage

MCP55,PXH-V Voltage +2.5VPLL0 CPU0,3 POWER +2.5VPLL1 CPU1,2 POWER +1.4V MCP55 Voltage +1.4VDUAL MCP55Voltage +5VSB +3.3VDUAL +5VDUAL LAN1_1V8 LAN2_1V8 P1V8_VGA VBAT

2

Standby Voltage

Dual-Voltage

Dual-Voltage (For G-LAN)

ATI RN50 VGA Voltage

Battrey Voltage

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

COVER

MS-9184

1

0AC

of

192Thursday, August 31, 2006

8

7

6

5

4

3

2

1

HTX_E1

D D

HTX Slot (X16/X1)

128 bit

200 - 400 MHz

4 DDR2 DIMM

Registered

HTLINK

2

Opteron II L1 Processor

1

HTLINK

HT_2

PCIE16 SLOT

1

Opteron II

0

HTLINK

L1 Processor

0

( H2 )( H3 )

2

BLOCK DIAGRAM

U88U62

128 bit

200 - 400 MHz

4 DDR2 DIMM

Registered

HTLINK

16x16 cHyperTransport @ 2000MT/s

U63 U1

C C

128 bit

200 - 400 MHz

Opteron II L1 Processor

2

0

PCIE16 SLOT

HTLINK

0

4 DDR2 DIMM

Registered

1

Opteron II L1 Processor

( H1 )( H0 )

2

128 bit

200 - 400 MHz

4 DDR2 DIMM

Registered

HT_1

100 MHz

HTLINK

PCI-X Slot

PCIX1

PCIX2

HTLINK

PCI1

PCI SLOT

B B

IDE Channel

USB Port 1/2/3/4

PCI

EIDE ATA/100

USB 2.0

U39

NVIDIA MCP-55

HTLINK

8 X PCI-E Slot

PCI-E Bus

8 X PCI-E Slot

PCIE3 PCIE2 PCIE1

HTLINK

16x16 ncHyperTransport @ 2000MT/s

4X PCI-E Slot

U128

INTEL PXH-V

U124

ATI RN-50

SATA Port 0/1/2/3/4/5

SATA

PCI Bus 32 bit / 33 MHz

8 MB RAM

VGA

LPC

U108

BMC H8

I2C Bus

U122

Flash ROM

A A

PS2 KB/MS

8

7

LPC SIO W83627

FDD

I2C Bus

Serial (COM1,2)

6

5

OR

HM W83792D

U89,U91

4

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

2

Block Diagram

MS-9184

0AA3

292Monday, August 28, 2006

1

5

D D

+5VSB +3.3VSB

C C

+3.3VSB

U84

C932

C932 X_0.1u_16V

X_0.1u_16V

C966

0.1u_16V

+3.3V +2.5VPLL_0

VIN3VOUT

ADJ

1

APL1084UC_TO252

C919

X_0.1u_16V

+2.5VPLL

VR4

B B

DDR_POWR_GD<15,16,17,18,56>

C533

C533 10u_10V-1206

10u_10V-1206

1

EN

2

IN

5

GND

6

GND

L6932D2.5

OUT GND

GND

PG

2

3 4 7 8

4

R879

R879 200R1%

200R1%

R875

R875 332R1%

332R1%

CPU 0/3: 300mA Totally 600mA

C554

C553

0.1u_16V

C925

0.1u_16V

5000mA

C935

C560

22uF_10V

22u_16V-1210

C559

22u_16V-1210

3

R639

4.7K

G

DS

Q18

ATX_PWR_OK<5,62,66,82>

ATX_PWR_OK

G

2N7002

R808

4.7K

G

DS

Q25

G

2N7002

+12V +3.3VSB+5VSB

+12V +5VSB+5VSB

R628

4.7K

DS

Q16

2N7002

R809

4.7K

DS

Q26

2N7002

2

Q15

SOT23SGD_TQ15

G

P-CH

G

N-CH

Q27

G

P-CH

+3.3V

SOT23SGD_T

P-SI2305DS_SOT23

SOT-23

D S

DS

Q17

Q17 IPD06N03LA/TO252

IPD06N03LA/TO252

TO-252

SOT23SGD_TQ27

SOT23SGD_T

P-SI2305DS_SOT23

SOT-23

D S

AC

D21

D21 RB1602

RB1602

+

1000u_6.3V

AC

D12

D12 RB1602

RB1602

EC5

+3.3VDUAL

+5VDUAL

1

C663

C663 1u_10V

1u_10V

3A

8A

G

N-CH

DS

Q28

Q28 IPD06N03LA/TO252

IPD06N03LA/TO252

TO-252

+

1000u_6.3V

EC10

C138

C138 1u_10V

1u_10V

+5V

CPU 1/2: 300mA

+3.3V +2.5VPLL_1

Totally 600mA

+2.5VPLL

VR3

DDR_POWR_GD

A A

5

C480

C480 10u_10V-1206

10u_10V-1206

VR3

1

EN

2

IN

5

GND

6

GND

L6932D2.5

OUT GND

GND

3 4

PG

7 8

4

C487

0.1u_16V

C486

0.1u_16V

C492

22uF_10V

C491

22u_16V-1210

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

3

2

Date: Sheet

Main Power

MS-9184

0AB

392Tuesday, September 05, 2006

of

1

of

5

4

3

2

1

1.5V 10 A Tranisent Voltage 1.5 V+/-5%

CHOCK0

+5V

C683

4.7u_6.3V-0805

D D

R662

R662 22K

22K

7

6

Vref = 0.8V P1V5 = 1.5097V

C681

C681 22p_50V

22p_50V C682

C682 3300p/50V

C C

+1.2V_HT

C493

C482

HT_VLD<56,62>

C482

10u_0805

0.1u_25V

R455 10KR455 10K

HT_VLD

B B

+3.3VDUAL

HTVDD_EN<56,62>

07.17 Joe, Need to fine-tune to meet 1.2V

07.25 33K CHANGE TO 30K, meet 1.2V spec

A A

C485

C494

0.1u_25V

10u_0805

R451 1K-0402R451 1K-0402

5

R437

R437 10R

10R

C540

0.1u_25V

R457 10KR457 10K R477 30KRSTR477 30KRST R447 43.2KRSTR447 43.2KRST

3300p/50V

MASTER

+5V +5V

U35

A1

VDD

A2

VDD

A3

VDD

C1

VDD

C2

VDD

C3

VDD

E1

VDD

E2

VDD

E3

VDD

G1

VDD

G2

VDD

G3

VDD

H1

AVDD

J1

STAT

K1

EN

K7

IMAX

K6

IRIPL

J7

BIAS

A4

GND

A5

GND

A6

GND

A7

GND

C4

GND

C5

GND

C6

GND

C7

GND

E4

GND

E5

GND

E6

GND

E7

GND

G4

GND

G5

GND

G6

GND

G7

GND

VT225

COMP

FB

R660 22KR660 22K

VFB

VDES

PGIN

VREF

AGND AGND AGND

5

VCC

GND

3

VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX

A C

D23

D23 1N5817S

1N5817S

UGATE

BOOT

PHASE LGATE

U62

U62 ISL6520A

ISL6520A

B1 B2 B3 B4 B5 B6 B7 D1 D2 D3 D4 D5 D6 D7 F1 F2 F3 F4 F5 F6 F7

K4 K3

K5 K2

H5 H6 H7

R453

R453 100K

100K

2 1

8 4

R1081

2.2R-0805

2.2R-0805 C700

C700 1u_10V

1u_10V

CHOK2 200nHCHOK2 200nH

1.2V_HT_VDES

R506

C565

42.2K

100p

4

CHOCK0

C686

CH-1.2U8A

1u_16V

Q20

Q20 AO4410

AO4410

4 5 3 2

Q19

AO4410

4 5 3 2

SB : 0.6A CPU 0: 3A CPU 1/2/3: 3A HTX: 1A Totally 14A

+1.2V_HT

C539

C539 22u/6.3V/8

22u/6.3V/8

C548

C550

1000p50VC3KX7R

0.01u

6 7 81

1000p50VC3KX7R

C545

C483

22u/6.3V/8

R541 0R541 0 R540 0R540 0

R493 220RR493 220R

R494 10KR494 10K

C549

C549 220P_50V_NPO

220P_50V_NPO

R666

2.2R-0805

C699

C495

C495 22u/6.3V/8

22u/6.3V/8

C708

C708 10u6.3V_X5R

10u6.3V_X5R C714

C714 10u6.3V_X5R

10u6.3V_X5R

+

1 2

CHOCK1

2.2uH

C503

C563

22u/6.3V/8

1.2V_HT_SENSE+

1.2V_HT_SENSE-

TC7

620u6.3V_OS

C528

C566

22u/6.3V/8

R659

1.1KR

R658

1.24K_1%

3

1 2 1 2

+1.4VDUAL

+

820u2.5V_OS

+

820u2.5V_OS

+1.5V

TC5

TC5 TC6

TC6

10u_10V-1206

C577

C597

C597 10u_0805

10u_0805

C577

0.1u_25V

C616

0.1u_25V

C598

C598 10u_0805

10u_0805

C584

0.1u_25V

HT_VLD

HTVDD_EN

R573 8.45KRSTR573 8.45KRST R584 30KRSTR584 30KRST

+1.4V

+1.5V

R726

68R

1.5KR

R729

+12V

3

+

2

-

4 8

1

U70A

LM358DR2G_SOIC8

+1.5V

C729

47p_50V

D

Q21

FDD6676/TO252

G

S

C815

C815 102p_50V

102p_50V

+1.4V

+1.4VDUAL For MCP55

+3.3VDUAL +1.4VDUAL

VR6

R566

R566 10R

10R

C723

1

EN IN2ADJ

5

GND

6

GND

L6932D1.2_SO8

SLAVE

U49

A1

VDD

A2

VDD

A3

VDD

C1

VDD

C2

VDD

C3

VDD

E1

VDD

E2

VDD

E3

VDD

G1

VDD

G2

VDD

G3

VDD

H1

AVDD

J1

STAT

K1

EN

K7

IMAX

K6

IRIPL

J7

BIAS

A4

GND

A5

GND

A6

GND

A7

GND

C4

GND

C5

GND

C6

GND

C7

GND

E4

GND

E5

GND

E6

GND

E7

GND

G4

GND

G5

GND

G6

GND

G7

GND

2

VT225

OUT GND

GND

VFB

VDES

PGIN

VREF

AGND AGND AGND

4 3

R673 18R673 18

7 8

R672

100

B1

VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX VX

CHOK5 200nHCHOK5 200nH

B2 B3 B4 B5 B6 B7 D1 D2 D3 D4 D5 D6 D7 F1 F2 F3 F4 F5 F6 F7

K4

1.2V_HT_VDES

K3

K5 K2

H5 H6 H7

Title

Size Document Number Rev

Date: Sheet

R583 220RR583 220R

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

C704

0.1u_16V

+1.2V_HT

C637

C637 220P_50V_NPO

220P_50V_NPO

1.2V Power

C703

0.1u_16V

C569

C569 22u/6.3V/8

22u/6.3V/8

1.2V_HT_SENSE+

1.2V_HT_SENSE-

MS-9184

EC8

+

1000u_6.3V

C724

C724 22u_16V-1210

22u_16V-1210

C583

C583 22u/6.3V/8

22u/6.3V/8

1

0ACustom

of

492Thursday, August 31, 2006

5

4

3

2

1

+5VSB

D D

PS_ONJ<75>

C C

JPWR2

1

GND

2

GND

3

GND GND4+12V

POWERCONN2X4

B B

R944 4.7K_0402R944 4.7K_0402

+12V +12V +12V

8 7 6 5

C927

C927 X_103P

X_103P

+3.3VDUAL

R948

4.7K

B

C959

C959 X_103P

X_103P

R970

R970 X_10K

X_10K

Q32

Q32 X_N-MMBT3904_SOT23

X_N-MMBT3904_SOT23

E C

R969 0R969 0

+

EC11

EC11 1000u/16V

1000u/16V

+3.3V

0.1u_0402/16V

C1014

0.1u_16V

EC14

+

1000u/16V

C971

C10151nC1015 1n

+5V

12VP0_IN 12VP3_IN

-12V

C10131nC1013 1n

C1010

0.1u_0402/16V

Power Connector

13

3.3V

14

-12V

15

GND4

16

PS_ON

17

GND5

18

GND6

19

GND7

20

3VSBY

21

5V

22

5V

23

5V

24

GND8

POWERCONN2X12

+12V

JPWR3

PWROK

5VSBY

+12V_IN

GND1 GND2 GND3

1

3.3V

2

3.3V

3 4

5V

5 6

+5V

7 8 9 10

12V

11

12V

12

3.3V

C972

0.1u_0402/16V

TOP_ATXPWOK<56>

ATXPWOK

+

EC15

EC15 1000u/16V

1000u/16V

3

4

+5VSB

C1012

0.1u_0402/16V

C970

0.1u_0402/16V

R305 0R305 0

JPWR0

GND

12V

GND

12V

Power Con 2*2

+3.3V

C975

0.1u_0402/16V

C1011

0.1u_0402/16V

+3.3V

1

2

+5V

0.1u_0402/16V

C974

+5V

R943

R943 10K

10K

CE

Q31

Q31 N-MMBT3904_SOT23

N-MMBT3904_SOT23

B

R928

R928 10K

10K

+3.3V

R929

R929 10K

10K

ATX_PWR_OK <3,62,66,82>

JPWR1

1

GND

2

GND

3

GND GND4+12V

POWERCONN2X4

A A

5

+12V +12V +12V

8 7 6 5

C957

C957 X_103P

X_103P

C977

C977 X_103P

X_103P

EC12

+

1000u/16V

12VP2_IN 12VP1_IN

EC13

+

1000u/16V

4

3

+5V

+12V_LD

JPWR4

4

12V

3

GND

2

GND

1

5V

D1x4

12V Aux power (Close to JPWR1)

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

FRONT PANEL

MS-9184

1

0AB

592Tuesday, September 05, 2006

of

5

4

3

2

1

EMI

+3.3V

D D

+3.3V

R529

R519

R519 130R

C1156

C1156 103P

103P

C1162

C1162 103P

103P

130R

R51882R518 82

C1158

C1158 103P

103P

SB_CLK0_P0<57>

C C

B B

SB_CLK0_N0<57>

R691 80.6_1%R691 80.6_1%

R690 178_1%R690 178_1%

R686 80.6_1%R686 80.6_1% C593 3900p_50VC593 3900p_50V

+3.3V

FB18 120ohm-500mAFB18 120ohm-500mA

SB_CLK0_P0_BUFF

SB_CLK0_N0_BUFF

C1168

C1166

103P

C1171

C1167

103P

R469 10RR469 10R

C581 3900p_50VC581 3900p_50V

C1172

C1172 103P

103P

C1157

C1157 103P

103P

R529 130R

130R

R53082R530 82

C1160

C1160 103P

103P

+3.3V

C1173

C1173 103P

103P

R470 1KR470 1K

R553 1KR553 1K R496 1KR496 1K

R484 1KR484 1K

C1163

C1163 103P

103P

C561

C561 103P

103P

31

32 24

16 17 25 30

C562

C562 103P

103P

3 4

5 6

7 2

1 8

9

U42

PLL_SEL CLK0

nCLK0 CLK1

nCLK1 CLK_SEL SEL1

SEL0 MR VCC#32

VCC#9 VCCO#24 VCCO#16 VCCO#17 VCCO#25 VCCA

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

FB_IN

nFB_IN

VEE#2929VEE#1313VEE#2828VEE#12

12

ICS8634BY-01_LQFP32

15 14

19 18

21 20

23 22

27 26

11 10

P0_CPUCLKIN P0_CPUCLKINJ

P1_CPUCLKIN P1_CPUCLKINJ

P2_CPUCLKIN P2_CPUCLKINJ

P3_CPUCLKIN P3_CPUCLKINJ

R468

49.9_1%

R467

49.9_1%

R466

49.9_1%

P0_CPUCLKIN <21> P0_CPUCLKINJ <21>

P1_CPUCLKIN <30> P1_CPUCLKINJ <30>

P2_CPUCLKIN <39> P2_CPUCLKINJ <39>

P3_CPUCLKIN <48> P3_CPUCLKINJ <48>

C1159

X_0.1u_16V

P0_CPUCLKIN P0_CPUCLKINJ

P1_CPUCLKIN P1_CPUCLKINJ

P2_CPUCLKIN P2_CPUCLKINJ

P3_CPUCLKIN P3_CPUCLKINJ

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

R568 180R568 180 R567 180R567 180

R544 180R544 180 R552 180R552 180

R522 180R522 180 R526 180R526 180

R507 180R507 180 R512 180R512 180

Clock Synthesizer

MS-9184

1

0AB

692Thursday, August 31, 2006

of

5

4

3

2

1

+3.3V +3.3V

U81

CPU0POWER_EN

P0_VID7<83> P0_VID6<83>

P0R_SEL7 P0R_SEL6 P0R_SEL5 P0R_SEL4 P0R_SEL3 P0R_SEL2 P0R_SEL1 P0R_SEL0 P0R_FREQ P0R_REF

P0_VID5<21,83> P0_VID4<21,83> P0_VID3<21,83> P0_VID2<21,83> P0_VID1<21,83> P0_VID0<21,83>

R839

R839 499_1%

499_1%

R838

1.96K

R871 5.9KST-0402R871 5.9KST-0402 R898 1.02K_0402R898 1.02K_0402 R904 340RSTR904 340RST R903 31.6KR1%R903 31.6KR1% R896 8.66KST-0402R896 8.66KST-0402 R902 11.3KR902 11.3K

R870 340RSTR870 340RST R895 26.1K-0402R895 26.1K-0402 R897 11KST-0402R897 11KST-0402

D D

R840

X_249R

C881

X_680P

C887

C887 X_103P

X_103P

X_680P

R825

R825 825R

825R

C886

C886 3300p/50V

3300p/50V

C C

B B

P0_VID7 P0_VID6 P0_VID5 P0_VID4 P0_VID3 P0_VID2 P0_VID1 P0_VID0

4.7u_6.3V-0805C924 4.7u_6.3V-0805C924

P0OVP+ P0OVPP0OVP_OUT P0R_FREQ

6800PC889 6800PC889

P0SENSE+ P0SENSE-

P0VR_HOT P0VR_FAN P0FAULTB

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

+3.3V

OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVPOVP_out Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB

VT1115M

U81

EXT_REF

R_sel<7> R_sel<6> R_sel<5> R_sel<4>

R_sel<3> R_sel<2>

Load_Current

R_sel<1>

R_sel<0>

G

49

VDD

SC SD

GND

R_ref

Pwrgd R_freq Vin_ov Vin_uv

Ides_n Ides_p

DBO

DBI

sphase

36 47 46 45 44 43 42 41 40 39 38 37 48 35 34 33 32 31 30 29 28 27 26 25

R_SEL0 =340ohm SMBUS = E0h

R862 4.7KR862 4.7K R867 4.7KR867 4.7K

P0_VID7 P0_VID6

MASTER Reported Faults

R860

10K-0402

10K-0402R894 5.11K-0402R894 5.11K-0402

P0FAULTB

P0OVP_OUT

P0VR_FAN P0VR_HOT

SMB_5_CLK <9,11,13,15,16,17,18,78>

P0R_SEL7 P0R_SEL6 P0R_SEL5 P0R_SEL4

P0R_REF P0R_SEL3 P0R_SEL2

P0VIN_OV P0VIN_UV

P0R_SEL1

P0R_SEL0

10K-0402

SMB_5_DATA <9,11,13,15,16,17,18,78>

R899 10KR899 10K R893 0_0402R893 0_0402

R892 0_0402R892 0_0402 R873 0_0402R873 0_0402

R891 0_0402R891 0_0402 R877 0_0402R877 0_0402

P0VIN_OV P0VIN_UV

R919

10.7KR

C934

0.1u_16V

R822

10K-0402

R918

R918 100K

100K

R857

+5V

R905

R905 10K

10K

C923

C923 1u_10V

1u_10V

P0IDES_N P0IDES_P

P0DBI P0DBO P0SPHASE

12VP0_IN

R864

10K-0402

P0_VCORE P3_VCORE

CPU0POWER_GD <9>

P0IDES_N <8> P0IDES_P <8>

P0DBI <8> P0DBO <8> P0SPHASE <8>

R917

63.4k 1%

R916

R916 10K

10K

+3.3V

C933

0.1u_16V

L13

1

50nH

2 3

50nH

4 5

50nH50nH

6 7

8

INDUCTOR_4_PHASE_8pin

P0_VX1 <8>

P0_VCORE

P0_VX2 <8>

P0_VCORE

P0_VX3 <8>

P0_VCORE

P0_VX4 <8>

P0_VCORE

Slave

10K-0402

Faults

P0Slave1_FAULTB<8> P0Slave2_FAULTB<8> P0Slave3_FAULTB<8> P0Slave4_FAULTB<8>

10K-0402

P0Slave1_FAULTB P0Slave2_FAULTB P0Slave3_FAULTB P0Slave4_FAULTB

P0_VCORE_FB_N<21> P0_VCORE_FB_P<21>

P0_VCORE

R1116

56_0603

56_0603 R8420R842

0

47u_6.3V_1206C1316 47u_6.3V_1206C1316 47u_6.3V_1206C1315 47u_6.3V_1206C1315 47u_6.3V_1206C876 47u_6.3V_1206C876 47u_6.3V_1206C877 47u_6.3V_1206C877

47u_6.3V_1206C1317 47u_6.3V_1206C1317 47u_6.3V_1206C1318 47u_6.3V_1206C1318 47u_6.3V_1206C893 47u_6.3V_1206C893 47u_6.3V_1206C911 47u_6.3V_1206C911

22u_6.3V_1206C909 22u_6.3V_1206C909 22u_6.3V_1206C890 22u_6.3V_1206C890 22u_6.3V_1206C891 22u_6.3V_1206C891 22u_6.3V_1206C908 22u_6.3V_1206C908

R827

R827 0_0402

0_0402

P0SENSE+

P0OVP+

R805 100/1206R805 100/1206

R826

R826 0_0402

0_0402

P0SENSE-

P0OVP-

47u_6.3V_1206C910 47u_6.3V_1206C910 47u_6.3V_1206C892 47u_6.3V_1206C892 47u_6.3V_1206C885 47u_6.3V_1206C885 47u_6.3V_1206C1320 47u_6.3V_1206C1320

47u_6.3V_1206C1272 47u_6.3V_1206C1272 47u_6.3V_1206C912 47u_6.3V_1206C912 47u_6.3V_1206C874 47u_6.3V_1206C874 47u_6.3V_1206C875 47u_6.3V_1206C875

R1115

56_0603

56_0603 R8410R841

0

10/4 Joe, 47uF x4 pcs per phase by Voltera recommend

R1137

R1133

10K-0402

R1134

10K-0402

+3.3V

R1135

10K-0402

+3.3V

Near U10 for EMI

R806

4.7K

VCORE_EN<9,11,13,56,62>

VCC

+5V+5V

5

CPU0POWER_EN

4

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

CPU0_VT1115M

MS-9184

1

0ACustom

792Monday, September 04, 2006

of

U79

R816

R816 10K

10K

DS

Q24

Q24 2N7002

G

2N7002

1 2 3

GND

NC7S08

3

Configuration Resistors,Rref

+5V

A A

H0_PRESENT_N<15,21,62>

5

4

5

4

3

2

1

P0SPHASE

H1

H2

DBO

SPHASE

R936

R936 0_0402

0_0402

P0_VX1_DBI

C2

G2

B1

D1

DBI

IDESP

IDESN

FAULTB

VT1135S

P0DBI

P0IDES_P P0IDES_N

C0_BST1

A3

VX

BST

VX VX VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C9631uC963

1uC955 1uC955

1u

P0DB3

D D

R966

1K_0402

12VP0_IN 12VP0_IN

C9831uC983

1u

C9911uC991

1u

C1005

10u_16V_1206

C C

10u_16V_1206

C1006

10u_16V_1206

R956

R956 0_0402

0_0402

C0_DBO2

SPHASE0_VT2

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

R1143 X_0R1143 X_0

U91

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R941

R941 0_0402

0_0402

P0_VX2_DBI

C2

G2

B1

D1

DBI

IDESP

IDESN

VT1135S

P0IDES_P P0IDES_N P0Slave2_FAULTB

C0_BST2

A3

A4

VX

A6

BST

VX

B4

VX

FAULTB

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C9541uC954

R962

1uC953 1uC953

P0_VX2

C9651uC965

1u

R962

P0_VX2 <7>

C9821uC982

1u

C9901uC990

1u

C1003

10u_16V_1206

C1004

10u_16V_1206

1K_0402

R1141 X_0R1141 X_0

R950

R950 0_0402

0_0402

C0_DBO1 P0Slave1_FAULTB

SPHASE0_VT1

U92

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

Input Cap. totally 1u/0603x3, 10u/16Vx2 each phase

P0SPHASE

R935

R935 0_0402

0_0402

P0_VX3_DBI

H1

G2

D1

DBI

DBO

IDESP

P0DB3

P0IDES_N

P0Slave3_FAULTB

C0_BST3

C2

B1

A3

VX

BST

VX

IDESN

VX

FAULTB

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

VT1135S

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C9491uC949

1uC948 1uC948

P0_VX3

1u

P0DBO<7>

R965

1K_0402

B B

12VP0_IN 12VP0_IN

C9851uC985

1u

C9931uC993

1u

C1009

10u_16V_1206

C1002

10u_16V_1206

R954 X_0R954 X_0

R955

R955 0_0402

0_0402

C0_DBO4

SPHASE0_VT4

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

U89

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

SPHASE

R940

P0IDES_P P0IDES_P

0_0402

P0_VX4_DBI

C2

G2

D1

DBI

DBO

IDESP

P0IDES_N

P0Slave4_FAULTB

C0_BST4

B1

A3

VX

BST

VX

IDESN

VX

FAULTB

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

VT1135S

P0IDES_P <7> P0IDES_N <7>

1uC950 1uC950

P0_VX4

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6

+3.3V +3.3V

F4 F6 F1 E2 A1 B2 A2

C9641uC964

C9521uC952

1u

R961

1K_0402

P0_VX4 <7> P0_VX3 <7>

C9841uC984

1u

C9921uC992

1u

C1007

10u_16V_1206

C1008

10u_16V_1206

R1142 X_0R1142 X_0

R949

R949 0_0402

0_0402

C0_DBO3

SPHASE0_VT3

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

H2

U90

VSS VSS VSS

SPHASE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

P0_VX1

+3.3V+3.3V

C9691uC969 1u

P0SPHASE <7> P0DBI <7>

P0_VX1 <7>

C9511uC951 1u

REMOVE BYPASS R

P0Slave1_FAULTB P0Slave2_FAULTB P0Slave3_FAULTB P0Slave4_FAULTB

P0Slave1_FAULTB <7> P0Slave2_FAULTB <7> P0Slave3_FAULTB <7> P0Slave4_FAULTB <7>

HS8

112

334

2

VRD_HEATSINK_4 Phase

4

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU0_VT1135S

MS-9184

1

0ACustom

of

892Monday, September 04, 2006

5

4

3

2

1

+3.3V

U80

CPU1POWER_EN

P1_VID7

P1_VID7<83>

D D

R830

X_249R

C873

C883

C883 X_103P

X_103P

C873

X_680P

R812

R812 825R

825R

C882

C882 3300p/50V

C C

R829

R829 499_1%

499_1%

R828

1.96K

P1_VID6

P1_VID6<83>

P1_VID5

P1_VID5<30,83>

P1_VID4

P1_VID4<30,83>

P1_VID3

P1_VID3<30,83>

P1_VID2

P1_VID2<30,83>

P1_VID1

P1_VID1<30,83>

P1_VID0

P1_VID0<30,83>

4.7u_6.3V-0805C922 4.7u_6.3V-0805C922

P1OVP+ P1OVPP1OVP_OUT

6800PC884 6800PC884

P1SENSE+ P1SENSE-

P1VR_HOT P1VR_FAN P1FAULTB

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

U80

OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVPOVP_out Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB

VT1115M

EXT_REF

R_sel<7> R_sel<6> R_sel<5> R_sel<4>

R_sel<3> R_sel<2>

Load_Current

R_sel<1>

R_sel<0>

G

49

R_SEL0 =1.02K SMBUS = E2h

MASTER

P1R_SEL7

R865 5.9KST-0402R865 5.9KST-0402

P1R_SEL6

R876 1.02K_0402R876 1.02K_0402

P1R_SEL5

R890 340RSTR890 340RST

P1R_SEL4

B B

P1R_SEL3 P1R_SEL2 P1R_SEL1 P1R_SEL0 P1R_FREQ P1R_REF

R889 31.6KR1%R889 31.6KR1% R884 8.66KST-0402R884 8.66KST-0402 R888 11.3KR888 11.3K R882 5.11K-0402R882 5.11K-0402 R886 1.02KSTR886 1.02KST R883 26.1K-0402R883 26.1K-0402 R885 11KST-0402R885 11KST-0402

Reported Faults

P1FAULTB P1OVP_OUT

P1VR_FAN P1VR_HOT

Configuration Resistors,Rref

U83

A A

CPU0POWER_GD<7>

CPU1POWER_GD

5

1 2 3

U83

GND

NC7S32

VCC

+3.3V

5 4

P0_P1_POWER_GD <11>

VDD

SC SD

GND

R_ref

Pwrgd R_freq Vin_ov Vin_uv

Ides_n Ides_p

DBO

DBI

sphase

R855

10K-0402

4

+3.3V

36 47 46 45

P1R_SEL7

44

P1R_SEL6

43

P1R_SEL5

42

P1R_SEL4

41 40

P1R_REF

39

P1R_SEL3

38

P1R_SEL2

37 48

P1R_FREQ

35

P1VIN_OV

34

P1VIN_UV

33 32

P1R_SEL1

31 30 29

P1R_SEL0

28 27 26 25

+3.3V

R815

10K-0402

SMB_5_CLK <7,11,13,15,16,17,18,78> SMB_5_DATA <7,11,13,15,16,17,18,78>

R887 10KR887 10K R881 0_0402R881 0_0402

R866 0_0402R866 0_0402 R872 0_0402R872 0_0402 R868 0_0402R868 0_0402

R856 4.7KR856 4.7K R861 4.7KR861 4.7K

10K-0402

H1_PRESENT_N<16,30,62>

R858

P1_VID7 P1_VID6

10K-0402

+5V

P1IDES_N P1IDES_P

P1DBI P1DBO P1SPHASE

+3.3V

R863

+5V

R801

R869

R869 10K

10K

CPU1POWER_GD

1u_10V

1u_10V C917

C917

P1IDES_N <10> P1IDES_P <10>

P1DBI <10> P1DBO <10> P1SPHASE <10>

4.7K

G

P1VIN_OV

C931

0.1u_16V

+5V

R807

R807 10K

10K

DS

VCORE_EN<7,11,13,56,62>

Q23

Q23 2N7002

2N7002

3

P1_VCORE P2_VCORE

L12

1

50nH

2 3

50nH

4 5

50nH50nH

6 7

8

INDUCTOR_4_PHASE_8pin

12VP1_IN

R909

R908

100K

63.4k 1%

P1VIN_UV

R910

10.7KR

R907

R907 10K

10K

C930

0.1u_16V

U78

1 2 3

GND

NC7S08

P1_VX2 <10>

P1_VCORE

P1_VX1 <10>

P1_VCORE

P1_VX3 <10>

P1_VCORE

P1_VX4 <10>

P1_VCORE

+5V

VCC

5

CPU1POWER_EN

4

+3.3V

Near U29 for EMI

2

P1_VCORE_FB_N<30> P1_VCORE_FB_P<30>

P1_VCORE

R1090

P1SENSE+ P1SENSE-

56_0603

56_0603 R8320R832

P1OVP+ P1OVP-

0

47u_6.3V_1206C906 47u_6.3V_1206C906 47u_6.3V_1206C900 47u_6.3V_1206C900 47u_6.3V_1206C904 47u_6.3V_1206C904 47u_6.3V_1206C905 47u_6.3V_1206C905

47u_6.3V_1206C902 47u_6.3V_1206C902 47u_6.3V_1206C901 47u_6.3V_1206C901 47u_6.3V_1206C899 47u_6.3V_1206C899 47u_6.3V_1206C1308 47u_6.3V_1206C1308

22u_6.3V_1206C1311 22u_6.3V_1206C1311 22u_6.3V_1206C903 22u_6.3V_1206C903 22u_6.3V_1206C879 22u_6.3V_1206C8793300p/50V 22u_6.3V_1206C898 22u_6.3V_1206C898

R817

R818

0_0402

R803 100/1206R803 100/1206

R1089

56_0603

56_0603 R8310R831

0

47u_6.3V_1206C894 47u_6.3V_1206C894R880 0_0402R880 0_0402 47u_6.3V_1206C895 47u_6.3V_1206C895 47u_6.3V_1206C1266 47u_6.3V_1206C1266 47u_6.3V_1206C1310 47u_6.3V_1206C1310

47u_6.3V_1206C1309 47u_6.3V_1206C1309 47u_6.3V_1206C1307 47u_6.3V_1206C1307 47u_6.3V_1206C1313 47u_6.3V_1206C1313 47u_6.3V_1206C1312 47u_6.3V_1206C1312

10/4 Joe, 47uF x4 pcs per phase by Voltera recommend

Slave

R1130

R1136

R1131

Faults

P1Slave1_FAULTB<10> P1Slave2_FAULTB<10> P1Slave3_FAULTB<10> P1Slave4_FAULTB<10>

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

10K-0402

P1Slave1_FAULTB P1Slave2_FAULTB P1Slave3_FAULTB P1Slave4_FAULTB

10K-0402

CPU3_VT1115M

10K-0402

MS-9184

1

R1131

10K-0402

992Thursday, August 31, 2006

+3.3V

R1132

0ACustom

of

5

P1DB3

D D

SPHASE1_VT2

R960

1K_0402

12VP1_IN 12VP1_IN

C9811uC981

1u

C9891uC989

C C

1u

C994

10u_16V_1206

C998

10u_16V_1206

R1138 X_0R1138 X_0

R947

R947 0_0402

0_0402

C1_DBO2

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7

F5

F7 B3 C3 D3 E3

F3

U88

4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

SPHASE

3

R1140 X_0R1140 X_0

R953

R934

R934 0_0402

0_0402

P1IDES_P

P1_VX2_DBI

P1IDES_N P1Slave2_FAULTB

1uC947 1uC947

C1_BST2 C1_BST1

BST

GND GND VDD VDD VCC

P1_VX2

A4

VX

A6

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1 E2 A1 B2 A2

C9461uC946

C9621uC962 1u

1u

DBO

G2

A3

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135S

C9801uC980

1u

C9881uC988

1u

C996

10u_16V_1206

C1000

10u_16V_1206

R964

R953 0_0402

0_0402

C1_DBO1 P1Slave1_FAULTB

SPHASE1_VT1

1K_0402

U87

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

H1

H2

DBO

SPHASE

R939

R939 0_0402

0_0402

P1IDES_P

P1_VX1_DBI

P1IDES_N

G2

D1

C2

B1

DBI

IDESP

IDESN

VT1135S

A3

VX

BST

VX VX

FAULTB

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C9441uC944

1uC945 1uC945

1u

P1_VX1

+3.3V+3.3V

P1SPHASE <9> P1DBI <9>

REMOVE BYPASS R

P1_VX1 <9>P1_VX2 <9>

C9611uC961 1u

2

HS2

VRD_HEATSINK_2 Phase

1

112

334

2

4

Input Cap. totally 1u/0603x3, 10u/16Vx2 each phase

P1SPHASE

P1DB3

P1IDES_P

P1IDES_N

P1Slave3_FAULTB

1uC940 1uC940

C1_BST3

A3

A4

VX

A6

BST

VX

B4

VX

B6

FAULTB

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C9601uC960

1u

P1_VX3

REMOVE BYPASS R

P1_VX3 <9>

C9431uC943 1u

2

R946

R946 0_0402

0_0402

1K_0402

R1139 X_0R1139 X_0

C1_DBO3 SPHASE1_VT3

A5 A7 B5

B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

3

U86

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R933

R933 0_0402

0_0402

P1_VX3_DBI

G2

D1

C2

B1

DBI

IDESP

IDESN

VT1135S

P1DBO<9>

B B

A A

5

C9861uC986

1u

C9781uC978

1u

C995

10u_16V_1206

C997

10u_16V_1206

R963

1K_0402

12VP1_IN 12VP1_IN

R951 X_0R951 X_0

R952

R952 0_0402

0_0402

C1_DBO4

SPHASE1_VT4

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

R938

R938 0_0402

0_0402

P1IDES_P P1IDES_N

P1_VX4_DBI

P1Slave4_FAULTB

C1_BST4

G2

A3

H1

D1

C2

B1

H2

U85

VSS VSS VSS

SPHASE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

4

DBO

DBI

IDESP

IDESN

FAULTB

VT1135S

BST

GND GND VDD VDD VCC

VX VX VX VX VX VX VX VX VX VX VX VX

P1IDES_P <9> P1IDES_N <9>

1uC942 1uC942

P1_VX4

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6

+3.3V +3.3V

F4 F6 F1 E2 A1 B2 A2

C9681uC968

C9411uC941 1u

1u

R959

P1_VX4 <9>

C9871uC987

1u

C9791uC979

1u

C999

10u_16V_1206

C1001

10u_16V_1206

P1Slave1_FAULTB P1Slave2_FAULTB P1Slave3_FAULTB P1Slave4_FAULTB

P1Slave1_FAULTB <9> P1Slave2_FAULTB <9> P1Slave3_FAULTB <9> P1Slave4_FAULTB <9>

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

CPU3_VT1135S

MS-9184

1

of

10 92Monday, September 04, 2006

0ACustom

5

4

3

2

1

+3.3V

U18

CPU2POWER_EN

P2_VID7

P2_VID7<84>

D D

R260

X_249R

C212

C203

C203 X_103P

X_103P

C212

X_680P

R272

R272 825R

825R

C204

C204 3300p/50V

3300p/50V

C C

R261

R261 499_1%

499_1%

R262

1.96K

P2_VID6

P2_VID6<84>

P2_VID5

P2_VID5<39,84>

P2_VID4

P2_VID4<39,84>

P2_VID3

P2_VID3<39,84>

P2_VID2

P2_VID2<39,84>

P2_VID1

P2_VID1<39,84>

P2_VID0

P2_VID0<39,84>

4.7u_6.3V-0805C145 4.7u_6.3V-0805C145

P2OVP+ P2OVPP2OVP_OUT

6800PC201 6800PC201

P2SENSE+ P2SENSE-

P2VR_HOT P2VR_FAN P2FAULTB

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

R_SEL0 =1.74K SMBUS = E4h

OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVPOVP_out Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB

VT1115M

U18

EXT_REF

R_sel<7> R_sel<6> R_sel<5> R_sel<4>

R_sel<3> R_sel<2>

Load_Current

R_sel<1>

R_sel<0>

G

49

MASTER

P2R_SEL7

R185 5.9KST-0402R185 5.9KST-0402

P2R_SEL6

R156 1.02K_0402R156 1.02K_0402

P2R_SEL5

R179 340RSTR179 340RST

P2R_SEL4

B B

P2R_SEL3 P2R_SEL2 P2R_SEL1 P2R_SEL0 P2R_FREQ P2R_REF

R135 31.6KR1%R135 31.6KR1% R157 8.66KST-0402R157 8.66KST-0402 R174 11.3KR174 11.3K R188 5.11K-0402R188 5.11K-0402 R223 1.74KR1%0402R223 1.74KR1%0402 R187 26.1K-0402R187 26.1K-0402 R186 11KST-0402R186 11KST-0402

Reported Faults

P2FAULTB P2OVP_OUT

P2VR_FAN P2VR_HOT

Configuration Resistors,Rref

U16

A A

P0_P1_POWER_GD<9>

CPU2POWER_GD

5

1 2 3

U16

GND

NC7S32

VCC

+3.3V

5 4

P1_P2_POWER_GD <13>

VDD

SC SD

GND

R_ref

Pwrgd R_freq Vin_ov Vin_uv

Ides_n Ides_p

DBO

DBI

sphase

R244

10K-0402

4

+3.3V

36 47 46 45

P2R_SEL7

44

P2R_SEL6

43

P2R_SEL5

42

P2R_SEL4

41 40

P2R_REF

39

P2R_SEL3

38

P2R_SEL2

37 48

P2R_FREQ

35

P2VIN_OV

34

P2VIN_UV

33 32

P2R_SEL1

31 30 29

P2R_SEL0

28 27 26 25

+3.3V

R269

10K-0402

SMB_5_CLK <7,9,13,15,16,17,18,78> SMB_5_DATA <7,9,13,15,16,17,18,78>

R180 10KR180 10K R189 0_0402R189 0_0402

R190 0_0402R190 0_0402 R210 0_0402R210 0_0402

R205 0_0402R205 0_0402 R199 0_0402R199 0_0402

R245 4.7KR245 4.7K R235 4.7KR235 4.7K

R237

10K-0402

P2IDES_N P2IDES_P

P2DBI P2DBO P2SPHASE

P2_VID7 P2_VID6

R232

10K-0402

+5V

+3.3V

R226

R226 10K

10K

CPU2POWER_GD

1u_10V

1u_10V C178

C178

P2IDES_N <12> P2IDES_P <12>

P2DBI <12> P2DBO <12> P2SPHASE <12>

P2VIN_OV

C131

0.1u_16V

R130

R130 100K

100K

R131

10.7KR

L4

INDUCTOR_4_PHASE_8pin

12VP2_IN

R133

63.4k 1%

R132

R132 10K

10K

1

50nH

2 3

50nH

4 5

50nH50nH

6 7

8

P2VIN_UV

C132

0.1u_16V

P2_VX2 <12>

P2_VCORE

P2_VX1 <12>

P2_VCORE

P2_VX3 <12>

P2_VCORE

P2_VX4 <12>

P2_VCORE

Near U29 for EMI

+3.3V

P2_VCORE_FB_N<39> P2_VCORE_FB_P<39>

P2_VCORE

R989

P2SENSE+ P2SENSE-

56_0603

56_0603 R2640R264

P2OVP+ P2OVP-

0

47u_6.3V_1206C150 47u_6.3V_1206C150 47u_6.3V_1206C154 47u_6.3V_1206C154 47u_6.3V_1206C149 47u_6.3V_1206C149 47u_6.3V_1206C155 47u_6.3V_1206C155

47u_6.3V_1206C1089 47u_6.3V_1206C1089 47u_6.3V_1206C177 47u_6.3V_1206C177 47u_6.3V_1206C297 47u_6.3V_1206C297 47u_6.3V_1206C199 47u_6.3V_1206C199

22u_6.3V_1206C157 22u_6.3V_1206C157 22u_6.3V_1206C158 22u_6.3V_1206C158 22u_6.3V_1206C152 22u_6.3V_1206C152 22u_6.3V_1206C151 22u_6.3V_1206C151

R271

R270

0_0402

R991 100/1206R991 100/1206

R988

56_0603

56_0603 R2650R265

0

47u_6.3V_1206C153 47u_6.3V_1206C153 47u_6.3V_1206C181 47u_6.3V_1206C181 47u_6.3V_1206C180 47u_6.3V_1206C180R260 47u_6.3V_1206C182 47u_6.3V_1206C182

47u_6.3V_1206C210 47u_6.3V_1206C210 47u_6.3V_1206C156 47u_6.3V_1206C156 47u_6.3V_1206C1091 47u_6.3V_1206C1091 47u_6.3V_1206C183 47u_6.3V_1206C183

10/4 Joe, 47uF x4 pcs per phase by Voltera recommend

+3.3V

Slave

R974

R977

Faults

VCORE_EN<7,9,13,56,62>

4.7K

+5V

U20

R273

R273 10K

10K

DS

Q8 2N7002Q82N7002

G

3

1 2 3

U20

GND

NC7S08

+5V

R274

H2_PRESENT_N<17,39,62>

VCC

+5V

5

CPU2POWER_EN

4

2

P2Slave1_FAULTB<12> P2Slave2_FAULTB<12> P2Slave3_FAULTB<12> P2Slave4_FAULTB<12>

P2Slave1_FAULTB P2Slave2_FAULTB P2Slave3_FAULTB P2Slave4_FAULTB

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

R977

10K-0402

CPU3_VT1115M

MS-9184

1

R976

R975

10K-0402

11 92Thursday, August 31, 2006

0ACustom

of

5

4

3

2

1

P2_VX1

+3.3V+3.3V

C871uC87 1u

P2SPHASE <11> P2DBI <11>

REMOVE BYPASS R

P2_VX1 <11>P2_VX2 <11>

C701uC70 1u

REMOVE BYPASS R

P2_VX3 <11>

VRD_HEATSINK_2 Phase

P2Slave1_FAULTB P2Slave2_FAULTB P2Slave3_FAULTB P2Slave4_FAULTB

HS3

112

2

P2Slave1_FAULTB <11> P2Slave2_FAULTB <11> P2Slave3_FAULTB <11> P2Slave4_FAULTB <11>

334

4

P2DB3

D D

R55

1K_0402

12VP2_IN 12VP2_IN

C541uC54

1u

C451uC45

C C

1u

C371uC37

1u

C15

10u_16V_1206

C31

10u_16V_1206

R66

R66 0_0402

0_0402

C2_DBO2

SPHASE2_VT2

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7

F5

F7 B3 C3 D3 E3

F3

R973 X_0R973 X_0

U3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

R75

R75 0_0402

0_0402

P2IDES_P

P2_VX2_DBI

P2IDES_N P2IDES_N P2Slave2_FAULTB

1uC83 1uC83

C2_BST2 C2_BST1

BST

GND

GND VDD VDD VCC

P2_VX2

A4

VX

A6

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1 E2 A1 B2 A2

C841uC84

C691uC69 1u

1u

H1

H2

DBO

SPHASE

G2

A3

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135SU3VT1135S

C551uC55

1u

C461uC46

1u

C381uC38

1u

C12

10u_16V_1206

C26

10u_16V_1206

R53

1K_0402

R971 X_0R971 X_0

R63

R63 0_0402

0_0402

C2_DBO1 P2Slave1_FAULTB

SPHASE2_VT1

U4

A5 A7 B5 B7

C5 C7 D5 D7

E5 E7 F5 F7 B3

C3 D3

E3 F3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R72

R72 0_0402

0_0402

P2IDES_P

P2_VX1_DBI

G2

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135SU4VT1135S

1uC85 1uC85

A3

A4

VX

A6

BST

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C861uC86

1u

Input Cap. totally 1u/0603x3, 10u/16Vx2 each phase

P2SPHASE

P2DB3

P2IDES_P P2IDES_N P2Slave3_FAULTB

1uC90 1uC90

C2_BST3

A3

A4

VX

A6

BST

VX

B4

VX

B6

FAULTB

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C711uC71

1u

P2_VX3

R67

R67 0_0402

0_0402

1K_0402

R972 X_0R972 X_0

C2_DBO3 SPHASE2_VT3

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

U5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R76

R76 0_0402

0_0402

P2_VX3_DBI

G2

D1

C2

DBI

IDESP

B1

IDESN

VT1135SU5VT1135S

P2DBO<11>

B B

A A

C571uC57

1u

C481uC48

1u

C401uC40

1u

C14

10u_16V_1206

C28

10u_16V_1206

R54

1K_0402

12VP2_IN 12VP2_IN

R65 X_0R65 X_0

R64

R64 0_0402

0_0402

C2_DBO4

SPHASE2_VT4

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

U6

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R73

R73 0_0402

0_0402

P2IDES_P

P2_VX4_DBI

P2IDES_N P2Slave4_FAULTB

G2

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135SU6VT1135S

C2_BST4

A3

VX

BST

VX VX VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

P2IDES_P <11> P2IDES_N <11>

1uC88 1uC88

P2_VX4

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6

+3.3V +3.3V

F4 F6 F1 E2 A1 B2 A2

C891uC89

C681uC68 1u

1u

R56

P2_VX4 <11>

C561uC56

1u

C471uC47

1u

C391uC39

1u

C27

10u_16V_1206

C13

10u_16V_1206

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU3_VT1135S

MS-9184

1

0ACustom

of

12 92Monday, September 04, 2006

5

4

3

2

1

+3.3V

U17

CPU3POWER_EN

P3_VID7

P3_VID7<84>

D D

R248

X_249R

C200

C194

C194 X_103P

X_103P

C200

X_680P

R257

R257 825R

825R

C195

C195 3300p/50V

3300p/50V

P3R_SEL7 P3R_SEL6 P3R_SEL5 P3R_SEL4 P3R_SEL3 P3R_SEL2 P3R_SEL1 P3R_SEL0 P3R_FREQ P3R_REF

C C

B B

R249

R249 499_1%

499_1%

R250

1.96K

R140 5.9KST-0402R140 5.9KST-0402 R115 1.02K_0402R115 1.02K_0402 R137 340RSTR137 340RST R111 31.6KR1%R111 31.6KR1% R116 8.66KST-0402R116 8.66KST-0402 R136 11.3KR136 11.3K R143 5.11K-0402R143 5.11K-0402 R106 2.43K-0603R106 2.43K-0603 R142 26.1K-0402R142 26.1K-0402 R141 11KST-0402R141 11KST-0402

P3_VID6

P3_VID6<84>

P3_VID5

P3_VID5<48,84>

P3_VID4

P3_VID4<48,84>

P3_VID3

P3_VID3<48,84>

P3_VID2

P3_VID2<48,84>

P3_VID1

P3_VID1<48,84>

P3_VID0

P3_VID0<48,84>

4.7u_6.3V-0805C133 4.7u_6.3V-0805C133

P3OVP+ P3OVPP3OVP_OUT

6800PC193 6800PC193

P3SENSE+ P3SENSE-

P3VR_HOT P3VR_FAN P3FAULTB

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

U17

OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVPOVP_out Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB

VT1115M

EXT_REF

R_sel<7> R_sel<6> R_sel<5> R_sel<4>

R_sel<3> R_sel<2>

Load_Current

R_sel<1>

R_sel<0>

G

49

R_SEL0 =2.43K SMBUS = E6h

+3.3V

R231 4.7KR231 4.7K R212 4.7KR212 4.7K

MASTER Reported Faults

10K-0402

P3FAULTB P3OVP_OUT

P3VR_FAN P3VR_HOT

Configuration Resistors,Rref

U10

A A

P1_P2_POWER_GD<11>

CPU3POWER_GD

5

1 2 3

U10

GND

NC7S32

VCC

+3.3V

5 4

VCORE_VLD <56,62>

VDD

GND

R_ref

Pwrgd R_freq Vin_ov Vin_uv

Ides_n Ides_p

DBO

sphase

R225

4

+3.3V

36 47

SC

46

SD

45

P3R_SEL7

44

P3R_SEL6

43

P3R_SEL5

42

P3R_SEL4

41 40

P3R_REF

39

P3R_SEL3

38

P3R_SEL2

37 48

P3R_FREQ

35

P3VIN_OV

34

P3VIN_UV

33 32

P3R_SEL1

31 30 29

P3R_SEL0

28 27 26

DBI

25

P3_VID7 P3_VID6

SMB_5_CLK <7,9,11,15,16,17,18,78> SMB_5_DATA <7,9,11,15,16,17,18,78>

R138 10KR138 10K R144 0_0402R144 0_0402

R145 0_0402R145 0_0402 R201 0_0402R201 0_0402

R195 0_0402R195 0_0402 R183 0_0402R183 0_0402

P3IDES_N P3IDES_P

P3DBI P3DBO P3SPHASE

P3VIN_OV

C102

0.1u_16V

+3.3V

+5V

R107

10.7KR

R197

R197 10K

10K

CPU3POWER_GD

1u_10V

1u_10V C166

C166

P3IDES_N <14> P3IDES_P <14>

P3DBI <14> P3DBO <14> P3SPHASE <14>

R108

R109

100K

63.4k 1%

12VP3_IN

R110

R110 10K

10K

P3VIN_UV

C103

0.1u_16V

L5

1

50nH

2 3

50nH

4 5

50nH50nH

6 7

8

INDUCTOR_4_PHASE_8pin

P3_VX2 <14>

P3_VCORE

P3_VX1 <14>

P3_VCORE

P3_VX3 <14>

P3_VCORE

P3_VX4 <14>

P3_VCORE

P3_VCORE_FB_N<48> P3_VCORE_FB_P<48>

P3_VCORE

R1000

P3SENSE+ P3SENSE-

56_0603

56_0603 R2460R246

P3OVP+ P3OVP-

0

47u_6.3V_1206C1096 47u_6.3V_1206C1096 47u_6.3V_1206C1097 47u_6.3V_1206C1097 47u_6.3V_1206C263 47u_6.3V_1206C263 47u_6.3V_1206C264 47u_6.3V_1206C264 47u_6.3V_1206C253 47u_6.3V_1206C253

47u_6.3V_1206C274 47u_6.3V_1206C274 47u_6.3V_1206C272 47u_6.3V_1206C272 47u_6.3V_1206C273 47u_6.3V_1206C273 47u_6.3V_1206C246 47u_6.3V_1206C246

22u_6.3V_1206C219 22u_6.3V_1206C219 22u_6.3V_1206C218 22u_6.3V_1206C218 22u_6.3V_1206C217 22u_6.3V_1206C217 22u_6.3V_1206C216 22u_6.3V_1206C216

R255

R254

0_0402

R996 100/1206R996 100/1206

R999

56_0603

56_0603 R2470R247

0

47u_6.3V_1206C275 47u_6.3V_1206C275 47u_6.3V_1206C247 47u_6.3V_1206C247 47u_6.3V_1206C220 47u_6.3V_1206C220

47u_6.3V_1206C271 47u_6.3V_1206C271 47u_6.3V_1206C245 47u_6.3V_1206C245 47u_6.3V_1206C244 47u_6.3V_1206C244 47u_6.3V_1206C243 47u_6.3V_1206C243

10/4 Joe, 47uF x4 pcs per phase by Voltera recommend

+3.3V

Slave

R982

R253

10K-0402

R206

R214

10K-0402

H3_PRESENT_N<18,48,62>

R206

10K-0402

+5V

R267

VCORE_EN<7,9,11,56,62>

+5V +5V

R258

R258 10K

10K

4.7K

DS

Q7 2N7002Q72N7002

G

3

Faults

P3Slave1_FAULTB<14> P3Slave2_FAULTB<14> P3Slave3_FAULTB<14> P3Slave4_FAULTB<14>

U19

VCC

1 2 3

GND

NC7S08

5

CPU3POWER_EN

4

10K-0402

P3Slave1_FAULTB P3Slave2_FAULTB P3Slave3_FAULTB P3Slave4_FAULTB

2

R983

R984

10K-0402

R982

R985

10K-0402

Near U29 for EMI

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

CPU3_VT1115M

MS-9184

1

13 92Friday, September 01, 2006

of

0ACustom

5

4

3

2

HS6

1

P3_VX1

1u

P3DB3

1uC172 1uC172

C1731uC173

1u

+3.3V+3.3V

P3_VX3

C1601uC160 1u

P3SPHASE <13> P3DBI <13>

REMOVE BYPASS R

P3_VX1 <13>P3_VX2 <13>

P3Slave1_FAULTB P3Slave2_FAULTB P3Slave3_FAULTB P3Slave4_FAULTB

REMOVE BYPASS R

P3_VX3 <13>

C1611uC161 1u

P3Slave1_FAULTB <13> P3Slave2_FAULTB <13> P3Slave3_FAULTB <13> P3Slave4_FAULTB <13>

P3DB3

D D

R150

C1341uC134

1u

C1241uC124

C C

1u

C1051uC105

1u

C96

10u_16V_1206

C1065

10u_16V_1206

R164

R164 0_0402

0_0402

C3_DBO1

SPHASE3_VT2

1K_0402

U11

A5 A7 B5 B7 C5 C7 D5 D7 E5

12VP3_IN 12VP3_IN

E7

F5

F7 B3 C3 D3 E3

F3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

SPHASE

R175

R175 0_0402

0_0402

P3IDES_P

P3_VX2_DBI

P3IDES_N P3Slave2_FAULTB

1uC168 1uC168

C3_BST2 C3_BST1

BST

GND GND VDD VDD VCC

P3_VX2

A4

VX

A6

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1 E2 A1 B2 A2

C1631uC163

C1691uC169

1u

DBO

G2

A3

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135S

R151

C1351uC135

1u

C1251uC125

1u

C1061uC106

1u

C97

10u_16V_1206

C1068

10u_16V_1206

1K_0402

R981 X_0R981 X_0R980 X_0R980 X_0

R165

R165 0_0402

0_0402

C3_DBO1

SPHASE3_VT1

A5 A7 B5

B7 C5 C7 D5 D7

E5

E7

F5

F7

B3 C3 D3

E3

F3

U12

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R176

R176 0_0402

0_0402

P3IDES_P

P3_VX1_DBI

P3IDES_N P3Slave1_FAULTB

G2

D1

C2

B1

DBI

IDESP

IDESN

VT1135S

A3

VX

BST

VX VX

FAULTB

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

1uC170 1uC170

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C1711uC171

Input Cap. totally 1u/0603x3, 10u/16Vx2 each phase

P3SPHASE

P3DBO<13>

B B

A A

C1371uC137

1u

C1271uC127

1u

C1081uC108

1u

C1066

10u_16V_1206

C99

10u_16V_1206

R153

1K_0402

12VP3_IN

R163 X_0R163 X_0

R167

R167 0_0402

0_0402

C3_DBO4

SPHASE3_VT4

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

U14

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R178

R178 0_0402

0_0402

P3IDES_P P3IDES_N

P3_VX4_DBI

P3Slave4_FAULTB

G2

D1

C2

B1

DBI

IDESP

IDESN

FAULTB

VT1135S

C3_BST4

A3

VX

BST

VX VX VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C1751uC175

1uC174 1uC174

1u

P3IDES_P <13> P3IDES_N <13>

P3_VX4

C1621uC162 1u

R152

P3_VX4 <13>

C1361uC136

1u

C1261uC126

1u

C1071uC107

1u

C98

10u_16V_1206

C1067

10u_16V_1206

12VP3_IN +3.3V+3.3V

R166

R166 0_0402

0_0402

1K_0402

R979 X_0R979 X_0

C3_DBO3 SPHASE3_VT3

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

U13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

H1

H2

DBO

SPHASE

R177

R177 0_0402

0_0402

P3IDES_P

P3_VX3_DBI

P3IDES_N P3Slave3_FAULTB

G2

D1

C2

B1

DBI

IDESP

IDESN

VT1135S

C3_BST3

A3

BST

FAULTB

GND GND

VDD VDD VCC

A4

VX

A6

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1 E2 A1 B2 A2

112

334

2

4

VRD_HEATSINK_2 Phase

HS4

112

334

2

4

VRD_HEATSINK_2 Phase

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU3_VT1135S

MS-9184

1

0ACustom

of

14 92Monday, September 04, 2006

5

+5V

10K

10K R585

R585

DDR_POWR_GD<3,16,17,18,56>

D D

C C

+3.3V

Near U36 for EMI

P0_P1V8VID5 P0_P1V8VID0 P0_P1V8OEN

R570

R570 X_10K

X_10K

R569

R569 X_0_0402

X_0_0402

1u_10V

1u_10V C621

C621

C557

C557 X_103P

X_103P

+3.3V+3.3V+3.3V

R536

R536 10K-0402

10K-0402

R535

R535 X_0_0402

X_0_0402

SMB_5_CLK<7,9,11,13,16,17,18,78> SMB_5_DATA <7,9,11,13,16,17,18,78>

RN60

1 2 3 4 5 6 7 8

0-8P4R

R486

249R

C558

680P

R449

R449 360RST

360RST

C546

3300p/50V

R473

R473 499_1%

499_1%

R485

1.96K

4.7u_6.3V-0805C590 4.7u_6.3V-0805C590

MASTER Reported Faults

R571

R571 10K-0402

10K-0402

+3.3V

R483

R483 10K-0402

R572

R572 X_0_0402

X_0_0402

10K-0402

P1V8 Regulator

+3.3V

Master

1

P0_P1V8OEN P0_P1V8VID5 P0_P1V8VID4 P0_P1V8VID3 P0_P1V8VID2 P0_P1V8VID1 P0_P1V8VID0

6800PC578 6800PC578

P0_P1V8SENSE+ P0_P1V8SENSE-

P0_P1V8FAULT

Vnom+ and Vnom- have to connect to cap directly, then connect to GND

P0_P1V8FAULT

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

R_SEL0

SMbus address=E8h

R_SEL1

Setpoint=-6.3mV

R_SEL2

PowerGood & OVP voltage

R_SEL3

VR9 VID codes

R_SEL4

Imax=36A,Slave setting=1

R_SEL5

Slave Program

R_SEL6

Uncoupled Inductor

4

U43

SC Pwrgd OEN

R_sel<6>

VID<5>

R_sel<5>

VID<4>

R_sel<4> VID<3> VID<2> VID<1> VID<0> VDD GND Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 FaultB#19sphase

R_sel<3>

R_sel<2>

R_freq Vin_ov

Vin_uv

R_sel<1>

Ides_n Ides_p

R_sel<0>

VT1105M

R_SEL0 =8.66K SMBUS = E8h

SLP_S5J<16,17,18,56,62>

H0_PRESENT_N<7,21,62>

R_ref

3

+3.3V

38

SD

37

GND

VDD

DBO

P0_P1V8SEL6

36

P0_P1V8SEL5

35

P0_P1V8SEL4

34

P0_P1V8REF

33

P0_P1V8SEL3

32

P0_P1V8SEL2

31

P0_P1V8FREQ

30 29

P0_P1V8VIN_OV

28

P0_P1V8VIN_UV

27

P0_P1V8SEL1

26

P0_P1V8IDESNR

25

P0_P1V8IDESPR

24

P0_P1V8SEL0

23 22 21

DBI

20

SLP_S5J

G

R516 0_0402R516 0_0402 R509 0_0402R509 0_0402

R482 0_0402R482 0_0402

R481 0_0402R481 0_0402

R480 0_0402R480 0_0402

IDESP & IDESN use T-routing is better than daisy chain.

+5V

R599

R599 10K

10K

1 2 3

DS

Q14

Q14 2N7002

2N7002

U53

GND

NC7S08

P0_P1V8DBI

P0_P1V8DBO

P0_P1V8SPHASE

VCC

5 4

P0_P1V8IDESN P0_P1V8IDESP

P0_P1V8OEN

Sense resistor should be together and away from controller. connect to a bypass cap is better.

P0_P1V8

R511 0_0402R511 0_0402

R495 0_0402R495 0_0402

P0_P1V8SENSE+

P0_P1V8SENSE-

P0_P1V8SEL6 P0_P1V8SEL5 P0_P1V8SEL4 P0_P1V8SEL3 P0_P1V8SEL2 P0_P1V8SEL1 P0_P1V8SEL0

P0_P1V8REF P0_P1V8FREQ

P0_P1V8SENSE+ <21>

P0_P1V8SENSE- <21>

R576 340RSTR576 340RST R575 340RSTR575 340RST R565 23.7KR565 23.7K R549 5.9KST-0402R549 5.9KST-0402 R542 23.7KST-0402R542 23.7KST-0402 R521 5.11K-0402R521 5.11K-0402 R489 8.66KR489 8.66K

R558 11KST-0402R558 11KST-0402 R527 26.1K-0402R527 26.1K-0402

Configuration Resistors,Rref

2

P0_P1V8 P0_P1V8

47u_6.3V_1206C692 47u_6.3V_1206C692 47u_6.3V_1206C693 47u_6.3V_1206C693 47u_6.3V_1206C694 47u_6.3V_1206C694 47u_6.3V_1206C695 47u_6.3V_1206C695

47u_6.3V_1206C696 47u_6.3V_1206C696 47u_6.3V_1206C697 47u_6.3V_1206C697

47u_6.3V_1206C1215 47u_6.3V_1206C1215

22u_6.3V_1206C849 22u_6.3V_1206C849

10/04 Joe, change 47u x 4 pcs per phase

For 1.8V application each phase needs 100u~150u capacitance

+12V

R508

R551

63.4k 1%

100K

P0_P1V8VIN_OV P0_P1V8VIN_UV

C596

C596 103P

103P

10.7KR

R543

R513

10K

C582

C582 103P

103P

1

+12V

Near C532 for EMI

B B

A A

5

P1V8 Regulator Slave

P0_P1V8DBO

R618

1K-0402

C11921uC1192 1u C6581uC658 1u C6561uC656 1u C1189

C1189 10u_16V_1206

10u_16V_1206 C648

C648 10u_16V_1206

10u_16V_1206

R620

R620 0_0402

0_0402

R1066 X_0_0402R1066 X_0_0402

U60

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

1K-0402

+12V+12V

R1067 X_0_0402R1067 X_0_0402

R621

R621 0_0402

0_0402

U59

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

R1068 0_0402R1068 0_0402

R622

R622 0_0402

0_0402

P0_P1V8IDESP P0_P1V8IDESN P0_P1V8FAULTS2 P0_P1V8FAULTS1

1uC668 1uC668

A3

D1

H2

C2

G2

B1

H1

DBO

SPHASE

A4

VX

A6

DBI

BST

VX

B4

IDESP

IDESN

VX

B6

FAULTB

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

+3.3V +3.3V

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C6641uC664

VT1135S

1u

4

CHOK9

120nH

C6691uC669 1u

R619

C6571uC657 1u C11911uC1191 1u C6551uC655 1u C1190

C1190 10u_16V_1206

10u_16V_1206 C647

C647 10u_16V_1206

10u_16V_1206

P0_P1V8SPHASE P0_P1V8DBI

R623

R623 0_0402

0_0402

P0_P1V8IDESP P0_P1V8IDESN

1uC666 1uC666

CHOK8

A3

D1

H2

C2

G2

B1

H1

VX

DBI

BST

VX

DBO

IDESP

IDESN

VX

FAULTB

SPHASE

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

VT1135S

CHOK8

120nH

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C6651uC665

C6671uC667

1u

3

Slave Faults

P0_P1V8P0_P1V8

P0_P1V8FAULTS1 P0_P1V8FAULTS2

+3.3V +3.3V

10K-0402

R1072

10K-0402

R1071

2

DDRII VTT Power

+3.3V

U74

U74 APL5331KAC

APL5331KAC

8

NC

7

NC

6

VCNTL

5

NC

C842

0.1u/25V

Title

Size Document Number Rev

Date: Sheet

P0_P1V8

1

VIN

2

GND

3

VREF1

4

VOUT

9

NC

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

P0_VTT_0.9V

C844

MS-9184

C844

0.1u/25V

15 92Monday, September 04, 2006

+

12

EC9

1000U

Micro-Star Int'l Co., Ltd.

CPU0 DDR POWER

1

P0_P1V8

of

R764

R764 1K_1%

1K_1%

R757

R757 1K_1%

1K_1%

0AC

5

+5V

10K

10K R586

R586

DDR_POWR_GD<3,15,17,18,56>

D D

C C

+3.3V

Near U36 for EMI

P1_P1V8VID5 P1_P1V8VID0 P1_P1V8OEN

CI1

0.1u/25V_0402

R547

R547 X_10K

X_10K

R539

R539 X_0_0402

X_0_0402

1u_10V

1u_10V C626

C626

C611

C611 X_103P

X_103P

+3.3V+3.3V+3.3V

R581

R581 10K-0402

10K-0402

R588

R588 X_0_0402

X_0_0402

SMB_5_CLK<7,9,11,13,15,17,18,78> SMB_5_DATA <7,9,11,13,15,17,18,78>

RN61

1 2 3 4 5 6 7 8

0-8P4R

R587

249R

C633

680P

R582

R582 360RST

360RST

C612

3300p/50V

R577

R577 499_1%

499_1%

R563

1.96K

4.7u_6.3V-0805C628 4.7u_6.3V-0805C628

MASTER Reported Faults

R557

R557 10K-0402

10K-0402

+3.3V

R548

R548 10K-0402

R564

R564 X_0_0402

X_0_0402

10K-0402

P1V8 Regulator

+3.3V

Master

1

P1_P1V8OEN P1_P1V8VID5 P1_P1V8VID4 P1_P1V8VID3 P1_P1V8VID2 P1_P1V8VID1 P1_P1V8VID0

6800PC627 6800PC627

P1_P1V8SENSE+ P1_P1V8SENSE-

P1_P1V8FAULT

Vnom+ and Vnom- have to connect to cap directly, then connect to GND

P1_P1V8FAULT

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

R_SEL0

SMbus address=E8h

R_SEL1

Setpoint=-6.3mV

R_SEL2

PowerGood & OVP voltage

R_SEL3

VR9 VID codes

R_SEL4

Imax=36A,Slave setting=1

R_SEL5

Slave Program

R_SEL6

Uncoupled Inductor

4

U47

SC Pwrgd OEN

R_sel<6>

VID<5>

R_sel<5>

VID<4>

R_sel<4> VID<3> VID<2> VID<1> VID<0> VDD GND Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 FaultB#19sphase

R_ref R_sel<3> R_sel<2>

R_freq Vin_ov

Vin_uv

R_sel<1>

Ides_n Ides_p

R_sel<0>

VT1105M

R_SEL0 =9.31K SMBUS = EAh

SLP_S5J<15,17,18,56,62>

H1_PRESENT_N<9,30,62>

3

+3.3V

38

SD

37

GND

VDD

DBO

P1_P1V8SEL6

36

P1_P1V8SEL5

35

P1_P1V8SEL4

34

P1_P1V8REF

33

P1_P1V8SEL3

32

P1_P1V8SEL2

31

P1_P1V8FREQ

30 29

P1_P1V8VIN_OV

28

P1_P1V8VIN_UV

27

P1_P1V8SEL1

26

P1_P1V8IDESNR

25

P1_P1V8IDESPR

24

P1_P1V8SEL0

23 22 21

DBI

20

R503 0_0402R503 0_0402 R504 0_0402R504 0_0402

R520 0_0402R520 0_0402

R528 0_0402R528 0_0402

R524 0_0402R524 0_0402

IDESP & IDESN use T-routing is better than daisy chain.

P1_P1V8IDESN P1_P1V8IDESP

P1_P1V8DBI

P1_P1V8DBO

P1_P1V8SPHASE

Sense resistor should be together and away from controller. connect to a bypass cap is better.

P1_P1V8

R579 0_0402R579 0_0402

R580 0_0402R580 0_0402

P1_P1V8SENSE+

P1_P1V8SENSE-

P1_P1V8SENSE+ <30>

P1_P1V8SENSE- <30>

2

P1_P1V8 P1_P1V8

47u_6.3V_1206C1183 47u_6.3V_1206C1183 47u_6.3V_1206C1176 47u_6.3V_1206C1176 47u_6.3V_1206C1187 47u_6.3V_1206C1187 47u_6.3V_1206C1188 47u_6.3V_1206C1188

47u_6.3V_1206C1177 47u_6.3V_1206C1177 47u_6.3V_1206C1186 47u_6.3V_1206C1186 47u_6.3V_1206C564 47u_6.3V_1206C564 47u_6.3V_1206C1178 47u_6.3V_1206C1178

22u_6.3V_1206C1185 22u_6.3V_1206C1185 22u_6.3V_1206C1184 22u_6.3V_1206C1184

10/04 Joe, change 47u x 4 pcs per phase

1

For 1.8V application each phase needs 100u~150u capacitance

+12V_IN

R460

R463

100K

63.4k 1%

10.7KR

R461

63.4k 1%

R462

10K

C556

C556 103P

103P

P1_P1V8VIN_OV P1_P1V8VIN_UV

C555

C555 103P

103P

HS1

1122334

VRD_HEATSINK_2 Phase

4

SLP_S5J

P1_P1V8SEL6

+5V

R556

R556 10K

10K

U50

VCC

1

5 2 3

DS

Q13

Q13 2N7002

2N7002

G

GND

NC7S08

4

P1_P1V8OEN

P1_P1V8SEL5 P1_P1V8SEL4 P1_P1V8SEL3 P1_P1V8SEL2 P1_P1V8SEL1 P1_P1V8SEL0

P1_P1V8REF P1_P1V8FREQ

R523 340RSTR523 340RST R514 340RSTR514 340RST R497 23.7KR497 23.7K R499 5.9KST-0402R499 5.9KST-0402 R500 23.7KST-0402R500 23.7KST-0402 R502 5.11K-0402R502 5.11K-0402 R505 9.31KR505 9.31K

R498 11KST-0402R498 11KST-0402 R501 26.1K-0402R501 26.1K-0402

Configuration Resistors,Rref

+12V_IN

Near C532 for EMI

B B

A A

5

P1V8 Regulator Slave

P1_P1V8DBO

R465

1K-0402

C5421uC542 1u C5411uC541 1u C5521uC552 1u C519

C519 10u_16V_1206

10u_16V_1206 C535

C535 10u_16V_1206

10u_16V_1206

R479

R479 0_0402

0_0402

R487 X_0_0402R487 X_0_0402

U41

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

R510 0_0402R510 0_0402

R492

R492 0_0402

0_0402

P1_P1V8IDESP P1_P1V8IDESN P1_P1V8FAULTS2 P1_P1V8FAULTS1

1uC588 1uC588

A3

D1

H2

C2

G2

B1

H1

DBO

SPHASE

A4

VX

A6

DBI

BST

VX

B4

IDESP

IDESN

VX

B6

FAULTB

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

+3.3V +3.3V

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C5891uC589

VT1135S

1u

4

CHOK7

120nH

C5701uC570 1u

R464

C5371uC537 1u C5511uC551 1u C5381uC538 1u C534

C534 10u_16V_1206

10u_16V_1206 C543

C543 10u_16V_1206

10u_16V_1206

1K-0402

R1032 X_0_0402R1032 X_0_0402

R478

R478 0_0402

0_0402

U40

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

+12V_IN+12V_IN

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

P1_P1V8SPHASE P1_P1V8DBI

R491

R491 0_0402

0_0402

P1_P1V8IDESP P1_P1V8IDESN

1uC586 1uC586

CHOK6

A3

D1

H2

C2

G2

B1

H1

VX

DBI

BST

VX

DBO

IDESP

IDESN

VX

FAULTB

SPHASE

VX VX VX VX VX VX VX VX

VX GND GND VDD VDD VCC

VT1135S

CHOK6

120nH

A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2

C5871uC587

C5681uC568

1u

3

Slave Faults

P1_P1V8P1_P1V8

P1_P1V8FAULTS1 P1_P1V8FAULTS2

+3.3V +3.3V

10K-0402

R1039

10K-0402

R1038

2

DDRII VTT Power

+3.3V

U38

U38 APL5331KAC

APL5331KAC

8

NC

7

NC

6

VCNTL

5

NC

C526

0.1u/25V

Title

Size Document Number Rev

Date: Sheet

P1_P1V8

1

VIN

2

GND

3

VREF1

4

VOUT

9

NC

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

P1_VTT_0.9V

C580

MS-9184

C580

0.1u/25V

16 92Monday, September 04, 2006

+

12

EC4

1000U

Micro-Star Int'l Co., Ltd.

CPU1 DDR POWER

1

P1_P1V8

of

R538

R538 1K_1%

1K_1%

R525

R525 1K_1%

1K_1%

0AC

5

+5V

10K

10K R438

R438

DDR_POWR_GD<3,15,16,18,56>

D D

+3.3V

Near U51 for EMI

1u_10V

1u_10V C530

C530

C497

C497 X_103P

X_103P

RN53

1 2 3 4 5 6 7 8

0-8P4R

R442

249R

C536

680P

R436

R436 360RST

360RST

C498

3300p/50V

SMB_5_CLK<7,9,11,13,15,16,18,78>

4.7u_6.3V-0805C532 4.7u_6.3V-0805C532

R428

R428 499_1%

499_1%

R421

1.96K

P1V8 Regulator

+3.3V

Master

1

P2_P1V8OEN P2_P1V8VID5 P2_P1V8VID4 P2_P1V8VID3 P2_P1V8VID2 P2_P1V8VID1 P2_P1V8VID0

6800PC531 6800PC531

P2_P1V8SENSE+ P2_P1V8SENSE-

P2_P1V8FAULT

Vnom+ and Vnom- have to connect to cap directly, then connect to GND

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

R_SEL0

SMbus address=EEh

R_SEL1

Setpoint=-6.3mV

R_SEL2

PowerGood & OVP voltage

R_SEL3

VR9 VID codes

R_SEL4

Imax=36A,Slave setting=1

R_SEL5

Slave Program

R_SEL6

Uncoupled Inductor

4

U32

SC Pwrgd OEN

R_sel<6>

VID<5>

R_sel<5>

VID<4>

R_sel<4> VID<3> VID<2> VID<1> VID<0> VDD GND Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 FaultB#19sphase

R_ref R_sel<3> R_sel<2>

R_freq Vin_ov

Vin_uv

R_sel<1>

Ides_n Ides_p

R_sel<0>

VT1105M

R_SEL0 =10K SMBUS =ECh

3

+3.3V

38

SD

37

GND

36 35 34 33 32 31 30 29

VDD

28 27 26 25 24 23 22

DBO

21

DBI

20

SMB_5_DATA <7,9,11,13,15,16,18,78>

P2_P1V8SEL6 P2_P1V8SEL5 P2_P1V8SEL4 P2_P1V8REF P2_P1V8SEL3 P2_P1V8SEL2 P2_P1V8FREQ

P2_P1V8VIN_OV P2_P1V8VIN_UV P2_P1V8SEL1 P2_P1V8IDESNR P2_P1V8IDESPR P2_P1V8SEL0

R380 0_0402R380 0_0402 R381 0_0402R381 0_0402

R389 0_0402R389 0_0402

R402 0_0402R402 0_0402

R395 0_0402R395 0_0402

IDESP & IDESN use T-routing is better than daisy chain.

P2_P1V8IDESN P2_P1V8IDESP

P2_P1V8DBI

P2_P1V8DBO

P2_P1V8SPHASE

Sense resistor should be together and away from controller. connect to a bypass cap is better.

P2_P1V8

R434 0_0402R434 0_0402

R435 0_0402R435 0_0402

P2_P1V8SENSE+

P2_P1V8SENSE-

P2_P1V8SENSE+ <39>

P2_P1V8SENSE- <39>

2

P2_P1V8 P2_P1V8

47u_6.3V_1206C280 47u_6.3V_1206C280 47u_6.3V_1206C449 47u_6.3V_1206C449 47u_6.3V_1206C448 47u_6.3V_1206C448

47u_6.3V_1206C447 47u_6.3V_1206C447 47u_6.3V_1206C496 47u_6.3V_1206C496

1

10/04 Joe, change 47u x 4 pcs per phase

+3.3V+3.3V+3.3V

C C

P2_P1V8VID5 P2_P1V8VID0 P2_P1V8OEN

R411

R411 X_10K

X_10K

R404

R404 X_0_0402

X_0_0402

R433

R433 10K-0402

10K-0402

R444

R444 X_0_0402

X_0_0402

MASTER Reported Faults

R419

R419 X_10K-0402

X_10K-0402

+3.3V

R412

R412 10K-0402

R423

R423 X_0_0402

X_0_0402

10K-0402

P2_P1V8FAULT

+5V

R418

R418 10K

10K

U33

VCC

Q10

Q10 2N7002

2N7002

VCC

1

5 2 3

GND

NC7S08

4

P2_P1V8OEN

SLP_S5J<15,16,18,56,62>

H2_PRESENT_N<11,39,62>

SLP_S5J

DS

G

P2_P1V8SEL6 P2_P1V8SEL5 P2_P1V8SEL4 P2_P1V8SEL3 P2_P1V8SEL2 P2_P1V8SEL1 P2_P1V8SEL0

P2_P1V8REF P2_P1V8FREQ

R388 340RSTR388 340RST R394 340RSTR394 340RST R374 23.7KR374 23.7K R376 5.9KST-0402R376 5.9KST-0402 R377 23.7KST-0402R377 23.7KST-0402 R379 5.11K-0402R379 5.11K-0402 R382 10KR382 10K

R375 11KST-0402R375 11KST-0402 R378 26.1K-0402R378 26.1K-0402

+12V_IN

R365

R362

63.4k 1%

100K

P2_P1V8VIN_OV P2_P1V8VIN_UV

R364

R363

C462

C462 103P

103P

10.7KR

10K

C463

C463 103P

103P

Heatsink

HS9

1122334

VRD_HEATSINK_2 Phase

4

Configuration Resistors,Rref

+12V_IN

Near C342 for EMI

B B

A A

P1V8 Regulator Slave

R1008 X_0_0402R1008 X_0_0402

R407

R407 0_0402

0_0402

R416

1K-0402

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7

+12V_IN +12V_IN

F5

C5021uC502 1u C5011uC501 1u C4901uC490 1u C522

C522 10u_16V_1206

10u_16V_1206 C521

C521 10u_16V_1206

10u_16V_1206

F7 B3 C3 D3 E3 F3

R400

R400 0_0402

0_0402

P2_P1V8IDESP P2_P1V8IDESN P2_P1V8FAULTS2

1uC470 1uC470

H1

A3

D1

H2

C2

G2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

B1

A4

VX

A6

DBI

BST

VX

DBO

SPHASE

B4

IDESP

IDESN

VX

FAULTB

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

+3.3V +3.3V

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C4691uC469

VT1135S

1u

U29

R414 0_0402R414 0_0402

CHOK1

120nH

C4741uC474 1u

C5001uC500 1u C4991uC499 1u C4891uC489 1u C544

C544 10u_16V_1206

10u_16V_1206 C520

C520 10u_16V_1206

10u_16V_1206

R415

1K-0402

P2_P1V8

R403 X_0_0402R403 X_0_0402

R406

R406 0_0402

0_0402

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

P2_P1V8SPHASE P2_P1V8DBIP2_P1V8DBO

R398

R398 0_0402

0_0402

P2_P1V8IDESP P2_P1V8IDESN P2_P1V8FAULTS1

1uC468 1uC468

CHOK0

H1

A3

D1

H2

C2

G2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

B1

A4

VX

A6

DBI

BST

VX

DBO

SPHASE

B4

IDESP

IDESN

VX

FAULTB

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C4731uC473

VT1135S

U28

CHOK0

120nH

C4671uC467 1u

1u

P2_P1V8

Slave Faults

+3.3V +3.3V

P2_P1V8FAULTS1 P2_P1V8FAULTS2

10K-0402

R1003

10K-0402

R1002

DDRII VTT Power

+3.3V

U31

U31 APL5331KAC

C453

0.1u/25V

APL5331KAC

8

NC

7

NC

6

VCTNL

5

NC

VREF1

VOUT

1

VIN

2

GND

3 4 9

NC

P2_P1V8

P2_VTT_0.9V

+

12

EC3

1000U

C525

0.1u/25V

P2_P1V8

R429

R429 1K_1%

1K_1%

R430

R430 1K_1%

1K_1%

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU3 DDR POWER

MS-9184

1

0AC

of

17 92Monday, September 04, 2006

5

+5V

10K

10K R1046

R1046

DDR_POWR_GD<3,15,16,17,56>

D D

+3.3V

Near U51 for EMI

1u_10V

1u_10V C1153

C1153

C1145

C1145 X_103P

X_103P

SMB_5_CLK<7,9,11,13,15,16,17,78> SMB_5_DATA <7,9,11,13,15,16,17,78>

RN154

1 2 3 4 5 6 7 8

0-8P4R

R1036

249R

C1152

680P

R1031

R1031 360RST

360RST

C1146

3300p/50V

R1030

R1030 499_1%

499_1%

R1027

1.96K

4.7u_6.3V-0805C1155 4.7u_6.3V-0805C1155

P1V8 Regulator

+3.3V

Master

1

P3_P1V8OEN P3_P1V8VID5 P3_P1V8VID4 P3_P1V8VID3 P3_P1V8VID2 P3_P1V8VID1 P3_P1V8VID0

6800PC1154 6800PC1154

P3_P1V8SENSE+ P3_P1V8SENSE-

P3_P1V8FAULT

Vnom+ and Vnom- have to connect to cap directly, then connect to GND

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

R_SEL0

SMbus address=EEh

R_SEL1

Setpoint=-6.3mV

R_SEL2

PowerGood & OVP voltage

R_SEL3

VR9 VID codes

R_SEL4

Imax=36A,Slave setting=1

R_SEL5

Slave Program

R_SEL6

Uncoupled Inductor

4

U96

SC Pwrgd OEN

R_sel<6>

VID<5>

R_sel<5>

VID<4>

R_sel<4> VID<3> VID<2> VID<1> VID<0> VDD GND Vnom+ Vnomsense+ senseVamp_out1 Vamp_in Vamp_out2 FaultB#19sphase

R_ref R_sel<3> R_sel<2>

R_freq Vin_ov

Vin_uv

R_sel<1>

Ides_n Ides_p

R_sel<0>

VT1105M

R_SEL0 =10.7K SMBUS = EEh

3

+3.3V

38

SD

37

GND

VDD

DBO

P3_P1V8SEL6

36

P3_P1V8SEL5

35

P3_P1V8SEL4

34

P3_P1V8REF

33

P3_P1V8SEL3

32

P3_P1V8SEL2

31

P3_P1V8FREQ

30 29

P3_P1V8VIN_OV

28

P3_P1V8VIN_UV

27

P3_P1V8SEL1

26

P3_P1V8IDESNR

25

P3_P1V8IDESPR

24

P3_P1V8SEL0

23 22 21

DBI

20

R1016 0_0402R1016 0_0402 R1017 0_0402R1017 0_0402

R1022 0_0402R1022 0_0402

R1020 0_0402R1020 0_0402

R1019 0_0402R1019 0_0402

IDESP & IDESN use T-routing is better than daisy chain.

P3_P1V8IDESN P3_P1V8IDESP

P3_P1V8DBI

P3_P1V8DBO

P3_P1V8SPHASE

Sense resistor should be together and away from controller. connect to a bypass cap is better.

P3_P1V8

R1034 0_0402R1034 0_0402

R1035 0_0402R1035 0_0402

P3_P1V8SENSE+

P3_P1V8SENSE-

P3_P1V8SENSE+ <48>

P3_P1V8SENSE- <48>

2

P3_P1V8 P3_P1V8

47u_6.3V_1206C516 47u_6.3V_1206C516 47u_6.3V_1206C517 47u_6.3V_1206C517 47u_6.3V_1206C518 47u_6.3V_1206C518

47u_6.3V_1206C523 47u_6.3V_1206C523 47u_6.3V_1206C524 47u_6.3V_1206C524

47u_6.3V_1206C515 47u_6.3V_1206C515

1

10/04 Joe, change 47u x 4 pcs per phase

+3.3V+3.3V+3.3V

C C

P3_P1V8VID5 P3_P1V8VID0 P3_P1V8OEN

R1023

R1023 X_10K

X_10K

R1025

R1025 X_0_0402

X_0_0402

R1033

R1033 10K-0402

10K-0402

R1044

R1044 X_0_0402

X_0_0402

MASTER Reported Faults

R1029

R1029 X_10K-0402

X_10K-0402

+3.3V

R1024

R1024 10K-0402

R1028

R1028 X_0_0402

X_0_0402

10K-0402

P3_P1V8FAULT

+5V

R1048

R1048 10K

10K

U98

VCC

Q33

Q33 2N7002

2N7002

1 2 3

GND

NC7S08

VCC

5

P3_P1V8OEN

4

SLP_S5J

SLP_S5J<15,16,17,56,62>

DS

H3_PRESENT_N<13,48,62>

G

P3_P1V8SEL6 P3_P1V8SEL5 P3_P1V8SEL4 P3_P1V8SEL3 P3_P1V8SEL2 P3_P1V8SEL1 P3_P1V8SEL0

P3_P1V8REF P3_P1V8FREQ

R1021 340RSTR1021 340RST R1018 340RSTR1018 340RST R1009 23.7KR1009 23.7K R1012 5.9KST-0402R1012 5.9KST-0402 R1013 23.7KST-0402R1013 23.7KST-0402 R1015 5.11K-0402R1015 5.11K-0402 R1010 10.7KRR1010 10.7KR

R1011 11KST-0402R1011 11KST-0402 R1014 26.1K-0402R1014 26.1K-0402

+12V

R1004

R1007

100K

63.4k 1%

R1005

10.7KR

63.4k 1%

R1006

10K

C1143

C1143 103P

103P

P3_P1V8VIN_OV P3_P1V8VIN_UV

C1142

C1142 103P

103P

Heatsink

HS0

1122334

VRD_HEATSINK_2 Phase

4

Configuration Resistors,Rref

+12V

Near C342 for EMI

B B

A A

P1V8 Regulator Slave

R554

R554 0_0402

0_0402

R561

1K-0402

C11751uC1175 1u C6191uC619 1u C6131uC613 1u C629

C629 10u_16V_1206

10u_16V_1206 C1180

C1180 10u_16V_1206

10u_16V_1206

R550 X_0_0402R550 X_0_0402

U45

A5

VSS

A7

VSS

B5

VSS

B7

VSS

C5

VSS

C7

VSS

D5

VSS

D7

VSS

E5

VSS

E7

VSS

F5

VSS

F7

VSS

B3

VDDH

C3

VDDH

D3

VDDH

E3

VDDH

F3

VDDH

P3_P1V8SPHASE

R545

R545 0_0402

0_0402

P3_P1V8IDESP P3_P1V8IDESN P3_P1V8FAULTS2

H1

A3

D1

H2

C2

G2

B1

DBI

BST

DBO

IDESP

IDESN

FAULTB

SPHASE

GND GND VDD VDD VCC

VT1135S

R1052 0_0402R1052 0_0402

1uC571 1uC571

CHOK3

120nH

A4

VX

A6

VX

B4

VX

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1 E2 A1 B2 A2

C5721uC572

120nH

+3.3V +3.3V

C6141uC614 1u C11741uC1174 1u C6201uC620

C5941uC594

1u C1182

C1182

1u

10u_16V_1206

10u_16V_1206 C630

C630 10u_16V_1206

10u_16V_1206

R562

1K-0402

P3_P1V8

+12V+12V

R1054 X_0_0402R1054 X_0_0402

R555

R555 0_0402

0_0402

A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3

P3_P1V8DBIP3_P1V8DBO

R546

R546 0_0402

0_0402

P3_P1V8IDESP P3_P1V8IDESN P3_P1V8FAULTS1

1uC574 1uC574

CHOK4

H1

A3

D1

H2

C2

G2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH

B1

A4

VX

A6

DBI

BST

VX

DBO

SPHASE

B4

IDESP

IDESN

VX

FAULTB

B6

VX

C4

VX

C6

VX

D4

VX

D6

VX

E4

VX

E6

VX

F4

VX

F6

VX

F1

GND

E2

GND

A1

VDD

B2

VDD

A2

VCC

C5951uC595

VT1135S

U46

CHOK4

120nH

C5731uC573 1u

1u

P3_P1V8

Slave Faults

+3.3V +3.3V

P3_P1V8FAULTS1 P3_P1V8FAULTS2

10K-0402

R1049

10K-0402

R1051

DDRII VTT Power

+3.3V

U25

U25 APL5331KAC

C443

0.1u/25V

APL5331KAC

8

NC

7

NC

6

VCTNL

5

NC

VREF1

VOUT

1

VIN

2

GND

3 4 9

NC

P3_P1V8

+

12

EC2

EC2 1000u_6.3V

1000u_6.3V

P3_VTT_0.9V

+

12

EC1

1000U

C442

0.1u/25V

P3_P1V8

R351

R351 1K_1%

1K_1%

R346

R346 1K_1%

1K_1%

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU3 DDR POWER

MS-9184

1

0AC

of

18 92Monday, September 04, 2006

5

U65A

D D

C C

P1_TO_P0_CLKOUT_H1<28> P1_TO_P0_CLKOUT_L1<28> P1_TO_P0_CLKOUT_H0<28> P1_TO_P0_CLKOUT_L0<28>

P1_TO_P0_CTLOUT_H1<28> P1_TO_P0_CTLOUT_L1<28> P1_TO_P0_CTLOUT_H0<28> P1_TO_P0_CTLOUT_L0<28>

P1_TO_P0_CADOUT_H15<28> P1_TO_P0_CADOUT_L15<28> P1_TO_P0_CADOUT_H14<28> P1_TO_P0_CADOUT_L14<28> P1_TO_P0_CADOUT_H13<28> P1_TO_P0_CADOUT_L13<28> P1_TO_P0_CADOUT_H12<28> P1_TO_P0_CADOUT_L12<28> P1_TO_P0_CADOUT_H11<28> P1_TO_P0_CADOUT_L11<28> P1_TO_P0_CADOUT_H10<28> P1_TO_P0_CADOUT_L10<28> P1_TO_P0_CADOUT_H9<28> P1_TO_P0_CADOUT_L9<28> P1_TO_P0_CADOUT_H8<28> P1_TO_P0_CADOUT_L8<28>

P1_TO_P0_CADOUT_H7<28> P1_TO_P0_CADOUT_L7<28> P1_TO_P0_CADOUT_H6<28> P1_TO_P0_CADOUT_L6<28> P1_TO_P0_CADOUT_H5<28> P1_TO_P0_CADOUT_L5<28> P1_TO_P0_CADOUT_H4<28> P1_TO_P0_CADOUT_L4<28> P1_TO_P0_CADOUT_H3<28> P1_TO_P0_CADOUT_L3<28> P1_TO_P0_CADOUT_H2<28> P1_TO_P0_CADOUT_L2<28> P1_TO_P0_CADOUT_H1<28> P1_TO_P0_CADOUT_L1<28> P1_TO_P0_CADOUT_H0<28> P1_TO_P0_CADOUT_L0<28>

M6

L0_CLKIN_H(1)

N6

L0_CLKIN_L(1)

M3

L0_CLKIN_H(0)

M2

L0_CLKIN_L(0)

U4

L0_CTLIN_H(1)

U5

L0_CTLIN_L(1)

T1

L0_CTLIN_H(0)

U1

L0_CTLIN_L(0)

T6

L0_CADIN_H(15)

U6

L0_CADIN_L(15)

R4

L0_CADIN_H(14)

R5

L0_CADIN_L(14)

P6

L0_CADIN_H(13)

R6

L0_CADIN_L(13)

N4

L0_CADIN_H(12)

N5

L0_CADIN_L(12)

L4

L0_CADIN_H(11)

L5

L0_CADIN_L(11)

K6

L0_CADIN_H(10)

L6

L0_CADIN_L(10)

J4

L0_CADIN_H(9)

J5

L0_CADIN_L(9)

H6

L0_CADIN_H(8)

J6

L0_CADIN_L(8)

T3

L0_CADIN_H(7)

T2

L0_CADIN_L(7)

P1

L0_CADIN_H(6)

R1

L0_CADIN_L(6)

P3

L0_CADIN_H(5)

P2

L0_CADIN_L(5)

M1

L0_CADIN_H(4)

N1

L0_CADIN_L(4)

K1

L0_CADIN_H(3)

L1

L0_CADIN_L(3)

K3

L0_CADIN_H(2)

K2

L0_CADIN_L(2)

H1

L0_CADIN_H(1)

J1

L0_CADIN_L(1)

H3

L0_CADIN_H(0)

H2

L0_CADIN_L(0)

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0) L0_CTLOUT_H(1)

L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0)

L0_CADOUT_H(15)

L0_CADOUT_L(15)

L0_CADOUT_H(14)

L0_CADOUT_L(14)

L0_CADOUT_H(13)

L0_CADOUT_L(13)

L0_CADOUT_H(12)

L0_CADOUT_L(12)

L0_CADOUT_H(11)

L0_CADOUT_L(11)

L0_CADOUT_H(10)

L0_CADOUT_L(10)

L0_CADOUT_H(9) L0_CADOUT_L(9) L0_CADOUT_H(8) L0_CADOUT_L(8)

L0_CADOUT_H(7) L0_CADOUT_L(7) L0_CADOUT_H(6) L0_CADOUT_L(6) L0_CADOUT_H(5) L0_CADOUT_L(5) L0_CADOUT_H(4) L0_CADOUT_L(4) L0_CADOUT_H(3) L0_CADOUT_L(3) L0_CADOUT_H(2) L0_CADOUT_L(2) L0_CADOUT_H(1) L0_CADOUT_L(1) L0_CADOUT_H(0) L0_CADOUT_L(0)

SOCKET-F(1207)

4

AC5 AC4 AC1 AB1

W6 V6 V2 V3

W5 W4 AA6 Y6 AA5 AA4 AC6 AB6 AE6 AD6 AE5 AE4 AG6 AF6 AG5 AG4

W1 V1 Y2 Y3 AA1 Y1 AB2 AB3 AD2 AD3 AE1 AD1 AF2 AF3 AG1 AF1

P0_TO_P1_CLKOUT_H1 <28> P0_TO_P1_CLKOUT_L1 <28> P0_TO_P1_CLKOUT_H0 <28> P0_TO_P1_CLKOUT_L0 <28>

P0_TO_P1_CTLOUT_H1 <28> P0_TO_P1_CTLOUT_L1 <28> P0_TO_P1_CTLOUT_H0 <28> P0_TO_P1_CTLOUT_L0 <28>

P0_TO_P1_CADOUT_H15 <28> P0_TO_P1_CADOUT_L15 <28> P0_TO_P1_CADOUT_H14 <28> P0_TO_P1_CADOUT_L14 <28> P0_TO_P1_CADOUT_H13 <28> P0_TO_P1_CADOUT_L13 <28> P0_TO_P1_CADOUT_H12 <28> P0_TO_P1_CADOUT_L12 <28> P0_TO_P1_CADOUT_H11 <28> P0_TO_P1_CADOUT_L11 <28> P0_TO_P1_CADOUT_H10 <28> P0_TO_P1_CADOUT_L10 <28> P0_TO_P1_CADOUT_H9 <28> P0_TO_P1_CADOUT_L9 <28> P0_TO_P1_CADOUT_H8 <28> P0_TO_P1_CADOUT_L8 <28>

P0_TO_P1_CADOUT_H7 <28> P0_TO_P1_CADOUT_L7 <28> P0_TO_P1_CADOUT_H6 <28> P0_TO_P1_CADOUT_L6 <28> P0_TO_P1_CADOUT_H5 <28> P0_TO_P1_CADOUT_L5 <28> P0_TO_P1_CADOUT_H4 <28> P0_TO_P1_CADOUT_L4 <28> P0_TO_P1_CADOUT_H3 <28> P0_TO_P1_CADOUT_L3 <28> P0_TO_P1_CADOUT_H2 <28> P0_TO_P1_CADOUT_L2 <28> P0_TO_P1_CADOUT_H1 <28> P0_TO_P1_CADOUT_L1 <28> P0_TO_P1_CADOUT_H0 <28> P0_TO_P1_CADOUT_L0 <28>

3

E18 E17 C18 B18

C13 D13 A14 A13

E14 E13 C15 D15 E16 E15 C17 D17 C19 D19 E20 E19 C21 D21 E22 E21

C14 B14 A16 A15 C16 B16 A18 A17 A20 A19 C20 B20 A22 A21 C22 B22

L1_CLKIN_H(1) L1_CLKIN_L(1) L1_CLKIN_H(0) L1_CLKIN_L(0)

L1_CTLIN_H(1) L1_CTLIN_L(1) L1_CTLIN_H(0) L1_CTLIN_L(0)

L1_CADIN_H(15) L1_CADIN_L(15) L1_CADIN_H(14) L1_CADIN_L(14) L1_CADIN_H(13) L1_CADIN_L(13) L1_CADIN_H(12) L1_CADIN_L(12) L1_CADIN_H(11) L1_CADIN_L(11) L1_CADIN_H(10) L1_CADIN_L(10) L1_CADIN_H(9) L1_CADIN_L(9) L1_CADIN_H(8) L1_CADIN_L(8)

L1_CADIN_H(7) L1_CADIN_L(7) L1_CADIN_H(6) L1_CADIN_L(6) L1_CADIN_H(5) L1_CADIN_L(5) L1_CADIN_H(4) L1_CADIN_L(4) L1_CADIN_H(3) L1_CADIN_L(3) L1_CADIN_H(2) L1_CADIN_L(2) L1_CADIN_H(1) L1_CADIN_L(1) L1_CADIN_H(0) L1_CADIN_L(0)

SB_TO_P0_CADOUT_H15<57> SB_TO_P0_CADOUT_L15<57> SB_TO_P0_CADOUT_H14<57> SB_TO_P0_CADOUT_L14<57> SB_TO_P0_CADOUT_H13<57> SB_TO_P0_CADOUT_L13<57> SB_TO_P0_CADOUT_H12<57> SB_TO_P0_CADOUT_L12<57> SB_TO_P0_CADOUT_H11<57> SB_TO_P0_CADOUT_L11<57> SB_TO_P0_CADOUT_H10<57> SB_TO_P0_CADOUT_L10<57> SB_TO_P0_CADOUT_H9<57> SB_TO_P0_CADOUT_L9<57> SB_TO_P0_CADOUT_H8<57> SB_TO_P0_CADOUT_L8<57>

SB_TO_P0_CADOUT_H7<57> SB_TO_P0_CADOUT_L7<57> SB_TO_P0_CADOUT_H6<57> SB_TO_P0_CADOUT_L6<57> SB_TO_P0_CADOUT_H5<57> SB_TO_P0_CADOUT_L5<57> SB_TO_P0_CADOUT_H4<57> SB_TO_P0_CADOUT_L4<57> SB_TO_P0_CADOUT_H3<57> SB_TO_P0_CADOUT_L3<57> SB_TO_P0_CADOUT_H2<57> SB_TO_P0_CADOUT_L2<57> SB_TO_P0_CADOUT_H1<57> SB_TO_P0_CADOUT_L1<57> SB_TO_P0_CADOUT_H0<57> SB_TO_P0_CADOUT_L0<57>

SB_TO_P0_CLKOUT_H1<57> SB_TO_P0_CLKOUT_L1<57> SB_TO_P0_CLKOUT_H0<57> SB_TO_P0_CLKOUT_L0<57>

+1.2V_HT

SB_TO_P0_CTLOUT_H0<57> SB_TO_P0_CTLOUT_L0<57>

R747 49.9_1%R747 49.9_1% R732 49.9_1%R732 49.9_1%

2

U65B

L1_CLKOUT_H(1)

L1_CLKOUT_L(1)

L1_CLKOUT_H(0)

L1_CLKOUT_L(0)

L1_CTLOUT_H(1)

L1_CTLOUT_L(1)

L1_CTLOUT_H(0)

L1_CTLOUT_L(0)

L1_CADOUT_H(15)

L1_CADOUT_L(15)

L1_CADOUT_H(14)

L1_CADOUT_L(14)

L1_CADOUT_H(13)

L1_CADOUT_L(13)

L1_CADOUT_H(12)

L1_CADOUT_L(12)

L1_CADOUT_H(11)

L1_CADOUT_L(11)

L1_CADOUT_H(10)

L1_CADOUT_L(10)

L1_CADOUT_H(9)

L1_CADOUT_L(9)

L1_CADOUT_H(8)

L1_CADOUT_L(8)

L1_CADOUT_H(7)

L1_CADOUT_L(7)

L1_CADOUT_H(6)

L1_CADOUT_L(6)

L1_CADOUT_H(5)

L1_CADOUT_L(5)

L1_CADOUT_H(4)

L1_CADOUT_L(4)

L1_CADOUT_H(3)

L1_CADOUT_L(3)

L1_CADOUT_H(2)

L1_CADOUT_L(2)

L1_CADOUT_H(1)

L1_CADOUT_L(1)

L1_CADOUT_H(0)

L1_CADOUT_L(0)

SOCKET-F(1207)

1

E6 D6 B6 B7

F10 F11 C11 D11

E10 D10 F8 F9 E8 D8 F6 F7 F4 F5 E4 D4 F2 F3 E2 D2

B10 B11 C9 D9 B8 B9 C7 D7 C5 D5 B4 B5 C3 D3 B2 B3

P0_TO_SB_CLKOUT_H1 <57> P0_TO_SB_CLKOUT_L1 <57> P0_TO_SB_CLKOUT_H0 <57> P0_TO_SB_CLKOUT_L0 <57>

P0_TO_SB_CTLOUT_H0 <57> P0_TO_SB_CTLOUT_L0 <57>

P0_TO_SB_CADOUT_H15 <57> P0_TO_SB_CADOUT_L15 <57> P0_TO_SB_CADOUT_H14 <57> P0_TO_SB_CADOUT_L14 <57> P0_TO_SB_CADOUT_H13 <57> P0_TO_SB_CADOUT_L13 <57> P0_TO_SB_CADOUT_H12 <57> P0_TO_SB_CADOUT_L12 <57> P0_TO_SB_CADOUT_H11 <57> P0_TO_SB_CADOUT_L11 <57> P0_TO_SB_CADOUT_H10 <57> P0_TO_SB_CADOUT_L10 <57> P0_TO_SB_CADOUT_H9 <57> P0_TO_SB_CADOUT_L9 <57> P0_TO_SB_CADOUT_H8 <57> P0_TO_SB_CADOUT_L8 <57>

P0_TO_SB_CADOUT_H7 <57> P0_TO_SB_CADOUT_L7 <57> P0_TO_SB_CADOUT_H6 <57> P0_TO_SB_CADOUT_L6 <57> P0_TO_SB_CADOUT_H5 <57> P0_TO_SB_CADOUT_L5 <57> P0_TO_SB_CADOUT_H4 <57> P0_TO_SB_CADOUT_L4 <57> P0_TO_SB_CADOUT_H3 <57> P0_TO_SB_CADOUT_L3 <57> P0_TO_SB_CADOUT_H2 <57> P0_TO_SB_CADOUT_L2 <57> P0_TO_SB_CADOUT_H1 <57> P0_TO_SB_CADOUT_L1 <57> P0_TO_SB_CADOUT_H0 <57> P0_TO_SB_CADOUT_L0 <57>

U65C

P3_TO_P0_CLKOUT_H1<46> P3_TO_P0_CLKOUT_L1<46> P3_TO_P0_CLKOUT_H0<46> P3_TO_P0_CLKOUT_L0<46>

P3_TO_P0_CTLOUT_H1<46> P3_TO_P0_CTLOUT_L1<46>

P3_TO_P0_CTLOUT_H0<46> P3_TO_P0_CTLOUT_L0<46>

B B

A A

P3_TO_P0_CADOUT_H15<46> P3_TO_P0_CADOUT_L15<46> P3_TO_P0_CADOUT_H14<46> P3_TO_P0_CADOUT_L14<46> P3_TO_P0_CADOUT_H13<46> P3_TO_P0_CADOUT_L13<46> P3_TO_P0_CADOUT_H12<46> P3_TO_P0_CADOUT_L12<46> P3_TO_P0_CADOUT_H11<46> P3_TO_P0_CADOUT_L11<46> P3_TO_P0_CADOUT_H10<46> P3_TO_P0_CADOUT_L10<46>

P3_TO_P0_CADOUT_H9<46>

P3_TO_P0_CADOUT_L9<46>

P3_TO_P0_CADOUT_H8<46>

P3_TO_P0_CADOUT_L8<46>

P3_TO_P0_CADOUT_H7<46>

P3_TO_P0_CADOUT_L7<46>

P3_TO_P0_CADOUT_H6<46>

P3_TO_P0_CADOUT_L6<46>

P3_TO_P0_CADOUT_H5<46>

P3_TO_P0_CADOUT_L5<46>

P3_TO_P0_CADOUT_H4<46>

P3_TO_P0_CADOUT_L4<46>

P3_TO_P0_CADOUT_H3<46>

P3_TO_P0_CADOUT_L3<46>

P3_TO_P0_CADOUT_H2<46>

P3_TO_P0_CADOUT_L2<46>

P3_TO_P0_CADOUT_H1<46>

P3_TO_P0_CADOUT_L1<46>

P3_TO_P0_CADOUT_H0<46>

P3_TO_P0_CADOUT_L0<46>

5

AK7 AK8 AM7 AN7

AM12

AL12 AP11 AP12

AK11 AK12 AM10

AL10

AK9

AK10

AM8 AL8 AM6 AL6 AK5 AK6 AM4 AL4 AK3 AK4

AM11 AN11

AP9

AP10

AM9 AN9 AP7 AP8 AP5 AP6 AM5 AN5 AP3 AP4 AM3 AN3

L2_CLKIN_H(1) L2_CLKIN_L(1) L2_CLKIN_H(0) L2_CLKIN_L(0)

L2_CTLIN_H(1) L2_CTLIN_L(1) L2_CTLIN_H(0) L2_CTLIN_L(0)

L2_CADIN_H(15) L2_CADIN_L(15) L2_CADIN_H(14) L2_CADIN_L(14) L2_CADIN_H(13) L2_CADIN_L(13) L2_CADIN_H(12) L2_CADIN_L(12) L2_CADIN_H(11) L2_CADIN_L(11) L2_CADIN_H(10) L2_CADIN_L(10) L2_CADIN_H(9) L2_CADIN_L(9) L2_CADIN_H(8) L2_CADIN_L(8)

L2_CADIN_H(7) L2_CADIN_L(7) L2_CADIN_H(6) L2_CADIN_L(6) L2_CADIN_H(5) L2_CADIN_L(5) L2_CADIN_H(4) L2_CADIN_L(4) L2_CADIN_H(3) L2_CADIN_L(3) L2_CADIN_H(2) L2_CADIN_L(2) L2_CADIN_H(1) L2_CADIN_L(1) L2_CADIN_H(0) L2_CADIN_L(0)

L2_CLKOUT_H(1)

L2_CLKOUT_L(1)

L2_CLKOUT_H(0)

L2_CLKOUT_L(0) L2_CTLOUT_H(1)

L2_CTLOUT_L(1) L2_CTLOUT_H(0) L2_CTLOUT_L(0)

L2_CADOUT_H(15)

L2_CADOUT_L(15)

L2_CADOUT_H(14)

L2_CADOUT_L(14)

L2_CADOUT_H(13)

L2_CADOUT_L(13)

L2_CADOUT_H(12)

L2_CADOUT_L(12)

L2_CADOUT_H(11)

L2_CADOUT_L(11)

L2_CADOUT_H(10)

L2_CADOUT_L(10)

L2_CADOUT_H(9) L2_CADOUT_L(9) L2_CADOUT_H(8) L2_CADOUT_L(8)

L2_CADOUT_H(7) L2_CADOUT_L(7) L2_CADOUT_H(6) L2_CADOUT_L(6) L2_CADOUT_H(5) L2_CADOUT_L(5) L2_CADOUT_H(4) L2_CADOUT_L(4) L2_CADOUT_H(3) L2_CADOUT_L(3) L2_CADOUT_H(2) L2_CADOUT_L(2) L2_CADOUT_H(1) L2_CADOUT_L(1) L2_CADOUT_H(0) L2_CADOUT_L(0)

SOCKET-F(1207)

AM18 AN18 AR18 AR17

AL14 AL13 AP13 AN13

AM14 AN14 AL16 AL15 AM16 AN16 AL18 AL17 AL20 AL19 AM20 AN20 AL22 AL21 AM22 AN22

AR14 AR13 AP15 AN15 AR16 AR15 AP17 AN17 AP19 AN19 AR20 AR19 AP21 AN21 AR22 AR21

4

P0_TO_P3_CLKOUT_H1 <46> P0_TO_P3_CLKOUT_L1 <46> P0_TO_P3_CLKOUT_H0 <46> P0_TO_P3_CLKOUT_L0 <46>

P0_TO_P3_CTLOUT_H1 <46> P0_TO_P3_CTLOUT_L1 <46> P0_TO_P3_CTLOUT_H0 <46> P0_TO_P3_CTLOUT_L0 <46>

P0_TO_P3_CADOUT_H15 <46> P0_TO_P3_CADOUT_L15 <46> P0_TO_P3_CADOUT_H14 <46> P0_TO_P3_CADOUT_L14 <46> P0_TO_P3_CADOUT_H13 <46> P0_TO_P3_CADOUT_L13 <46> P0_TO_P3_CADOUT_H12 <46> P0_TO_P3_CADOUT_L12 <46> P0_TO_P3_CADOUT_H11 <46> P0_TO_P3_CADOUT_L11 <46> P0_TO_P3_CADOUT_H10 <46> P0_TO_P3_CADOUT_L10 <46> P0_TO_P3_CADOUT_H9 <46> P0_TO_P3_CADOUT_L9 <46> P0_TO_P3_CADOUT_H8 <46> P0_TO_P3_CADOUT_L8 <46>

P0_TO_P3_CADOUT_H7 <46> P0_TO_P3_CADOUT_L7 <46> P0_TO_P3_CADOUT_H6 <46> P0_TO_P3_CADOUT_L6 <46> P0_TO_P3_CADOUT_H5 <46> P0_TO_P3_CADOUT_L5 <46> P0_TO_P3_CADOUT_H4 <46> P0_TO_P3_CADOUT_L4 <46> P0_TO_P3_CADOUT_H3 <46> P0_TO_P3_CADOUT_L3 <46> P0_TO_P3_CADOUT_H2 <46> P0_TO_P3_CADOUT_L2 <46> P0_TO_P3_CADOUT_H1 <46> P0_TO_P3_CADOUT_L1 <46> P0_TO_P3_CADOUT_H0 <46> P0_TO_P3_CADOUT_L0 <46>

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

3

2

Date: Sheet

CPU0 HT Interface

MS-9184

1

0ACustom

of

19 92Tuesday, September 05, 2006

5

U65D

P0_MA_CLK_P0<22> P0_MA_CLK_N0<22>

P0_MA0_CS1<22,26>

D D

C C

B B

A A

P0_MA0_CS0<22,26> P0_MA_ODT0<22,26> P0_MA_CLK_P1<23>

P0_MA_CLK_N1<23> P0_MA1_CS1<23,26>

P0_MA1_CS0<23,26> P0_MA_ODT1<23,26>

P0_MA2_CS1<22,26> P0_MA2_CS0<22,26>

P0_MA_ODT2<22,26>

P0_MA3_CS1<23,26> P0_MA3_CS0<23,26>

P0_MA_ODT3<23,26>

P0_MA_ERR_R_N<26>

P0_MA_PAR<22,23,26> P0_MA_CAS_N<22,23,26> P0_MA_RAS_N<22,23,26> P0_MA_WE_N<22,23,26> P0_MA_RESET_N<22,23>

P0_MA_BA2<22,23,26> P0_MA_BA1<22,23,26> P0_MA_BA0<22,23,26>

P0_MA_CKE1<23,26> P0_MA_CKE0<22,26>

P0_MA_A15<22,23,26> P0_MA_A14<22,23,26> P0_MA_A13<22,23,26> P0_MA_A12<22,23,26> P0_MA_A11<22,23,26> P0_MA_A10<22,23,26> P0_MA_A9<22,23,26> P0_MA_A8<22,23,26> P0_MA_A7<22,23,26> P0_MA_A6<22,23,26> P0_MA_A5<22,23,26> P0_MA_A4<22,23,26> P0_MA_A3<22,23,26> P0_MA_A2<22,23,26> P0_MA_A1<22,23,26> P0_MA_A0<22,23,26>

P0_MA_DQS_P17<22,23> P0_MA_DQS_N17<22,23> P0_MA_DQS_P16<22,23> P0_MA_DQS_N16<22,23> P0_MA_DQS_P15<22,23> P0_MA_DQS_N15<22,23> P0_MA_DQS_P14<22,23> P0_MA_DQS_N14<22,23> P0_MA_DQS_P13<22,23> P0_MA_DQS_N13<22,23> P0_MA_DQS_P12<22,23> P0_MA_DQS_N12<22,23> P0_MA_DQS_P11<22,23> P0_MA_DQS_N11<22,23> P0_MA_DQS_P10<22,23> P0_MA_DQS_N10<22,23> P0_MA_DQS_P9<22,23> P0_MA_DQS_N9<22,23> P0_MA_DQS_P8<22,23> P0_MA_DQS_N8<22,23> P0_MA_DQS_P7<22,23> P0_MA_DQS_N7<22,23> P0_MA_DQS_P6<22,23> P0_MA_DQS_N6<22,23> P0_MA_DQS_P5<22,23> P0_MA_DQS_N5<22,23> P0_MA_DQS_P4<22,23> P0_MA_DQS_N4<22,23> P0_MA_DQS_P3<22,23> P0_MA_DQS_N3<22,23> P0_MA_DQS_P2<22,23> P0_MA_DQS_N2<22,23>

P0_MA_DQS_P1<22,23>

P0_MA_DQS_N1<22,23> P0_MA_DQS_P0<22,23> P0_MA_DQS_N0<22,23>

5

AD31 AD32

AM34 AH33

AJ32

AE31 AF31

AM35 AH34

AK34

AC30 AB32

AB31 AA31

AA32 AD30

AB30 AC32

AF32

AJ33

AH32

AJ31

AF33 AG32

M30 M31

M32

AL34

AG31

AE33

AL26 AM26 AL31 AM31 AH29 AG29 AB27 AC27

AK25 AK26 AK30 AK31 AH28

AJ28 AD26 AD27

G29

Y30 Y31

P30

D33 N32

N30 P31

R30 P32

T31 R31 T32 U30 U32 U31 Y33 V33

T27 T26

J31

J32 L29 K29 D31 D32 F27 F26 U25 U26

K33

J33 H29

F31 E31 D27 D26

MA0_CLK_H MA0_CLK_L

MA0_CS_L(1) MA0_CS_L(0)

MA0_ODT(0) MA1_CLK_H

MA1_CLK_L MA1_CS_L(1)

MA1_CS_L(0) MA1_ODT(0) MA2_CLK_H

MA2_CLK_L MA2_CS_L(1)

MA2_CS_L(0) MA2_ODT(0) MA3_CLK_H

MA3_CLK_L MA3_CS_L(1)

MA3_CS_L(0) MA3_ODT(0) MA_ERR_L

MA_PAR MA_CAS_L MA_RAS_L MA_WE_L MA_RESET_L

MA_BANK(2) MA_BANK(1) MA_BANK(0)

MA_CKE(1) MA_CKE(0)

MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)

MA_DQS_H(17) MA_DQS_L(17) MA_DQS_H(16) MA_DQS_L(16) MA_DQS_H(15) MA_DQS_L(15) MA_DQS_H(14) MA_DQS_L(14) MA_DQS_H(13) MA_DQS_L(13) MA_DQS_H(12) MA_DQS_L(12) MA_DQS_H(11) MA_DQS_L(11) MA_DQS_H(10) MA_DQS_L(10) MA_DQS_H(9) MA_DQS_L(9) MA_DQS_H(8) MA_DQS_L(8) MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)

SOCKET-F(1207)

4

MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)

MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)

MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)

4

AM24 AM25 AL28 AK28 AK24 AL24 AM27 AL27 AK29 AM30 AL33 AK33 AM29 AL29 AM32 AL32 AF28 AF29 AG30 AE30 AE28 AE29 AH30 AJ30 AB25 AB26 AC29 AB29 AC25 AD25 AD28 AC28 L31 K31 G32 G31 L32 L33 H33 H32 H30 G30 K28 L28 K30 J30 H28 J28 E33 D35 F29 E29 F33 F32 E30 D30 F28 E26 B24 C24 E28 D28 E25 D25

V29 V27 R29 R28 V25 V28 R25 R26

P0_MA_DATA63 <22,23> P0_MA_DATA62 <22,23> P0_MA_DATA61 <22,23> P0_MA_DATA60 <22,23> P0_MA_DATA59 <22,23> P0_MA_DATA58 <22,23> P0_MA_DATA57 <22,23> P0_MA_DATA56 <22,23> P0_MA_DATA55 <22,23> P0_MA_DATA54 <22,23> P0_MA_DATA53 <22,23> P0_MA_DATA52 <22,23> P0_MA_DATA51 <22,23> P0_MA_DATA50 <22,23> P0_MA_DATA49 <22,23> P0_MA_DATA48 <22,23> P0_MA_DATA47 <22,23> P0_MA_DATA46 <22,23> P0_MA_DATA45 <22,23> P0_MA_DATA44 <22,23> P0_MA_DATA43 <22,23> P0_MA_DATA42 <22,23> P0_MA_DATA41 <22,23> P0_MA_DATA40 <22,23> P0_MA_DATA39 <22,23> P0_MA_DATA38 <22,23> P0_MA_DATA37 <22,23> P0_MA_DATA36 <22,23> P0_MA_DATA35 <22,23> P0_MA_DATA34 <22,23> P0_MA_DATA33 <22,23> P0_MA_DATA32 <22,23> P0_MA_DATA31 <22,23> P0_MA_DATA30 <22,23> P0_MA_DATA29 <22,23> P0_MA_DATA28 <22,23> P0_MA_DATA27 <22,23> P0_MA_DATA26 <22,23> P0_MA_DATA25 <22,23> P0_MA_DATA24 <22,23> P0_MA_DATA23 <22,23> P0_MA_DATA22 <22,23> P0_MA_DATA21 <22,23> P0_MA_DATA20 <22,23> P0_MA_DATA19 <22,23> P0_MA_DATA18 <22,23> P0_MA_DATA17 <22,23> P0_MA_DATA16 <22,23> P0_MA_DATA15 <22,23> P0_MA_DATA14 <22,23> P0_MA_DATA13 <22,23> P0_MA_DATA12 <22,23> P0_MA_DATA11 <22,23> P0_MA_DATA10 <22,23> P0_MA_DATA9 <22,23> P0_MA_DATA8 <22,23> P0_MA_DATA7 <22,23> P0_MA_DATA6 <22,23> P0_MA_DATA5 <22,23> P0_MA_DATA4 <22,23> P0_MA_DATA3 <22,23> P0_MA_DATA2 <22,23> P0_MA_DATA1 <22,23> P0_MA_DATA0 <22,23>

P0_MA_ECC7 <22,23> P0_MA_ECC6 <22,23> P0_MA_ECC5 <22,23> P0_MA_ECC4 <22,23> P0_MA_ECC3 <22,23> P0_MA_ECC2 <22,23> P0_MA_ECC1 <22,23> P0_MA_ECC0 <22,23>

3

TP114TP114 TP113TP113

TP116TP116 TP115TP115

AJ35

AE35

AG34

AA34 AA33

AK35

AD35 AG35

W31

W32

W30

W33

AB34 AF34

AD33

AE34

AC34 AC33

AH35

AC35

W35

AB35

AN28 AN27 AN33 AN32 AG27 AH27

AA29 AA28

AP26 AP27 AP31 AP32

AJ26 AJ27 W26 W27

Y35 Y34

U29 U28

V32

T29 T28

V30

P33

A33 N33

M34 M35

N34 N35

P35 R34

R35 T34 R33 T33 U35 U34 V35

V34

M29 N29

G34 G35 K26

A31 A32 A26 A27 N27 N28

H35 H34 H27 G27 C32 B32 B27 C27

J26

P0_MB_CLK_P0<24> P0_MB_CLK_N0<24>

P0_MB0_CS1<24,26> P0_MB0_CS0<24,26>

P0_MB_ODT0<24,26>

P0_MB_CLK_P1<25> P0_MB_CLK_N1<25>

P0_MB1_CS1<25,26> P0_MB1_CS0<25,26>

P0_MB_ODT1<25,26>

P0_MB2_CS1<24,26> P0_MB2_CS0<24,26>

P0_MB_ODT2<24,26>

P0_MB3_CS1<25,26> P0_MB3_CS0<25,26>

P0_MB_ODT3<25,26>

P0_MB_ERR_R_N<26> P0_MB_PAR<24,25,26> P0_MB_CAS_N<24,25,26> P0_MB_RAS_N<24,25,26> P0_MB_WE_N<24,25,26> P0_MB_RESET_N<24,25>

P0_MB_BA2<24,25,26> P0_MB_BA1<24,25,26> P0_MB_BA0<24,25,26>

P0_MB_CKE1<25,26> P0_MB_CKE0<24,26>

P0_MB_A15<24,25,26> P0_MB_A14<24,25,26> P0_MB_A13<24,25,26> P0_MB_A12<24,25,26> P0_MB_A11<24,25,26> P0_MB_A10<24,25,26> P0_MB_A9<24,25,26> P0_MB_A8<24,25,26> P0_MB_A7<24,25,26> P0_MB_A6<24,25,26> P0_MB_A5<24,25,26> P0_MB_A4<24,25,26> P0_MB_A3<24,25,26> P0_MB_A2<24,25,26> P0_MB_A1<24,25,26> P0_MB_A0<24,25,26>

P0_MB_DQS_P17<24,25> P0_MB_DQS_N17<24,25> P0_MB_DQS_P16<24,25> P0_MB_DQS_N16<24,25> P0_MB_DQS_P15<24,25> P0_MB_DQS_N15<24,25> P0_MB_DQS_P14<24,25> P0_MB_DQS_N14<24,25> P0_MB_DQS_P13<24,25> P0_MB_DQS_N13<24,25> P0_MB_DQS_P12<24,25> P0_MB_DQS_N12<24,25> P0_MB_DQS_P11<24,25> P0_MB_DQS_N11<24,25> P0_MB_DQS_P10<24,25> P0_MB_DQS_N10<24,25> P0_MB_DQS_P9<24,25> P0_MB_DQS_N9<24,25> P0_MB_DQS_P8<24,25> P0_MB_DQS_N8<24,25> P0_MB_DQS_P7<24,25> P0_MB_DQS_N7<24,25> P0_MB_DQS_P6<24,25> P0_MB_DQS_N6<24,25> P0_MB_DQS_P5<24,25> P0_MB_DQS_N5<24,25> P0_MB_DQS_P4<24,25> P0_MB_DQS_N4<24,25> P0_MB_DQS_P3<24,25>

P0_MB_DQS_P2<24,25> P0_MB_DQS_N2<24,25> P0_MB_DQS_P1<24,25> P0_MB_DQS_N1<24,25> P0_MB_DQS_P0<24,25> P0_MB_DQS_N0<24,25>

3

MB0_CLK_H MB0_CLK_L

MB0_CS_L(1) MB0_CS_L(0)

MB0_ODT(0) MB1_CLK_H

MB1_CLK_L MB1_CS_L(1)

MB1_CS_L(0) MB1_ODT(0) MB2_CLK_H

MB2_CLK_L MB2_CS_L(1)

MB2_CS_L(0) MB2_ODT(0) MB3_CLK_H

MB3_CLK_L MB3_CS_L(1)

MB3_CS_L(0) MB3_ODT(0) MB_ERR_L

MB_PAR MB_CAS_L MB_RAS_L MB_WE_L MB_RESET_L

MB_BANK(2) MB_BANK(1) MB_BANK(0)

MB_CKE(1) MB_CKE(0)

MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)

MB_DQS_H(17) MB_DQS_L(17) MB_DQS_H(16) MB_DQS_L(16) MB_DQS_H(15) MB_DQS_L(15) MB_DQS_H(14) MB_DQS_L(14) MB_DQS_H(13) MB_DQS_L(13) MB_DQS_H(12) MB_DQS_L(12) MB_DQS_H(11) MB_DQS_L(11) MB_DQS_H(10) MB_DQS_L(10) MB_DQS_H(9) MB_DQS_L(9) MB_DQS_H(8) MB_DQS_L(8) MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)

SOCKET-F(1207)

2

U65E

AN25

MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)

MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)

MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)

2

P0_MB_DATA63 <24,25>

AR26

P0_MB_DATA62 <24,25>

AN29

P0_MB_DATA61 <24,25>

AR29

P0_MB_DATA60 <24,25>

AP25

P0_MB_DATA59 <24,25>

AR25

P0_MB_DATA58 <24,25>

AR28

P0_MB_DATA57 <24,25>

AP28

P0_MB_DATA56 <24,25>

AN30

P0_MB_DATA55 <24,25>

AR31

P0_MB_DATA54 <24,25>

AR34

P0_MB_DATA53 <24,25>

AN34

P0_MB_DATA52 <24,25>

AR30

P0_MB_DATA51 <24,25>

AP30

P0_MB_DATA50 <24,25>

AR33

P0_MB_DATA49 <24,25>

AP33

P0_MB_DATA48 <24,25>

AG25

P0_MB_DATA47 <24,25>

AE25

P0_MB_DATA46 <24,25>

AF26

P0_MB_DATA45 <24,25>

AE26

P0_MB_DATA44 <24,25>

AF24

P0_MB_DATA43 <24,25>

AE24

P0_MB_DATA42 <24,25>

AG26

P0_MB_DATA41 <24,25>

AF27

P0_MB_DATA40 <24,25>

Y26

P0_MB_DATA39 <24,25>

AA27

P0_MB_DATA38 <24,25>

W28

P0_MB_DATA37 <24,25>

W25

P0_MB_DATA36 <24,25>

Y25

P0_MB_DATA35 <24,25>

AA26

P0_MB_DATA34 <24,25>

Y28

P0_MB_DATA33 <24,25>

Y29

P0_MB_DATA32 <24,25>

K35

P0_MB_DATA31 <24,25>

J35

P0_MB_DATA30 <24,25>

E35

P0_MB_DATA29 <24,25>

C35

P0_MB_DATA28 <24,25>

L34

P0_MB_DATA27 <24,25>

K34

P0_MB_DATA26 <24,25>

F34

P0_MB_DATA25 <24,25>

E34

P0_MB_DATA24 <24,25>

L24

P0_MB_DATA23 <24,25>

J27

P0_MB_DATA22 <24,25>

K25

P0_MB_DATA21 <24,25>

K24

P0_MB_DATA20 <24,25>

L27

P0_MB_DATA19 <24,25>

L26

P0_MB_DATA18 <24,25>

G26

P0_MB_DATA17 <24,25>

J25

P0_MB_DATA16 <24,25>

B34

P0_MB_DATA15 <24,25>

A34

P0_MB_DATA14 <24,25>

C30

P0_MB_DATA13 <24,25>

C29

P0_MB_DATA12 <24,25>

C34

P0_MB_DATA11 <24,25>

C33

P0_MB_DATA10 <24,25>

B31

P0_MB_DATA9 <24,25>

B30

P0_MB_DATA8 <24,25>

C28

P0_MB_DATA7 <24,25>

A28

P0_MB_DATA6 <24,25>

B25

P0_MB_DATA5 <24,25>

A24

P0_MB_DATA4 <24,25>

A29

P0_MB_DATA3 <24,25>

B29

P0_MB_DATA2 <24,25>

B26

P0_MB_DATA1 <24,25>

C25

P0_MB_DATA0 <24,25>

P27

P0_MB_ECC7 <24,25>

P28

P0_MB_ECC6 <24,25>P0_MB_DQS_N3<24,25>

N25

P0_MB_ECC5 <24,25>

M25

P0_MB_ECC4 <24,25>

P25

P0_MB_ECC3 <24,25>

P26

P0_MB_ECC2 <24,25>

M26

P0_MB_ECC1 <24,25>

M27

P0_MB_ECC0 <24,25>

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

1

CPU0 Memory Interface

MS-9184

20 92Tuesday, September 05, 2006

1

0ACustom

of

5

C8573300p-0402 C8573300p-0402

C8620.22u_16V C8620.22u_16V

P0_VDDA_2.5V

3900p_50V

R1103

C1273

169_1%

C1267

C1267 3900p_50V

3900p_50V

P0_PWROK P0_RESET_J P0_LDTSTOP_N

P0_SIC

P0_VTTSENSE P0_M_VREF

P0_M_ZN P0_M_ZP

TP100TP100

R761 300RR761 300R R720 300RR720 300R

TP94TP94 TP97TP97

P0_TEST25_H P0_TEST25_L

R647 300RR647 300R

TP91TP91 TP95TP95 TP96TP96 TP101TP101 TP90TP90

TP89TP89

R648 39.2_1% R648 39.2_1% R646 39.2_1% R646 39.2_1%

R1102 44.2_1%R1102 44.2_1% R1105 44.2_1%R1105 44.2_1%

C8634.7u_6.3V-0805 C8634.7u_6.3V-0805

G2 G3 G4

K22

J22

F21 F19 H25

AP1

AG19

AF19 AJ22

AG22

AF22 AJ21

F24

J9

J10

AF17

F18

AJ25

AH25

AF20

F23 F20

AG8 AG9

G21 H21

AJ20 AH20 AG20 AG21

AF21 AH21

AF18

U8

AH9

VDDA1 VDDA2 VDDA3

CLKIN_H CLKIN_L

PWROK RESET_L LDTSTOP_L

CPU_PRESENT_L

SIC SID

TDI TRST_L TCK TMS

DBREQ_L VDD_FB_H

VDD_FB_L VTT_SENSE M_VREF

M_ZN M_ZP

TEST23 TEST18

TEST19 TEST2

TEST3 TEST25_H

TEST25_L TEST21

TEST20 TEST24 TEST22 TEST12 TEST27 TEST26

TEST9 TEST6

SOCKET-F(1207)

U65F

THERMTRIP_L

TEST pins need more detail check

C859

0.1u_16V

C861

0.1u_16V

P0_M_ZN P0_M_ZP

P0_HTREF1 P0_HTREF0

P0_M_VREF

C8601nC860

1n

VID(5) VID(4) VID(3) VID(2) VID(1) VID(0)

PROCHOT_L

DBRDY

VDDIO_FB_H

VDDIO_FB_L

HTREF1 HTREF0

TEST4 TEST5

TEST13

TEST28_H

TEST28_L

TEST17 TEST16 TEST15 TEST14

TEST7

TEST10

TEST8

TEST29_H

TEST29_L

P0_P1V8

E24 G18 J19 H19 K19 H18

AH19 AJ19

AH22

TDO

J24 AG17

AH17

V7 U7

AF8 AF9

AH8 L8

M9 J20

G20 K20 H20

J8 V8

H8 G23

G24

P0_TDO_P1_TDI

R722 510R722 510 R754 510R754 510

P0_TEST29_H P0_TEST29_L

R644 300RR644 300R R742 300RR742 300R

R727 300RR727 300R R719 300RR719 300R

R656 X_300RR656 X_300R R655 300RR655 300R

R645 300RR645 300R

+2.5VPLL_0

P0_CPUCLKIN<6>

P0_CPUCLKINJ<6>

D D

H0_PRESENT_N<7,15,62>

P0_VTT_0.9V

C C

B B

MEN ZN/ZP

DRIVE STRENGTH

L11 180nH_.45A-1210L11 180nH_.45A-1210

P0_PWROK<57>

P0_RESET_J<57>

P0_LDTSTOP_N<57>

H0_PRESENT_N

P0_TDI<55> PX_TRSTJ<30,39,48,55,56> P0_TCK<55> P0_TMS<55>

P0_DBREQJ<55> P0_DBRDY <55>

P0_VCORE_FB_P<7> P0_VCORE_FB_N<7>

R649 0_0402R649 0_0402

P0_P1V8

R643 300RR643 300R

P0_P1V8

R792

R792 100_1%

100_1%

R793

R793 100_1%

100_1%

P0_P1V8

+1.2V_HT

4

P0_VID5 <7,83> P0_VID4 <7,83> P0_VID3 <7,83> P0_VID2 <7,83>

P0_VID1

P0_VID1 <7,83> P0_VID0 <7,83>

P0_THERM_N P0_PROCHOT_N

P0_TDO_P1_TDI

P0_HTREF1 P0_HTREF0

TP117TP117 TP118TP118

TP124TP124 TP133TP133 TP120TP120 TP127TP127

TP123TP123 TP111TP111

TP125TP125

P0_TEST29_H P0_TEST29_L

ROUTE AS 80 OHM DIFF IMPEDANCE

P0_THERM_N <57>

P0_TDO_P1_TDI <30,55>

P0_P1V8SENSE+ <15> P0_P1V8SENSE- <15>

TO SI/O,LAYOUT DISTANCE CAREFULLY

H0_THERMDA <83> H0_THERMDC <83>

TP92TP92

P0_TEST25_H P0_TEST25_L

R756

80.6_1%

P0_VID1 P0_PWROK

P0_RESET_J P0_LDTSTOP_N

P0_THERM_N P0_PROCHOT_N

P0_SIC

P0_VCORE

AA10 AA12 AA14 AA16 AA18 AA20

AB11 AB13 AB15 AB17 AB19 AB21

AC10 AC12 AC14 AC16 AC18 AC20

AD11 AD13 AD15 AD17 AD19 AD21

AE10 AE12 AE14 AE16 AE18 AE20

AF11 AF13 AF15

AG10 AG12 AG14 AG16

AH11 AH13 AH15

AJ10 AJ12 AJ14 AJ16

AK13 AK15 AK17 AK19 AK21

AM13 AM17 AM21

AN12 AP16 AP20

AR10

A10

AA8

AB4 AB5 AB7 AB9

AC2 AC3 AC8

AD7 AD9

AE8

AF4 AF5 AF7

AG2 AG3

AH5 AH7

AJ2 AJ4 AJ6 AJ8

AK1

AL2 AL5 AL9 AM1

AN4 AN8

AR6 B15

B19

C10 C12 D16 D20

E11 E12 F13 F15 F17

G10 G12 G14 G16

H13 H15 H17

J12 J14 J16

A6

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD76 VDD77 VDD78 VDD79 VDD80 VDD81 VDD82 VDD83 VDD84 VDD85 VDD86 VDD87 VDD88 VDD89 VDD90

C2

VDD91

C6

VDD92 VDD93 VDD94 VDD95 VDD96

E3

VDD97

E7

VDD98 VDD99 VDD100 VDD101 VDD102 VDD103

G1

VDD104

G6

VDD105

G8

VDD106 VDD107 VDD108 VDD109 VDD110

H7

VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117

K4

VDD118

K5

VDD119

K7

VDD120

SOCKET-F(1207)

U65H

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99

VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120

A5 A9 A25 A30 AA2 AA3 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB28 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AC26 AD4 AD5 AD8 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD29 AE2 AE3 AE7 AE9 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE27 AF10 AF12 AF14 AF16 AF25 AF30 AG7 AG11 AG13 AG15 AG23 AG28 AH6 AH10 AH12 AH14 AH16 AH24 AH26 AJ1 AJ3 AJ5 AJ7 AJ9 AJ11 AJ15 AJ17 AJ23 AJ24 AJ29 AK2 AK14 AK16 AK18 AK20 AK22 AK23 AK27 AK32 AL1 AL3 AL7 AL11 AL25 AL30 AM15 AM19 AM28 AM33 AN6 AN10 AN24 AN26 AN31 AN35 AP14 AP18 AP22 AP24 AP29

3

P0_VCORE

AA22 AA24 AB23 AC22 AC24 AD23 AE22 AF23 AG24 AH23

W22 W24

2

U65K

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21

VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10

VLDT_01 VLDT_02 VLDT_03 VLDT_04

VLDT_11 VLDT_12 VLDT_13 VLDT_14

VLDT_21 VLDT_22 VLDT_23 VLDT_24

SOCKET-F(1207)

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6

SOCKET-F(1207)

U65K

VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81

U65G

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11

N15 N17 N19 N21 N23 N26 P8 P10 P12 P14 P16 P18 P20 P22 P24 P29 R7 R9 R11 R13 R15 R17 R19 R21 R23 R27 T4 T5 T8 T10 T12 T14 T16 T18 T20 T22 T24 T25 U2 U3 U11 U13 U15 U17 U19 U21 U23 U27 V12 V14 V16 V18 V20 V22 V24 V26 W7 W9 W11 W13 W15 W17 W19 W21 W23 W29 Y4 Y5 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y27 T7 F12 AJ13

H10 H9

AJ18 AH18 AG18

U65I

U65J

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84

AP34 AP35 AR5 AR9 AR24 AR27 AR32 B12 B13 B17 B21 B28 B33 B35 C4 C8 C26 C31 D12 D14 D18 D22 D24 D29 D34 E5 E9 E27 E32 F14 F16 F22 F25 F30 F35 G5 G7 G9 G11 G13 G15 G17 G22 G25 G28 G33 H4 H5 H12 H14 H16 H22 H23 H24 H26 H31 J2 J3 J7 J13 J15 J17 J21 J23 J29 J34 K8 K10 K12 K14 K16 K18 K21 K23 K27 K32 L7 L9 L11 L13 L15 L17 U9 V10

L19 L21 L23 L25 L30 L35 M4 M5 M8 M10 M12 M14 M16 M18 M20 M22 M24 M28 N2 N3 N7 N9 N11 N13

K9

VDD1

K13

VDD2

K15

VDD3

K17

VDD4

L2

VDD5

L3

VDD6

L10

VDD7

L12

VDD8

L14

VDD9

L16

VDD10

L18

VDD11

L20

VDD12

M7

VDD13

M11

VDD14

M13

VDD15

M15

VDD16

M17

VDD17

M19

VDD18

M21

VDD19

N8

VDD20

N10

VDD21

N12

VDD22

N14

VDD23

N16

VDD24

N18

VDD25

N20

VDD26

P4

VDD27

P5

VDD28

P7

VDD29

P9

VDD30

P11

VDD31

P13

VDD32

P15

VDD33

P17

VDD34

P19

VDD35

P21

VDD36

R2

VDD37

R3

VDD38

R8

VDD39

R10

VDD40

R12

VDD41

R14

VDD42

R16

VDD43

R18

VDD44

R20

VDD45

T9

VDD46

T11

VDD47

T13

VDD48

T15

VDD49

T17

VDD50

T19

VDD51

T21

VDD52

U12

VDD53

U14

VDD54

U16

VDD55

U18

VDD56

U20

VDD57

V4

VDD58

V5

VDD59

V11

VDD60

V13

VDD61

V15

VDD62

V17

VDD63

V19

VDD64

V21

VDD65

W2

VDD66

W3

VDD67

W8

VDD68

W10

VDD69

W12

VDD70

W14

VDD71

W16

VDD72

W18

VDD73

W20

VDD74

Y7

VDD75

Y9

VDD76

Y11

VDD77

Y13

VDD78

Y15

VDD79

Y17

VDD80

Y19

VDD81

Y21

VDD82

V9

VDD83

U10

VDD84

SOCKET-F(1207)

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

L22

VDD11

M23

VDD12

N22

VDD13

N24

VDD14

P23

VDD15

R22

VDD16

R24

VDD17

T23

VDD18

U22

VDD19

U24

VDD20

V23

VDD21 VDD22 VDD23

Y23

VDD24

SOCKET-F(1207)

P0_VTT_0.9V

+1.2V_HT

P0_P1V8

AM23

AA30 AA35 AB33 AC31 AD34 AE32 AF35 AG33 AH31 AJ34 AL35

AN23 AP23 AR23

AL23

M33 N31 P34 R32

T30

T35 U33 V31

W34

Y32 A23

B23 C23 D23

E23 AH1

AH2 AH3 AH4

C1 D1

E1 F1

AM2

AN2 AP2 AR2

J18 G19 AN1 H11

J11 K11

1

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

CPU0 MISC/POWER/GND

MS-9184

21 92Tuesday, September 05, 2006

1

21 92Tuesday, September 05, 2006

0AC

of

5

4

3

2

1

P0_DIMM3A

D D

C C

B B

A A

P0_MA_WE_N<20,23,26> P0_MA_RAS_N<20,23,26> P0_MA_CAS_N<20,23,26>

P0_MA_A15<20,23,26> P0_MA_A14<20,23,26> P0_MA_A13<20,23,26> P0_MA_A12<20,23,26> P0_MA_A11<20,23,26> P0_MA_A10<20,23,26> P0_MA_A9<20,23,26> P0_MA_A8<20,23,26> P0_MA_A7<20,23,26> P0_MA_A6<20,23,26> P0_MA_A5<20,23,26> P0_MA_A4<20,23,26> P0_MA_A3<20,23,26> P0_MA_A2<20,23,26> P0_MA_A1<20,23,26> P0_MA_A0<20,23,26>

P0_MA2_CS0<20,26> P0_MA2_CS1<20,26>

P0_MA_CLK_P0<20> P0_MA_CLK_N0<20>

P0_MA0_CS1<20,26> P0_MA0_CS0<20,26>

P0_MA_CKE0<20,26> P0_MA_BA2<20,23,26> P0_MA_BA1<20,23,26> P0_MA_BA0<20,23,26>

SMB_0_DATA<23,24,25,78> SMB_0_CLK<23,24,25,78>

P0_DIMM_VREF<23,24,25>

P0_MA_ERR_N<23,26>

P0_MA_RESET_N<20,23>

P0_MA_ECC7<20,23> P0_MA_ECC6<20,23> P0_MA_ECC5<20,23> P0_MA_ECC4<20,23> P0_MA_ECC3<20,23> P0_MA_ECC2<20,23> P0_MA_ECC1<20,23> P0_MA_ECC0<20,23>

P0_MA_ODT2<20,26> P0_MA_ODT0<20,26>

P0_MA_DQS_N8<20,23> P0_MA_DQS_P8<20,23>

P0_MA_DQS_N7<20,23> P0_MA_DQS_P7<20,23>

P0_MA_DQS_N6<20,23> P0_MA_DQS_P6<20,23>

P0_MA_DQS_N5<20,23> P0_MA_DQS_P5<20,23>

P0_MA_DQS_N4<20,23> P0_MA_DQS_P4<20,23>

P0_MA_DQS_N3<20,23> P0_MA_DQS_P3<20,23>

P0_MA_DQS_N2<20,23> P0_MA_DQS_P2<20,23>

P0_MA_DQS_N1<20,23> P0_MA_DQS_P1<20,23>

P0_MA_DQS_N0<20,23> P0_MA_DQS_P0<20,23>

5

+3.3V

P0_DIMM_VREF

C973 0.1u_16VC973 0.1u_16V

73

WE_N

192

RAS_N

74

CAS_N

54

A16/BA2

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A09

179

A08

58

A07

180

A06

60

A05

61

A04

182

A03

63

A02

183

A01

188

A00

220

CK2P

221

CK2N

137

CK1P

138

CK1N

185

CK0P

186

CK0N

76

CS1_N

193

CS0_N

171

CKE1

52

CKE0

190

BA1

71

BA0

101

SA2

240

SA1

239

SA0

119

SDA

120

SCL

1

VREF

238

VDDSPD

55

RC0

18

RFU/RC1

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

77

ODT1

195

ODT0

45

DQS8N

46

DQS8P

113

DQS7N

114

DQS7P

104

DQS6N

105

DQS6P

92

DQS5N

93

DQS5P

83

DQS4N

84

DQS4P

36

DQS3N

37

DQS3P

27

DQS2N

28

DQS2P

15

DQS1N

16

DQS1P

6

DQS0N

7

DQS0P

DDRII

* P0_DIMM1 Slave Addr : 0XA0

DDRII 1/2

4

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ09 DQ08 DQ07 DQ06 DQ05 DQ04 DQ03 DQ02 DQ01 DQ00

NC/DQS17N NC/DQS17P

NC/DQS16N NC/DQS16P

NC/DQS15N NC/DQS15P

NC/DQS14N NC/DQS14P

NC/DQS13N NC/DQS13P

NC/DQS12N NC/DQS12P

NC/DQS11N NC/DQS11P

NC/DQS10N NC/DQS10P

NC/DQS09N NC/DQS09P

236 235 230 229 117 116 111 110 227 226 218 217 108 107 99 98 215 214 209 208 96 95 90 89 206 205 200 199 87 86 81 80 159 158 153 152 40 39 34 33 150 149 144 143 31 30 25 24 141 140 132 131 22 21 13 12 129 128 123 122 10 9 4 3

165 164

233 232

224 223

212 211

203 202

156 155

147 146

135 134

126 125

P0_MA_DATA63 <20,23> P0_MA_DATA62 <20,23> P0_MA_DATA61 <20,23> P0_MA_DATA60 <20,23> P0_MA_DATA59 <20,23> P0_MA_DATA58 <20,23> P0_MA_DATA57 <20,23> P0_MA_DATA56 <20,23> P0_MA_DATA55 <20,23> P0_MA_DATA54 <20,23> P0_MA_DATA53 <20,23> P0_MA_DATA52 <20,23> P0_MA_DATA51 <20,23> P0_MA_DATA50 <20,23> P0_MA_DATA49 <20,23> P0_MA_DATA48 <20,23> P0_MA_DATA47 <20,23> P0_MA_DATA46 <20,23> P0_MA_DATA45 <20,23> P0_MA_DATA44 <20,23> P0_MA_DATA43 <20,23> P0_MA_DATA42 <20,23> P0_MA_DATA41 <20,23> P0_MA_DATA40 <20,23> P0_MA_DATA39 <20,23> P0_MA_DATA38 <20,23> P0_MA_DATA37 <20,23> P0_MA_DATA36 <20,23> P0_MA_DATA35 <20,23> P0_MA_DATA34 <20,23> P0_MA_DATA33 <20,23> P0_MA_DATA32 <20,23> P0_MA_DATA31 <20,23> P0_MA_DATA30 <20,23> P0_MA_DATA29 <20,23> P0_MA_DATA28 <20,23> P0_MA_DATA27 <20,23> P0_MA_DATA26 <20,23> P0_MA_DATA25 <20,23> P0_MA_DATA24 <20,23> P0_MA_DATA23 <20,23> P0_MA_DATA22 <20,23> P0_MA_DATA21 <20,23> P0_MA_DATA20 <20,23> P0_MA_DATA19 <20,23> P0_MA_DATA18 <20,23> P0_MA_DATA17 <20,23> P0_MA_DATA16 <20,23> P0_MA_DATA15 <20,23> P0_MA_DATA14 <20,23> P0_MA_DATA13 <20,23> P0_MA_DATA12 <20,23> P0_MA_DATA11 <20,23> P0_MA_DATA10 <20,23> P0_MA_DATA9 <20,23> P0_MA_DATA8 <20,23> P0_MA_DATA7 <20,23> P0_MA_DATA6 <20,23> P0_MA_DATA5 <20,23> P0_MA_DATA4 <20,23> P0_MA_DATA3 <20,23> P0_MA_DATA2 <20,23> P0_MA_DATA1 <20,23> P0_MA_DATA0 <20,23>

P0_MA_DQS_N17 <20,23> P0_MA_DQS_P17 <20,23>

P0_MA_DQS_N16 <20,23> P0_MA_DQS_P16 <20,23>

P0_MA_DQS_N15 <20,23> P0_MA_DQS_P15 <20,23>

P0_MA_DQS_N14 <20,23> P0_MA_DQS_P14 <20,23>

P0_MA_DQS_N13 <20,23> P0_MA_DQS_P13 <20,23>

P0_MA_DQS_N12 <20,23> P0_MA_DQS_P12 <20,23>

P0_MA_DQS_N11 <20,23> P0_MA_DQS_P11 <20,23>

P0_MA_DQS_N10 <20,23> P0_MA_DQS_P10 <20,23>

P0_MA_DQS_N9 <20,23> P0_MA_DQS_P9 <20,23>

3

P0_MA_PAR<20,23,26>

P0_P1V8 P0_P1V8

P0_DIMM3B

197

VDD

189

VDD

187

VDD

184

VDD

178

VDD

172

VDD

69

VDD

67

VDD

64

VDD

59

VDD

53

VDD

102

NC

68

NC

19

NC

115

GND

112

GND

109

GND

106

GND

103

GND

100

GND

97

GND

94

GND

91

GND

88

GND

85

GND

82

GND

79

GND

66

GND

65

GND

50

GND

47

GND

44

GND

41

GND

38

GND

35

GND

32

GND

29

GND

26

GND

23

GND

20

GND

17

GND

14

GND

11

GND

8

GND

5

GND

2

GND

DDRII

P0_P1V8

10/04 Joe, not be defined in DesignGuide

P0_P1V8

2

DDRII 2/2

R924

C9361uC936

75_1%

1u

C976

R930

1u_6.3V

75_1%

P0_DIMM_VREF

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

Micro-Star Int'l Co., Ltd.

191

VDDQ

181

VDDQ

175

VDDQ

170

VDDQ

78

VDDQ

75

VDDQ

72

VDDQ

62

VDDQ

56

VDDQ

51

VDDQ

194

VDDQ

237

GND

234

GND

231

GND

228

GND

225

GND

222

GND

219

GND

216

GND

213

GND

210

GND

207

GND

204

GND

201

GND

198

GND

169

GND

166

GND

163

GND

160

GND

157

GND

154

GND

151

GND

148

GND

145

GND

142

GND

139

GND

136

GND

133

GND

130

GND

127

GND

124

GND

121

GND

118

GND

DDR2 Connector A1_P0

MS-9184

1

0ACustom

of

22 92Monday, August 28, 2006

5

P0_DIMM1A

P0_MA_WE_N<20,22,26> P0_MA_RAS_N<20,22,26> P0_MA_CAS_N<20,22,26>

P0_MA_A15<20,22,26>

D D

C C

B B

P0_MA_A14<20,22,26> P0_MA_A13<20,22,26> P0_MA_A12<20,22,26> P0_MA_A11<20,22,26> P0_MA_A10<20,22,26> P0_MA_A9<20,22,26> P0_MA_A8<20,22,26> P0_MA_A7<20,22,26> P0_MA_A6<20,22,26> P0_MA_A5<20,22,26> P0_MA_A4<20,22,26> P0_MA_A3<20,22,26> P0_MA_A2<20,22,26> P0_MA_A1<20,22,26> P0_MA_A0<20,22,26>

P0_MA3_CS0<20,26> P0_MA3_CS1<20,26>

P0_MA_CLK_P1<20> P0_MA_CLK_N1<20>

P0_MA1_CS1<20,26> P0_MA1_CS0<20,26>

P0_MA_CKE1<20,26> P0_MA_BA2<20,22,26> P0_MA_BA1<20,22,26> P0_MA_BA0<20,22,26>

+3.3V

SMB_0_DATA<22,24,25,78> SMB_0_CLK<22,24,25,78>

P0_DIMM_VREF<22,24,25>

P0_MA_ERR_N<22,26>

P0_MA_RESET_N<20,22>

P0_MA_ECC7<20,22> P0_MA_ECC6<20,22> P0_MA_ECC5<20,22> P0_MA_ECC4<20,22> P0_MA_ECC3<20,22> P0_MA_ECC2<20,22> P0_MA_ECC1<20,22> P0_MA_ECC0<20,22>

P0_MA_ODT3<20,26> P0_MA_ODT1<20,26>

P0_MA_DQS_N8<20,22> P0_MA_DQS_P8<20,22>

P0_MA_DQS_N7<20,22> P0_MA_DQS_P7<20,22>

P0_MA_DQS_N6<20,22> P0_MA_DQS_P6<20,22>

P0_MA_DQS_N5<20,22> P0_MA_DQS_P5<20,22>

P0_MA_DQS_N4<20,22> P0_MA_DQS_P4<20,22>

P0_MA_DQS_N3<20,22> P0_MA_DQS_P3<20,22>

P0_MA_DQS_N2<20,22> P0_MA_DQS_P2<20,22>

P0_MA_DQS_N1<20,22> P0_MA_DQS_P1<20,22>

P0_MA_DQS_N0<20,22> P0_MA_DQS_P0<20,22>

+3.3V

P0_DIMM_VREF

C939 0.1u_16VC939 0.1u_16V

73

WE_N

192

RAS_N

74

CAS_N

54

A16/BA2

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A09

179

A08

58

A07

180

A06

60

A05

61

A04

182

A03

63

A02

183

A01

188

A00

220

CK2P

221

CK2N

137

CK1P

138

CK1N

185

CK0P

186

CK0N

76

CS1_N

193

CS0_N

171

CKE1

52

CKE0

190

BA1

71

BA0

101

SA2

240

SA1

239

SA0

119

SDA

120

SCL

1

VREF

238

VDDSPD

55

RC0

18

RFU/RC1

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

77

ODT1

195

ODT0

45

DQS8N

46

DQS8P

113

DQS7N

114

DQS7P

104

DQS6N

105

DQS6P

92

DQS5N

93

DQS5P

83

DQS4N

84

DQS4P

36

DQS3N

37

DQS3P

27

DQS2N

28

DQS2P

15

DQS1N

16

DQS1P

6

DQS0N

7

DQS0P

DDRII

* DIMMA3 Slave Addr : 0XA4

4

DDRII 1/2

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ09 DQ08 DQ07 DQ06 DQ05 DQ04 DQ03 DQ02 DQ01 DQ00

NC/DQS17N

NC/DQS17P

NC/DQS16N

NC/DQS16P

NC/DQS15N

NC/DQS15P

NC/DQS14N

NC/DQS14P

NC/DQS13N

NC/DQS13P

NC/DQS12N

NC/DQS12P

NC/DQS11N

NC/DQS11P

NC/DQS10N

NC/DQS10P

NC/DQS09N

NC/DQS09P

3

236 235 230 229 117 116 111 110 227 226 218 217 108 107 99 98 215 214 209 208 96 95 90 89 206 205 200 199 87 86 81 80 159 158 153 152 40 39 34 33 150 149 144 143 31 30 25 24 141 140 132 131 22 21 13 12 129 128 123 122 10 9 4 3

165 164

233 232

224 223

212 211

203 202

156 155

147 146

135 134

126 125

P0_MA_DATA63 <20,22> P0_MA_DATA62 <20,22> P0_MA_DATA61 <20,22> P0_MA_DATA60 <20,22> P0_MA_DATA59 <20,22> P0_MA_DATA58 <20,22> P0_MA_DATA57 <20,22> P0_MA_DATA56 <20,22> P0_MA_DATA55 <20,22> P0_MA_DATA54 <20,22> P0_MA_DATA53 <20,22> P0_MA_DATA52 <20,22> P0_MA_DATA51 <20,22> P0_MA_DATA50 <20,22> P0_MA_DATA49 <20,22> P0_MA_DATA48 <20,22> P0_MA_DATA47 <20,22> P0_MA_DATA46 <20,22> P0_MA_DATA45 <20,22> P0_MA_DATA44 <20,22> P0_MA_DATA43 <20,22> P0_MA_DATA42 <20,22> P0_MA_DATA41 <20,22> P0_MA_DATA40 <20,22> P0_MA_DATA39 <20,22> P0_MA_DATA38 <20,22> P0_MA_DATA37 <20,22> P0_MA_DATA36 <20,22> P0_MA_DATA35 <20,22> P0_MA_DATA34 <20,22> P0_MA_DATA33 <20,22> P0_MA_DATA32 <20,22> P0_MA_DATA31 <20,22> P0_MA_DATA30 <20,22> P0_MA_DATA29 <20,22> P0_MA_DATA28 <20,22> P0_MA_DATA27 <20,22> P0_MA_DATA26 <20,22> P0_MA_DATA25 <20,22> P0_MA_DATA24 <20,22> P0_MA_DATA23 <20,22> P0_MA_DATA22 <20,22> P0_MA_DATA21 <20,22> P0_MA_DATA20 <20,22> P0_MA_DATA19 <20,22> P0_MA_DATA18 <20,22> P0_MA_DATA17 <20,22> P0_MA_DATA16 <20,22> P0_MA_DATA15 <20,22> P0_MA_DATA14 <20,22> P0_MA_DATA13 <20,22> P0_MA_DATA12 <20,22> P0_MA_DATA11 <20,22> P0_MA_DATA10 <20,22> P0_MA_DATA9 <20,22> P0_MA_DATA8 <20,22> P0_MA_DATA7 <20,22> P0_MA_DATA6 <20,22> P0_MA_DATA5 <20,22> P0_MA_DATA4 <20,22> P0_MA_DATA3 <20,22> P0_MA_DATA2 <20,22> P0_MA_DATA1 <20,22> P0_MA_DATA0 <20,22>

P0_MA_DQS_N17 <20,22> P0_MA_DQS_P17 <20,22>

P0_MA_DQS_N16 <20,22> P0_MA_DQS_P16 <20,22>

P0_MA_DQS_N15 <20,22> P0_MA_DQS_P15 <20,22>

P0_MA_DQS_N14 <20,22> P0_MA_DQS_P14 <20,22>

P0_MA_DQS_N13 <20,22> P0_MA_DQS_P13 <20,22>

P0_MA_DQS_N12 <20,22> P0_MA_DQS_P12 <20,22>

P0_MA_DQS_N11 <20,22> P0_MA_DQS_P11 <20,22>

P0_MA_DQS_N10 <20,22> P0_MA_DQS_P10 <20,22>

P0_MA_DQS_N9 <20,22> P0_MA_DQS_P9 <20,22>

P0_MA_PAR<20,22,26>

2

P0_P1V8 P0_P1V8

P0_DIMM1B

197

VDD

189 187 184 178 172

69 67 64 59 53

102

68 19

115 112 109 106 103 100

97 94 91 88 85 82 79 66 65 50 47 44 41 38 35 32 29 26 23 20 17 14 11

8 5 2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

NC NC NC

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

DDRII

P0_P1V8

DDRII 2/2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

1

191 181 175 170 78 75 72 62 56 51 194

237 234 231 228 225 222 219 216 213 210 207 204 201 198 169 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 118

10/04 Joe, not be defined in DesignGuide

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

DDR2 Connector A2_P0

MS-9184

23 92Monday, August 28, 2006

1

0ACustom

of

5

4

3

2

1

P0_DIMM2A

P0_MB_WE_N<20,25,26> P0_MB_RAS_N<20,25,26> P0_MB_CAS_N<20,25,26>

P0_MB_A15<20,25,26> P0_MB_A14<20,25,26>

D D

C C

B B

P0_MB_A13<20,25,26> P0_MB_A12<20,25,26> P0_MB_A11<20,25,26> P0_MB_A10<20,25,26> P0_MB_A9<20,25,26> P0_MB_A8<20,25,26> P0_MB_A7<20,25,26> P0_MB_A6<20,25,26> P0_MB_A5<20,25,26> P0_MB_A4<20,25,26> P0_MB_A3<20,25,26> P0_MB_A2<20,25,26> P0_MB_A1<20,25,26> P0_MB_A0<20,25,26>

P0_MB2_CS0<20,26> P0_MB2_CS1<20,26>

P0_MB_CLK_P0<20> P0_MB_CLK_N0<20>

P0_MB0_CS1<20,26> P0_MB0_CS0<20,26>

P0_MB_CKE0<20,26> P0_MB_BA2<20,25,26> P0_MB_BA1<20,25,26> P0_MB_BA0<20,25,26>

+3.3V

SMB_0_DATA<22,23,25,78> SMB_0_CLK<22,23,25,78>

P0_DIMM_VREF<22,23,25>

P0_MB_ERR_N<25,26>

P0_MB_RESET_N<20,25>

P0_MB_ECC7<20,25> P0_MB_ECC6<20,25> P0_MB_ECC5<20,25> P0_MB_ECC4<20,25> P0_MB_ECC3<20,25> P0_MB_ECC2<20,25> P0_MB_ECC1<20,25> P0_MB_ECC0<20,25>

P0_MB_ODT2<20,26> P0_MB_ODT0<20,26>

P0_MB_DQS_N8<20,25> P0_MB_DQS_P8<20,25>

P0_MB_DQS_N7<20,25> P0_MB_DQS_P7<20,25>

P0_MB_DQS_N6<20,25> P0_MB_DQS_P6<20,25>

P0_MB_DQS_N5<20,25> P0_MB_DQS_P5<20,25>

P0_MB_DQS_N4<20,25> P0_MB_DQS_P4<20,25>

P0_MB_DQS_N3<20,25> P0_MB_DQS_P3<20,25>

P0_MB_DQS_N2<20,25> P0_MB_DQS_P2<20,25>

P0_MB_DQS_N1<20,25>

P0_MB_DQS_P1<20,25>

P0_MB_DQS_N0<20,25> P0_MB_DQS_P0<20,25>

+3.3V

P0_DIMM_VREF

C938 0.1u_16VC938 0.1u_16V

73

WE_N

192

RAS_N

74

CAS_N

54

A16/BA2

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A09

179

A08

58

A07

180

A06

60

A05

61

A04

182

A03

63

A02

183

A01

188

A00

220

CK2P

221

CK2N

137

CK1P

138

CK1N

185

CK0P

186

CK0N

76

CS1_N

193

CS0_N

171

CKE1

52

CKE0

190

BA1

71

BA0

101

SA2

240

SA1

239

SA0

119

SDA

120

SCL

1

VREF

238

VDDSPD

55

RC0

18

RFU/RC1

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

77

ODT1

195

ODT0

45

DQS8N

46

DQS8P

113

DQS7N

114

DQS7P

104

DQS6N

105

DQS6P

92

DQS5N

93

DQS5P

83

DQS4N

84

DQS4P

36

DQS3N

37

DQS3P

27

DQS2N

28

DQS2P

15

DQS1N

16

DQS1P

6

DQS0N

7

DQS0P

DDRII

* DIMMB1 Slave Addr : 0XA2

DDRII 1/2

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ09 DQ08 DQ07 DQ06 DQ05 DQ04 DQ03 DQ02 DQ01 DQ00

NC/DQS17N NC/DQS17P

NC/DQS16N NC/DQS16P

NC/DQS15N NC/DQS15P

NC/DQS14N NC/DQS14P

NC/DQS13N NC/DQS13P

NC/DQS12N NC/DQS12P

NC/DQS11N NC/DQS11P

NC/DQS10N NC/DQS10P

NC/DQS09N NC/DQS09P

236 235 230 229 117 116 111 110 227 226 218 217 108 107 99 98 215 214 209 208 96 95 90 89 206 205 200 199 87 86 81 80 159 158 153 152 40 39 34 33 150 149 144 143 31 30 25 24 141 140 132 131 22 21 13 12 129 128 123 122 10 9 4 3

165 164

233 232

224 223

212 211

203 202

156 155

147 146

135 134

126 125

P0_MB_DATA63 <20,25> P0_MB_DATA62 <20,25> P0_MB_DATA61 <20,25> P0_MB_DATA60 <20,25> P0_MB_DATA59 <20,25> P0_MB_DATA58 <20,25> P0_MB_DATA57 <20,25> P0_MB_DATA56 <20,25> P0_MB_DATA55 <20,25> P0_MB_DATA54 <20,25> P0_MB_DATA53 <20,25> P0_MB_DATA52 <20,25> P0_MB_DATA51 <20,25> P0_MB_DATA50 <20,25> P0_MB_DATA49 <20,25> P0_MB_DATA48 <20,25> P0_MB_DATA47 <20,25> P0_MB_DATA46 <20,25> P0_MB_DATA45 <20,25> P0_MB_DATA44 <20,25> P0_MB_DATA43 <20,25> P0_MB_DATA42 <20,25> P0_MB_DATA41 <20,25> P0_MB_DATA40 <20,25> P0_MB_DATA39 <20,25> P0_MB_DATA38 <20,25> P0_MB_DATA37 <20,25> P0_MB_DATA36 <20,25> P0_MB_DATA35 <20,25> P0_MB_DATA34 <20,25> P0_MB_DATA33 <20,25> P0_MB_DATA32 <20,25> P0_MB_DATA31 <20,25> P0_MB_DATA30 <20,25> P0_MB_DATA29 <20,25> P0_MB_DATA28 <20,25> P0_MB_DATA27 <20,25> P0_MB_DATA26 <20,25> P0_MB_DATA25 <20,25> P0_MB_DATA24 <20,25> P0_MB_DATA23 <20,25> P0_MB_DATA22 <20,25> P0_MB_DATA21 <20,25> P0_MB_DATA20 <20,25> P0_MB_DATA19 <20,25> P0_MB_DATA18 <20,25> P0_MB_DATA17 <20,25> P0_MB_DATA16 <20,25> P0_MB_DATA15 <20,25> P0_MB_DATA14 <20,25> P0_MB_DATA13 <20,25> P0_MB_DATA12 <20,25> P0_MB_DATA11 <20,25> P0_MB_DATA10 <20,25> P0_MB_DATA9 <20,25> P0_MB_DATA8 <20,25> P0_MB_DATA7 <20,25> P0_MB_DATA6 <20,25> P0_MB_DATA5 <20,25> P0_MB_DATA4 <20,25> P0_MB_DATA3 <20,25> P0_MB_DATA2 <20,25> P0_MB_DATA1 <20,25> P0_MB_DATA0 <20,25>

P0_MB_DQS_N17 <20,25>

P0_MB_DQS_P17 <20,25>

P0_MB_DQS_N16 <20,25>

P0_MB_DQS_P16 <20,25>

P0_MB_DQS_N15 <20,25>

P0_MB_DQS_P15 <20,25>

P0_MB_DQS_N14 <20,25>

P0_MB_DQS_P14 <20,25>

P0_MB_DQS_N13 <20,25>

P0_MB_DQS_P13 <20,25>

P0_MB_DQS_N12 <20,25>

P0_MB_DQS_P12 <20,25>

P0_MB_DQS_N11 <20,25>

P0_MB_DQS_P11 <20,25>

P0_MB_DQS_N10 <20,25>

P0_MB_DQS_P10 <20,25>

P0_MB_DQS_N9 <20,25>

P0_MB_DQS_P9 <20,25>

P0_MB_PAR<20,25,26>

P0_P1V8 P0_P1V8

P0_DIMM2B

197 189 187 184 178 172

69 67 64 59 53

102

68 19

115 112 109 106 103 100

97 94 91 88 85 82 79 66 65 50 47 44 41 38 35 32 29 26 23 20 17 14 11

8 5 2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

NC NC NC

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

DDRII

P0_P1V8

DDRII 2/2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

191 181 175 170 78 75 72 62 56 51 194

237 234 231 228 225 222 219 216 213 210 207 204 201 198 169 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 118

10/04 Joe, not be defined in DesignGuide

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

DDR2 Connector B1_P0

MS-9184

24 92Tuesday, August 29, 2006

1

0ACustom

of

5

4

3

2

1

P0_DIMM0A

P0_MB_WE_N<20,24,26> P0_MB_RAS_N<20,24,26> P0_MB_CAS_N<20,24,26>

P0_MB_A15<20,24,26> P0_MB_A14<20,24,26>

D D

C C

B B

P0_MB_A13<20,24,26> P0_MB_A12<20,24,26> P0_MB_A11<20,24,26> P0_MB_A10<20,24,26> P0_MB_A9<20,24,26> P0_MB_A8<20,24,26> P0_MB_A7<20,24,26> P0_MB_A6<20,24,26> P0_MB_A5<20,24,26> P0_MB_A4<20,24,26> P0_MB_A3<20,24,26> P0_MB_A2<20,24,26> P0_MB_A1<20,24,26> P0_MB_A0<20,24,26>

P0_MB3_CS0<20,26> P0_MB3_CS1<20,26>

P0_MB_CLK_P1<20> P0_MB_CLK_N1<20>

P0_MB1_CS1<20,26> P0_MB1_CS0<20,26>

P0_MB_CKE1<20,26> P0_MB_BA2<20,24,26> P0_MB_BA1<20,24,26> P0_MB_BA0<20,24,26>

+3.3V

SMB_0_DATA<22,23,24,78> SMB_0_CLK<22,23,24,78>

P0_DIMM_VREF<22,23,24>

P0_MB_ERR_N<24,26>

P0_MB_RESET_N<20,24>

P0_MB_ECC7<20,24> P0_MB_ECC6<20,24> P0_MB_ECC5<20,24> P0_MB_ECC4<20,24> P0_MB_ECC3<20,24> P0_MB_ECC2<20,24> P0_MB_ECC1<20,24> P0_MB_ECC0<20,24>

P0_MB_ODT3<20,26> P0_MB_ODT1<20,26>

P0_MB_DQS_N8<20,24> P0_MB_DQS_P8<20,24>

P0_MB_DQS_N7<20,24> P0_MB_DQS_P7<20,24>

P0_MB_DQS_N6<20,24> P0_MB_DQS_P6<20,24>

P0_MB_DQS_N5<20,24> P0_MB_DQS_P5<20,24>

P0_MB_DQS_N4<20,24> P0_MB_DQS_P4<20,24>

P0_MB_DQS_N3<20,24> P0_MB_DQS_P3<20,24>

P0_MB_DQS_N2<20,24> P0_MB_DQS_P2<20,24>

P0_MB_DQS_N1<20,24>

P0_MB_DQS_P1<20,24>

P0_MB_DQS_N0<20,24> P0_MB_DQS_P0<20,24>

+3.3V

P0_DIMM_VREF

C937 0.1u_16VC937 0.1u_16V

73

WE_N

192

RAS_N

74

CAS_N

54

A16/BA2

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A09

179

A08

58

A07

180

A06

60

A05

61

A04

182

A03

63

A02

183

A01

188

A00

220

CK2P

221

CK2N

137

CK1P

138

CK1N

185

CK0P

186

CK0N

76

CS1_N

193

CS0_N

171

CKE1

52

CKE0

190

BA1

71

BA0

101

SA2

240

SA1

239

SA0

119

SDA

120

SCL

1

VREF

238

VDDSPD

55

RC0

18

RFU/RC1

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

77

ODT1

195

ODT0

45

DQS8N

46

DQS8P

113

DQS7N

114

DQS7P

104

DQS6N

105

DQS6P

92

DQS5N

93

DQS5P

83

DQS4N

84

DQS4P

36

DQS3N

37

DQS3P

27

DQS2N

28

DQS2P

15

DQS1N

16

DQS1P

6

DQS0N

7

DQS0P

DDRII

* DIMMB2 Slave Addr : 0XA6

DDRII 1/2

DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ09 DQ08 DQ07 DQ06 DQ05 DQ04 DQ03 DQ02 DQ01 DQ00

NC/DQS17N NC/DQS17P

NC/DQS16N NC/DQS16P

NC/DQS15N NC/DQS15P

NC/DQS14N NC/DQS14P

NC/DQS13N NC/DQS13P

NC/DQS12N NC/DQS12P

NC/DQS11N NC/DQS11P

NC/DQS10N NC/DQS10P

NC/DQS09N NC/DQS09P

236 235 230 229 117 116 111 110 227 226 218 217 108 107 99 98 215 214 209 208 96 95 90 89 206 205 200 199 87 86 81 80 159 158 153 152 40 39 34 33 150 149 144 143 31 30 25 24 141 140 132 131 22 21 13 12 129 128 123 122 10 9 4 3

165 164

233 232

224 223

212 211

203 202

156 155

147 146

135 134

126 125

P0_MB_DATA63 <20,24> P0_MB_DATA62 <20,24> P0_MB_DATA61 <20,24> P0_MB_DATA60 <20,24> P0_MB_DATA59 <20,24> P0_MB_DATA58 <20,24> P0_MB_DATA57 <20,24> P0_MB_DATA56 <20,24> P0_MB_DATA55 <20,24> P0_MB_DATA54 <20,24> P0_MB_DATA53 <20,24> P0_MB_DATA52 <20,24> P0_MB_DATA51 <20,24> P0_MB_DATA50 <20,24> P0_MB_DATA49 <20,24> P0_MB_DATA48 <20,24> P0_MB_DATA47 <20,24> P0_MB_DATA46 <20,24> P0_MB_DATA45 <20,24> P0_MB_DATA44 <20,24> P0_MB_DATA43 <20,24> P0_MB_DATA42 <20,24> P0_MB_DATA41 <20,24> P0_MB_DATA40 <20,24> P0_MB_DATA39 <20,24> P0_MB_DATA38 <20,24> P0_MB_DATA37 <20,24> P0_MB_DATA36 <20,24> P0_MB_DATA35 <20,24> P0_MB_DATA34 <20,24> P0_MB_DATA33 <20,24> P0_MB_DATA32 <20,24> P0_MB_DATA31 <20,24> P0_MB_DATA30 <20,24> P0_MB_DATA29 <20,24> P0_MB_DATA28 <20,24> P0_MB_DATA27 <20,24> P0_MB_DATA26 <20,24> P0_MB_DATA25 <20,24> P0_MB_DATA24 <20,24> P0_MB_DATA23 <20,24> P0_MB_DATA22 <20,24> P0_MB_DATA21 <20,24> P0_MB_DATA20 <20,24> P0_MB_DATA19 <20,24> P0_MB_DATA18 <20,24> P0_MB_DATA17 <20,24> P0_MB_DATA16 <20,24> P0_MB_DATA15 <20,24> P0_MB_DATA14 <20,24> P0_MB_DATA13 <20,24> P0_MB_DATA12 <20,24> P0_MB_DATA11 <20,24> P0_MB_DATA10 <20,24> P0_MB_DATA9 <20,24> P0_MB_DATA8 <20,24> P0_MB_DATA7 <20,24> P0_MB_DATA6 <20,24> P0_MB_DATA5 <20,24> P0_MB_DATA4 <20,24> P0_MB_DATA3 <20,24> P0_MB_DATA2 <20,24> P0_MB_DATA1 <20,24> P0_MB_DATA0 <20,24>

P0_MB_DQS_N17 <20,24>

P0_MB_DQS_P17 <20,24>

P0_MB_DQS_N16 <20,24>

P0_MB_DQS_P16 <20,24>

P0_MB_DQS_N15 <20,24>

P0_MB_DQS_P15 <20,24>

P0_MB_DQS_N14 <20,24>

P0_MB_DQS_P14 <20,24>

P0_MB_DQS_N13 <20,24>

P0_MB_DQS_P13 <20,24>

P0_MB_DQS_N12 <20,24>

P0_MB_DQS_P12 <20,24>

P0_MB_DQS_N11 <20,24>

P0_MB_DQS_P11 <20,24>

P0_MB_DQS_N10 <20,24>

P0_MB_DQS_P10 <20,24>

P0_MB_DQS_N9 <20,24>

P0_MB_DQS_P9 <20,24>

P0_MB_PAR<20,24,26>

P0_P1V8 P0_P1V8

P0_DIMM0B

197 189 187 184 178 172

69 67 64 59 53

102

68 19

115 112 109 106 103 100

97 94 91 88 85 82 79 66 65 50 47 44 41 38 35 32 29 26 23 20 17 14 11

8 5 2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

NC NC NC

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

DDRII

P0_P1V8

DDRII 2/2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

191 181 175 170 78 75 72 62 56 51 194

237 234 231 228 225 222 219 216 213 210 207 204 201 198 169 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 118

10/04 Joe, not be defined in DesignGuide

A A

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

DDR2 Connector B2_P0

MS-9184

25 92Tuesday, August 29, 2006

1

0ACustom

of

5

Put RTT at the end of the bus,

P0_VTT_0.9V

P0_MB_A5 P0_MB_A6 P0_MB_A8 P0_MB_A7 P0_MA_BA2 P0_MA_A12 P0_MA_A9

D D

C C

P0_MA_A11 P0_MB_A2 P0_MB_A1 P0_MB_A3 P0_MB_A4 P0_MB_ODT0 P0_MB_ODT1 P0_MA_ODT1 P0_MB_CAS_N

P0_MA1_CS0 P0_MA0_CS0 P0_MB_A10 P0_MA_RAS_N

P0_MB_WE_N P0_MB1_CS0 P0_MB_RAS_N P0_MB_BA0 P0_MA2_CS0 P0_MA2_CS1 P0_MA3_CS1 P0_MA3_CS0

P0_MB_A11 P0_MB_A9 P0_MB_A12 P0_MB_BA2 P0_MA_CKE1 P0_MA_CKE0 P0_MA_A15 P0_MB_CKE0

P0_MA1_CS1 P0_MB1_CS1 P0_MB_A13

P0_MA_ERR_N P0_MB_ERR_N

RN9047-8P4R RN9047-8P4R

12 34 56

RN18347-8P4R RN18347-8P4R

78 12 34 56

RN8647-8P4R RN8647-8P4R

78 12 34 56

RN7147-8P4R RN7147-8P4R

78 12 34 56 78

P0_VTT_0.9V

RN7947-8P4R RN7947-8P4R

12 34 56 78

RN7547-8P4R RN7547-8P4R

12 34 56

RN6347-8P4R RN6347-8P4R

78 12 34 56 78

P0_VTT_0.9V

RN9547-8P4R RN9547-8P4R

12 34 56

RN18647-8P4R RN18647-8P4R

78 12 34 56

RN6847-8P4R RN6847-8P4R

78 12 34 56 78

P0_P1V8 P0_P1V8

4

P0_MA_PAR P0_MA_BA1 P0_MA_A10 P0_MA_BA0 P0_MA_A4 P0_MA_A3 P0_MA_A1 P0_MA_A2 P0_MB_BA1 P0_MB_PAR P0_MB_A0 P0_MA_A0

P0_MB3_CS1 P0_MB3_CS0 P0_MB2_CS1 P0_MB2_CS0 P0_MA_CAS_N P0_MB0_CS1 P0_MB_ODT3 P0_MB_ODT2 P0_MA_ODT0 P0_MA_WE_N P0_MA0_CS1 P0_MB0_CS0

P0_MA_A14 P0_MB_A14 P0_MB_A15 P0_MB_CKE1 P0_MA_A7 P0_MA_A8 P0_MA_A6 P0_MA_A5 P0_MA_ODT2 P0_MA_A13 P0_MA_ODT3

R721 47R721 47R717 47R717 47

3

P0_P1V8

P0_VTT_0.9V

RN17147-8P4R RN17147-8P4R

12 34 56

RN17447-8P4R RN17447-8P4R

78 12 34 56

RN8247-8P4R RN8247-8P4R

78 12 34 56 78

P0_VTT_0.9V

RN15647-8P4R RN15647-8P4R

12 34 56

RN16347-8P4R RN16347-8P4R

78 12 34 56

RN16647-8P4R RN16647-8P4R

78 12 34 56 78

P0_VTT_0.9V

RN10147-8P4R RN10147-8P4R

12 34 56

RN17947-8P4R RN17947-8P4R

78 12 34 56

RN16147-8P4R RN16147-8P4R

78 12 34 56 78

C1229 180p-0402C1229 180p-0402

C716 180p-0402C716 180p-0402 C798 180p-0402C798 180p-0402 C1234 0.01uC1234 0.01u C1275 0.01uC1275 0.01u C707 10u_6.3V_0805C707 10u_6.3V_0805 C1263 10u_6.3V_0805C1263 10u_6.3V_0805

AMD Doc#31329 VDDIO Decoupling

---------------2 10uF 6 0.22uF 2 0.01uF 2 10pF 4 4.7uF

AMD Doc#31329 VLDT Decoupling

---------------2 X 3 4.7uF 2 X 3 0.22uF 2 X 3 10pF

2

P0_P1V8

C1241 0.22u_16VC1241 0.22u_16V C710 0.22u_16VC710 0.22u_16V C770 0.22u_16VC770 0.22u_16V C744 0.22u_16VC744 0.22u_16V C733 0.22u_16VC733 0.22u_16V C1230 0.22u_16VC1230 0.22u_16V

AMD Doc#31329 VDD Decoupling

---------------2 22uF 17 10uF 3 0.22uF 1 0.01uF 1 10pF

AMD Doc#31329 VTT Decoupling

---------------4 4.7uF 4 0.22uF 4 1nF 4 10pF

Per RPAKs

---------------4 0.1uF VTT/VSS 4 0.1uF VTT/VDDIO

1

P0_P1V8

C690 4.7u_6.3V-0805C690 4.7u_6.3V-0805 C688 4.7u_6.3V-0805C688 4.7u_6.3V-0805 C691 4.7u_6.3V-0805C691 4.7u_6.3V-0805 C689 4.7u_6.3V-0805C689 4.7u_6.3V-0805

P0_VTT_0.9V

C1222 1000p/0402C1222 1000p/0402 C774 1000p/0402C774 1000p/0402 C1216 1000p/0402C1216 1000p/0402 C1245 1000p/0402C1245 1000p/0402

C717 0.22u_16VC717 0.22u_16V C745 0.22u_16VC745 0.22u_16V C804 0.22u_16VC804 0.22u_16V C764 0.22u_16VC764 0.22u_16V

C741 180p-0402C741 180p-0402 C1259 180p-0402C1259 180p-0402 C836 180p-0402C836 180p-0402 C759 180p-0402C759 180p-0402

3

12 34 56 78

Top layer

P0_P1V8

P0_VTT_0.9V

2

C1221 0.1u_16VC1221 0.1u_16V C750 0.1u_16VC750 0.1u_16V C730 0.1u_16VC730 0.1u_16V C1224 0.1u_16VC1224 0.1u_16V C789 0.1u_16VC789 0.1u_16V C797 0.1u_16VC797 0.1u_16V C816 0.1u_16VC816 0.1u_16V C1214 0.1u_16VC1214 0.1u_16V C769 0.1u_16VC769 0.1u_16V C810 0.1u_16VC810 0.1u_16V

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

Bottom layer

P0_MA_ODT1<20,23> P0_MA_A13<20,22,23> P0_MA0_CS1<20,22> P0_MA1_CS1<20,23>

P0_MA0_CS0<20,22> P0_MA_WE_N<20,22,23> P0_MA_CAS_N<20,22,23> P0_MA_ODT0<20,22>

P0_MA_ODT2<20,22>

B B

A A

P0_MA_BA0<20,22,23>

P0_MA_RAS_N<20,22,23>

P0_MA1_CS0<20,23>

P0_MA_A0<20,22,23> P0_MA_PAR<20,22,23> P0_MA_BA1<20,22,23> P0_MA_A10<20,22,23>

P0_MA_A9<20,22,23> P0_MA_A11<20,22,23> P0_MA_A7<20,22,23> P0_MA_A8<20,22,23>

P0_MA_A1<20,22,23> P0_MA_A2<20,22,23> P0_MB_ODT3<20,25> P0_MB_ODT2<20,24>

P0_MA_A6<20,22,23> P0_MA_A5<20,22,23> P0_MA_A4<20,22,23> P0_MA_A3<20,22,23>

P0_MB3_CS1<20,25> P0_MB3_CS0<20,25> P0_MB2_CS1<20,24> P0_MB2_CS0<20,24>

P0_MA_A15<20,22,23> P0_MA_A14<20,22,23> P0_MA_BA2<20,22,23> P0_MA_A12<20,22,23>

P0_MA_CKE1<20,23> P0_MA_CKE0<20,22>

P0_MA_ERR_R_N<20> P0_MA_ERR_N <22,23> P0_MB_ERR_N <24,25>P0_MB_ERR_R_N<20>

5

Put CP and RP between the processor and the DIMM sockets,

RN1570-8P4R RN1570-8P4R

RN1590-8P4R RN1590-8P4R

RN1620-8P4R RN1620-8P4R

RN1670-8P4R RN1670-8P4R

RN1820-8P4R RN1820-8P4R

RN1730-8P4R RN1730-8P4R

RN1770-8P4R RN1770-8P4R

RN1550-8P4R RN1550-8P4R

RN1870-8P4R RN1870-8P4R

RN1890-8P4R RN1890-8P4R

R1113 22RR1113 22R

CN61 15p-8P4CCN61 15p-8P4C

12 34 56 78

CN63 15p-8P4CCN63 15p-8P4C

12 34 56 78

CN65 15p-8P4CCN65 15p-8P4C

12 34 56 78

CN67 15p-8P4CCN67 15p-8P4C

12 34 56 78

CN74 15p-8P4CCN74 15p-8P4C

12 34 56 78

CN70 15p-8P4CCN70 15p-8P4C

12 34 56 78

CN72 15p-8P4CCN72 15p-8P4C

12 34 56 78

CN60 15p-8P4CCN60 15p-8P4C

12 34 56 78

CN76 15p-8P4CCN76 15p-8P4C

12 34 56 78

CN77 15p-8P4CCN77 15p-8P4C

12 34 56 78

P0_P1V8

12 34 56 78

P0_P1V8

12 34 56 78

P0_P1V8

12 34 56 78

4

P0_MB1_CS1<20,25> P0_MB0_CS1<20,24> P0_MB_A13<20,24,25> P0_MB_ODT0<20,24>

P0_MB_ODT1<20,25>

P0_MB_CAS_N<20,24,25>

P0_MB_WE_N<20,24,25>

P0_MB0_CS0<20,24>

P0_MA2_CS0<20,22> P0_MA2_CS1<20,22> P0_MA3_CS0<20,23> P0_MA3_CS1<20,23>

P0_MB1_CS0<20,25> P0_MA_ODT3<20,23>

P0_MB_RAS_N<20,24,25>

P0_MB_BA0<20,24,25>

P0_MB_A10<20,24,25> P0_MB_BA1<20,24,25> P0_MB_PAR<20,24,25> P0_MB_A0<20,24,25>

P0_MB_A2<20,24,25> P0_MB_A1<20,24,25> P0_MB_A3<20,24,25> P0_MB_A4<20,24,25>

P0_MB_A5<20,24,25> P0_MB_A6<20,24,25> P0_MB_A8<20,24,25> P0_MB_A7<20,24,25>

P0_MB_A11<20,24,25> P0_MB_A9<20,24,25> P0_MB_A12<20,24,25> P0_MB_BA2<20,24,25>

P0_MB_A14<20,24,25> P0_MB_A15<20,24,25> P0_MB_CKE0<20,24> P0_MB_CKE1<20,25>

R1109 22RR1109 22R

CN24 15p-8P4CCN24 15p-8P4C

RN650-8P4R RN650-8P4R

12 34 56 78

CN25 15p-8P4CCN25 15p-8P4C

RN660-8P4R RN660-8P4R

12 34 56 78

RN620-8P4R RN620-8P4R

CN23 15p-8P4CCN23 15p-8P4C

12 34 56 78

CN27 15p-8P4CCN27 15p-8P4C

RN700-8P4R RN700-8P4R

12 34 56 78

CN29 15p-8P4CCN29 15p-8P4C

RN760-8P4R RN760-8P4R

12 34 56 78

CN32 15p-8P4CCN32 15p-8P4C

RN850-8P4R RN850-8P4R

12 34 56 78

RN890-8P4R RN890-8P4R

CN34 15p-8P4CCN34 15p-8P4C

12 34 56 78

RN940-8P4R RN940-8P4R

CN36 15p-8P4CCN36 15p-8P4C

12 34 56 78

CN38 15p-8P4CCN38 15p-8P4C

RN1020-8P4R RN1020-8P4R

12 34 56 78

C780 4.7u_6.3V-0805C780 4.7u_6.3V-0805 C821 4.7u_6.3V-0805C821 4.7u_6.3V-0805 C705 4.7u_6.3V-0805C705 4.7u_6.3V-0805 C813 4.7u_6.3V-0805C813 4.7u_6.3V-0805

P0_VTT_0.9V

C779 0.1u_16VC779 0.1u_16V C736 0.1u_16VC736 0.1u_16V C1235 0.1u_16VC1235 0.1u_16V C1225 0.1u_16VC1225 0.1u_16V C1223 0.1u_16VC1223 0.1u_16V C711 0.1u_16VC711 0.1u_16V C1232 0.1u_16VC1232 0.1u_16V C1228 0.1u_16VC1228 0.1u_16V C726 0.1u_16VC726 0.1u_16V C808 0.1u_16VC808 0.1u_16V

DD2 Termination/Caps_P0

MS-9184

1

P0_P1V8

0ACustom

of

26 92Wednesday, August 30, 2006

5

P0_VCORE P0_VCORE

4

3

2

1

D D

Place close to the socket

P0_VCORE

C1319

C1319 22uF_10V

22uF_10V

P0_VCORE

C C

P0_VCORE

C907

C907 22uF_10V

22uF_10V

P0_VCORE

C1261

0.22u_16V

Place between VRM & Processor

C1244

0.22u_16V

SP-CAP

Place under the socket

C1289

C1237

C1289

0.01u

C1239

C1239 180p-0402

180p-0402

10/04 Joe, these cap. are evaluated in VRD output cap.

+1.2V_HT

B B

C412

4.7u_10V_0805

C766

4.7u_10V_0805

C760

4.7u_10V_0805

C751

4.7u_10V_0805

C393

C782

4.7u_10V_0805

+1.2V_HT

C718

C408

C400

C400 180p-0402

180p-0402

C718

0.22u_16V

C337

0.22u_16V

C402

C402 180p-0402

180p-0402

C800

C800 180p-0402

180p-0402

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

4

3

2

Date: Sheet

CPU0 Decoupling CAP

MS-9184

1

0AB

27 92Monday, August 28, 2006

of

C712

C785

0.22u_16V

+1.2V_HT

C354

A A

C354 180p-0402

180p-0402

5

0.22u_16V

C351

C351 180p-0402

180p-0402

C788

C712

0.22u_16V

C397

C397 180p-0402

180p-0402

0.22u_16V

5

U66A

D D

C C

HT1_TO_P1_CLKOUT_H1<56> HT1_TO_P1_CLKOUT_L1<56> HT1_TO_P1_CLKOUT_H0<56> HT1_TO_P1_CLKOUT_L0<56>

+1.2V_HT

HT1_TO_P1_CTLOUT_H0<56> HT1_TO_P1_CTLOUT_L0<56>

HT1_TO_P1_CADOUT_H15<56> HT1_TO_P1_CADOUT_L15<56> HT1_TO_P1_CADOUT_H14<56> HT1_TO_P1_CADOUT_L14<56> HT1_TO_P1_CADOUT_H13<56> HT1_TO_P1_CADOUT_L13<56> HT1_TO_P1_CADOUT_H12<56> HT1_TO_P1_CADOUT_L12<56> HT1_TO_P1_CADOUT_H11<56> HT1_TO_P1_CADOUT_L11<56> HT1_TO_P1_CADOUT_H10<56> HT1_TO_P1_CADOUT_L10<56> HT1_TO_P1_CADOUT_H9<56> HT1_TO_P1_CADOUT_L9<56> HT1_TO_P1_CADOUT_H8<56> HT1_TO_P1_CADOUT_L8<56>

HT1_TO_P1_CADOUT_H7<56> HT1_TO_P1_CADOUT_L7<56> HT1_TO_P1_CADOUT_H6<56> HT1_TO_P1_CADOUT_L6<56> HT1_TO_P1_CADOUT_H5<56> HT1_TO_P1_CADOUT_L5<56> HT1_TO_P1_CADOUT_H4<56> HT1_TO_P1_CADOUT_L4<56> HT1_TO_P1_CADOUT_H3<56> HT1_TO_P1_CADOUT_L3<56> HT1_TO_P1_CADOUT_H2<56> HT1_TO_P1_CADOUT_L2<56> HT1_TO_P1_CADOUT_H1<56> HT1_TO_P1_CADOUT_L1<56> HT1_TO_P1_CADOUT_H0<56> HT1_TO_P1_CADOUT_L0<56>

R1101 49.9_1%R1101 49.9_1% R1099 49.9_1%R1099 49.9_1%

M6

L0_CLKIN_H(1)

N6

L0_CLKIN_L(1)

M3

L0_CLKIN_H(0)

M2

L0_CLKIN_L(0)

U4

L0_CTLIN_H(1)

U5

L0_CTLIN_L(1)

T1

L0_CTLIN_H(0)

U1

L0_CTLIN_L(0)

T6

L0_CADIN_H(15)

U6

L0_CADIN_L(15)

R4

L0_CADIN_H(14)

R5

L0_CADIN_L(14)

P6

L0_CADIN_H(13)

R6

L0_CADIN_L(13)

N4

L0_CADIN_H(12)

N5

L0_CADIN_L(12)

L4

L0_CADIN_H(11)

L5

L0_CADIN_L(11)

K6

L0_CADIN_H(10)

L6

L0_CADIN_L(10)

J4

L0_CADIN_H(9)

J5

L0_CADIN_L(9)

H6

L0_CADIN_H(8)

J6

L0_CADIN_L(8)

T3

L0_CADIN_H(7)

T2

L0_CADIN_L(7)

P1

L0_CADIN_H(6)

R1

L0_CADIN_L(6)

P3

L0_CADIN_H(5)

P2

L0_CADIN_L(5)

M1

L0_CADIN_H(4)

N1

L0_CADIN_L(4)

K1

L0_CADIN_H(3)

L1

L0_CADIN_L(3)

K3

L0_CADIN_H(2)

K2

L0_CADIN_L(2)

H1

L0_CADIN_H(1)

J1

L0_CADIN_L(1)

H3

L0_CADIN_H(0)

H2

L0_CADIN_L(0)

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0) L0_CTLOUT_H(1)

L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0)

L0_CADOUT_H(15)

L0_CADOUT_L(15)

L0_CADOUT_H(14)

L0_CADOUT_L(14)

L0_CADOUT_H(13)

L0_CADOUT_L(13)

L0_CADOUT_H(12)

L0_CADOUT_L(12)

L0_CADOUT_H(11)

L0_CADOUT_L(11)

L0_CADOUT_H(10)

L0_CADOUT_L(10)

L0_CADOUT_H(9) L0_CADOUT_L(9) L0_CADOUT_H(8) L0_CADOUT_L(8)

L0_CADOUT_H(7) L0_CADOUT_L(7) L0_CADOUT_H(6) L0_CADOUT_L(6) L0_CADOUT_H(5) L0_CADOUT_L(5) L0_CADOUT_H(4) L0_CADOUT_L(4) L0_CADOUT_H(3) L0_CADOUT_L(3) L0_CADOUT_H(2) L0_CADOUT_L(2) L0_CADOUT_H(1) L0_CADOUT_L(1) L0_CADOUT_H(0) L0_CADOUT_L(0)

SOCKET-F(1207)

4

AC5 AC4 AC1 AB1

W6 V6 V2 V3

W5 W4 AA6 Y6 AA5 AA4 AC6 AB6 AE6 AD6 AE5 AE4 AG6 AF6 AG5 AG4

W1 V1 Y2 Y3 AA1 Y1 AB2 AB3 AD2 AD3 AE1 AD1 AF2 AF3 AG1 AF1

P1_TO_HT1_CLKOUT_H1 <56> P1_TO_HT1_CLKOUT_L1 <56> P1_TO_HT1_CLKOUT_H0 <56> P1_TO_HT1_CLKOUT_L0 <56>

P1_TO_HT1_CTLOUT_H0 <56> P1_TO_HT1_CTLOUT_L0 <56>

P1_TO_HT1_CADOUT_H15 <56> P1_TO_HT1_CADOUT_L15 <56> P1_TO_HT1_CADOUT_H14 <56> P1_TO_HT1_CADOUT_L14 <56> P1_TO_HT1_CADOUT_H13 <56> P1_TO_HT1_CADOUT_L13 <56> P1_TO_HT1_CADOUT_H12 <56> P1_TO_HT1_CADOUT_L12 <56> P1_TO_HT1_CADOUT_H11 <56> P1_TO_HT1_CADOUT_L11 <56> P1_TO_HT1_CADOUT_H10 <56> P1_TO_HT1_CADOUT_L10 <56> P1_TO_HT1_CADOUT_H9 <56> P1_TO_HT1_CADOUT_L9 <56> P1_TO_HT1_CADOUT_H8 <56> P1_TO_HT1_CADOUT_L8 <56>

P1_TO_HT1_CADOUT_H7 <56> P1_TO_HT1_CADOUT_L7 <56> P1_TO_HT1_CADOUT_H6 <56> P1_TO_HT1_CADOUT_L6 <56> P1_TO_HT1_CADOUT_H5 <56> P1_TO_HT1_CADOUT_L5 <56> P1_TO_HT1_CADOUT_H4 <56> P1_TO_HT1_CADOUT_L4 <56> P1_TO_HT1_CADOUT_H3 <56> P1_TO_HT1_CADOUT_L3 <56> P1_TO_HT1_CADOUT_H2 <56> P1_TO_HT1_CADOUT_L2 <56> P1_TO_HT1_CADOUT_H1 <56> P1_TO_HT1_CADOUT_L1 <56> P1_TO_HT1_CADOUT_H0 <56> P1_TO_HT1_CADOUT_L0 <56>

3

P2_TO_P1_CLKOUT_H1<37> P2_TO_P1_CLKOUT_L1<37> P2_TO_P1_CLKOUT_H0<37> P2_TO_P1_CLKOUT_L0<37>

P2_TO_P1_CTLOUT_H1<37> P2_TO_P1_CTLOUT_L1<37> P2_TO_P1_CTLOUT_H0<37> P2_TO_P1_CTLOUT_L0<37>

P2_TO_P1_CADOUT_H15<37> P2_TO_P1_CADOUT_L15<37> P2_TO_P1_CADOUT_H14<37> P2_TO_P1_CADOUT_L14<37> P2_TO_P1_CADOUT_H13<37> P2_TO_P1_CADOUT_L13<37> P2_TO_P1_CADOUT_H12<37> P2_TO_P1_CADOUT_L12<37> P2_TO_P1_CADOUT_H11<37> P2_TO_P1_CADOUT_L11<37> P2_TO_P1_CADOUT_H10<37> P2_TO_P1_CADOUT_L10<37> P2_TO_P1_CADOUT_H9<37> P2_TO_P1_CADOUT_L9<37> P2_TO_P1_CADOUT_H8<37> P2_TO_P1_CADOUT_L8<37>

P2_TO_P1_CADOUT_H7<37> P2_TO_P1_CADOUT_L7<37> P2_TO_P1_CADOUT_H6<37> P2_TO_P1_CADOUT_L6<37> P2_TO_P1_CADOUT_H5<37> P2_TO_P1_CADOUT_L5<37> P2_TO_P1_CADOUT_H4<37> P2_TO_P1_CADOUT_L4<37> P2_TO_P1_CADOUT_H3<37> P2_TO_P1_CADOUT_L3<37> P2_TO_P1_CADOUT_H2<37> P2_TO_P1_CADOUT_L2<37> P2_TO_P1_CADOUT_H1<37> P2_TO_P1_CADOUT_L1<37> P2_TO_P1_CADOUT_H0<37> P2_TO_P1_CADOUT_L0<37>

E18 E17 C18 B18

C13 D13 A14 A13

E14 E13 C15 D15 E16 E15 C17 D17 C19 D19 E20 E19 C21 D21 E22 E21

C14 B14 A16 A15 C16 B16 A18 A17 A20 A19 C20 B20 A22 A21 C22 B22

L1_CLKIN_H(1) L1_CLKIN_L(1) L1_CLKIN_H(0) L1_CLKIN_L(0)

L1_CTLIN_H(1) L1_CTLIN_L(1) L1_CTLIN_H(0) L1_CTLIN_L(0)

L1_CADIN_H(15) L1_CADIN_L(15) L1_CADIN_H(14) L1_CADIN_L(14) L1_CADIN_H(13) L1_CADIN_L(13) L1_CADIN_H(12) L1_CADIN_L(12) L1_CADIN_H(11) L1_CADIN_L(11) L1_CADIN_H(10) L1_CADIN_L(10) L1_CADIN_H(9) L1_CADIN_L(9) L1_CADIN_H(8) L1_CADIN_L(8)

L1_CADIN_H(7) L1_CADIN_L(7) L1_CADIN_H(6) L1_CADIN_L(6) L1_CADIN_H(5) L1_CADIN_L(5) L1_CADIN_H(4) L1_CADIN_L(4) L1_CADIN_H(3) L1_CADIN_L(3) L1_CADIN_H(2) L1_CADIN_L(2) L1_CADIN_H(1) L1_CADIN_L(1) L1_CADIN_H(0) L1_CADIN_L(0)

2

U66B

L1_CLKOUT_H(1)

L1_CLKOUT_L(1)

L1_CLKOUT_H(0)

L1_CLKOUT_L(0)

L1_CTLOUT_H(1)

L1_CTLOUT_L(1)

L1_CTLOUT_H(0)

L1_CTLOUT_L(0)

L1_CADOUT_H(15)

L1_CADOUT_L(15)

L1_CADOUT_H(14)

L1_CADOUT_L(14)

L1_CADOUT_H(13)

L1_CADOUT_L(13)

L1_CADOUT_H(12)

L1_CADOUT_L(12)

L1_CADOUT_H(11)

L1_CADOUT_L(11)

L1_CADOUT_H(10)

L1_CADOUT_L(10)

L1_CADOUT_H(9)

L1_CADOUT_L(9)

L1_CADOUT_H(8)

L1_CADOUT_L(8)

L1_CADOUT_H(7)

L1_CADOUT_L(7)

L1_CADOUT_H(6)

L1_CADOUT_L(6)

L1_CADOUT_H(5)

L1_CADOUT_L(5)

L1_CADOUT_H(4)

L1_CADOUT_L(4)

L1_CADOUT_H(3)

L1_CADOUT_L(3)

L1_CADOUT_H(2)

L1_CADOUT_L(2)

L1_CADOUT_H(1)

L1_CADOUT_L(1)

L1_CADOUT_H(0)

L1_CADOUT_L(0)

SOCKET-F(1207)

1

E6 D6 B6 B7

F10 F11 C11 D11

E10 D10 F8 F9 E8 D8 F6 F7 F4 F5 E4 D4 F2 F3 E2 D2

B10 B11 C9 D9 B8 B9 C7 D7 C5 D5 B4 B5 C3 D3 B2 B3

P1_TO_P2_CLKOUT_H1 <37> P1_TO_P2_CLKOUT_L1 <37> P1_TO_P2_CLKOUT_H0 <37> P1_TO_P2_CLKOUT_L0 <37>

P1_TO_P2_CTLOUT_H1 <37> P1_TO_P2_CTLOUT_L1 <37> P1_TO_P2_CTLOUT_H0 <37> P1_TO_P2_CTLOUT_L0 <37>

P1_TO_P2_CADOUT_H15 <37> P1_TO_P2_CADOUT_L15 <37> P1_TO_P2_CADOUT_H14 <37> P1_TO_P2_CADOUT_L14 <37> P1_TO_P2_CADOUT_H13 <37> P1_TO_P2_CADOUT_L13 <37> P1_TO_P2_CADOUT_H12 <37> P1_TO_P2_CADOUT_L12 <37> P1_TO_P2_CADOUT_H11 <37> P1_TO_P2_CADOUT_L11 <37> P1_TO_P2_CADOUT_H10 <37> P1_TO_P2_CADOUT_L10 <37> P1_TO_P2_CADOUT_H9 <37> P1_TO_P2_CADOUT_L9 <37> P1_TO_P2_CADOUT_H8 <37> P1_TO_P2_CADOUT_L8 <37>

P1_TO_P2_CADOUT_H7 <37> P1_TO_P2_CADOUT_L7 <37> P1_TO_P2_CADOUT_H6 <37> P1_TO_P2_CADOUT_L6 <37> P1_TO_P2_CADOUT_H5 <37> P1_TO_P2_CADOUT_L5 <37> P1_TO_P2_CADOUT_H4 <37> P1_TO_P2_CADOUT_L4 <37> P1_TO_P2_CADOUT_H3 <37> P1_TO_P2_CADOUT_L3 <37> P1_TO_P2_CADOUT_H2 <37> P1_TO_P2_CADOUT_L2 <37> P1_TO_P2_CADOUT_H1 <37> P1_TO_P2_CADOUT_L1 <37> P1_TO_P2_CADOUT_H0 <37> P1_TO_P2_CADOUT_L0 <37>

U66C

P0_TO_P1_CLKOUT_H1<19> P0_TO_P1_CLKOUT_L1<19> P0_TO_P1_CLKOUT_H0<19> P0_TO_P1_CLKOUT_L0<19>

P0_TO_P1_CTLOUT_H1<19> P0_TO_P1_CTLOUT_L1<19> P0_TO_P1_CTLOUT_H0<19> P0_TO_P1_CTLOUT_L0<19>

B B

A A

P0_TO_P1_CADOUT_H15<19> P0_TO_P1_CADOUT_L15<19> P0_TO_P1_CADOUT_H14<19> P0_TO_P1_CADOUT_L14<19> P0_TO_P1_CADOUT_H13<19> P0_TO_P1_CADOUT_L13<19> P0_TO_P1_CADOUT_H12<19> P0_TO_P1_CADOUT_L12<19> P0_TO_P1_CADOUT_H11<19> P0_TO_P1_CADOUT_L11<19> P0_TO_P1_CADOUT_H10<19> P0_TO_P1_CADOUT_L10<19> P0_TO_P1_CADOUT_H9<19> P0_TO_P1_CADOUT_L9<19> P0_TO_P1_CADOUT_H8<19> P0_TO_P1_CADOUT_L8<19>

P0_TO_P1_CADOUT_H7<19> P0_TO_P1_CADOUT_L7<19> P0_TO_P1_CADOUT_H6<19> P0_TO_P1_CADOUT_L6<19> P0_TO_P1_CADOUT_H5<19> P0_TO_P1_CADOUT_L5<19> P0_TO_P1_CADOUT_H4<19> P0_TO_P1_CADOUT_L4<19> P0_TO_P1_CADOUT_H3<19> P0_TO_P1_CADOUT_L3<19> P0_TO_P1_CADOUT_H2<19> P0_TO_P1_CADOUT_L2<19> P0_TO_P1_CADOUT_H1<19> P0_TO_P1_CADOUT_L1<19> P0_TO_P1_CADOUT_H0<19> P0_TO_P1_CADOUT_L0<19>

5

AK7 AK8 AM7 AN7

AM12

AL12 AP11 AP12

AK11 AK12 AM10

AL10

AK9

AK10

AM8 AL8 AM6 AL6 AK5 AK6 AM4 AL4 AK3 AK4

AM11 AN11

AP9

AP10

AM9 AN9 AP7 AP8 AP5 AP6 AM5 AN5 AP3 AP4 AM3 AN3

L2_CLKIN_H(1) L2_CLKIN_L(1) L2_CLKIN_H(0) L2_CLKIN_L(0)

L2_CTLIN_H(1) L2_CTLIN_L(1) L2_CTLIN_H(0) L2_CTLIN_L(0)

L2_CADIN_H(15) L2_CADIN_L(15) L2_CADIN_H(14) L2_CADIN_L(14) L2_CADIN_H(13) L2_CADIN_L(13) L2_CADIN_H(12) L2_CADIN_L(12) L2_CADIN_H(11) L2_CADIN_L(11) L2_CADIN_H(10) L2_CADIN_L(10) L2_CADIN_H(9) L2_CADIN_L(9) L2_CADIN_H(8) L2_CADIN_L(8)

L2_CADIN_H(7) L2_CADIN_L(7) L2_CADIN_H(6) L2_CADIN_L(6) L2_CADIN_H(5) L2_CADIN_L(5) L2_CADIN_H(4) L2_CADIN_L(4) L2_CADIN_H(3) L2_CADIN_L(3) L2_CADIN_H(2) L2_CADIN_L(2) L2_CADIN_H(1) L2_CADIN_L(1) L2_CADIN_H(0) L2_CADIN_L(0)

L2_CLKOUT_H(1)

L2_CLKOUT_L(1)

L2_CLKOUT_H(0)

L2_CLKOUT_L(0) L2_CTLOUT_H(1)

L2_CTLOUT_L(1) L2_CTLOUT_H(0) L2_CTLOUT_L(0)

L2_CADOUT_H(15)

L2_CADOUT_L(15)

L2_CADOUT_H(14)

L2_CADOUT_L(14)

L2_CADOUT_H(13)

L2_CADOUT_L(13)

L2_CADOUT_H(12)

L2_CADOUT_L(12)

L2_CADOUT_H(11)

L2_CADOUT_L(11)

L2_CADOUT_H(10)

L2_CADOUT_L(10)

L2_CADOUT_H(9) L2_CADOUT_L(9) L2_CADOUT_H(8) L2_CADOUT_L(8)

L2_CADOUT_H(7) L2_CADOUT_L(7) L2_CADOUT_H(6) L2_CADOUT_L(6) L2_CADOUT_H(5) L2_CADOUT_L(5) L2_CADOUT_H(4) L2_CADOUT_L(4) L2_CADOUT_H(3) L2_CADOUT_L(3) L2_CADOUT_H(2) L2_CADOUT_L(2) L2_CADOUT_H(1) L2_CADOUT_L(1) L2_CADOUT_H(0) L2_CADOUT_L(0)

SOCKET-F(1207)

AM18 AN18 AR18 AR17

AL14 AL13 AP13 AN13

AM14 AN14 AL16 AL15 AM16 AN16 AL18 AL17 AL20 AL19 AM20 AN20 AL22 AL21 AM22 AN22

AR14 AR13 AP15 AN15 AR16 AR15 AP17 AN17 AP19 AN19 AR20 AR19 AP21 AN21 AR22 AR21

4

P1_TO_P0_CLKOUT_H1 <19> P1_TO_P0_CLKOUT_L1 <19> P1_TO_P0_CLKOUT_H0 <19> P1_TO_P0_CLKOUT_L0 <19>

P1_TO_P0_CTLOUT_H1 <19> P1_TO_P0_CTLOUT_L1 <19> P1_TO_P0_CTLOUT_H0 <19> P1_TO_P0_CTLOUT_L0 <19>

P1_TO_P0_CADOUT_H15 <19> P1_TO_P0_CADOUT_L15 <19> P1_TO_P0_CADOUT_H14 <19> P1_TO_P0_CADOUT_L14 <19> P1_TO_P0_CADOUT_H13 <19> P1_TO_P0_CADOUT_L13 <19> P1_TO_P0_CADOUT_H12 <19> P1_TO_P0_CADOUT_L12 <19> P1_TO_P0_CADOUT_H11 <19> P1_TO_P0_CADOUT_L11 <19> P1_TO_P0_CADOUT_H10 <19> P1_TO_P0_CADOUT_L10 <19> P1_TO_P0_CADOUT_H9 <19> P1_TO_P0_CADOUT_L9 <19> P1_TO_P0_CADOUT_H8 <19> P1_TO_P0_CADOUT_L8 <19>

P1_TO_P0_CADOUT_H7 <19> P1_TO_P0_CADOUT_L7 <19> P1_TO_P0_CADOUT_H6 <19> P1_TO_P0_CADOUT_L6 <19> P1_TO_P0_CADOUT_H5 <19> P1_TO_P0_CADOUT_L5 <19> P1_TO_P0_CADOUT_H4 <19> P1_TO_P0_CADOUT_L4 <19> P1_TO_P0_CADOUT_H3 <19> P1_TO_P0_CADOUT_L3 <19> P1_TO_P0_CADOUT_H2 <19> P1_TO_P0_CADOUT_L2 <19> P1_TO_P0_CADOUT_H1 <19> P1_TO_P0_CADOUT_L1 <19> P1_TO_P0_CADOUT_H0 <19> P1_TO_P0_CADOUT_L0 <19>

Micro-Star Int'l Co., Ltd.

No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw

Title

Size Document Number Rev

Date: Sheet

3

2

Date: Sheet

CPU1 HT Interface

MS-9184

1

0ACustom

of

28 92Tuesday, September 05, 2006

MSI MS-9184 9184_0A_0831

Specifications and Main Features

Frequently Asked Questions

User Manual