MSI MS-9181, MS- Schematic 21

A B C

Dell Controlled Print

D

REVISIONS

1

2

3

SUB=NP Always no-pop
SUB=NP0 Populate only for debug

BOM options

0 = 5708 Production
1 = 5708 development

2 = LOM2 5721J
3 = CTPM Sinosun Populated

4 = ROW TPM ST Populated
6 = LOM1 5721J

7 = Adds London Parts
8 = Adds Berlin Parts
9 = Adds System Test debug components (non-production)

BOM Instructions

Builds 0, 1, and 2 are leveraged from Montreal
builds 7 and 8 are specfic to london/berlin

Build 3 is specific to China TPM (CTPM)
In order to build a proper BOM, you must run a combo build
To build london for production (ROW TPM), use builds 0, 4 and 7

To build london for production (CTPM), use builds 0, 3 and 7
To build a 5708 debug build for london (ROW TPM) use builds 1,4 and 7

To build Berlin for production (ROW TPM), use builds 0,4 and 8
To build Berlin for production (CTPM), use builds 0, 3 and 8

To build a 5708 debug build for berlin (ROW TPM) use builds 1,4 and 8
Only add build 5 if you want microview parts

London system test build (With ROW TPM) is a combined build of 0479
London system test build (With CTPM) is a combined build of 0379

Berlin system test build (With ROW TPM) is a combined build of 0489
Berlin system test build (With CTPM) is a combined build of 0389

REV

X00

PNR724925

229098 09/07/2007

INITIAL PROTOTYPE RELEASE
INITIAL PRODUCTION RELEASE

DESCRIPTIONECO DATE

TABLE OF CONTENTS

Page 1-11.
Page 12-15.
Page 16-19.
Page 20-21.
Page 22-29.
Page 30-31.
Page 32-39.
Page 40-43.

Page 45.
Page 46-47.

Page 59.
Page 60.
Page 61.
Page 62.
Page 63.
Page 64-65.
Page 66.
Page 67.
Page 68.
Page 69.
Page 70.
Page 71-73.
Page 74-79.
Page 81-82.
Page 83-84.
Page 85.
Page 86-88
Page 89. BMC - temp sensors/debug port
Page 90.
Page 91.
Page 92.
Page 93.
Page 80, 94.
Page 95.
Page 96.
Page 97-103.
Page 104-107.
Page 108-119.
Page 120.
Page 121.
Page 122.
Page 123.
Page 124.
Page 125. Impedance Coupons (48SE, 50SE, 75D, 85D)

Page 126-127.
Page 128-129.
Page 130-135.
Page 136.

BLOCK DIAGRAMS
Processor 0
Processor 1
XDP0 and GTL Translation
Blackford MCH
CPU decoupling
FB DIMMs (8)
Blank
FBD ResetPage 44.
Clock Generator: CK410B
Clock buffer: DB1200
Clock buffer: DB800Page 48.
ESB2Page 49-57.
USB Connectors and ButtonsPage 58.
Floppy Connector
Blank (LAI Connectors if there is room)
SATA Connectors
Voltage Doubler and Intusion Detect
ESB2 I2C MUX and Header
Blank
Super I/O
TPM, PCI Reset, Jumpers
Firmware Hub
Coin Cell Battery
Sideplane (PERC5/I, Control Panel, IDE)
Risers (3)
Blank, PME to Wake on Page 77
Broadcom LOM 1
Broadcom LOM 2
LOM power switch
BMC

COM port
BMC I2C MUX and Header
San Marco Connectors (Mgmt, MII)
Rear ID, Cyclops
Fan Connectors and Tach
BMC - CPLD, master and slave
OmniIVu- CPLD and header
Video RN50
Video Output
VRDs
Power Connectors
Power LED
Power sequencing and VRD enable chaining
Ground Clips
Impedance Coupons (90D, 95D, 100D)

System powergood and Reset buffering
Second source CPLDs
Blank, strappings, SATA, OV/UV
+1.8V Current sense

APPROVED

JINTO JOSE02/25/2007
JINTO JOSEA00

1

2

3

4

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

Berlin MLK PWA (CTPM): XR362

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY
OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN
WHOLE OR IN PART AND MUST BE RETURNED TO DELL INC.
UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE
OF THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED
FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE
LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

M2LB_Change_Note:
1 - 11, 13, 17, 24, 28, 29, 32 - 43,

45 - 51, 53, 54, 58 - 61, 64 - 66, 68, 70 - 81,
83, 86 - 88, 89, 90, 94, 95, 106, 108 - 128

PROPRIETARY NOTE

London MLK PWA (ROW): HX368London MLK PWA (CTPM): RU411
Berlin MLK PWA (ROW): TT740
PWB: JN309
SCH: HX601
London MLK ASSY: WY108
Berlin MLK ASSY: CR344

DRAWN

DESIGNED

CHECKED

APPROVED

APPROVED

APPROVED

APPROVED

RELEASED

SHOBHIT CHAHAR
SHOBHIT CHAHAR
JINTO N JOSE
JINTO N JOSE

04/04/2007
04/04/2007
06/15/2007
06/15/2007

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO
ECO

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

INC.

ROUND ROCK,TEXAS

HX601

DATE

SHEET

9/7/2007 1 OF 136

09/07/2007229098

4

REV.

A00

DCBA

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

P19_DT9214_rt_update_block_diagram

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 2 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

P19_DT9214_rt_update_block_diagram

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 3 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 4 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 5 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 6 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

Powerup Timing- VRDs

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 7 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

Power up Timing - Chipset

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 8 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

9/7/2007 9 OF 136

DCBA

4

A00

A B C

D

1

1

2

2

3

3

4

JTAG Block Diagram

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 10 OF 136

DCBA

4

A B C

D

1

1

2

2

3

3

4

NOTE: this is not completely up to date

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 11 OF 136

DCBA

4

1

2

3

A B C

J_CPU0

MOD_MCH_FSB0_A16_N

22

MOD_MCH_FSB0_A15_N

22

MOD_MCH_FSB0_A14_N

22

MOD_MCH_FSB0_A13_N

22

MOD_MCH_FSB0_A12_N

22

MOD_MCH_FSB0_A11_N

22

MOD_MCH_FSB0_A10_N

22

MOD_MCH_FSB0_A9_N

22

MOD_MCH_FSB0_A8_N

22

MOD_MCH_FSB0_A7_N

22

MOD_MCH_FSB0_A6_N

22

MOD_MCH_FSB0_A5_N

22

MOD_MCH_FSB0_A4_N

22

MOD_MCH_FSB0_A3_N

22

MOD_MCH_FSB0_REQ_4_N

22

MOD_MCH_FSB0_REQ_3_N

22

MOD_MCH_FSB0_REQ_2_N

22

MOD_MCH_FSB0_REQ_1_N

22

MOD_MCH_FSB0_REQ_0_N

22

MOD_MCH_FSB0_ADSTB_0_N

22

MOD_MCH_FSB0_D15_N

22

MOD_MCH_FSB0_D14_N

22

MOD_MCH_FSB0_D13_N

22

MOD_MCH_FSB0_D12_N

22

MOD_MCH_FSB0_D11_N

22

MOD_MCH_FSB0_D10_N

22

MOD_MCH_FSB0_D9_N

22

MOD_MCH_FSB0_D8_N

22

MOD_MCH_FSB0_D7_N

22

MOD_MCH_FSB0_D6_N

22

MOD_MCH_FSB0_D5_N

22

MOD_MCH_FSB0_D4_N

22

MOD_MCH_FSB0_D3_N

22

MOD_MCH_FSB0_D2_N

22

MOD_MCH_FSB0_D1_N

22

MOD_MCH_FSB0_D0_N

22

MOD_MCH_FSB0_DBI_0_N

22

MOD_MCH_FSB0_DSTBN_0_N

22

MOD_MCH_FSB0_DSTBP_0_N

22

MOD_MCH_FSB0_D31_N

22

MOD_MCH_FSB0_D30_N

22

MOD_MCH_FSB0_D29_N

22

MOD_MCH_FSB0_D28_N

22

MOD_MCH_FSB0_D27_N

22

MOD_MCH_FSB0_D26_N

22

MOD_MCH_FSB0_D25_N

22

MOD_MCH_FSB0_D24_N

22

MOD_MCH_FSB0_D23_N

22

MOD_MCH_FSB0_D22_N

22

MOD_MCH_FSB0_D21_N

22

MOD_MCH_FSB0_D20_N

22

MOD_MCH_FSB0_D19_N

22

MOD_MCH_FSB0_D18_N

22

MOD_MCH_FSB0_D17_N

22

MOD_MCH_FSB0_D16_N

22

MOD_MCH_FSB0_DBI_1_N

22

MOD_MCH_FSB0_DSTBN_1_N

22

MOD_MCH_FSB0_DSTBP_1_N

22

W5

A16_N

V4

A15_N

V5

A14_N

U4

A13_N

U5

A12_N

T4

A11_N

U6

A10_N

T5

A9_N

R4

A8_N

M4

A7_N

L4

A6_N

L5

A5_N

P6

A4_N

M5

A3_N

J6

REQ_4_N

K6

REQ_3_N

M6

REQ_2_N

J5

REQ_1_N

K4

REQ_0_N

R6 AD5

ADSTB0_N ADSTB1_N

D11

D15_N

C12

D14_N

B12

D13_N

D8

D12_N

C11

D11_N

B10

D10_N

A11

D9_N

A10

D8_N

A7

D7_N

B7

D6_N

B6

D5_N

A5

D4_N

C6

D3_N

A4

D2_N

C5

D1_N

B4

D0_N

A8

DBI0_N

C8

DSTBN0_N

B9

DSTBP0_N

G15

D31_N

F15

D30_N

G14

D29_N

F14

D28_N

G13

D27_N

E13

D26_N

D13

D25_N

F12

D24_N

F11

D23_N

D10

D22_N

E10

D21_N

D7

D20_N

E9

D19_N

F9

D18_N

F8

D17_N

G9

D16_N

G11

DBI1_N

G12

DSTBN1_N

E12

DSTBP1_N

A35_N
A34_N
A33_N
A32_N
A31_N
A30_N
A29_N
A28_N
A27_N
A26_N
A25_N
A24_N
A23_N
A22_N
A21_N
A20_N
A19_N
A18_N
A17_N

D47_N
D46_N
D45_N
D44_N
D43_N
D42_N
D41_N
D40_N
D39_N
D38_N
D37_N
D36_N
D35_N
D34_N
D33_N
D32_N

DBI2_N
DSTBN2_N
DSTBP2_N

D63_N
D62_N
D61_N
D60_N
D59_N
D58_N
D57_N
D56_N
D55_N
D54_N
D53_N
D52_N
D51_N
D50_N
D49_N
D48_N

DBI3_N
DSTBN3_N
DSTBP3_N

INTEL LGA771 PINOUT

HETERO 2 OF 9

SILKSCREEN=CPU1

ADD*_PR288

AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
AB5
AA5
AD6
AA4
Y4
Y6
W6
AB6

G22
D22
E22
G21
F21
E21
F20
E19
E18
F18
F17
G17
G18
E16
E15
G16
D19
G20
G19

B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
B15
C14
C15
A14
D17
D20
C20
A16
C17

MOD_MCH_FSB0_A35_N
MOD_MCH_FSB0_A34_N
MOD_MCH_FSB0_A33_N
MOD_MCH_FSB0_A32_N
MOD_MCH_FSB0_A31_N
MOD_MCH_FSB0_A30_N
MOD_MCH_FSB0_A29_N
MOD_MCH_FSB0_A28_N
MOD_MCH_FSB0_A27_N
MOD_MCH_FSB0_A26_N
MOD_MCH_FSB0_A25_N
MOD_MCH_FSB0_A24_N
MOD_MCH_FSB0_A23_N
MOD_MCH_FSB0_A22_N
MOD_MCH_FSB0_A21_N
MOD_MCH_FSB0_A20_N
MOD_MCH_FSB0_A19_N
MOD_MCH_FSB0_A18_N
MOD_MCH_FSB0_A17_N

MOD_MCH_FSB0_ADSTB_1_N

MOD_MCH_FSB0_D47_N
MOD_MCH_FSB0_D46_N
MOD_MCH_FSB0_D45_N
MOD_MCH_FSB0_D44_N
MOD_MCH_FSB0_D43_N
MOD_MCH_FSB0_D42_N
MOD_MCH_FSB0_D41_N
MOD_MCH_FSB0_D40_N
MOD_MCH_FSB0_D39_N
MOD_MCH_FSB0_D38_N
MOD_MCH_FSB0_D37_N
MOD_MCH_FSB0_D36_N
MOD_MCH_FSB0_D35_N
MOD_MCH_FSB0_D34_N
MOD_MCH_FSB0_D33_N

MOD_MCH_FSB0_D32_N
MOD_MCH_FSB0_DBI_2_N
MOD_MCH_FSB0_DSTBN_2_N
MOD_MCH_FSB0_DSTBP_2_N

MOD_MCH_FSB0_D63_N

MOD_MCH_FSB0_D62_N

MOD_MCH_FSB0_D61_N

MOD_MCH_FSB0_D60_N

MOD_MCH_FSB0_D59_N

MOD_MCH_FSB0_D58_N

MOD_MCH_FSB0_D57_N

MOD_MCH_FSB0_D56_N

MOD_MCH_FSB0_D55_N

MOD_MCH_FSB0_D54_N

MOD_MCH_FSB0_D53_N

MOD_MCH_FSB0_D52_N

MOD_MCH_FSB0_D51_N

MOD_MCH_FSB0_D50_N

MOD_MCH_FSB0_D49_N

MOD_MCH_FSB0_D48_N
MOD_MCH_FSB0_DBI_3_N
MOD_MCH_FSB0_DSTBN_3_N
MOD_MCH_FSB0_DSTBP_3_N

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22
22
22

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22
22
22

Processor 0 heatsink retention modules

ST1

NC_MOD_MCH_ST1_1
NC_MOD_MCH_ST1_2

10

1
2
3
4
5
6
7
8
9

NC1
NC2
GND_V1
GND_V2
GND_V3
GND_V4
GND_V5
GND_V6
GND_V7
GND_V8

BRACKET RETENTION
SUPPORT, GROUNDED

ADD1=ADD*_JC664

ADD2=ADD*_JC664

ADD3=ADD*_JC664

NOTE : heatsink retention clips needing a single trace to each pin, not solid

connection concern doesn't apply to the CPU HS brackets

Nocona-T Dempsy-T Dempsy/WoodcrestPlatform Change

requiredrequired

Use "LE" Blackford

Pull down reserved pin F6

Pull down MS_ID[1:0] to Vss

Isolate LL_ID[1:0]

Manually set VR loadline

required

optional

optional

optional

required required

required

required

required

required

Mechanical Parts on the following pages:
12, 16

Socket J part numbers:

DescriptionDell p/n

Y9236

P9381

Leaded Socket J - SKT,LGA,771P,G,SF,ZIF,SL,SM
Vendors:

Foxconn PN: PE077107-1041-01
Tyco PN: 1747890-1

Lead-free socket J - SKT,LGA,771P,G,SF,ZIF,SL,SM
Vendors:

Foxconn PN: PE077127-1041-01
Tyco PN: 1-1747890-1

D

CPU Heatsink

frame screws

ADD4=ADD*_RC078
ADD5=ADD*_RC078
ADD6=ADD*_RC078
ADD7=ADD*_RC078

1

CPU Heatsink

clip asm

ADD8=ADD*_H3668
ADD9=ADD*_H3668

2

No use LGA771Use LGA775

No use real blackford

No treat as reserved and leave pin No Connect

No revert back to POR

No revert back to POR

No revert back to POR

3

4

ROOM=PROC0

ECAD NOTE: Please put triangle pointing to pin1

CPU0_REG

NC_CPU0_REG_1 NC_CPU0_REG_2

1 2

COMMON NEG

REG07 A NGO
COUPON TEST

ROOM=PROC0

PROCESSOR 0

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

C

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

HX601

SHEET

12 OF 1369/7/2007

DBA

CPUS,FSB,NB,XDP0,XDP1

SEC

REV.

A00

MCH

211

4

A B C

D

9-7-2007_16:36

1

2

3

13,117
13,117
13,117
13,117
13,117
13,117

13,117

15

15,17,21,54

NP

X

1 2

C8600

15,95,117,128

MLK: Routed to CPLD for CPU Identification

13,95,117,128

FSB0_VID_6
FSB0_VID_5
FSB0_VID_4
FSB0_VID_3
FSB0_VID_2
FSB0_VID_1

FSB0_VID_0

MOD_MCH_CPU0_BSEL_2

20

MOD_MCH_CPU0_BSEL_1

20

MOD_MCH_CPU0_BSEL_0

20

MOD_MCH_FSB0_GTLREF_DATA_CORE1

15

MOD_MCH_FSB0_GTLREF_ADD_CORE1

15

MOD_MCH_FSB0_GTLREF_DATA_CORE0

15

MOD_MCH_FSB0_GTLREF_ADD_CORE0

CPU_PWRGOOD

15
15
15

100pF

50V-5%

15
15
15
15
15

13,117
13,117
13,117
13,117
13,117
13,117
13,117

15
15
15

117
117
117
117

13,89
13,89

**

CPU0_VCC_DIE_SENSE
CPU0_VCC_DIE_SENSE2
CPU0_VSS_DIE_SENSE
CPU0_VSS_DIE_SENSE2

CPU0_PRES_N
CPU0_THERMD_A_1

89

CPU0_THERMD_A_2

89

CPU0_THERMD_C_12
CPU0_THERMD_C_12

*

NC_MOD_MCH_FSB0_DBR_N

*

NC_MOD_MCH_FSB0_ITP_CLK1

*

NC_MOD_MCH_FSB0_ITP_CLK0
NC_MOD_MCH_FSB0_RSVD_Y1
MOD_MCH_FSB0_TESTBUS

15

MOD_MCH_FSB0_COMP_3

MOD_MCH_FSB0_COMP_1

MOD_MCH_FSB0_COMP_0

FSB0_VID_6
FSB0_VID_5
FSB0_VID_4
FSB0_VID_3
FSB0_VID_2
FSB0_VID_1
FSB0_VID_0
FSB0_VID_SELECT

MOD_MCH_V_VTT_FSB0_VCCA
MOD_MCH_V_VSS_FSB0_VSSA
MOD_MCH_V_1V5_FSB0_VCCPLL

21

R4248

R4247

MOD_MCH_FSB0_COMP_5

MOD_MCH_FSB0_COMP_4

MOD_MCH_FSB0_COMP_2

511-1%

1 2

MOD_MCH_FSB0_COMP_7
MOD_MCH_FSB0_COMP_6

511-1%

R4249

1 2

+CPU_VTT

21

R4250

511-1%

511-1%

R4251

1 2

21

R4252

511-1%

+CPU_VTT

511-1%

R26

R4253

G30
H30
G29

F2
H2

G10

H1
N1

AE3

Y3
T2
J2
R1
G2
T1

A13

AM5
AL4
AK4
AL6
AM3
AL5
AM2
AN7

A23
B23
D23
C23
AN3
AL8
AN4
AL7 AM6

AE8
AL1
AJ7
AK1
AH7
AC2
AJ3
AK3

Y1

AH2

511-1%

1 2

J_CPU0

BSEL2
BSEL1
BSEL0
GTLREF_DATA_CORE1
GTLREF_ADD_CORE1
GTLREF_DATA_CORE0
GTLREF_ADD_CORE0
PWRGOOD
COMP7
COMP6
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID_SELECT

VCCA
VSSA
VCCPLL
VCCIOPLL
VCC_DIE_SENSE
VCC_DIE_SENSE2
VSS_DIE_SENSE
VSS_DIE_SENSE2 VTTPWRGD

SKTOCC_N
THERMDA
THERMDA2
THERMDC
THERMDC2
DBR_N
ITP_CLK1
ITP_CLK0
BOOT_SELECT
TEST_BUS

INTEL LGA771 PINOUT

HETERO 3 OF 9

SILKSCREEN=CPU1

51-5%

1 2

MOD_MCH_XDP0_TDI_CPU0

MLK: Pull Up Added on XDP0_TDI_CPU0 signal

VTT_A25
VTT_A26
VTT_B25
VTT_B26
VTT_B27
VTT_B28
VTT_B29
VTT_B30
VTT_C25
VTT_C26
VTT_C27
VTT_C28
VTT_C29
VTT_C30
VTT_D25
VTT_D26
VTT_D27
VTT_D28
VTT_D29

VTT_D30
VTT_E30/NC_E30
VTT_F30/NC_F30

VTT_OUT_1
VTT_OUT_0

VTT_SEL

LL_ID1
LL_ID0
MS_ID1
MS_ID0

A25
A26
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
E30
F30

AA1
J1
F27

AA2
V2
V1
W1

13,21

+CPU_VTT

MOD_MCH_VTT_CPU_PWRGOOD

NC_MOD_MCH_FSB0_VTT_OUT_1
NC_MOD_MCH_FSB0_VTT_OUT_0

MOD_MCH_VTT_SEL_CPU0

MOD_MCH_CPU0_LL_ID1_R

MOD_MCH_CPU0_LL_ID0_R
CPU0_MS_ID1
CPU0_MS_ID0

15,17,20

13,95,128
13,95,128

15,22

45
45

15,17,54
15,17,54
15,17,20
15,17,54
15,17,54
15,17,54
15,17,54

15,17,54

17,21
13,21

17,21,24
17,21,24

15,20

15,17,54

15,20
15,20

MOD_MCH_FSB0_TESTHI_11

15

MOD_MCH_FSB0_TESTHI_10

15

21
21

15

15

MLK: VTT_SEL Signal going to VTT REG Ckt

109

R5498

0-5%

12

R5499

12

0-5%

MOD_MCH_FSB0_BPMB_2_N
MOD_MCH_FSB0_BPMB_3_N

MOD_MCH_FSB0_TESTHI_02_07

MOD_MCH_FSB0_TESTHI_00_01

CPU0_LL_ID1

Depop for dempsyT

MOD_MCH_XDP0_TCK0
MOD_MCH_XDP0_TDI_CPU0
MOD_MCH_XDP0_TDO_CPU0

21

MOD_MCH_XDP0_TMS
MOD_MCH_XDP0_TRST_N

MOD_MCH_CPU0_IERR_N
FSB_FERR_N
MOD_MCH_CPU0_PROCHOT_N
MOD_MCH_CPU0_THERMTRIP_N

CPU0_LL_ID0

MOD_MCH_FSB0_RST_N
MOD_MCH_FSB0_RSP_N

22

MOD_MCH_FSB0_BPRI_N

22

MOD_MCH_FSB0_TRDY_N

22

MOD_MCH_FSB0_DEFER_N

22

MOD_MCH_FSB0_RS_0_N

22

MOD_MCH_FSB0_RS_1_N

22
22

MOD_MCH_FSB0_RS_2_N

CK_333M_CPU0_N
CK_333M_CPU0_P

FSB_SMI_N
FSB_A20M_N

MOD_MCH_CPU_FORCEPR_N

FSB_INTR
FSB_NMI
FSB_IGNNE_N
FSB_STPCLK_N

FSB_INIT_N

117

117

+3.3V

G23

RESET_N

H4

RSP_N

G8

BPRI_N

E3

TRDY_N

G7

DEFER_N

B3

RS0_N

F5

RS1_N

A3

RS2_N

G28

BCLK1

P2

SMI_N

K3

A20M_N

AK6

FORCEPR_N

K1

LINT0

L1

LINT1

N2

IGNNE_N

M3

STPCLK_N

P3

INIT_N

AE1

TCK

AD1

TDI

AF1

TDO

AC1

TMS

AG1

TRST_N

AB2

IERR_N

R3

FERR/PBE_N

AL2

PROCHOT_N

M2

THRMTRIP_N

L2

TESTHI11

P1

TESTHI10

G4

TESTHI09/BPMB2_N

G3

TESTHI08/BPMB3_N

F24

TESTHI07

G24

TESTHI06

G26

TESTHI05

G27

TESTHI04

G25

TESTHI03

F25

TESTHI02

W3

TESTHI01

F26

TESTHI00

J_CPU0

INTEL LGA771 PINOUT

HETERO 1 OF 9

SILKSCREEN=CPU1

J_CPU0

Clovertown

INTEL LGA771 PINOUT

HETERO 4 OF 9

SILKSCREEN=CPU1

ADS_N
BNR_N

HIT_N
DBSY_N
DRDY_N
HITM_N
LOCK_N

BINIT_N
MCERR_N

AP1_NBCLK0

AP0_N

BR1_N

BR0_N

DP3_N

DP2_N

DP1_N

DP0_N

BPM5_N
BPM4_N

BPM3_N
BPM2_N
BPM1_N
BPM0_N

D2
C2
D4
B2
C1
E4
C3
AD3
AB3

U3F28
U2
H5
F3

J17
H16
H15
J16

AG3
AF2
AG2
AD2
AJ1
AJ2

RSVD_C9/BPMB1_N

RSVD_E1/NC_E1

RSVD_W2/TESTIN1

MOD_MCH_FSB0_BPM_5_N
MOD_MCH_FSB0_BPM_4_N
MOD_MCH_FSB0_BPM_3_N
MOD_MCH_FSB0_BPM_2_N
MOD_MCH_FSB0_BPM_1_N
MOD_MCH_FSB0_BPM_0_N

RSVD_A20
RSVD_AC4
RSVD_AE4
RSVD_AE6
RSVD_B13

RSVD_D1
RSVD_D14
RSVD_D16
RSVD_E23
RSVD_E24

RSVD_E5

RSVD_E6

RSVD_E7
RSVD_F23
RSVD_F29

RSVD_F6

PECI
RSVD_G6
RSVD_J3
RSVD_N4
RSVD_N5
RSVD_P5

RSVD_AN5
RSVD_AN6

MOD_MCH_FSB0_ADS_N
MOD_MCH_FSB0_BNR_N
MOD_MCH_FSB0_HIT_N
MOD_MCH_FSB0_DBSY_N
MOD_MCH_FSB0_DRDY_N
MOD_MCH_FSB0_HITM_N
MOD_MCH_FSB0_LOCK_N
MOD_MCH_FSB0_BINIT_N
MOD_MCH_FSB0_MCERR_N

MOD_MCH_FSB0_AP_1_N
MOD_MCH_FSB0_AP_0_N
MOD_MCH_FSB0_BREQ_1_N
MOD_MCH_FSB0_BREQ_0_N

MOD_MCH_FSB0_DP_3_N
MOD_MCH_FSB0_DP_2_N
MOD_MCH_FSB0_DP_1_N
MOD_MCH_FSB0_DP_0_N

A20
AC4
AE4
AE6
B13
C9
D1
D14
D16
E23
E24
E1
E5
E6
E7
F23
F29
F6
G5
G6
J3
N4
N5
P5
AN5
AN6
W2

NC_MOD_MCH_FSB0_RSVD_A20
NC_MOD_MCH_FSB0_RSVD_AC24
NC_MOD_MCH_FSB0_RSVD_AE24
NC_MOD_MCH_FSB0_RSVD_AE6
NC_MOD_MCH_FSB0_RSVD_B13

NC_MOD_MCH_FSB0_RSVD_D1
NC_MOD_MCH_FSB0_RSVD_D14
NC_MOD_MCH_FSB0_RSVD_D16
NC_MOD_MCH_FSB0_RSVD_E23
NC_MOD_MCH_FSB0_RSVD_E24
NC_MOD_MCH_FSB0_RSVD_E1
NC_MOD_MCH_FSB0_RSVD_E5
NC_MOD_MCH_FSB0_RSVD_E6
NC_MOD_MCH_FSB0_RSVD_E7
NC_MOD_MCH_FSB0_RSVD_F23
NC_MOD_MCH_FSB0_RSVD_F29

PECI_CPU
NC_MOD_MCH_FSB0_RSVD_G6
NC_MOD_MCH_FSB0_RSVD_J3
NC_MOD_MCH_FSB0_RSVD_N4
NC_MOD_MCH_FSB0_RSVD_N5
NC_MOD_MCH_FSB0_RSVD_P5
NC_MOD_MCH_FSB0_RSVD_AN5
NC_MOD_MCH_FSB0_RSVD_AN6

MOD_MCH_CPU0_TESTIN

22
22
22
22
22
22
22
22
22

22
22
15,22
15,22

22
22
22
22

21,22
21,22
21
21
21
21

MOD_MCH_FSB0_BPMB_1_N

MOD_MCH_FSB0_F6_PD_DEMPSY_T

17,90

14,15

Don't care for NoconaT
Populate for DempseyT
Depop for Dempsey/Woodcrest

NP

R5495

X

2 1

1

2

21

3

49.9-1%

4

Do not place VTT_SEL or CPU_PRES_N on 3v3Aux, VTT_SEL is used in main domain VRD logic,
CPU_PRES_N is used on 3v3 part during development.
The rest are placed on 3v3 to simplify routing, no need for 3v3 aux near CPU.ort (leave LL_ID float)

ECAD: VCC/VSS_DIE_SENSE LINES

Route DIFF @ 25mil thick /5 mil space, same length, 20mil to other sigs
Follow PDG 0.7 256-257

ECAD: CPU THERMD_C_12 to be routed as 2 nets, differentially with A_1 and A_2. Only bring nets together as they enter sensor

* NOTE: DBR and ITP_CLK are outputs from a in-socket debugger- Dell has no plans for this debug model.mpsey-T support8
** NOTE: WW10 MOW documents that bootselect is being removed

and to leave pin floating

ROOM=PROC0

13,95,117,128

13,95,128
13,95,128

CPU0_PRES_N
CPU0_MS_ID1
CPU0_MS_ID0

R211

1 2

4.7K-5%

R4829

NP

R5503

X

1 2

2 1

R4828

4.7K-5%

1 2

NP

R5502

X

49.9-1%

2 1

Depop for dempsyT

4.7K-5%49.9-1%

Pop for DempseyT

PROCESSOR 0

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

M2LB_Change_Note:
Changed PECI_CPU1 to PECI_CPU.

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

HX601

DATE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

REV.

A00

SHEET

13 OF 1369/7/2007

MCH

211

4

C

DBA

A B C

D

1

2

3

21

13,15

NC_J_CPU0_A24.

NC_J_CPU0_E29
MOD_MCH_FSB0_BPMB_0_N
MOD_MCH_CPU0_TESTIN

AA8

AB8
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30

AC8
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30

AD8
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23

AE9
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22

AF8

AF9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30

AG8

AG9
AH11

VCC_AA8
VCC_AB8
VCC_AC23
VCC_AC24
VCC_AC25
VCC_AC26
VCC_AC27
VCC_AC28
VCC_AC29
VCC_AC30
VCC_AC8
VCC_AD23
VCC_AD24
VCC_AD25
VCC_AD26
VCC_AD27
VCC_AD28
VCC_AD29
VCC_AD30
VCC_AD8
VCC_AE11
VCC_AE12
VCC_AE14
VCC_AE15
VCC_AE18
VCC_AE19
VCC_AE21
VCC_AE22
VCC_AE23
VCC_AE9
VCC_AF11
VCC_AF12
VCC_AF14
VCC_AF15
VCC_AF18
VCC_AF19
VCC_AF21
VCC_AF22
VCC_AF8
VCC_AF9
VCC_AG11
VCC_AG12
VCC_AG14
VCC_AG15
VCC_AG18
VCC_AG19
VCC_AG21
VCC_AG22
VCC_AG25
VCC_AG26
VCC_AG27
VCC_AG28
VCC_AG29
VCC_AG30
VCC_AG8
VCC_AG9
VCC_AH11

SILKSCREEN=CPU1

A24
E29

G1
U1

J_CPU0

INTEL LGA771 PINOUT

HETERO 5 OF 9

J_CPU0

VSS_A24/RSVD
VSS_E29/RSVD
VSS_G1/BPMB0_N
VSS_U1/TESTIN2

Clovertown

INTEL LGA771 PINOUT

HETERO 9 OF 9

VCC_AH12
VCC_AH14
VCC_AH15
VCC_AH18
VCC_AH19
VCC_AH21
VCC_AH22
VCC_AH25
VCC_AH26
VCC_AH27
VCC_AH28
VCC_AH29
VCC_AH30

VCC_AH8

VCC_AH9
VCC_AJ11
VCC_AJ12
VCC_AJ14
VCC_AJ15
VCC_AJ18
VCC_AJ19
VCC_AJ21
VCC_AJ22
VCC_AJ25
VCC_AJ26

VCC_AJ8

VCC_AJ9
VCC_AK11
VCC_AK12
VCC_AK14
VCC_AK15
VCC_AK18
VCC_AK19
VCC_AK21
VCC_AK22
VCC_AK25
VCC_AK26

VCC_AK8

VCC_AK9
VCC_AL11
VCC_AL12
VCC_AL14
VCC_AL15
VCC_AL18
VCC_AL19
VCC_AL21
VCC_AL22
VCC_AL25
VCC_AL26
VCC_AL29
VCC_AL30

VCC_AL9
VCC_AM11
VCC_AM12

AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30

AL9
AM11
AM12

M23
M24
M25
M26
M27
M28
M29
M30
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
U23
U24
U25
U26
U27
U28
U29
U30
U8
V8
W23
W24
W25
W26
W27
W28
W29
W30
W8
Y8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30

+CPU_VID0

A12
A15
A18

A2

A21

A6

A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA3

AA30

AA6
AA7

AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AB7

AC3

AC6

AC7

AD4

AD7
AE10
AE13
AE16
AE17

AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30

AE5

AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29

AF3
AF30

AF6

AF7
AG10
AG13
AG16
AG17

VSS_A12
VSS_A15
VSS_A18
VSS_A2
VSS_A21

VSS_A6
VSS_A9
VSS_AA23
VSS_AA24
VSS_AA25
VSS_AA26
VSS_AA27
VSS_AA28
VSS_AA29
VSS_AA3
VSS_AA30
VSS_AA6
VSS_AA7
VSS_AB1
VSS_AB23
VSS_AB24
VSS_AB25
VSS_AB26
VSS_AB27
VSS_AB28
VSS_AB29
VSS_AB30
VSS_AB7
VSS_AC3
VSS_AC6
VSS_AC7
VSS_AD4
VSS_AD7
VSS_AE10
VSS_AE13
VSS_AE16
VSS_AE17
VSS_AE2
VSS_AE20
VSS_AE24
VSS_AE25
VSS_AE26
VSS_AE27
VSS_AE28
VSS_AE29
VSS_AE30
VSS_AE5
VSS_AE7
VSS_AF10
VSS_AF13
VSS_AF16
VSS_AF17
VSS_AF20
VSS_AF23
VSS_AF24
VSS_AF25
VSS_AF26
VSS_AF27
VSS_AF28
VSS_AF29
VSS_AF3
VSS_AF30
VSS_AF6
VSS_AF7
VSS_AG10
VSS_AG13
VSS_AG16
VSS_AG17

SILKSCREEN=CPU1

J_CPU0

INTEL LGA771 PINOUT

HETERO 7 OF 9

VSS_AG20
VSS_AG23
VSS_AG24

VSS_AG7

VSS_AH1
VSS_AH10
VSS_AH13
VSS_AH16
VSS_AH17
VSS_AH20
VSS_AH23
VSS_AH24

VSS_AH3

VSS_AH6

VSS_AJ10
VSS_AJ13
VSS_AJ16
VSS_AJ17
VSS_AJ20
VSS_AJ23
VSS_AJ24
VSS_AJ27
VSS_AJ28
VSS_AJ29
VSS_AJ30

VSS_AJ4

VSS_AK10
VSS_AK13
VSS_AK16
VSS_AK17

VSS_AK2
VSS_AK20
VSS_AK23
VSS_AK24
VSS_AK27
VSS_AK28
VSS_AK29
VSS_AK30

VSS_AK5

VSS_AK7
VSS_AL10
VSS_AL13
VSS_AL16
VSS_AL17
VSS_AL20
VSS_AL23
VSS_AL24
VSS_AL27
VSS_AL28

VSS_AL3

VSS_AM1
VSS_AM10
VSS_AM13
VSS_AM16
VSS_AM17
VSS_AM20
VSS_AM23
VSS_AM24
VSS_AM27
VSS_AM28

VSS_AM4

VSS_AM7
VSS_AN01
VSS_AN02
VSS_AN10
VSS_AN13
VSS_AN16

AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6

AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4

AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3

AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AM7
AN1
AN2
AN10
AN13
AN16

AN17
AN20
AN23
AN24

B1
B11
B14
B17
B20
B24

B8

B5
C10
C13
C16
C19
C22
C24

C4

C7
D12
D15
D18
D21
D24

D3

D5

D6

D9
E11
E14
E17

E2
E20
E25
E26
E27
E28

E8

F1
F10
F13
F16
F19
F22

F4

F7

H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29

VSS_AN17
VSS_AN20
VSS_AN23
VSS_AN24
VSS_B1
VSS_B11
VSS_B14
VSS_B17
VSS_B20
VSS_B24
VSS_B5
VSS_B8
VSS_C10
VSS_C13
VSS_C16
VSS_C19
VSS_C22
VSS_C24
VSS_C4
VSS_C7
VSS_D12
VSS_D15
VSS_D18
VSS_D21
VSS_D24
VSS_D3
VSS_D5
VSS_D6
VSS_D9
VSS_E11
VSS_E14
VSS_E17
VSS_E2
VSS_E20
VSS_E25
VSS_E26
VSS_E27
VSS_E28

VSS_E8
VSS_F1
VSS_F10
VSS_F13
VSS_F16
VSS_F19
VSS_F22
VSS_F4
VSS_F7

VSS_H10
VSS_H11
VSS_H12
VSS_H13
VSS_H14
VSS_H17
VSS_H18
VSS_H19
VSS_H20
VSS_H21
VSS_H22
VSS_H23
VSS_H24
VSS_H25
VSS_H26
VSS_H27
VSS_H28
VSS_H29

J_CPU0

INTEL LGA771 PINOUT

HETERO 8 OF 9

SILKSCREEN=CPU1

VSS_H3
VSS_H6
VSS_H7
VSS_H8
VSS_H9
VSS_J4
VSS_J7
VSS_K2
VSS_K5

VSS_K7
VSS_L23
VSS_L24
VSS_L25
VSS_L26
VSS_L27
VSS_L28
VSS_L29

VSS_L3
VSS_L30

VSS_L6

VSS_L7

VSS_M1

VSS_M7

VSS_N3

VSS_N6

VSS_N7
VSS_P23
VSS_P24
VSS_P25
VSS_P26
VSS_P27
VSS_P28
VSS_P29
VSS_P30

VSS_P4

VSS_P7

VSS_R2
VSS_R23
VSS_R24
VSS_R25
VSS_R26
VSS_R27
VSS_R28
VSS_R29
VSS_R30

VSS_R5

VSS_R7

VSS_T3

VSS_T6

VSS_T7

VSS_U7
VSS_V23
VSS_V24
VSS_V25
VSS_V26
VSS_V27
VSS_V28
VSS_V29

VSS_V3
VSS_V30

VSS_V6

VSS_V7

VSS_W4

VSS_W7

VSS_Y2

VSS_Y5

VSS_Y7

9-7-2007_16:36

H3
H6
H7
H8
H9
J4
J7
K2
K5
K7
L23
L24
L25
L26
L27
L28
L29
L3
L30
L6
L7
M1
M7
N3
N6
N7
P23
P24
P25
P26
P27
P28
P29
P30
P4
P7
R2
R23
R24
R25
R26
R27
R28
R29
R30
R5
R7
T3
T6
T7

U7
V23
V24
V25
V26
V27
V28
V29
V3
V30
V6
V7
W4
W7
Y2
Y5
Y7

1

2

3

+CPU_VID0+CPU_VID0

+CPU_VTT

21

+CPU_VID0

21

AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30

AM8

AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AN25
AN26

AN8

AN9

J10

J11

J12

J13

J14

J15

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J8

J9
K23
K24
K25
K26
K27
K28
K29
K30

K8

L8

VCC_AM14
VCC_AM15
VCC_AM18
VCC_AM19
VCC_AM21
VCC_AM22
VCC_AM25
VCC_AM26
VCC_AM29
VCC_AM30
VCC_AM8
VCC_AM9
VCC_AN11
VCC_AN12
VCC_AN14
VCC_AN15
VCC_AN18
VCC_AN19
VCC_AN21
VCC_AN22
VCC_AN25
VCC_AN26
VCC_AN8
VCC_AN9
VCC_J10
VCC_J11
VCC_J12
VCC_J13
VCC_J14
VCC_J15
VCC_J18
VCC_J19
VCC_J20
VCC_J21
VCC_J22
VCC_J23
VCC_J24
VCC_J25
VCC_J26
VCC_J27
VCC_J28
VCC_J29
VCC_J30
VCC_J8
VCC_J9
VCC_K23
VCC_K24
VCC_K25
VCC_K26
VCC_K27
VCC_K28
VCC_K29
VCC_K30
VCC_K8
VCC_L8

INTEL LGA771 PINOUT

SILKSCREEN=CPU1

J_CPU0

VCC_M23
VCC_M24
VCC_M25
VCC_M26
VCC_M27
VCC_M28
VCC_M29
VCC_M30

VCC_M8
VCC_N23
VCC_N24
VCC_N25
VCC_N26
VCC_N27
VCC_N28
VCC_N29
VCC_N30

VCC_N8

VCC_P8

VCC_R8
VCC_T23
VCC_T24
VCC_T25
VCC_T26
VCC_T27
VCC_T28
VCC_T29
VCC_T30

VCC_T8
VCC_U23
VCC_U24
VCC_U25
VCC_U26
VCC_U27
VCC_U28
VCC_U29
VCC_U30

VCC_U8

VCC_V8
VCC_W23
VCC_W24
VCC_W25
VCC_W26
VCC_W27
VCC_W28
VCC_W29
VCC_W30

VCC_W8

VCC_Y8
VCC_Y23
VCC_Y24
VCC_Y25
VCC_Y26
VCC_Y27
VCC_Y28
VCC_Y29
VCC_Y30

HETERO 6 OF 9

Room = PROC0_VTT_CAPS_22UF

C2568

1 2

+CPU_VTT

C2566

22uF 6.3V

21

C2567

1 2

22uF 6.3V

C2565

22uF 6.3V

21

dell p/n C5127

22uF 6.3V

21

Room = PROC0_VTT_CAPS_1uF
dell p/n D8579

C2547

1 2

C2546

1uF 6.3V

C2548

1 2

1uF 6.3V

C2545

1uF 6.3V

C2543

1uF 6.3V

C2544

1 2

1uF 6.3V

1uF 6.3V

4

ROOM=PROC0

SILKSCREEN=CPU1

+CPU_VTT

21

C2587

.1uF

C2586

10V-10%

21

.1uF

C2585

10V-10%

21

TODO: Intel: VTT decoup reqs TBDetero

.1uF

C2588

10V-10%

MODULE:
DESC:
REV: OF

21

21

21

21

Room = PROC0_VTT_CAPS_P1UF

CPUS,FSB,NB,XDP0,XDP1

SEC

dell p/n J5734

.1uF

C2583

10V-10%

.1uF

C2584

10V-10%

.1uF

C2582

10V-10%

.1uF

10V-10%

INC.

ROUND ROCK,TEXAS

TITLE

MCH

211

4

PROCESSOR 0

SCHEM, PLN, SV, PE2950, MLK

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

REV.

HX601

SHEET

A00

9/7/2007 14 OF 136

DCBA

A B C

D

1

MOD_MCH_FSB0_GTLREF_DATA/ ADD
(800mV @1.2V VTT)
(733mV @1.1V VTT)

Place components:
Group associate components together
and as physically close to the associated
pin as possbile with the 220pf cap
closest to the pin

Make traces wide as possible >12mils

ROOM = PROC0_VREF_CORE1

CPU0 GTL VREF

+CPU_VTT

R4379

1 2

49.9-1%

R4386

1 2

21

R4354

680-5%

SUB=NP0

100-1%

TP_MOD_MCH_FSB0_GTLREF_DATA_R

NET_PHYSICAL_TYPE=30MIL

0-5%

R5270

0-5%

R5414

C2601

1 2

1uF 6.3V

Place termination close to CPU 0 at end of bus

rewired 5271 and 5270. Added C3396 C3395 R5415 and R5414

MOD_MCH_FSB0_GTLREF_DATA_CORE1

21

MOD_MCH_FSB0_GTLREF_ADD_CORE1

21

1 2

220pF

50V-10%

C2746

1 2

220pF

50V-10%

ECAD: Place 220pf caps under CPU
ECAD: Route <1.5" trace.
ECAD: Route at 30-50milscs (& Paris) DT#2256

C3395

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

13

13

+CPU_VTT

+3.3V

1 2

51-5%

R4677

R139

R5978

4.7K-5%

NP

1 2

4.7K-5%

1 2

51-5%

21

R210

R140

21

X

FSB0_VID_SELECT

MOD_MCH_FSB0_BREQ_1_N

MOD_MCH_FSB0_BREQ_0_N

MOD_MCH_CPU0_IERR_N

1

13,95,117,128

13,22

13,22

13,20

2

MOD_MCH_V_VTT_FSB0_VCCA / VSS

Place components:
Route trace from one of the L to
pin A23 of the CPU.
Route a trace from the other L to
pin of cap.
Place cap between CPU.A23 and VSSA.

Make traces wide as possible >12mils

ROOM = PROC0_VREF_CORE0

+CPU_VTT

+CPU_VTT

R4378

21

49.9-1%

L1759 & L1758 = dell p/n: N3305

L1759

10uH 165MA

26ohm+/-30%

L1758

1 2

10uH 165MA

R4385

1 2

R4353

680-5%

SUB=NP0

100-1%

21

TP_MOD_MCH_FSB0_GTLREF_ADD_R

21

NET_PHYSICAL_TYPE=30MIL

0-5%

1 2

R5271

0-5%

1 2

R5415

21

C2600

1uF 6.3V

MOD_MCH_V_VTT_FSB0_VCCA

12

C2569

22uF 6.3V

MOD_MCH_V_VSS_FSB0_VSSA

C2745

1 2

220pF

C3396

50V-10%

1 2

220pF

50V-10%

MOD_MCH_FSB0_GTLREF_DATA_CORE0

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

MOD_MCH_FSB0_GTLREF_ADD_CORE0

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

ECAD: Place 220pf caps under CPU

ECAD: Route <1.5" trace.

ECAD: Route at 30-50mils

13

13

13

13

51-5%

R4679

1 2

51-5%

R252

NP

1 2

220-5%

R246

NP

1 2

220-5%

R250

NP

1 2

220-5%

R1861

NP

1 2

220-5%

R4928

51-5%

X

R248

NP

220-5%

X

R247

NP

220-5%

X

R249

NP

220-5%

X

R125

1 2

51-5%

R92

1 2

150-1%

R5632

21

R138

51-5%

MOD_MCH_CPU0_PROCHOT_N

MOD_MCH_CPU0_THERMTRIP_N

21

21

MOD_MCH_FSB0_RST_N

X

21

X

21

X

CPU_PWRGOOD

21

MOD_MCH_VTT_CPU_PWRGOOD

FSB_SMI_N

FSB_A20M_N

FSB_NMI

FSB_INTR

FSB_INIT_N

FSB_IGNNE_N

FSB_STPCLK_N

FSB_FERR_N

13,20

13,20

13,22

13,17,54

13,17,54

13,17,54

13,17,54

13,17,54

13,17,54

13,17,54

13,17,54

BSEL PU's on Translation page

13,17,21,54

13,17,20

2

3

MOD_MCH_V_1V5_FSB0_VCCPLL

Place components:
Group associate components together
and as physically close to the associated
pin as possbile with one of the 0.1uF cap
closest to the pin

Make traces wide as possible >12mils

Route VCCIOPLL in parrallel to VSSA.

+CPU_VTT

Inductor stats: DCR (worst case) = .338 ohms SRF=30MHz 10uH +/- 10%& AR409 DT#2287

+1.5V

R4237

1 2

ROOM = PROCO_1V5_VCC

220mA Total

0-5%

6.3V-10%

4.7uF

21

C2575

ROOM = PROC0_VTT_VCC

CT:250mA, WC:125mA

6.3V-10%

4.7uF

C2577

21

50V-10%

0.01uF

C2569 = Dell p/n: C5127

MOD_MCH_V_1V5_FSB0_VCCPLL

21

50V-10%

C2950

0.01uF

C2589

21

P19_DT9175_jp

13

301-1%

X01_DT5560_SMR - deleted notes

R4244

21

MOD_MCH_FSB0_TESTHI_11

R4240

1 2

51-5%

R4245

1 2

51-5%

51-5%

R4243

51-5%

R5805

1 2

MOD_MCH_FSB0_TESTHI_10

21

MOD_MCH_FSB0_TESTHI_02_07

MOD_MCH_FSB0_TESTHI_00_01

MOD_MCH_CPU0_TESTIN

13

13

3

13

13

13,14

4

R5252

49.9-1%

R5251

49.9-1%

R5249

49.9-1%

R4299

49.9-1%

per MOW WW11 comp[7:4] now 50ohm +/- 15 ohm

21

R5253

1 2

21

21

21

49.9-1%

R5250

1 2

49.9-1%

R5248

1 2

49.9-1%

R4300

1 2

49.9-1%

MOD_MCH_FSB0_COMP_7

MOD_MCH_FSB0_COMP_6

MOD_MCH_FSB0_COMP_5

MOD_MCH_FSB0_COMP_4

MOD_MCH_FSB0_COMP_3

MOD_MCH_FSB0_COMP_2

MOD_MCH_FSB0_COMP_1

MOD_MCH_FSB0_COMP_0

X01_DT5511_SMR - added constraints to comp signalsm intel

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=15MIL

13

13

13

13

13

13

13

13

13,17,20

ECAD: Total length of trace < 6"

17

PSMI

MOD_MCH_CPU_FORCEPR_N

Note: FORCEPR has internal termination

MOD_MCH_FSB1_TESTBUS

+CPU_VTT

NP

R4588

X

1 2

1K-1%

1 2

0-5%

R95

MOD_MCH_FSB0_TESTBUS

13

51-5%

TITLE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

MCH

211

4

SCHEM, PLN, SV, PE2950, MLK

ROOM=PROC0

todo: can 1k be 5%?

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

REV.

HX601

SHEET

A00

9/7/2007 15 OF 136

DCBA

A B C

D

Processor 1 heatsink retention modules

ST2

1

2

22
22
22
22
22
22

22
22
22
22
22
22
22
22
22
22
22
22
22
22

MOD_MCH_FSB1_A16_N
MOD_MCH_FSB1_A15_N
MOD_MCH_FSB1_A14_N
MOD_MCH_FSB1_A13_N
MOD_MCH_FSB1_A12_N
MOD_MCH_FSB1_A11_N
MOD_MCH_FSB1_A10_N
MOD_MCH_FSB1_A9_N
MOD_MCH_FSB1_A8_N
MOD_MCH_FSB1_A7_N
MOD_MCH_FSB1_A6_N
MOD_MCH_FSB1_A5_N
MOD_MCH_FSB1_A4_N

MOD_MCH_FSB1_A3_N
MOD_MCH_FSB1_REQ_4_N
MOD_MCH_FSB1_REQ_3_N
MOD_MCH_FSB1_REQ_2_N
MOD_MCH_FSB1_REQ_1_N
MOD_MCH_FSB1_REQ_0_N
MOD_MCH_FSB1_ADSTB_0_N

J_CPU1

W5

A16_N

V4

A15_N

V5

A14_N

U4

A13_N

U5

A12_N

T4

A11_N

U6

A10_N

T5

A9_N

R4

A8_N

M4

A7_N

L4

A6_N

L5

A5_N

P6

A4_N

M5

A3_N

J6

REQ_4_N

K6

REQ_3_N

M6

REQ_2_N

J5

REQ_1_N

K4

REQ_0_N

R6 AD5

ADSTB0_N ADSTB1_N

A35_N
A34_N
A33_N
A32_N
A31_N
A30_N
A29_N
A28_N
A27_N
A26_N
A25_N
A24_N
A23_N
A22_N
A21_N
A20_N
A19_N
A18_N
A17_N

AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
AB5
AA5
AD6
AA4
Y4
Y6
W6
AB6

MOD_MCH_FSB1_A35_N
MOD_MCH_FSB1_A34_N
MOD_MCH_FSB1_A33_N
MOD_MCH_FSB1_A32_N
MOD_MCH_FSB1_A31_N
MOD_MCH_FSB1_A30_N
MOD_MCH_FSB1_A29_N
MOD_MCH_FSB1_A28_N
MOD_MCH_FSB1_A27_N
MOD_MCH_FSB1_A26_N
MOD_MCH_FSB1_A25_N
MOD_MCH_FSB1_A24_N
MOD_MCH_FSB1_A23_N
MOD_MCH_FSB1_A22_N
MOD_MCH_FSB1_A21_N
MOD_MCH_FSB1_A20_N
MOD_MCH_FSB1_A19_N
MOD_MCH_FSB1_A18_N
MOD_MCH_FSB1_A17_N

MOD_MCH_FSB1_ADSTB_1_N

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22

NC_MOD_MCH_ST2_1
NC_MOD_MCH_ST2_2

1

NC1

2

NC2

3

GND_V1

4

GND_V2

5

GND_V3

6

GND_V4

7

GND_V5

8

GND_V6

9

GND_V7

10

GND_V8

BRACKET RETENTION
SUPPORT, GROUNDED

CPU Heatsink
frame screws

ADD4=ADD*_RC078
ADD5=ADD*_RC078
ADD6=ADD*_RC078
ADD7=ADD*_RC078

CPU Heatsink

ADD8=ADD*_H3668
ADD9=ADD*_H3668

ADD1=ADD*_JC664

ADD2=ADD*_JC664

ADD3=ADD*_JC664

NOTE : heatsink retention clips needing a single trace to each pin, not solid

connection concern *doesn't* apply to the CPU HS brackets

Nocona-T

Platform Change

Dempsy-T

1

clip asm

Dempsy/Woodcrest

2

3

22
22
22

22
22
22

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

MOD_MCH_FSB1_D15_N
MOD_MCH_FSB1_D14_N
MOD_MCH_FSB1_D13_N
MOD_MCH_FSB1_D12_N
MOD_MCH_FSB1_D11_N
MOD_MCH_FSB1_D10_N
MOD_MCH_FSB1_D9_N
MOD_MCH_FSB1_D8_N
MOD_MCH_FSB1_D7_N
MOD_MCH_FSB1_D6_N
MOD_MCH_FSB1_D5_N
MOD_MCH_FSB1_D4_N
MOD_MCH_FSB1_D3_N
MOD_MCH_FSB1_D2_N
MOD_MCH_FSB1_D1_N

MOD_MCH_FSB1_D0_N
MOD_MCH_FSB1_DBI_0_N
MOD_MCH_FSB1_DSTBN_0_N
MOD_MCH_FSB1_DSTBP_0_N

MOD_MCH_FSB1_D31_N

MOD_MCH_FSB1_D30_N

MOD_MCH_FSB1_D29_N

MOD_MCH_FSB1_D28_N

MOD_MCH_FSB1_D27_N

MOD_MCH_FSB1_D26_N

MOD_MCH_FSB1_D25_N

MOD_MCH_FSB1_D24_N

MOD_MCH_FSB1_D23_N

MOD_MCH_FSB1_D22_N

MOD_MCH_FSB1_D21_N

MOD_MCH_FSB1_D20_N

MOD_MCH_FSB1_D19_N

MOD_MCH_FSB1_D18_N

MOD_MCH_FSB1_D17_N

MOD_MCH_FSB1_D16_N
MOD_MCH_FSB1_DBI_1_N
MOD_MCH_FSB1_DSTBN_1_N
MOD_MCH_FSB1_DSTBP_1_N

D11
C12
B12

D8
C11
B10
A11
A10

A7

B7

B6

A5

C6

A4

C5

B4

A8

C8

B9

G15
F15
G14
F14
G13
E13
D13
F12
F11
D10
E10

D7

E9

F9

F8

G9
G11
G12
E12

D15_N
D14_N
D13_N
D12_N
D11_N
D10_N
D9_N
D8_N
D7_N
D6_N
D5_N
D4_N
D3_N
D2_N
D1_N
D0_N
DBI0_N
DSTBN0_N
DSTBP0_N

D31_N
D30_N
D29_N
D28_N
D27_N
D26_N
D25_N
D24_N
D23_N
D22_N
D21_N
D20_N
D19_N
D18_N
D17_N
D16_N
DBI1_N
DSTBN1_N
DSTBP1_N

D47_N
D46_N
D45_N
D44_N
D43_N
D42_N
D41_N
D40_N
D39_N
D38_N
D37_N
D36_N
D35_N
D34_N
D33_N
D32_N

DBI2_N
DSTBN2_N
DSTBP2_N

D63_N
D62_N
D61_N
D60_N
D59_N
D58_N
D57_N
D56_N
D55_N
D54_N
D53_N
D52_N
D51_N
D50_N
D49_N
D48_N

DBI3_N
DSTBN3_N
DSTBP3_N

G22
D22
E22
G21
F21
E21
F20
E19
E18
F18
F17
G17
G18
E16
E15
G16
D19
G20
G19

B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
B15
C14
C15
A14
D17
D20
C20
A16
C17

MOD_MCH_FSB1_D47_N
MOD_MCH_FSB1_D46_N
MOD_MCH_FSB1_D45_N
MOD_MCH_FSB1_D44_N
MOD_MCH_FSB1_D43_N
MOD_MCH_FSB1_D42_N
MOD_MCH_FSB1_D41_N
MOD_MCH_FSB1_D40_N
MOD_MCH_FSB1_D39_N
MOD_MCH_FSB1_D38_N
MOD_MCH_FSB1_D37_N
MOD_MCH_FSB1_D36_N
MOD_MCH_FSB1_D35_N
MOD_MCH_FSB1_D34_N
MOD_MCH_FSB1_D33_N

MOD_MCH_FSB1_D32_N
MOD_MCH_FSB1_DBI_2_N
MOD_MCH_FSB1_DSTBN_2_N
MOD_MCH_FSB1_DSTBP_2_N

MOD_MCH_FSB1_D63_N

MOD_MCH_FSB1_D62_N

MOD_MCH_FSB1_D61_N

MOD_MCH_FSB1_D60_N

MOD_MCH_FSB1_D59_N

MOD_MCH_FSB1_D58_N

MOD_MCH_FSB1_D57_N

MOD_MCH_FSB1_D56_N

MOD_MCH_FSB1_D55_N

MOD_MCH_FSB1_D54_N

MOD_MCH_FSB1_D53_N

MOD_MCH_FSB1_D52_N

MOD_MCH_FSB1_D51_N

MOD_MCH_FSB1_D50_N

MOD_MCH_FSB1_D49_N

MOD_MCH_FSB1_D48_N
MOD_MCH_FSB1_DBI_3_N
MOD_MCH_FSB1_DSTBN_3_N
MOD_MCH_FSB1_DSTBP_3_N

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

22
22
22

22
22
22

requiredrequired

Use "LE" Blackford

Pull down reserved pin F6

Pull down MS_ID[1:0] to Vss

Isolate LL_ID[1:0]

Manually set VR loadline

required

optional

optional

optional

required

required

required

required

required

required

Mechanical Parts on the following pages:
12, 16

Socket J part numbers:

Dell p/n

Y9236

P9381

Description

Leaded Socket J - SKT,LGA,771P,G,SF,ZIF,SL,SM

Vendors:

Foxconn PN: PE077107-1041-01
Tyco PN: 1747890-1

Lead-free socket J - SKT,LGA,771P,G,SF,ZIF,SL,SM

Vendors:

No use LGA771Use LGA775

No use real blackford

No treat as reserved, leave pin No Connect

No revert back to POR

No revert back to POR

No revert back to POR

3

4

ROOM=PROC1

INTEL LGA771 PINOUT

HETERO 2 OF 9

SILKSCREEN=CPU2

ADD*_PR288

ECAD NOTE: Please put triangle pointing to pin1

NC_CPU1_REG_1

CPU1_REG

1 2

COMMON NEG

REG07 A NGO
COUPON TEST

NC_CPU1_REG_2

Foxconn PN: PE077127-1041-01
Tyco PN: 1-1747890-1

PROCESSOR 1

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

HX601

SHEET

16 OF 1369/7/2007

CPUS,FSB,NB,XDP0,XDP1

SEC

REV.

A00

MCH

211

4

C

DBA

A B C

+CPU_VTT

D

1

2

3

21

R4255

R4260

17,119
17,119
17,119
17,119
17,119
17,119
17,119

13,15,21,54

NP

X

1 2

C8599

19,95,119,128

MLK: Routed to CPLD for CPU Identification

17,21,95,119,128

Do not place VTT_SEL or CPU_PRES_N on 3v3Aux, VTT_SEL is used in main domain VRD logic,
CPU_PRES_N is used on 3v3 part during development.
The rest are placed on 3v3 to simply routing, no need for 3v3 aux near CPU.

FSB1_VID_6
FSB1_VID_5
FSB1_VID_4
FSB1_VID_3
FSB1_VID_2
FSB1_VID_1
FSB1_VID_0

20
20
20
19
19
19
19

100pF

50V-5%

17,119
17,119
17,119
17,119
17,119
17,119
17,119

119
119
119
119

17,89
17,89

**

MOD_MCH_CPU1_BSEL_2
MOD_MCH_CPU1_BSEL_1
MOD_MCH_CPU1_BSEL_0
MOD_MCH_FSB1_GTLREF_DATA_CORE1
MOD_MCH_FSB1_GTLREF_ADD_CORE1
MOD_MCH_FSB1_GTLREF_DATA_CORE0
MOD_MCH_FSB1_GTLREF_ADD_CORE0
CPU_PWRGOOD

19
19
19
19
19
19
19
19

19
19
19

89
89

15

MOD_MCH_FSB1_COMP_7
MOD_MCH_FSB1_COMP_6
MOD_MCH_FSB1_COMP_5
MOD_MCH_FSB1_COMP_4
MOD_MCH_FSB1_COMP_3
MOD_MCH_FSB1_COMP_2
MOD_MCH_FSB1_COMP_1
MOD_MCH_FSB1_COMP_0

FSB1_VID_6
FSB1_VID_5
FSB1_VID_4
FSB1_VID_3
FSB1_VID_2
FSB1_VID_1
FSB1_VID_0
FSB1_VID_SELECT

MOD_MCH_V_VTT_FSB1_VCCA
MOD_MCH_V_VSS_FSB1_VSSA
MOD_MCH_V_1V5_FSB1_VCCPLL

CPU1_VCC_DIE_SENSE
CPU1_VCC_DIE_SENSE2
CPU1_VSS_DIE_SENSE
CPU1_VSS_DIE_SENSE2

CPU1_PRES_N

CPU1_THERMD_A_2
CPU1_THERMD_C_12
CPU1_THERMD_C_12
NC_MOD_MCH_FSB1_DBR_N

*

NC_MOD_MCH_FSB1_ITP_CLK1

*

NC_MOD_MCH_FSB1_ITP_CLK0

*

NC_MOD_MCH_FSB1_RSVD_Y1

MOD_MCH_FSB1_TESTBUS

511-1%

511-1%

PROC1

R4256

1 2

21

R4257

511-1%

511-1%

R4259

1 2

21

R4258

511-1%

511-1%

R4254

G30
H30
G29

G10

AE3

A13

AM5
AL4
AK4
AL6
AM3
AL5
AM2
AN7

A23
B23
D23
C23
AN3
AL8
AN4
AL7 AM6

AE8
AL1
AJ7
AK1
AH7
AC2
AJ3
AK3

AH2

511-1%

1 2

J_CPU1

BSEL2
BSEL1
BSEL0

F2

GTLREF_DATA_CORE1

H2

GTLREF_ADD_CORE1
GTLREF_DATA_CORE0

H1

GTLREF_ADD_CORE0

N1

PWRGOOD
COMP7

Y3

COMP6

T2

COMP5

J2

COMP4

R1

COMP3

G2

COMP2

T1

COMP1
COMP0

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID_SELECT

VCCA
VSSA
VCCPLL
VCCIOPLL
VCC_DIE_SENSE
VCC_DIE_SENSE2
VSS_DIE_SENSE
VSS_DIE_SENSE2 VTTPWRGD

SKTOCC_N
THERMDA
THERMDA2
THERMDC
THERMDC2
DBR_N
ITP_CLK1
ITP_CLK0

Y1

BOOT_SELECT
TEST_BUS

INTEL LGA771 PINOUT

HETERO 3 OF 9

SILKSCREEN=CPU2

VTT_E30/NC_E30
VTT_F30/NC_F30

VTT_OUT_1
VTT_OUT_0

VTT_A25
VTT_A26
VTT_B25
VTT_B26
VTT_B27
VTT_B28
VTT_B29
VTT_B30
VTT_C25
VTT_C26
VTT_C27
VTT_C28
VTT_C29
VTT_C30
VTT_D25
VTT_D26
VTT_D27
VTT_D28
VTT_D29
VTT_D30

VTT_SEL

LL_ID1
LL_ID0
MS_ID1
MS_ID0

A25
A26
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
E30
F30

AA1
J1
F27

AA2
V2
V1
W1

* NOTE: DBR and ITP_CLK are outputs from a in-socket debugger- Dell has no plans for this debug model.

** NOTE: WW10 MOW documents that bootselect is being removed
and to leave pin floating

+CPU_VTT

MOD_MCH_VTT_CPU_PWRGOOD

NC_MOD_MCH_FSB1_VTT_OUT_1
NC_MOD_MCH_FSB1_VTT_OUT_0CPU1_THERMD_A_1

MOD_MCH_VTT_SEL_CPU1

MOD_MCH_CPU1_LL_ID1_R

MOD_MCH_CPU1_LL_ID0_R CPU1_LL_ID0

CPU1_MS_ID1
CPU1_MS_ID0

19,21,22

45
45

13,15,54
13,15,54
13,15,20
13,15,54
13,15,54
13,15,54
13,15,54

13,15,54

13,21

21

21
13,21,24
13,21,24

19,20

13,15,54

19,20
19,20

19

19

19

13,15,20

19

109

MLK: VTT_SEL Signal going to VTT REG Ckt

17,95,128
17,95,128

17,21,95,119,128

17,95,128
17,95,128

R5501

0-5%

12

NP for DempseyT

CPU1_PRES_N
CPU1_MS_ID1
CPU1_MS_ID0

MOD_MCH_FSB1_RST_N
MOD_MCH_FSB1_RSP_N

22

MOD_MCH_FSB1_BPRI_N

22

MOD_MCH_FSB1_TRDY_N

22

MOD_MCH_FSB1_DEFER_N

22

MOD_MCH_FSB1_RS_0_N

22

MOD_MCH_FSB1_RS_1_N

22

MOD_MCH_FSB1_RS_2_N

22

CK_333M_CPU1_N
CK_333M_CPU1_P

FSB_SMI_N
FSB_A20M_N

MOD_MCH_CPU_FORCEPR_N

FSB_INTR
FSB_NMI
FSB_IGNNE_N
FSB_STPCLK_N

FSB_INIT_N

MOD_MCH_XDP0_TCK0
MOD_MCH_XDP0_TDI_CPU1
MOD_MCH_XDP0_TDO_CPU1
MOD_MCH_XDP0_TMS
MOD_MCH_XDP0_TRST_N

MOD_MCH_CPU1_IERR_N
FSB_FERR_N
MOD_MCH_CPU1_PROCHOT_N
MOD_MCH_CPU1_THERMTRIP_N

MOD_MCH_FSB1_TESTHI_11
MOD_MCH_FSB1_TESTHI_10

MOD_MCH_FSB1_BPMB_2_N

21

MOD_MCH_FSB1_BPMB_3_N

21

MOD_MCH_FSB1_TESTHI_02_07

MOD_MCH_FSB1_TESTHI_00_01

R5500

0-5%

J_CPU1

G23

RESET_N

H4

RSP_N

G8

BPRI_N

E3

TRDY_N

G7

DEFER_N

B3

RS0_N

F5

RS1_N

A3

RS2_N

G28

BCLK1

P2

SMI_N

K3

A20M_N

AK6

FORCEPR_N

K1

LINT0

L1

LINT1

N2

IGNNE_N

M3

STPCLK_N

P3

INIT_N

AE1

TCK

AD1

TDI

AF1

TDO

AC1

TMS

AG1

TRST_N

AB2

IERR_N

R3

FERR/PBE_N

AL2

PROCHOT_N

M2

THRMTRIP_N

INTEL LGA771 PINOUT

HETERO 1 OF 9

SILKSCREEN=CPU2

J_CPU1

L2

TESTHI11

P1

TESTHI10

G4

TESTHI09/BPMB2_N

G3

TESTHI08/BPMB3_N

F24

TESTHI07

G24

TESTHI06

G26

TESTHI05

G27

TESTHI04

G25

TESTHI03

F25

TESTHI02

W3

TESTHI01

F26

TESTHI00

12

CPU1_LL_ID1

119

119

R213

1 2

4.7K-5%

R5629

1 2

+3.3V

R4831

4.7K-5%

1 2

4.7K-5%

INTEL LGA771 PINOUT

SILKSCREEN=CPU2

ADS_N
BNR_N

HIT_N
DBSY_N
DRDY_N
HITM_N
LOCK_N

BINIT_N
MCERR_N

AP1_NBCLK0

AP0_N

BR1_N

BR0_N

DP3_N

DP2_N

DP1_N

DP0_N

BPM5_N
BPM4_N

BPM3_N
BPM2_N
BPM1_N
BPM0_N

Clovertown

HETERO 4 OF 9

D2
C2
D4
B2
C1
E4
C3
AD3
AB3

U3F28
U2
H5
F3

J17
H16
H15
J16

AG3
AF2
AG2
AD2
AJ1
AJ2

NP for DempseyT

MOD_MCH_FSB1_ADS_N
MOD_MCH_FSB1_BNR_N
MOD_MCH_FSB1_HIT_N
MOD_MCH_FSB1_DBSY_N
MOD_MCH_FSB1_DRDY_N
MOD_MCH_FSB1_HITM_N
MOD_MCH_FSB1_LOCK_N
MOD_MCH_FSB1_BINIT_N
MOD_MCH_FSB1_MCERR_N

MOD_MCH_FSB1_AP_1_N
MOD_MCH_FSB1_AP_0_N
MOD_MCH_FSB1_BREQ_1_N
MOD_MCH_FSB1_BREQ_0_N

MOD_MCH_FSB1_DP_3_N
MOD_MCH_FSB1_DP_2_N
MOD_MCH_FSB1_DP_1_N
MOD_MCH_FSB1_DP_0_N

MOD_MCH_FSB1_BPM_5_N
MOD_MCH_FSB1_BPM_4_N
MOD_MCH_FSB1_BPM_3_N
MOD_MCH_FSB1_BPM_2_N
MOD_MCH_FSB1_BPM_1_N
MOD_MCH_FSB1_BPM_0_N

RSVD_A20
RSVD_AC4
RSVD_AE4
RSVD_AE6
RSVD_B13

RSVD_C9/BPMB1_N

RSVD_D1
RSVD_D14
RSVD_D16
RSVD_E23
RSVD_E24

RSVD_E1/NC_E1

RSVD_E5

RSVD_E6

RSVD_E7
RSVD_F23
RSVD_F29

RSVD_F6

PECI
RSVD_G6
RSVD_J3
RSVD_N4
RSVD_N5
RSVD_P5

RSVD_AN5
RSVD_AN6

RSVD_W2/TESTIN1

M2LB_Change_Note:
Changed PECI_CPU2 to PECI_CPU.

Added 100pF to CPU_PWRGOOD.

A20
AC4
AE4
AE6
B13
C9
D1
D14
D16
E23
E24
E1
E5
E6
E7
F23
F29
F6
G5
G6
J3
N4
N5
P5
AN5
AN6
W2

22
22
22
22
22
22
22
22
22

22
22
19,22
19,22

22
22
22
22

21,22
21,22
21
21
21
21

NC_MOD_MCH_FSB1_RSVD_A20
NC_MOD_MCH_FSB1_RSVD_AC24
NC_MOD_MCH_FSB1_RSVD_AE24
NC_MOD_MCH_FSB1_RSVD_AE6
NC_MOD_MCH_FSB1_RSVD_B13

MOD_MCH_FSB1_BPMB_1_N
NC_MOD_MCH_FSB1_RSVD_D1
NC_MOD_MCH_FSB1_RSVD_D14
NC_MOD_MCH_FSB1_RSVD_D16
NC_MOD_MCH_FSB1_RSVD_E23
NC_MOD_MCH_FSB1_RSVD_E24
NC_MOD_MCH_FSB1_RSVD_E1
NC_MOD_MCH_FSB1_RSVD_E5
NC_MOD_MCH_FSB1_RSVD_E6
NC_MOD_MCH_FSB1_RSVD_E7
NC_MOD_MCH_FSB1_RSVD_F23
NC_MOD_MCH_FSB1_RSVD_F29

MOD_MCH_FSB1_F6_PD_DEMPSY-T
PECI_CPU
NC_MOD_MCH_FSB1_RSVD_G6
NC_MOD_MCH_FSB1_RSVD_J3
NC_MOD_MCH_FSB1_RSVD_N4
NC_MOD_MCH_FSB1_RSVD_N5
NC_MOD_MCH_FSB1_RSVD_P5
NC_MOD_MCH_FSB1_RSVD_AN5
NC_MOD_MCH_FSB1_RSVD_AN6
MOD_MCH_CPU1_TESTIN

Don't care for NoconaT
Populate for DempseyT/NoconaT
Depop for Dempsey/Woodcrest

13,90

18,19

NP

R5496

X

2 1

21

49.9-1%

1

2

3

4

ECAD: VCC/VSS_DIE_SENSE LINES

Route DIFF @ 25mil thick /5 mil space, same length, 20mil to other sigs
Follow PDG 0.7 256-257

ROOM=PROC1

POP for DempsyT

NP

R5505

X

2 1

NP

R5504

X

49.9-1%

2 1

C

PROCESSOR 1

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS

49.9-1%

ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 17 OF 136

DBA

MCH

211

4

A B C

D

1

2

3

21

17,19

AA8

AB8
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30

AC8
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30

AD8
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23

AE9
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22

AF8

AF9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30

AG8

AG9
AH11

NC_J_CPU1_A24

NC_J_CPU1_E29
MOD_MCH_FSB1_BPMB_0_N
MOD_MCH_CPU1_TESTIN

VCC_AA8
VCC_AB8
VCC_AC23
VCC_AC24
VCC_AC25
VCC_AC26
VCC_AC27
VCC_AC28
VCC_AC29
VCC_AC30
VCC_AC8
VCC_AD23
VCC_AD24
VCC_AD25
VCC_AD26
VCC_AD27
VCC_AD28
VCC_AD29
VCC_AD30
VCC_AD8
VCC_AE11
VCC_AE12
VCC_AE14
VCC_AE15
VCC_AE18
VCC_AE19
VCC_AE21
VCC_AE22
VCC_AE23
VCC_AE9
VCC_AF11
VCC_AF12
VCC_AF14
VCC_AF15
VCC_AF18
VCC_AF19
VCC_AF21
VCC_AF22
VCC_AF8
VCC_AF9
VCC_AG11
VCC_AG12
VCC_AG14
VCC_AG15
VCC_AG18
VCC_AG19
VCC_AG21
VCC_AG22
VCC_AG25
VCC_AG26
VCC_AG27
VCC_AG28
VCC_AG29
VCC_AG30
VCC_AG8
VCC_AG9
VCC_AH11

SILKSCREEN=CPU2

J_CPU1

INTEL LGA771 PINOUT

HETERO 5 OF 9

A24

VSS_A24/RSVD

E29

VSS_E29/RSVD

G1

VSS_G1/BPMB0_N

U1

VSS_U1/TESTIN2

Clovertown

INTEL LGA771 PINOUT

HETERO 9 OF 9

VCC_AH12
VCC_AH14
VCC_AH15
VCC_AH18
VCC_AH19
VCC_AH21
VCC_AH22
VCC_AH25
VCC_AH26
VCC_AH27
VCC_AH28
VCC_AH29
VCC_AH30

VCC_AH8

VCC_AH9
VCC_AJ11
VCC_AJ12
VCC_AJ14
VCC_AJ15
VCC_AJ18
VCC_AJ19
VCC_AJ21
VCC_AJ22
VCC_AJ25
VCC_AJ26

VCC_AJ8

VCC_AJ9
VCC_AK11
VCC_AK12
VCC_AK14
VCC_AK15
VCC_AK18
VCC_AK19
VCC_AK21
VCC_AK22
VCC_AK25
VCC_AK26

VCC_AK8

VCC_AK9
VCC_AL11
VCC_AL12
VCC_AL14
VCC_AL15
VCC_AL18
VCC_AL19
VCC_AL21
VCC_AL22
VCC_AL25
VCC_AL26
VCC_AL29
VCC_AL30

VCC_AL9
VCC_AM11
VCC_AM12

J_CPU1

AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30

AL9
AM11
AM12

9-7-2007_16:36

M23
M24
M25
M26
M27
M28
M29
M30
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
U23
U24
U25
U26
U27
U28
U29
U30
U8
V8
W23
W24
W25
W26
W27
W28
W29
W30
W8
Y8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30

+CPU_VID1

A12
A15
A18

A2

A21

A6

A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA3

AA30

AA6
AA7

AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AB7

AC3

AC6

AC7

AD4

AD7
AE10
AE13
AE16
AE17

AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30

AE5

AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29

AF3
AF30

AF6

AF7
AG10
AG13
AG16
AG17

VSS_A12
VSS_A15
VSS_A18
VSS_A2
VSS_A21

VSS_A6
VSS_A9
VSS_AA23
VSS_AA24
VSS_AA25
VSS_AA26
VSS_AA27
VSS_AA28
VSS_AA29
VSS_AA3
VSS_AA30
VSS_AA6
VSS_AA7
VSS_AB1
VSS_AB23
VSS_AB24
VSS_AB25
VSS_AB26
VSS_AB27
VSS_AB28
VSS_AB29
VSS_AB30
VSS_AB7
VSS_AC3
VSS_AC6
VSS_AC7
VSS_AD4
VSS_AD7
VSS_AE10
VSS_AE13
VSS_AE16
VSS_AE17
VSS_AE2
VSS_AE20
VSS_AE24
VSS_AE25
VSS_AE26
VSS_AE27
VSS_AE28
VSS_AE29
VSS_AE30
VSS_AE5
VSS_AE7
VSS_AF10
VSS_AF13
VSS_AF16
VSS_AF17
VSS_AF20
VSS_AF23
VSS_AF24
VSS_AF25
VSS_AF26
VSS_AF27
VSS_AF28
VSS_AF29
VSS_AF3
VSS_AF30
VSS_AF6
VSS_AF7
VSS_AG10
VSS_AG13
VSS_AG16
VSS_AG17

SILKSCREEN=CPU2

J_CPU1

INTEL LGA771 PINOUT

HETERO 7 OF 9

VSS_AG20
VSS_AG23
VSS_AG24

VSS_AG7

VSS_AH1
VSS_AH10
VSS_AH13
VSS_AH16
VSS_AH17
VSS_AH20
VSS_AH23
VSS_AH24

VSS_AH3

VSS_AH6

VSS_AJ10
VSS_AJ13
VSS_AJ16
VSS_AJ17
VSS_AJ20
VSS_AJ23
VSS_AJ24
VSS_AJ27
VSS_AJ28
VSS_AJ29
VSS_AJ30

VSS_AJ4

VSS_AK10
VSS_AK13
VSS_AK16
VSS_AK17

VSS_AK2
VSS_AK20
VSS_AK23
VSS_AK24
VSS_AK27
VSS_AK28
VSS_AK29
VSS_AK30

VSS_AK5

VSS_AK7
VSS_AL10
VSS_AL13
VSS_AL16
VSS_AL17
VSS_AL20
VSS_AL23
VSS_AL24
VSS_AL27
VSS_AL28

VSS_AL3

VSS_AM1
VSS_AM10
VSS_AM13
VSS_AM16
VSS_AM17
VSS_AM20
VSS_AM23
VSS_AM24
VSS_AM27
VSS_AM28

VSS_AM4

VSS_AM7
VSS_AN01
VSS_AN02
VSS_AN10
VSS_AN13
VSS_AN16

AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6

AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4

AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3

AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AM7
AN1
AN2
AN10
AN13
AN16

AN17
AN20
AN23
AN24

B1
B11
B14
B17
B20
B24

B8

B5
C10
C13
C16
C19
C22
C24

C4

C7
D12
D15
D18
D21
D24

D3

D5

D6

D9
E11
E14
E17

E2
E20
E25
E26
E27
E28

E8

F1
F10
F13
F16
F19
F22

F4

F7

H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29

VSS_AN17
VSS_AN20
VSS_AN23
VSS_AN24
VSS_B1
VSS_B11
VSS_B14
VSS_B17
VSS_B20
VSS_B24
VSS_B5
VSS_B8
VSS_C10
VSS_C13
VSS_C16
VSS_C19
VSS_C22
VSS_C24
VSS_C4
VSS_C7
VSS_D12
VSS_D15
VSS_D18
VSS_D21
VSS_D24
VSS_D3
VSS_D5
VSS_D6
VSS_D9
VSS_E11
VSS_E14
VSS_E17
VSS_E2
VSS_E20
VSS_E25
VSS_E26
VSS_E27
VSS_E28

VSS_E8
VSS_F1
VSS_F10
VSS_F13
VSS_F16
VSS_F19
VSS_F22
VSS_F4
VSS_F7

VSS_H10
VSS_H11
VSS_H12
VSS_H13
VSS_H14
VSS_H17
VSS_H18
VSS_H19
VSS_H20
VSS_H21
VSS_H22
VSS_H23
VSS_H24
VSS_H25
VSS_H26
VSS_H27
VSS_H28
VSS_H29

SILKSCREEN=CPU2

J_CPU1

INTEL LGA771 PINOUT

HETERO 8 OF 9

VSS_H3
VSS_H6
VSS_H7
VSS_H8
VSS_H9
VSS_J4
VSS_J7
VSS_K2
VSS_K5

VSS_K7
VSS_L23
VSS_L24
VSS_L25
VSS_L26
VSS_L27
VSS_L28
VSS_L29

VSS_L3
VSS_L30

VSS_L6

VSS_L7

VSS_M1

VSS_M7

VSS_N3

VSS_N6

VSS_N7
VSS_P23
VSS_P24
VSS_P25
VSS_P26
VSS_P27
VSS_P28
VSS_P29
VSS_P30

VSS_P4

VSS_P7

VSS_R2
VSS_R23
VSS_R24
VSS_R25
VSS_R26
VSS_R27
VSS_R28
VSS_R29
VSS_R30

VSS_R5

VSS_R7

VSS_T3

VSS_T6

VSS_T7

VSS_U7
VSS_V23
VSS_V24
VSS_V25
VSS_V26
VSS_V27
VSS_V28
VSS_V29

VSS_V3
VSS_V30

VSS_V6

VSS_V7

VSS_W4

VSS_W7

VSS_Y2

VSS_Y5

VSS_Y7

H3
H6
H7
H8
H9
J4
J7
K2
K5
K7
L23
L24
L25
L26
L27
L28
L29
L3
L30
L6
L7
M1
M7
N3
N6
N7
P23
P24
P25
P26
P27
P28
P29
P30
P4
P7
R2
R23
R24
R25
R26
R27
R28
R29
R30
R5
R7
T3
T6
T7

U7
V23
V24
V25
V26
V27
V28
V29
V3
V30
V6
V7
W4
W7
Y2
Y5
Y7

1

2

3

+CPU_VID1+CPU_VID1

+CPU_VTT

+CPU_VID1

AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30

AM8

AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AN25
AN26

AN8

AN9

J10

J11

J12

J13

J14

J15

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J8

J9
K23
K24
K25
K26
K27
K28
K29
K30

K8

L8

VCC_AM14
VCC_AM15
VCC_AM18
VCC_AM19
VCC_AM21
VCC_AM22
VCC_AM25
VCC_AM26
VCC_AM29
VCC_AM30
VCC_AM8
VCC_AM9
VCC_AN11
VCC_AN12
VCC_AN14
VCC_AN15
VCC_AN18
VCC_AN19
VCC_AN21
VCC_AN22
VCC_AN25
VCC_AN26
VCC_AN8
VCC_AN9
VCC_J10
VCC_J11
VCC_J12
VCC_J13
VCC_J14
VCC_J15
VCC_J18
VCC_J19
VCC_J20
VCC_J21
VCC_J22
VCC_J23
VCC_J24
VCC_J25
VCC_J26
VCC_J27
VCC_J28
VCC_J29
VCC_J30
VCC_J8
VCC_J9
VCC_K23
VCC_K24
VCC_K25
VCC_K26
VCC_K27
VCC_K28
VCC_K29
VCC_K30
VCC_K8
VCC_L8

J_CPU1

VCC_M23
VCC_M24
VCC_M25
VCC_M26
VCC_M27
VCC_M28
VCC_M29
VCC_M30

VCC_M8
VCC_N23
VCC_N24
VCC_N25
VCC_N26
VCC_N27
VCC_N28
VCC_N29
VCC_N30

VCC_N8

VCC_P8

VCC_R8
VCC_T23
VCC_T24
VCC_T25
VCC_T26
VCC_T27
VCC_T28
VCC_T29
VCC_T30

VCC_T8
VCC_U23
VCC_U24
VCC_U25
VCC_U26
VCC_U27
VCC_U28
VCC_U29
VCC_U30

VCC_U8

VCC_V8
VCC_W23
VCC_W24
VCC_W25
VCC_W26
VCC_W27
VCC_W28
VCC_W29
VCC_W30

VCC_W8

VCC_Y8
VCC_Y23
VCC_Y24
VCC_Y25
VCC_Y26
VCC_Y27
VCC_Y28
VCC_Y29
VCC_Y30

INTEL LGA771 PINOUT

HETERO 6 OF 9

SILKSCREEN=CPU2

Room = PROC1_VTT_CAPS_22uF

C2570

1 2

+CPU_VTT

21

C2571

22uF 6.3V

21

C2572

1 2

22uF 6.3V

21

C2573

22uF 6.3V

21

dell p/n C5127

22uF 6.3V

21

Room = PROC1_VTT_CAPS_1uF
dell p/n D8579

C2551

1 2

C2552

1uF 6.3V

C2553

1 2

1uF 6.3V

C2554

1uF 6.3V

C2555

1uF 6.3V

C2556

1 2

1uF 6.3V

1uF 6.3V

4

ROOM=PROC1

SILKSCREEN=CPU2

+CPU_VTT

21

C2591

.1uF

C2592

10V-10%

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

MCH

211

4

21

.1uF

C2593

10V-10%

21

.1uF

C2594

10V-10%

21

.1uF

C2596

10V-10%

21

21

.1uF

C259721C2595

10V-10%

.1uF

10V-10%

.1uF

10V-10%

Room = PROC1_VTT_CAPS_p1UF
dell p/n J5734

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT

AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE

OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE

LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH

USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

PROCESSOR 1

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

HX601

DATE

9/7/2007 18 OF 136

INC.

ROUND ROCK,TEXAS

REV.

A00

SHEET

DCBA

1

A B C

MOD_MCH_FSB1_GTLREF_DATA/ ADD
(800mV @1.2V VTT)
(733mV @1.1V VTT)

Place components:
Group associate components together
and as physically close to the associated
pin as possbile with the 220pf cap
closest to the pin

Make traces wide as possible >12mils

CPU1 GTL VREF

ROOM = PROC1_VREF_CORE1

+CPU_VTT

R4302

1 2

49.9-1%

R4282

1 2

680-5%

SUB=NP0

MOD_FSB1_GTLREF_49P9

21

R4306

100-1%

TP_MOD_MCH_FSB1_GTLREF_DATA_R

NET_PHYSICAL_TYPE=30MIL

0-5%

0-5%

21

21

C2581

1 2

C2558

1 2

R5273

R5416

1uF 6.3V

220pF

50V-10%

ECAD: Follow PDG topoolgies for all sigs, esp: Thermtrip, Prochot, IERR, FERR/PBE

ECAD: Place termination close to CPU 1

C3397

1 2

220pF

50V-10%

MOD_MCH_FSB1_GTLREF_DATA_CORE1

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

MOD_MCH_FSB1_GTLREF_ADD_CORE1

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

ECAD: Place 220pf caps under CPU
ECAD: Route <1.5" trace.
ECAD: Route at 30-50mils

17

17

+CPU_VTT

R154

1 2

51-5%

R4661

1 2

R155

21

51-5%

MOD_MCH_FSB1_BREQ_1_N

MOD_MCH_FSB1_BREQ_0_N

MOD_MCH_CPU1_IERR_N

D

1

17,22

17,22

17,20

2

ROOM = PROC1_VREF_CORE0

+CPU_VTT

R5387

49.9-1%

R4355

680-5%

SUB=NP0

21

MOD_FSB0_GTLREF_49P9

R4387

1 2

100-1%

TP_MOD_MCH_FSB1_GTLREF_ADD_R

21

NET_PHYSICAL_TYPE=30MIL

0-5%

1 2

R5417

0-5%

1 2

R5272

21

C2602

1uF 6.3V

C2747

1 2

220pF

50V-10%

C3398

1 2

MOD_MCH_FSB1_GTLREF_DATA_CORE0

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

MOD_MCH_FSB1_GTLREF_ADD_CORE0

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MILS

ECAD: Place 220pf caps under CPU

220pF

50V-10%

ECAD: Route <1.5" trace.

17

17

51-5%

R4682

1 2

51-5%

R153

21

51-5%

R151

51-5%

R4929

51-5%

R4246

1 2

51-5%

21

R147

1 2

51-5%

21

MOD_MCH_CPU1_PROCHOT_N

MOD_MCH_CPU1_THERMTRIP_N

MOD_MCH_FSB1_RST_N

MOD_MCH_FSB1_TESTHI_11

MOD_MCH_FSB1_TESTHI_10

MOD_MCH_FSB1_TESTHI_02_07

17,21,22

17

17

17,20

17,20

17

2

3

MOD_MCH_V_VTT_FSB1_VCCA / VSS

Place components:
Route trace from one of the L to
pin A23 of the CPU.
Route a trace from the other L to
pin of cap.
Place cap between CPU.A23 and VSSA.

Make traces wide as possible >12mils

MOD_MCH_V_1V5_FSB1_VCCPLL

Place components:
Group associate components together
and as physically close to the associated
pin as possbile with one of the 1.uF cap
closest to the pin

ROOM = PROC1_VTT_VCC

+CPU_VTT

L31

10uH 165MA

26ohm+/-30%

L32

1 2

10uH 165MA

21

C980

1 2

22uF 6.3V

MOD_MCH_V_VTT_FSB1_VCCA

MOD_MCH_V_VSS_FSB1_VSSA

220mA Total

TODO: Verify cap ESL and ESR per 275 or PDG

ECAD: Route at 30-50milsAR409 DT#228709 DT#2287

17

17

R141

51-5%

+3.3V

21

R5979

4.7K-5%

R212

NP

1 2

4.7K-5%

R5806

1 2

51-5%

MOD_MCH_FSB1_TESTHI_00_01

21

FSB1_VID_SELECT

X

MOD_MCH_CPU1_TESTIN

17

17,95,119,128

17,18

3

4

Make traces wide as possible >12mils

+CPU_VTT

R5256

49.9-1%

R5255

49.9-1%

R5259

49.9-1%

R5260

49.9-1%

per MOW WW11 comp[7:4] now 50ohm +/- 15 ohm

21

R5257

1 2

21

21

21

49.9-1%

R5254

1 2

49.9-1%

R5258

1 2

49.9-1%

R5261

1 2

49.9-1%

MOD_MCH_FSB1_COMP_7

MOD_MCH_FSB1_COMP_6

MOD_MCH_FSB1_COMP_5

MOD_MCH_FSB1_COMP_4

MOD_MCH_FSB1_COMP_3

MOD_MCH_FSB1_COMP_2

MOD_MCH_FSB1_COMP_1

MOD_MCH_FSB1_COMP_0

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=15MIL

17

17

17

17

17

17

17

17

ROOM = PROC1_1V5_VCC

ROOM=PROC1

+1.5V

R97

1 2

0-5%

6.3V-10%

4.7uF

21

C362

CT:250mA, WC:125mA

6.3V-10%

4.7uF

21

50V-10%

C810

0.01uF

21

50V-10%

0.01uF

C824

21

P19_DT9175_jp

MOD_MCH_V_1V5_FSB1_VCCPLL

C825

17

PROCESSOR 1

TITLE

MODULE:
DESC:
REV: OF

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

MCH

CPUS,FSB,NB,XDP0,XDP1

SEC

211

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

REV.

HX601

SHEET

A00

9/7/2007 19 OF 136

DCBA

A B C

D

1

Keep popped

MOD_MCH_CPU0_BSEL_2

13

MOD_MCH_CPU0_BSEL_1

13

13

MOD_MCH_CPU0_BSEL_0

R3872

1 2

+CPU_VTT

R3873

470-5%

21

R3874

470-5%

1 2

470-5%

R3882

1 2

2.7K-5%

R3881

2.7K-5%

R3880

1 2

2.7K-5%

13,15,17

+3.3V

To MCH

To board CPLD

+3.3V

R3843

Q1811

3904

1

21

1K-1%

1 2

3

2

Q1813

3904

1

R3844

1K-1%

1 2

3

Q1812

2

3904

1

R3845

1K-1%

1 2

14 U1127

CPU0_BSEL_2_3V_N

CPU0_BSEL_1_3V_N

CPU0_BSEL_0_3V_N

3

20,95,128

20,95,128

20,95,129

20,95,129
20,95,129

CPU0_BSEL_0_3V_N

CPU1_BSEL_0_3V_N

2
3

74VHC02

1

ROOM=BSEL_TRANS

2

R5432

1.5K-1%

R5426

1.5K-1%

21

21

MOD_MCH_PSEL_0_1V5

FREQ_SEL_0

R5429

1 2

1.24K-1%

R5433

1 2

To clk generators

1.24K-1%

22

45,46

VTT_CPU_PWRGOOD

128

ROOM=PROC0

No cost difference between NOR and NAND

FSEL SPEC

MOD_MCH_VTT_CPU_PWRGOOD

+3.3V_AUX

21

Q3934

R5930

Q3935

3904

1

1K-1%

3904

1

3

2

3

2

1

2

ROOM=PROC0_BSEL_TRANSL

+CPU_VTT

Keep popped

MOD_MCH_CPU1_BSEL_2

17

MOD_MCH_CPU1_BSEL_1

17

MOD_MCH_CPU1_BSEL_0

17

R3988

1 2

470-5%

R3989

21

470-5%

R3990

1 2

470-5%

R4685

1 2

2.7K-5%

R4684

2.7K-5%

R4683

1 2

2.7K-5%

3.6V
< 2.0V

0.35V

21

R5959

MAX

11
12

1K-1%

+3.3V

14 U1127

74VHC02

13,15,17

TEST
NORMAL
NORMAL

13

NC_U1127_PIN13

MOD_MCH_CPU_FORCEPR_N

+3.3V_AUX

R5958

1 2

Q3948

1K-1%

2

3

3904

1

MIN MODE

2.0V

0.7V

+3.3V

Note: CPU#_BSEL to CPLDs must have a pull-up

regardless of which proc controls clk

20,95,128
20,95,128

CPU0_BSEL_1_3V_N
CPU1_BSEL_1_3V_N

+3.3V

14 U1127

5
6

74VHC02

R5434

1.5K-1%

R5427

4

1.5K-1%

21

21

MOD_MCH_PSEL_1_1V5

To MCH

FREQ_SEL_1

To clk generators

45

22

VIH_FS

VIH_FS
VIL_FS -0.3V

To board CPLD

R4675

Q1913

3904

1

21

1K-1%

1 2

3

2

Q1914

3904

1

R4674

1K-1%

1 2

3

Q1915

2

3904

1

R4673

1K-1%

1 2

CPU1_BSEL_2_3V_N

CPU1_BSEL_1_3V_N

CPU1_BSEL_0_3V_N

3

2

20,95,128

20,95,128

20,95,129

20,95,128
20,95,128

CPU0_BSEL_2_3V_N
CPU1_BSEL_2_3V_N

+3.3V

14 U1127

8
9

74VHC02

10

R5436

21

1.5K-1%

R5428

21

1.5K-1%

R5430

1.24K-1%

1 2

MOD_MCH_PSEL_2_1V5

R5435

1 2

1.24K-1%

To MCH

FREQ_SEL_2

22

45

To clk generators

R5423

1 2

1K-1%

+3.3V_AUX

3

ROOM=PROC1_BSEL_TRANSL

BSEL2, BSEL1, BSEL0, Processor Bus Speed
0, 0, 0, 1066MHz
0, 0, 1, 533MHz
0, 1, ?, 667MHz?
0, 1, ?, 667MHz?
1, 0, 0, 1333MHz

ROOM=PROC0_TRANS ROOM=PROC1_TRANS

13,15

13,15

13,15

MOD_MCH_CPU0_THERMTRIP_N

MOD_MCH_CPU0_PROCHOT_N

MOD_MCH_CPU0_IERR_N

ECAD: the components within each circuit need to stay clumped

+3.3V

21

To Debug CPLD

R3875

2.7K-5%

R4936

1 2

2.7K-5%

R3877

3

2

1K-1%

Q1808

3904

R3840

1

R3838

Q1806

3904

21

21

1

1K-1%

1 2

3

2

Q1920

3904

1

R4907

1K-1%

1 2

CPU0_THRMTRIP_3V

CPU0_PROCHOT_3V

CPU0_IERR_3V

3

95,128

96

95,129

17,19

17,19

17,19

C3408

1 2

1uF 6.3V

MOD_MCH_CPU1_THERMTRIP_N

MOD_MCH_CPU1_PROCHOT_N

MOD_MCH_CPU1_IERR_N

R5431

TODO: REMOVE PROCHOT IF NOT NEEDED

1.24K-1%

1 2

R4587

2.7K-5%

R4935

2.7K-5%

R3991

1 2

2.7K-5%

R5437

21

21

1 2

Q1904

3904

1

1.24K-1%

+3.3V

R4540

1 2

3

2

1K-1%

Q1919

3904

1

R4906

1 2

3

2

1K-1%

Q1818

3904

95,128

1

CPU_FORCEPR_N

21

R3981

1K-1%

3

2

1 2

CPU1_THRMTRIP_3V

CPU1_PROCHOT_3V

CPU1_IERR_3V

R5965

0-5%

Q3947

3904

1

3

2

ROOM=PROC0

95,128

96

95,129

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

2

3

MCH

211

4

2.7K-5%

FSB0&1: PU's & GTL LEVEL TRANSLATION

2

INC.

4

ROUND ROCK,TEXAS

TITLE

SCHEM, PLN, SV, PE2950, MLK

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

REV.

HX601

SHEET

A00

9/7/2007 20 OF 136

DCBA

A B C

D

9-7-2007_16:37

ROOM=XDP

ECAD: Place zero ohms near CPU1 to mimize stub
ECAD: BPMS must daisy chain, no stubs!

1

13,15,17,54

24,30,53,63,71,72,91,96

24,30,53,63,71,72,91,96

2

I2C_CHIPSET_SDA

I2C_CHIPSET_SCL

CPU_PWRGOOD

POP9

POP9

POP9

17,21,22
17,21,22

R4800

1 2

0-5%

R5274

0-5%

R5275

1 2

0-5%

MOD_MCH_FSB1_BPM_5_N
MOD_MCH_FSB1_BPM_4_N

17,21
17,21

17,21
17,21

17,21
17,21

17,21
18,21

21

MOD_MCH_FSB1_BPM_3_N
MOD_MCH_FSB1_BPM_2_N

MOD_MCH_FSB1_BPM_1_N
MOD_MCH_FSB1_BPM_0_N

NC_MOD_MCH_XDP0_23

MOD_MCH_FSB1_BPMB_3_N
MOD_MCH_FSB1_BPMB_2_N

MOD_MCH_FSB1_BPMB_1_N
MOD_MCH_FSB1_BPMB_0_N

MOD_MCH_XDP0_PWRGOOD

NC_MOD_MCH_XDP0_41

NC_MOD_MCH_XDP0_45
NC_MOD_MCH_XDP0_47

21,24
13,17

MOD_MCH_XDP0_TCK1
MOD_MCH_XDP0_TCK0

MOD_MCH_XDP0_SDA_R
MOD_MCH_XDP0_SCL_R

21

R4511

51-5%

R4510

+CPU_VTT

ECAD: Terminate JTAG TCK0, TMS, TRST_N 51ohm PD/U's within 1" of end of last terminated CPU
ECAD: Terminate JTAG TCK1- 51ohm PD's within 1" of level translation ckt

J_XDP0_CPU

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2X30 MICRO-SOCKET CONN

POP9

51-5%

1 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

MOD_MCH_FSB0_BPM_5_N

MOD_MCH_FSB0_BPM_4_N

MOD_MCH_FSB0_BPM_3_N
MOD_MCH_FSB0_BPM_2_N

MOD_MCH_FSB0_BPM_1_N
MOD_MCH_FSB0_BPM_0_N

NC_MOD_MCH_XDP0_27NC_MOD_MCH_XDP0_21
NC_MOD_MCH_XDP0_24

MOD_MCH_FSB0_BPMB_3_N
MOD_MCH_FSB0_BPMB_2_N

MOD_MCH_FSB0_BPMB_1_N
MOD_MCH_FSB0_BPMB_0_N

CK_333M_XDP0_P
CK_333M_XDP0_N

MOD_MCH_XDP0_CPURST_N_R
RESET_BTN_N

MOD_MCH_XDP0_TDO_MAIN
MOD_MCH_XDP0_TRST_N
MOD_MCH_XDP0_TDI_MAIN
MOD_MCH_XDP0_TMS

21

R1006

51-5%

Depop R1006 for first rev

46,47
46,47

ECAD: Placement of TDI PU is arbitrary

13,21,22
13,21,22

13,21
13,21

13,21
13,21

+CPU_VTT

51-5%

R4512

51-5%

1 2

POP9

21
30,54,58,95,128

21
13,17,21,24
21
13,17,21,24

13,21
13,21

13,21
14,21

+CPU_VTT

21

R4822

XDP_BCLK

MLK: 0 ohm Res R25 added to reduce the stub on TDI MCH & ESB Signals

ECAD: Place PU's within 1" of corresponding PROC

CPU 0 or 1 JTAG jumper

JTAG CHAIN BUSTERS

NP

1 2

MOD_MCH_XDP0_TDI_MAIN

21

24

21

MOD_MCH_XDP0_TDO_MCH

MOD_MCH_XDP0_TDO_ESB

R4663

1 2

0-5%
0-5%

NP

R25

0-5%

X

1 2

NP

1 2

R5752

0-5%

R5751

X
X

ROOM = MCH

ECAD: place by MCH and GTL level shifters to reduce stubs

NP

0-5%

0-5%

NP

1 2

R5753

X

+CPU_VTT

MOD_MCH_XDP0_TDI_CPU0

MOD_MCH_XDP0_TDI_MCH

MOD_MCH_XDP0_TDI_ESB

NP

R5750

X

R5754

X

12

0-5%

1 2

MOD_MCH_XDP0_TDO_MAIN

13

1

24

21

21

2

3

4

+CPU_VTT

+CPU_VTT

R994

NP

1 2

51-5%

R996

1 2

51-5%

R998

1 2

51-5%

R5807

1 2

51-5%

R5809

1 2

51-5%

R1002

NP

51-5%

R1004

51-5%

R1001

51-5%

R5814

1 2

51-5%

R5812

1 2

51-5%

X

21

X

21

21

BPM[4:5]# sigs - XDP:BNB:2.2

MOD_MCH_FSB0_BPM_5_N

R995

NP

NP

1 2

1 2

1 2

51-5%

51-5%

R5808

51-5%

R997

R999

51-5%

R5810

51-5%

R1003

51-5%

R1005

51-5%

R1000

51-5%

R5813

51-5%

R5811

51-5%

21

X

21

21

21

21

X

21

21

MOD_MCH_FSB0_BPM_4_N

MOD_MCH_FSB0_BPM_3_N

MOD_MCH_FSB0_BPM_2_N

MOD_MCH_FSB0_BPM_1_N

MOD_MCH_FSB0_BPM_0_N

MOD_MCH_FSB0_BPMB_3_N

MOD_MCH_FSB0_BPMB_2_N

MOD_MCH_FSB0_BPMB_1_N

MOD_MCH_FSB0_BPMB_0_N

MOD_MCH_FSB1_BPM_5_N

MOD_MCH_FSB1_BPM_4_N

MOD_MCH_FSB1_BPM_3_N

MOD_MCH_FSB1_BPM_2_N

MOD_MCH_FSB1_BPM_1_N

MOD_MCH_FSB1_BPM_0_N

MOD_MCH_FSB1_BPMB_3_N

MOD_MCH_FSB1_BPMB_2_N

MOD_MCH_FSB1_BPMB_1_N

MOD_MCH_FSB1_BPMB_0_N

13,21,22

13,21,22

13,21

13,21

13,21

13,21

13,21

13,21

13,21

14,21

17,21,22

17,21,22

17,21

17,21

17,21

17,21

17,21

17,21

17,21

18,21

ECAD: Place PU near translator <1"

GTL side of translator ESB2 side of translator

13,17,21,24
13,17,21,24

21,24

21

21

MOD_MCH_XDP0_TRST_N
MOD_MCH_XDP0_TMS
MOD_MCH_XDP0_TCK1
MOD_MCH_XDP0_TDI_ESB

MOD_MCH_XDP0_TDO_ESB
NC_MOD_MCH_U_JTAG_T_2_3
NC_MOD_MCH_U_JTAG_T_2_5
NC_MOD_MCH_U_JTAG_T_2_6

XDP 0 header and logic

NP

21

R4823

X

51-5%

+3.3V

NP

R4745

X

+CPU_VTT

R4821

1 2

NP

R4744

X

1 2

1K-1%

1 2

ECAD: Place PU near translator <1"

51-5%

+3.3V

NP

1K-1%

NP

2

A0

3

A1

5

A2

6

A3

1

DIR

14 7

VCC GND1

NP

2

A0

3

A1

5

A2

6

A3

1

DIR

VCC GND1

NP

U_JTAG_T_1

GTLREF

GND2
GND3

GTL2005

U_JTAG_T_2

GTLREF

GND2
GND3

GTL2005

13

B0

12

B1

10

B2

9

B3

4

8

X

11

13

B0

12

B1

10

B2

9

B3

4

714
8

X

11

XDP0_TRST_N_3V
XDP0_TMS_3V
XDP0_TCK1_3V
XDP0_TDI_ESB_3V

XDP0_TDO_ESB_3V
MOD_MCH_U_JTAG_T_2_PD

NP

R4746

X

1 2

53
53
53
53

53

1K-1%

MOD_MCH_XDP0_TDI_CPU1

17

MOD_MCH_XDP0_TDO_CPU0

MOD_MCH_XDP0_TDO_CPU1

13,21

17,21

17,19,22

MOD_MCH_XDP0_TDO_CPU0

MOD_MCH_XDP0_TDO_CPU1

MOD_MCH_FSB1_RST_N

+CPU_VTT

NP

21

R4769

X

NP

R4775

X

1 2

13,21

17,21 21

100-1% 49.9-1%

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

R4499

R4498

1 2

0-5%

NP

POP9

0-5%

1 2

MOD_MCH_XDP0_TDO_MAIN

X

U_XDP_QS

1

B1

2

GND

NC7SB3157

POP9

S: L -> A= B0; H -> A=B1

R4797

1 2

1K-1%

POP9

MOD_MCH_XDP0_CPURST_N_R

TITLE

DWG NO.

DATE

R3832

Do not use header if QS
populated, see XDP JTAG pdf

6

S

5

VCC

43

AB0

51-5%

1 2

WARNING:

J_XDP_JTAG

1
2
3

X

+3.3V

CPU1_PRES_N

MOD_MCH_XDP0_TDO_MAIN

MODULE:
DESC:
REV: OF

NP

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

HX601

SHEET

21

3

17,95,119,128

21

MCH

CPUS,FSB,NB,XDP0,XDP1

SEC

211

4

REV.

A00

21 OF 1369/7/2007

C

DBA

A B C

D

1

2

3

12
12
12
12

12
12
12
12

MOD_MCH_FSB0_D63_N

12

MOD_MCH_FSB0_D62_N

12

MOD_MCH_FSB0_D61_N

12

MOD_MCH_FSB0_D60_N

12

MOD_MCH_FSB0_D59_N

12

MOD_MCH_FSB0_D58_N

12

MOD_MCH_FSB0_D57_N

12

MOD_MCH_FSB0_D56_N

12

MOD_MCH_FSB0_D55_N

12

MOD_MCH_FSB0_D54_N

12

MOD_MCH_FSB0_D53_N

12

MOD_MCH_FSB0_D52_N

12

MOD_MCH_FSB0_D51_N

12

MOD_MCH_FSB0_D50_N

12

MOD_MCH_FSB0_D49_N

12

MOD_MCH_FSB0_D48_N

12

MOD_MCH_FSB0_D47_N

12

MOD_MCH_FSB0_D46_N

12

MOD_MCH_FSB0_D45_N

12

MOD_MCH_FSB0_D44_N

12

MOD_MCH_FSB0_D43_N

12

MOD_MCH_FSB0_D42_N

12

MOD_MCH_FSB0_D41_N

12

MOD_MCH_FSB0_D40_N

12

MOD_MCH_FSB0_D39_N

12

MOD_MCH_FSB0_D38_N

12

MOD_MCH_FSB0_D37_N

12

MOD_MCH_FSB0_D36_N

12

MOD_MCH_FSB0_D35_N

12

MOD_MCH_FSB0_D34_N

12

MOD_MCH_FSB0_D33_N

12

MOD_MCH_FSB0_D32_N

12

MOD_MCH_FSB0_D31_N

12

MOD_MCH_FSB0_D30_N

12

MOD_MCH_FSB0_D29_N

12

MOD_MCH_FSB0_D28_N

12

MOD_MCH_FSB0_D27_N

12

MOD_MCH_FSB0_D26_N

12

MOD_MCH_FSB0_D25_N

12

MOD_MCH_FSB0_D24_N

12

MOD_MCH_FSB0_D23_N

12

MOD_MCH_FSB0_D22_N

12

MOD_MCH_FSB0_D21_N

12

MOD_MCH_FSB0_D20_N

12

MOD_MCH_FSB0_D19_N

12

MOD_MCH_FSB0_D18_N

12

MOD_MCH_FSB0_D17_N

12

MOD_MCH_FSB0_D16_N

12

MOD_MCH_FSB0_D15_N

12

MOD_MCH_FSB0_D14_N

12

MOD_MCH_FSB0_D13_N

12

MOD_MCH_FSB0_D12_N

12

MOD_MCH_FSB0_D11_N

12

MOD_MCH_FSB0_D10_N

12

MOD_MCH_FSB0_D9_N

12

MOD_MCH_FSB0_D8_N

12

MOD_MCH_FSB0_D7_N

12

MOD_MCH_FSB0_D6_N

12

MOD_MCH_FSB0_D5_N

12

MOD_MCH_FSB0_D4_N

12

MOD_MCH_FSB0_D3_N

12

MOD_MCH_FSB0_D2_N

12

MOD_MCH_FSB0_D1_N

12

MOD_MCH_FSB0_D0_N

12

MOD_MCH_FSB0_DBI_3_N
MOD_MCH_FSB0_DBI_2_N
MOD_MCH_FSB0_DBI_1_N
MOD_MCH_FSB0_DBI_0_N

MOD_MCH_FSB0_DSTBP_3_N
MOD_MCH_FSB0_DSTBP_2_N
MOD_MCH_FSB0_DSTBP_1_N
MOD_MCH_FSB0_DSTBP_0_N

AE37
AE36
AH36
AG36
AF38
AE38
AH38
AJ38
AJ37
AG35
AK36
AL37
AL36
AL38
AJ34
AF37
AE28
AD29
AF28
AC31
AE29
AC30
AD30
AE31
AE32
AD35
AF33
AG32
AF31
AE34
AG30
AG33
AM37
AK35
AM34
AM38
AP38
AN36
AL35
AN35
AP36
AT37
AU36
AP34
AT36
AP35
AL34
AN33
AJ33
AG27
AG29
AM33
AH31
AJ30
AH32
AJ31
AL31
AK30
AN32
AH29
AK29
AH28
AL29
AJ28

AH37
AF30
AP37
AL32

AH35
AD33
AR38
AK33

FSB0_D_63_N
FSB0_D_62_N
FSB0_D_61_N
FSB0_D_60_N
FSB0_D_59_N
FSB0_D_58_N
FSB0_D_57_N
FSB0_D_56_N
FSB0_D_55_N
FSB0_D_54_N
FSB0_D_53_N
FSB0_D_52_N
FSB0_D_51_N
FSB0_D_50_N
FSB0_D_49_N
FSB0_D_48_N
FSB0_D_47_N
FSB0_D_46_N
FSB0_D_45_N
FSB0_D_44_N
FSB0_D_43_N
FSB0_D_42_N
FSB0_D_41_N
FSB0_D_40_N
FSB0_D_39_N
FSB0_D_38_N
FSB0_D_37_N
FSB0_D_36_N
FSB0_D_35_N
FSB0_D_34_N
FSB0_D_33_N
FSB0_D_32_N
FSB0_D_31_N
FSB0_D_30_N
FSB0_D_29_N
FSB0_D_28_N
FSB0_D_27_N
FSB0_D_26_N
FSB0_D_25_N
FSB0_D_24_N
FSB0_D_23_N
FSB0_D_22_N
FSB0_D_21_N
FSB0_D_20_N
FSB0_D_19_N
FSB0_D_18_N
FSB0_D_17_N
FSB0_D_16_N
FSB0_D_15_N
FSB0_D_14_N
FSB0_D_13_N
FSB0_D_12_N
FSB0_D_11_N
FSB0_D_10_N
FSB0_D_9_N
FSB0_D_8_N
FSB0_D_7_N
FSB0_D_6_N
FSB0_D_5_N
FSB0_D_4_N
FSB0_D_3_N
FSB0_D_2_N
FSB0_D_1_N
FSB0_D_0_N

FSB0_DBI_3_N
FSB0_DBI_2_N
FSB0_DBI_1_N
FSB0_DBI_0_N

FSB0_DSTBP_3_N
FSB0_DSTBP_2_N
FSB0_DSTBP_1_N
FSB0_DSTBP_0_N

U_MCH

FSB0_A_35_N
FSB0_A_34_N
FSB0_A_33_N
FSB0_A_32_N
FSB0_A_31_N
FSB0_A_30_N
FSB0_A_29_N
FSB0_A_28_N
FSB0_A_27_N
FSB0_A_26_N
FSB0_A_25_N
FSB0_A_24_N
FSB0_A_23_N
FSB0_A_22_N
FSB0_A_21_N
FSB0_A_20_N
FSB0_A_19_N
FSB0_A_18_N
FSB0_A_17_N
FSB0_A_16_N
FSB0_A_15_N
FSB0_A_14_N
FSB0_A_13_N
FSB0_A_12_N
FSB0_A_11_N
FSB0_A_10_N

FSB0_A_9_N
FSB0_A_8_N
FSB0_A_7_N
FSB0_A_6_N
FSB0_A_5_N
FSB0_A_4_N
FSB0_A_3_N

FSB0_REQ_4_N
FSB0_REQ_3_N
FSB0_REQ_2_N
FSB0_REQ_1_N
FSB0_REQ_0_N

FSB0_ADSTB_1_N
FSB0_ADSTB_0_N

FSB0_BPRI_N
FSB0_DEFER_N
FSB0_RESET_N

FSB0_RS_2_N

FSB0_RS_1_N

FSB0_RS_0_N

FSB0_RSP_N

FSB0_TRDY_N

FSB0_ADS_N
FSB0_AP_1_N
FSB0_AP_0_N

FSB0_BINIT_N

FSB0_BNR_N

FSB0_BPM_5_N

FSB0_BPM_4_N
FSB0_BREQ_1_N
FSB0_BREQ_0_N

FSB0_DBSY_N
FSB0_DP_3_N
FSB0_DP_2_N
FSB0_DP_1_N
FSB0_DP_0_N
FSB0_DRDY_N

FSB0_HIT_N
FSB0_HITM_N
FSB0_LOCK_N

FSB0_MCERR_N

AV22
AU22
AR22
AP22
AV24
AT23
AU23
AV25
AT24
AR25
AU26
AT26
AT27
AU25
AU28
AR24
AR27
AP25
AV28
AF22
AG23
AF25
AH22
AL22
AJ22
AG24
AM22
AH23
AP26
AN26
AM25
AN24
AL25

AJ25
AJ24
AK24
AH25
AL26

AP23
AL23

AU34
AV34
AN30
AU31
AL28
AV31
AN27
AT32

AU29
AK26
AH26
AK27
AV30
AP29
AR28
AG26
AM28
AR30
AN29
AP31
AT33
AR31
AT29
AU32
AV33
AT30
AJ27

MOD_MCH_FSB0_A35_N
MOD_MCH_FSB0_A34_N
MOD_MCH_FSB0_A33_N
MOD_MCH_FSB0_A32_N
MOD_MCH_FSB0_A31_N
MOD_MCH_FSB0_A30_N
MOD_MCH_FSB0_A29_N
MOD_MCH_FSB0_A28_N
MOD_MCH_FSB0_A27_N
MOD_MCH_FSB0_A26_N
MOD_MCH_FSB0_A25_N
MOD_MCH_FSB0_A24_N
MOD_MCH_FSB0_A23_N
MOD_MCH_FSB0_A22_N
MOD_MCH_FSB0_A21_N
MOD_MCH_FSB0_A20_N
MOD_MCH_FSB0_A19_N
MOD_MCH_FSB0_A18_N
MOD_MCH_FSB0_A17_N
MOD_MCH_FSB0_A16_N
MOD_MCH_FSB0_A15_N
MOD_MCH_FSB0_A14_N
MOD_MCH_FSB0_A13_N
MOD_MCH_FSB0_A12_N
MOD_MCH_FSB0_A11_N
MOD_MCH_FSB0_A10_N
MOD_MCH_FSB0_A9_N
MOD_MCH_FSB0_A8_N
MOD_MCH_FSB0_A7_N
MOD_MCH_FSB0_A6_N
MOD_MCH_FSB0_A5_N
MOD_MCH_FSB0_A4_N
MOD_MCH_FSB0_A3_N

MOD_MCH_FSB0_REQ_4_N
MOD_MCH_FSB0_REQ_3_N
MOD_MCH_FSB0_REQ_2_N
MOD_MCH_FSB0_REQ_1_N
MOD_MCH_FSB0_REQ_0_N

MOD_MCH_FSB0_ADSTB_1_N
MOD_MCH_FSB0_ADSTB_0_N

MOD_MCH_FSB0_BPRI_N
MOD_MCH_FSB0_DEFER_N
MOD_MCH_FSB0_RST_N
MOD_MCH_FSB0_RS_2_N
MOD_MCH_FSB0_RS_1_N
MOD_MCH_FSB0_RS_0_N
MOD_MCH_FSB0_RSP_N
MOD_MCH_FSB0_TRDY_N

MOD_MCH_FSB0_ADS_N
MOD_MCH_FSB0_AP_1_N
MOD_MCH_FSB0_AP_0_N
MOD_MCH_FSB0_BINIT_N
MOD_MCH_FSB0_BNR_N
MOD_MCH_FSB0_BPM_5_N
MOD_MCH_FSB0_BPM_4_N
MOD_MCH_FSB0_BREQ_1_N
MOD_MCH_FSB0_BREQ_0_N
MOD_MCH_FSB0_DBSY_N
MOD_MCH_FSB0_DP_3_N
MOD_MCH_FSB0_DP_2_N
MOD_MCH_FSB0_DP_1_N
MOD_MCH_FSB0_DP_0_N
MOD_MCH_FSB0_DRDY_N
MOD_MCH_FSB0_HIT_N
MOD_MCH_FSB0_HITM_N
MOD_MCH_FSB0_LOCK_N
MOD_MCH_FSB0_MCERR_N

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12
12
12
12
12

12
12

13
13
13,15
13
13
13
13
13

13
13
13
13
13

13,15
13,15
13
13
13
13
13
13
13
13
13
13

13,21
13,21

MOD_MCH_FSB1_D63_N

16

MOD_MCH_FSB1_D62_N

16

MOD_MCH_FSB1_D61_N

16

MOD_MCH_FSB1_D60_N

16

MOD_MCH_FSB1_D59_N

16

MOD_MCH_FSB1_D58_N

16

MOD_MCH_FSB1_D57_N

16

MOD_MCH_FSB1_D56_N

16

MOD_MCH_FSB1_D55_N

16

MOD_MCH_FSB1_D54_N

16

MOD_MCH_FSB1_D53_N

16

MOD_MCH_FSB1_D52_N

16

MOD_MCH_FSB1_D51_N

16

MOD_MCH_FSB1_D50_N

16

MOD_MCH_FSB1_D49_N

16

MOD_MCH_FSB1_D48_N

16

MOD_MCH_FSB1_D47_N

16

MOD_MCH_FSB1_D46_N

16

MOD_MCH_FSB1_D45_N

16

MOD_MCH_FSB1_D44_N

16

MOD_MCH_FSB1_D43_N

16

MOD_MCH_FSB1_D42_N

16

MOD_MCH_FSB1_D41_N

16

MOD_MCH_FSB1_D40_N

16

MOD_MCH_FSB1_D39_N

16

MOD_MCH_FSB1_D38_N

16

MOD_MCH_FSB1_D37_N

16

MOD_MCH_FSB1_D36_N

16

MOD_MCH_FSB1_D35_N

16

MOD_MCH_FSB1_D34_N

16

MOD_MCH_FSB1_D33_N

16

MOD_MCH_FSB1_D32_N

16

MOD_MCH_FSB1_D31_N

16

MOD_MCH_FSB1_D30_N

16

MOD_MCH_FSB1_D29_N

16

MOD_MCH_FSB1_D28_N

16

MOD_MCH_FSB1_D27_N

16

MOD_MCH_FSB1_D26_N

16

MOD_MCH_FSB1_D25_N

16

MOD_MCH_FSB1_D24_N

16

MOD_MCH_FSB1_D23_N

16

MOD_MCH_FSB1_D22_N

16

MOD_MCH_FSB1_D21_N

16

MOD_MCH_FSB1_D20_N

16

MOD_MCH_FSB1_D19_N

16

MOD_MCH_FSB1_D18_N

16

MOD_MCH_FSB1_D17_N

16

MOD_MCH_FSB1_D16_N

16

MOD_MCH_FSB1_D15_N

16

MOD_MCH_FSB1_D14_N

16

MOD_MCH_FSB1_D13_N

16

MOD_MCH_FSB1_D12_N

16

MOD_MCH_FSB1_D11_N

16

MOD_MCH_FSB1_D10_N

16

MOD_MCH_FSB1_D9_N

16

MOD_MCH_FSB1_D8_N

16

MOD_MCH_FSB1_D7_N

16

MOD_MCH_FSB1_D6_N

16

MOD_MCH_FSB1_D5_N

16

MOD_MCH_FSB1_D4_N

16

MOD_MCH_FSB1_D3_N

16

MOD_MCH_FSB1_D2_N

16

MOD_MCH_FSB1_D1_N

16

MOD_MCH_FSB1_D0_N

16

MOD_MCH_FSB1_DBI_3_N

16

MOD_MCH_FSB1_DBI_2_N

16

MOD_MCH_FSB1_DBI_1_N

16

MOD_MCH_FSB1_DBI_0_N

16

MOD_MCH_FSB1_DSTBP_3_N

16

MOD_MCH_FSB1_DSTBP_2_N

16

MOD_MCH_FSB1_DSTBP_1_N

16

MOD_MCH_FSB1_DSTBP_0_N

16

AF16
AG14
AJ16
AJ15
AG15
AF15
AJ13
AL16
AP16
AH16
AN15
AL14
AM15
AN14
AM16
AH14
AP14
AR12
AR13
AP11
AP13
AT12
AT11
AV12
AV10
AU10

AV9
AT8
AR9
AT9
AU8

AV7
AK12
AL13
AL11
AM13
AN11
AM12
AN12

AN9

AN8

AP8

AM9

AM6

AK9

AN6

AL8

AL7

AU5

AR7

AU7

AR6

AT6

AV4

AV6

AT5

AT3

AT2

AR4

AR3

AR1

AP4

AP5

AP1

AH13
AU11
AK11

AP7

AK15
AR10
AM10

AU4

FSB1_D_63_N
FSB1_D_62_N
FSB1_D_61_N
FSB1_D_60_N
FSB1_D_59_N
FSB1_D_58_N
FSB1_D_57_N
FSB1_D_56_N
FSB1_D_55_N
FSB1_D_54_N
FSB1_D_53_N
FSB1_D_52_N
FSB1_D_51_N
FSB1_D_50_N
FSB1_D_49_N
FSB1_D_48_N
FSB1_D_47_N
FSB1_D_46_N
FSB1_D_45_N
FSB1_D_44_N
FSB1_D_43_N
FSB1_D_42_N
FSB1_D_41_N
FSB1_D_40_N
FSB1_D_39_N
FSB1_D_38_N
FSB1_D_37_N
FSB1_D_36_N
FSB1_D_35_N
FSB1_D_34_N
FSB1_D_33_N
FSB1_D_32_N
FSB1_D_31_N
FSB1_D_30_N
FSB1_D_29_N
FSB1_D_28_N
FSB1_D_27_N
FSB1_D_26_N
FSB1_D_25_N
FSB1_D_24_N
FSB1_D_23_N
FSB1_D_22_N
FSB1_D_21_N
FSB1_D_20_N
FSB1_D_19_N
FSB1_D_18_N
FSB1_D_17_N
FSB1_D_16_N
FSB1_D_15_N
FSB1_D_14_N
FSB1_D_13_N
FSB1_D_12_N
FSB1_D_11_N
FSB1_D_10_N
FSB1_D_9_N
FSB1_D_8_N
FSB1_D_7_N
FSB1_D_6_N
FSB1_D_5_N
FSB1_D_4_N
FSB1_D_3_N
FSB1_D_2_N
FSB1_D_1_N
FSB1_D_0_N

FSB1_DBI_3_N
FSB1_DBI_2_N
FSB1_DBI_1_N
FSB1_DBI_0_N

FSB1_DSTBP_3_N
FSB1_DSTBP_2_N
FSB1_DSTBP_1_N
FSB1_DSTBP_0_N

U_MCH

FSB1_A_35_N
FSB1_A_34_N
FSB1_A_33_N
FSB1_A_32_N
FSB1_A_31_N
FSB1_A_30_N
FSB1_A_29_N
FSB1_A_28_N
FSB1_A_27_N
FSB1_A_26_N
FSB1_A_25_N
FSB1_A_24_N
FSB1_A_23_N
FSB1_A_22_N
FSB1_A_21_N
FSB1_A_20_N
FSB1_A_19_N
FSB1_A_18_N
FSB1_A_17_N
FSB1_A_16_N
FSB1_A_15_N
FSB1_A_14_N
FSB1_A_13_N
FSB1_A_12_N
FSB1_A_11_N
FSB1_A_10_N

FSB1_A_9_N
FSB1_A_8_N
FSB1_A_7_N
FSB1_A_6_N
FSB1_A_5_N
FSB1_A_4_N
FSB1_A_3_N

FSB1_REQ_4_N
FSB1_REQ_3_N
FSB1_REQ_2_N
FSB1_REQ_1_N
FSB1_REQ_0_N

FSB1_ADSTB_1_N
FSB1_ADSTB_0_N

FSB1_BPRI_N
FSB1_DEFER_N
FSB1_RESET_N

FSB1_RS_2_N

FSB1_RS_1_N

FSB1_RS_0_N

FSB1_RSP_N

FSB1_TRDY_N

FSB1_ADS_N
FSB1_AP_1_N
FSB1_AP_0_N

FSB1_BINIT_N

FSB1_BNR_N

FSB1_BPM_5_N

FSB1_BPM_4_N
FSB1_BREQ_1_N
FSB1_BREQ_0_N

FSB1_DBSY_N
FSB1_DP_3_N
FSB1_DP_2_N
FSB1_DP_1_N
FSB1_DP_0_N
FSB1_DRDY_N

FSB1_HIT_N
FSB1_HITM_N
FSB1_LOCK_N

FSB1_MCERR_N

AC3
AC4
AD2
AE1
AE2
AE4
AD3
AF3
AF1
AJ3
AH1
AH2
AD5
AC6
AE5
AD6
AH5
AG5
AF4
AA12
AC7
AB10
AC9
AD8
AF6
AB11
AE7
AF7
AG8
AH8
AC12
AD9
AD12

AE10
AF9
AJ6
AD11
AG9

AG3
AC10

AJ10
AJ9
AE11
AL5
AL1
AK5
AK2
AK6

AP2
AG10
AG12
AJ4
AK3
AN3
AN2
AM1
AL2
AM4
AF13
AF12
AJ12
AG11
AM3
AK8
AJ7
AL4
AH11

MOD_MCH_FSB1_A35_N
MOD_MCH_FSB1_A34_N
MOD_MCH_FSB1_A33_N
MOD_MCH_FSB1_A32_N
MOD_MCH_FSB1_A31_N
MOD_MCH_FSB1_A30_N
MOD_MCH_FSB1_A29_N
MOD_MCH_FSB1_A28_N
MOD_MCH_FSB1_A27_N
MOD_MCH_FSB1_A26_N
MOD_MCH_FSB1_A25_N
MOD_MCH_FSB1_A24_N
MOD_MCH_FSB1_A23_N
MOD_MCH_FSB1_A22_N
MOD_MCH_FSB1_A21_N
MOD_MCH_FSB1_A20_N
MOD_MCH_FSB1_A19_N
MOD_MCH_FSB1_A18_N
MOD_MCH_FSB1_A17_N
MOD_MCH_FSB1_A16_N
MOD_MCH_FSB1_A15_N
MOD_MCH_FSB1_A14_N
MOD_MCH_FSB1_A13_N
MOD_MCH_FSB1_A12_N
MOD_MCH_FSB1_A11_N
MOD_MCH_FSB1_A10_N
MOD_MCH_FSB1_A9_N
MOD_MCH_FSB1_A8_N
MOD_MCH_FSB1_A7_N
MOD_MCH_FSB1_A6_N
MOD_MCH_FSB1_A5_N
MOD_MCH_FSB1_A4_N
MOD_MCH_FSB1_A3_N

MOD_MCH_FSB1_REQ_4_N
MOD_MCH_FSB1_REQ_3_N
MOD_MCH_FSB1_REQ_2_N
MOD_MCH_FSB1_REQ_1_N
MOD_MCH_FSB1_REQ_0_N

MOD_MCH_FSB1_ADSTB_1_N
MOD_MCH_FSB1_ADSTB_0_N

MOD_MCH_FSB1_BPRI_N
MOD_MCH_FSB1_DEFER_N
MOD_MCH_FSB1_RST_N
MOD_MCH_FSB1_RS_2_N
MOD_MCH_FSB1_RS_1_N
MOD_MCH_FSB1_RS_0_N
MOD_MCH_FSB1_RSP_N
MOD_MCH_FSB1_TRDY_N

MOD_MCH_FSB1_ADS_N
MOD_MCH_FSB1_AP_1_N
MOD_MCH_FSB1_AP_0_N
MOD_MCH_FSB1_BINIT_N

MOD_MCH_FSB1_BNR_N
MOD_MCH_FSB1_BPM_5_N
MOD_MCH_FSB1_BPM_4_N

MOD_MCH_FSB1_BREQ_1_N
MOD_MCH_FSB1_BREQ_0_N
MOD_MCH_FSB1_DBSY_N
MOD_MCH_FSB1_DP_3_N
MOD_MCH_FSB1_DP_2_N
MOD_MCH_FSB1_DP_1_N
MOD_MCH_FSB1_DP_0_N
MOD_MCH_FSB1_DRDY_N
MOD_MCH_FSB1_HIT_N
MOD_MCH_FSB1_HITM_N
MOD_MCH_FSB1_LOCK_N
MOD_MCH_FSB1_MCERR_N

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

16
16
16
16
16

17
17

17,19,21

17
17
17
17

17

17
17
17
17
17

17,19
17,19
17
17
17
17
17
17
17
17
17
17

1

2

16
16

17,21
17,21

3

4

12
12
12
12

CK_333M_MCH_P

45

CK_333M_MCH_N

45

MOD_MCH_FSB0_DSTBN_3_N
MOD_MCH_FSB0_DSTBN_2_N
MOD_MCH_FSB0_DSTBN_1_N
MOD_MCH_FSB0_DSTBN_0_N

AH34
AD32
AR37
AK32

AN17
AP17

FSB0_DSTBN_3_N
FSB0_DSTBN_2_N
FSB0_DSTBN_1_N
FSB0_DSTBN_0_N

CORECLKP
CORECLKN

ECAD: Place VREF caps as close as possible to MCH pin

GREENCREEK REV 3.1

HETERO 4 OF 11

PSEL_2
PSEL_1
PSEL_0

FSB0_VREF_AF34
FSB0_VREF_AM27
FSB0_VREF_AM30

AB1
AB2
AC1

AF34

MOD_MCH_PSEL_2_1V5
MOD_MCH_PSEL_1_1V5
MOD_MCH_PSEL_0_1V5

MOD_MCH_FSB0_VREF

20
20
20

28

AM27
AM30

C2753

1 2

220pF

50V-10%

C2752

1 2

220pF

50V-10%

C2749

1 2

220pF

50V-10%

ROOM = MCH_FSB0_VREF_CAPS

MCH CPU interface

MOD_MCH_FSB1_DSTBN_3_N

16

MOD_MCH_FSB1_DSTBN_2_N

16

MOD_MCH_FSB1_DSTBN_1_N

16

MOD_MCH_FSB1_DSTBN_0_N

16

28
28
28

MOD_MCH_CORE_VCCA

MOD_MCH_FSB_VCCA

MOD_MCH_CORE_VSSA

AK14
AP10
AL10

AT17
AU17
AU16

FSB1_DSTBN_3_N
FSB1_DSTBN_2_N
FSB1_DSTBN_1_N

AU3

FSB1_DSTBN_0_N

COREVCCA
FSBVCCA
COREVSSA

FSB1_VREF_AH4
FSB1_VREF_AN5

FSB1_VREF_AT14

GREENCREEK REV 3.1

HETERO 5 OF 11

ECAD: Place VREF caps as close as possible to MCH pin

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

FSBCRES
FSBODTCRES
FSBSLWCRES
FSBSLWCTRL

AT35
AR34
AU35
AV13

AH4
AN5
AT14

MOD_MCH_FSB_CRES
MOD_MCH_FSB_ODTCRES
MOD_MCH_FSB_SLWCRES
MOD_MCH_FSB_SLWCTRL

MOD_MCH_FSB1_VREF

1 2

220pF

50V-10%

C2750

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

DATE

9/7/2007 22 OF 136

C2751

1 2

HX601

220pF

50V-10%

C2748

1 2

28
28
28
28

28

ROOM = MCH_FSB1_VREF_CAPS

220pF

50V-10%

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

REV.

A00

SHEET

MCH

211

4

C

DBA

A B C

D

1

2

FBD_CH0_MCH_NB_13_P

32

FBD_CH0_MCH_NB_12_P

32

FBD_CH0_MCH_NB_11_P

32

FBD_CH0_MCH_NB_10_P

32

FBD_CH0_MCH_NB_9_P

32

FBD_CH0_MCH_NB_8_P

32

FBD_CH0_MCH_NB_7_P

32

FBD_CH0_MCH_NB_6_P

32

FBD_CH0_MCH_NB_5_P

32

FBD_CH0_MCH_NB_4_P

32

FBD_CH0_MCH_NB_3_P

32

FBD_CH0_MCH_NB_2_P

32

FBD_CH0_MCH_NB_1_P

32

FBD_CH0_MCH_NB_0_P

32

FBD_CH0_MCH_NB_13_N

32

FBD_CH0_MCH_NB_12_N

32

FBD_CH0_MCH_NB_11_N

32

FBD_CH0_MCH_NB_10_N

32

FBD_CH0_MCH_NB_9_N

32

FBD_CH0_MCH_NB_8_N

32

FBD_CH0_MCH_NB_7_N

32

FBD_CH0_MCH_NB_6_N

32

FBD_CH0_MCH_NB_5_N

32

FBD_CH0_MCH_NB_4_N

32

FBD_CH0_MCH_NB_3_N

32

FBD_CH0_MCH_NB_2_N

32

FBD_CH0_MCH_NB_1_N

32

FBD_CH0_MCH_NB_0_N

32

V29
U30
U36
V35
W34
U33
V32
T31
W28
U28
V27

AB31

Y30
Y27

V30
U31
U37
V36
W35
U34
V33
T32
W29
T28
U27

AB32

Y31
Y28

FBD0NBIP_13
FBD0NBIP_12
FBD0NBIP_11
FBD0NBIP_10
FBD0NBIP_9
FBD0NBIP_8
FBD0NBIP_7
FBD0NBIP_6
FBD0NBIP_5
FBD0NBIP_4
FBD0NBIP_3
FBD0NBIP_2
FBD0NBIP_1
FBD0NBIP_0

FBD0NBIN_13
FBD0NBIN_12
FBD0NBIN_11
FBD0NBIN_10
FBD0NBIN_9
FBD0NBIN_8
FBD0NBIN_7
FBD0NBIN_6
FBD0NBIN_5
FBD0NBIN_4
FBD0NBIN_3
FBD0NBIN_2
FBD0NBIN_1
FBD0NBIN_0

U_MCH

Chan 0

Branch 0

FBD0SBOP_9
FBD0SBOP_8
FBD0SBOP_7
FBD0SBOP_6
FBD0SBOP_5
FBD0SBOP_4
FBD0SBOP_3
FBD0SBOP_2
FBD0SBOP_1
FBD0SBOP_0

FBD0SBON_9
FBD0SBON_8
FBD0SBON_7
FBD0SBON_6
FBD0SBON_5
FBD0SBON_4
FBD0SBON_3
FBD0SBON_2
FBD0SBON_1
FBD0SBON_0

AA36
AC34
AB35
AB37
AA38
Y36
Y34
AA32
V38
W32

AA35
AC33
AB34
AC37
AB38
Y37
Y33
AA33
W38
W31

FBD_CH0_MCH_SB_9_P
FBD_CH0_MCH_SB_8_P
FBD_CH0_MCH_SB_7_P
FBD_CH0_MCH_SB_6_P
FBD_CH0_MCH_SB_5_P
FBD_CH0_MCH_SB_4_P
FBD_CH0_MCH_SB_3_P
FBD_CH0_MCH_SB_2_P
FBD_CH0_MCH_SB_1_P
FBD_CH0_MCH_SB_0_P

FBD_CH0_MCH_SB_9_N
FBD_CH0_MCH_SB_8_N
FBD_CH0_MCH_SB_7_N
FBD_CH0_MCH_SB_6_N
FBD_CH0_MCH_SB_5_N
FBD_CH0_MCH_SB_4_N
FBD_CH0_MCH_SB_3_N
FBD_CH0_MCH_SB_2_N
FBD_CH0_MCH_SB_1_N
FBD_CH0_MCH_SB_0_N

32
32
32
32
32
32
32
32
32
32

32
32
32
32
32
32
32
32
32
32

FBD_CH2_MCH_NB_13_P

34

FBD_CH2_MCH_NB_12_P

34

FBD_CH2_MCH_NB_11_P

34

FBD_CH2_MCH_NB_10_P

34

FBD_CH2_MCH_NB_9_P

34

FBD_CH2_MCH_NB_8_P

34

FBD_CH2_MCH_NB_7_P

34

FBD_CH2_MCH_NB_6_P

34

FBD_CH2_MCH_NB_5_P

34

FBD_CH2_MCH_NB_4_P

34

FBD_CH2_MCH_NB_3_P

34

FBD_CH2_MCH_NB_2_P

34

FBD_CH2_MCH_NB_1_P

34

FBD_CH2_MCH_NB_0_P

34

FBD_CH2_MCH_NB_13_N

34

FBD_CH2_MCH_NB_12_N

34

FBD_CH2_MCH_NB_11_N

34

FBD_CH2_MCH_NB_10_N

34

FBD_CH2_MCH_NB_9_N

34

FBD_CH2_MCH_NB_8_N

34

FBD_CH2_MCH_NB_7_N

34

FBD_CH2_MCH_NB_6_N

34

FBD_CH2_MCH_NB_5_N

34

FBD_CH2_MCH_NB_4_N

34

FBD_CH2_MCH_NB_3_N

34

FBD_CH2_MCH_NB_2_N

34

FBD_CH2_MCH_NB_1_N

34

FBD_CH2_MCH_NB_0_N

34

C31

FBD2NBIP_13

B32

FBD2NBIP_12

D38

FBD2NBIP_11

C37

FBD2NBIP_10

C36

FBD2NBIP_9

B35

FBD2NBIP_8

C34

FBD2NBIP_7

B33

FBD2NBIP_6

B30

FBD2NBIP_5

B29

FBD2NBIP_4

C28

FBD2NBIP_3

B27

FBD2NBIP_2

B26

FBD2NBIP_1

C25

FBD2NBIP_0

B31

FBD2NBIN_13

A32

FBD2NBIN_12

E38

FBD2NBIN_11

D37

FBD2NBIN_10

B36

FBD2NBIN_9

A35

FBD2NBIN_8

B34

FBD2NBIN_7

A33

FBD2NBIN_6

A30

FBD2NBIN_5

A29

FBD2NBIN_4

B28

FBD2NBIN_3

A27

FBD2NBIN_2

A26

FBD2NBIN_1

B25

FBD2NBIN_0

U_MCH

Branch 1

Chan 2

FBD2SBOP_9
FBD2SBOP_8
FBD2SBOP_7
FBD2SBOP_6
FBD2SBOP_5
FBD2SBOP_4
FBD2SBOP_3
FBD2SBOP_2
FBD2SBOP_1
FBD2SBOP_0

FBD2SBON_9
FBD2SBON_8
FBD2SBON_7
FBD2SBON_6
FBD2SBON_5
FBD2SBON_4
FBD2SBON_3
FBD2SBON_2
FBD2SBON_1
FBD2SBON_0

E33
J32
H33
G34
D34
F32
D31
E30
F29
G28

E34
J33
H34
G35
D35
F33
D32
E31
F30
G29

FBD_CH2_MCH_SB_9_P
FBD_CH2_MCH_SB_8_P
FBD_CH2_MCH_SB_7_P
FBD_CH2_MCH_SB_6_P
FBD_CH2_MCH_SB_5_P
FBD_CH2_MCH_SB_4_P
FBD_CH2_MCH_SB_3_P
FBD_CH2_MCH_SB_2_P
FBD_CH2_MCH_SB_1_P
FBD_CH2_MCH_SB_0_P

FBD_CH2_MCH_SB_9_N
FBD_CH2_MCH_SB_8_N
FBD_CH2_MCH_SB_7_N
FBD_CH2_MCH_SB_6_N
FBD_CH2_MCH_SB_5_N
FBD_CH2_MCH_SB_4_N
FBD_CH2_MCH_SB_3_N
FBD_CH2_MCH_SB_2_N
FBD_CH2_MCH_SB_1_N
FBD_CH2_MCH_SB_0_N

34
34
34
34
34
34
34
34
34
34

34
34
34
34
34
34
34
34
34
34

1

2

3

33
33
33
33
33
33
33
33
33
33
33
33
33
33

33
33
33
33
33
33
33
33
33
33
33
33
33
33

46,47
46,47

FBD_CH1_MCH_NB_13_P
FBD_CH1_MCH_NB_12_P
FBD_CH1_MCH_NB_11_P
FBD_CH1_MCH_NB_10_P
FBD_CH1_MCH_NB_9_P
FBD_CH1_MCH_NB_8_P
FBD_CH1_MCH_NB_7_P
FBD_CH1_MCH_NB_6_P
FBD_CH1_MCH_NB_5_P
FBD_CH1_MCH_NB_4_P
FBD_CH1_MCH_NB_3_P
FBD_CH1_MCH_NB_2_P
FBD_CH1_MCH_NB_1_P
FBD_CH1_MCH_NB_0_P

FBD_CH1_MCH_NB_13_N
FBD_CH1_MCH_NB_12_N
FBD_CH1_MCH_NB_11_N
FBD_CH1_MCH_NB_10_N
FBD_CH1_MCH_NB_9_N
FBD_CH1_MCH_NB_8_N
FBD_CH1_MCH_NB_7_N
FBD_CH1_MCH_NB_6_N
FBD_CH1_MCH_NB_5_N
FBD_CH1_MCH_NB_4_N
FBD_CH1_MCH_NB_3_N
FBD_CH1_MCH_NB_2_N
FBD_CH1_MCH_NB_1_N
FBD_CH1_MCH_NB_0_N

CK_167M_BRANCH0_P
CK_167M_BRANCH0_N

K31

FBD1NBIP_13

M32

FBD1NBIP_12

G38

FBD1NBIP_11

H36

FBD1NBIP_10

F36

FBD1NBIP_9

J35

FBD1NBIP_8

K34

FBD1NBIP_7

L33

FBD1NBIP_6

L30

FBD1NBIP_5

M29

FBD1NBIP_4

N28

FBD1NBIP_3

L27

FBD1NBIP_2

M26

FBD1NBIP_1

P27

FBD1NBIP_0

K32

FBD1NBIN_13

N32

FBD1NBIN_12

H38

FBD1NBIN_11

H37

FBD1NBIN_10

F37

FBD1NBIN_9

K35

FBD1NBIN_8

L34

FBD1NBIN_7

M33

FBD1NBIN_6

L31

FBD1NBIN_5

M30

FBD1NBIN_4

N29

FBD1NBIN_3

L28

FBD1NBIN_2

M27

FBD1NBIN_1

P28

FBD1NBIN_0

R38

FBD01CLKP

T38

FBD01CLKN

Chan 1

FBD1SBOP_9
FBD1SBOP_8
FBD1SBOP_7
FBD1SBOP_6
FBD1SBOP_5
FBD1SBOP_4
FBD1SBOP_3
FBD1SBOP_2
FBD1SBOP_1
FBD1SBOP_0

FBD1SBON_9
FBD1SBON_8
FBD1SBON_7
FBD1SBON_6
FBD1SBON_5
FBD1SBON_4
FBD1SBON_3
FBD1SBON_2
FBD1SBON_1
FBD1SBON_0

SPD0SMBCLK

SPD0SMBDATA

N38
R33
P34
R36
P37
N34
M35
K38
L36
J36

N37
R32
P33
R35
P36
N35
M36
L38
L37
J37

H13
G13

FBD_CH1_MCH_SB_9_P
FBD_CH1_MCH_SB_8_P
FBD_CH1_MCH_SB_7_P
FBD_CH1_MCH_SB_6_P
FBD_CH1_MCH_SB_5_P
FBD_CH1_MCH_SB_4_P
FBD_CH1_MCH_SB_3_P
FBD_CH1_MCH_SB_2_P
FBD_CH1_MCH_SB_1_P
FBD_CH1_MCH_SB_0_P

FBD_CH1_MCH_SB_9_N
FBD_CH1_MCH_SB_8_N
FBD_CH1_MCH_SB_7_N
FBD_CH1_MCH_SB_6_N
FBD_CH1_MCH_SB_5_N
FBD_CH1_MCH_SB_4_N
FBD_CH1_MCH_SB_3_N
FBD_CH1_MCH_SB_2_N
FBD_CH1_MCH_SB_1_N
FBD_CH1_MCH_SB_0_N

I2C_FBD_CH0_SCL
I2C_FBD_CH0_SDA

33
33
33
33
33
33
33
33
33
33

33
33
33
33
33
33
33
33
33
33

MCH SM BUS 1 CH 0)

32
32

FBD_CH3_MCH_NB_13_P

35

FBD_CH3_MCH_NB_12_P

35

FBD_CH3_MCH_NB_11_P

35

FBD_CH3_MCH_NB_10_P

35

FBD_CH3_MCH_NB_9_P

35

FBD_CH3_MCH_NB_8_P

35

FBD_CH3_MCH_NB_7_P

35

FBD_CH3_MCH_NB_6_P

35

FBD_CH3_MCH_NB_5_P

35

FBD_CH3_MCH_NB_4_P

35

FBD_CH3_MCH_NB_3_P

35

FBD_CH3_MCH_NB_2_P

35

FBD_CH3_MCH_NB_1_P

35

FBD_CH3_MCH_NB_0_P

35

FBD_CH3_MCH_NB_13_N

35

FBD_CH3_MCH_NB_12_N

35

FBD_CH3_MCH_NB_11_N

35

FBD_CH3_MCH_NB_10_N

35

FBD_CH3_MCH_NB_9_N

35

FBD_CH3_MCH_NB_8_N

35

FBD_CH3_MCH_NB_7_N

35

FBD_CH3_MCH_NB_6_N

35

FBD_CH3_MCH_NB_5_N

35

FBD_CH3_MCH_NB_4_N

35

FBD_CH3_MCH_NB_3_N

35

FBD_CH3_MCH_NB_2_N

35

FBD_CH3_MCH_NB_1_N

35

FBD_CH3_MCH_NB_0_N

35

46,47
46,47

CK_167M_BRANCH1_P
CK_167M_BRANCH1_N

D20

FBD3NBIP_13

C21

FBD3NBIP_12

D25

FBD3NBIP_11

E24

FBD3NBIP_10

F23

FBD3NBIP_9

A24

FBD3NBIP_8

D23

FBD3NBIP_7

B22

FBD3NBIP_6

D19

FBD3NBIP_5

A19

FBD3NBIP_4

B18

FBD3NBIP_3

C17

FBD3NBIP_2

F18

FBD3NBIP_1

G20

FBD3NBIP_0

C20

FBD3NBIN_13

B21

FBD3NBIN_12

D26

FBD3NBIN_11

E25

FBD3NBIN_10

F24

FBD3NBIN_9

B24

FBD3NBIN_8

C23

FBD3NBIN_7

A22

FBD3NBIN_6

E19

FBD3NBIN_5

B19

FBD3NBIN_4

C18

FBD3NBIN_3

D17

FBD3NBIN_2

E18

FBD3NBIN_1

F20

FBD3NBIN_0

D28

FBD23CLKP

E28

FBD23CLKN

Chan 3

FBD3SBOP_9
FBD3SBOP_8
FBD3SBOP_7
FBD3SBOP_6
FBD3SBOP_5
FBD3SBOP_4
FBD3SBOP_3
FBD3SBOP_2
FBD3SBOP_1
FBD3SBOP_0

FBD3SBON_9
FBD3SBON_8
FBD3SBON_7
FBD3SBON_6
FBD3SBON_5
FBD3SBON_4
FBD3SBON_3
FBD3SBON_2
FBD3SBON_1
FBD3SBON_0

SPD2SMBCLK

SPD2SMBDATA

H22
K19
H18
G19
J21
G23
J24
H25
G26
D22

H21
K18
J18
H19
J20
G22
J23
H24
G25
E22

F15
E15

FBD_CH3_MCH_SB_9_P
FBD_CH3_MCH_SB_8_P
FBD_CH3_MCH_SB_7_P
FBD_CH3_MCH_SB_6_P
FBD_CH3_MCH_SB_5_P
FBD_CH3_MCH_SB_4_P
FBD_CH3_MCH_SB_3_P
FBD_CH3_MCH_SB_2_P
FBD_CH3_MCH_SB_1_P
FBD_CH3_MCH_SB_0_P

FBD_CH3_MCH_SB_9_N
FBD_CH3_MCH_SB_8_N
FBD_CH3_MCH_SB_7_N
FBD_CH3_MCH_SB_6_N
FBD_CH3_MCH_SB_5_N
FBD_CH3_MCH_SB_4_N
FBD_CH3_MCH_SB_3_N
FBD_CH3_MCH_SB_2_N
FBD_CH3_MCH_SB_1_N
FBD_CH3_MCH_SB_0_N

I2C_FBD_CH2_SCL
I2C_FBD_CH2_SDA

35
35
35
35
35
35
35
35
35
35

35
35
35
35
35
35
35
35
35
35

MCH SM BUS 3 CH 2)

34
34

3

4

28
28

MOD_MCH_FBD_BRANCH0_VCCA
MOD_MCH_FBD_BRANCH0_VSSA

ROOM=MCH_I2C_PU

T35

FBD01VCCA

T34

FBD01VSSA

SUB*_UX211

P23_DT9261_jp

GREENCREEK REV 3.1

HETERO 1 OF 11

SPD1SMBCLK

SPD1SMBDATA

FBDICOMPBIAS

FBDRESIN

FBDBGBIASEXT

J16
K15

F35
E36
E37

I2C_FBD_CH1_SCL
I2C_FBD_CH1_SDA

33
33

MCH SM BUS 2 CH 1)

MOD_MCH_FBD_ICOMP_BIAS
MOD_MCH_FBD_RESIN
MOD_MCH_FBD_BGBIAS_EXT

28
28
28

MCH FBD interface

28
28

MOD_MCH_FBD_BRANCH1_VCCA
MOD_MCH_FBD_BRANCH1_VSSA

E27
F27

FBD23VCCA
FBD23VSSA

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

GREENCREEK REV 3.1

HETERO 2 OF 11

SPD3SMBCLK

SPD3SMBDATA

H15
H16

TITLE

DWG NO.

DATE

I2C_FBD_CH3_SCL
I2C_FBD_CH3_SDA

MCH SM BUS 4 CH 3)

MODULE:
DESC:
REV: OF

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

HX601

SHEET

35
35

CPUS,FSB,NB,XDP0,XDP1

SEC

REV.

A00

MCH

211

4

C

9/7/2007 23 OF 136

DBA

A B C

ECAD: MCH: Ensure accessable test point pads on TESTHI (top or bot)

+3.3V

NP

D

NP

1

2

3

EXP_MCH_0_NB_3_P

50

EXP_MCH_0_NB_2_P

50

EXP_MCH_0_NB_1_P

50

EXP_MCH_0_NB_0_P

50

EXP_MCH_0_NB_3_N

50

EXP_MCH_0_NB_2_N

50

EXP_MCH_0_NB_1_N

50

EXP_MCH_0_NB_0_N

50

EXP_MCH_2_NB_3_P

50

EXP_MCH_2_NB_2_P

50

EXP_MCH_2_NB_1_P

50

EXP_MCH_2_NB_0_P

50

EXP_MCH_2_NB_3_N

50

EXP_MCH_2_NB_2_N

50

EXP_MCH_2_NB_1_N

50

EXP_MCH_2_NB_0_N

50

EXP_MCH_3_NB_3_P

70

EXP_MCH_3_NB_2_P

70

EXP_MCH_3_NB_1_P

70

EXP_MCH_3_NB_0_P

70

EXP_MCH_3_NB_3_N

70

EXP_MCH_3_NB_2_N

70

EXP_MCH_3_NB_1_N

70

EXP_MCH_3_NB_0_N

70

EXP_MCH_4_NB_3_P

72

EXP_MCH_4_NB_2_P

72

EXP_MCH_4_NB_1_P

72

EXP_MCH_4_NB_0_P

72

EXP_MCH_4_NB_3_N

72

EXP_MCH_4_NB_2_N

72

EXP_MCH_4_NB_1_N

72

EXP_MCH_4_NB_0_N

72

EXP_MCH_5_NB_3_P

72

EXP_MCH_5_NB_2_P

72

EXP_MCH_5_NB_1_P

72

EXP_MCH_5_NB_0_P

72

EXP_MCH_5_NB_3_N

72

EXP_MCH_5_NB_2_N

72

EXP_MCH_5_NB_1_N

72

EXP_MCH_5_NB_0_N

72

EXP_MCH_6_NB_3_P

71

EXP_MCH_6_NB_2_P

71

EXP_MCH_6_NB_1_P

71

EXP_MCH_6_NB_0_P

71

EXP_MCH_6_NB_3_N

71

EXP_MCH_6_NB_2_N

71

EXP_MCH_6_NB_1_N

71

EXP_MCH_6_NB_0_N

71

EXP_MCH_7_NB_3_P

71

EXP_MCH_7_NB_2_P

71

EXP_MCH_7_NB_1_P

71

EXP_MCH_7_NB_0_P

71

EXP_MCH_7_NB_3_N

71

EXP_MCH_7_NB_2_N

71

EXP_MCH_7_NB_1_N

71

EXP_MCH_7_NB_0_N

71

AA5
AB8

Y4
Y10
AA6
AB7

Y3

Y9

T1

P3

N4

T5

U1

R3

P4

R5

U9

W7

V5

V2
U10

W8

V6

W2

K10
D10
G11
F12
L10
E10
F11
E12

G7

F8

C9
H10

H7

G8

B9
G10

J8

F6

E4

C6

K8

F5

E3

C5

K4

H3

D1

F3

L4

H4

E1

F2

PE0RP_3
PE0RP_2
PE0RP_1
PE0RP_0
PE0RN_3
PE0RN_2
PE0RN_1
PE0RN_0

PE2RP_3
PE2RP_2
PE2RP_1
PE2RP_0
PE2RN_3
PE2RN_2
PE2RN_1
PE2RN_0

PE3RP_3
PE3RP_2
PE3RP_1
PE3RP_0
PE3RN_3
PE3RN_2
PE3RN_1
PE3RN_0

PE4RP_3
PE4RP_2
PE4RP_1
PE4RP_0
PE4RN_3
PE4RN_2
PE4RN_1
PE4RN_0

PE5RP_3
PE5RP_2
PE5RP_1
PE5RP_0
PE5RN_3
PE5RN_2
PE5RN_1
PE5RN_0

PE6RP_3
PE6RP_2
PE6RP_1
PE6RP_0
PE6RN_3
PE6RN_2
PE6RN_1
PE6RN_0

PE7RP_3
PE7RP_2
PE7RP_1
PE7RP_0
PE7RN_3
PE7RN_2
PE7RN_1
PE7RN_0

U_MCH

PE0TP_3
PE0TP_2
PE0TP_1
PE0TP_0
PE0TN_3
PE0TN_2
PE0TN_1
PE0TN_0

PE2TP_3
PE2TP_2
PE2TP_1
PE2TP_0
PE2TN_3
PE2TN_2
PE2TN_1
PE2TN_0

PE3TP_3
PE3TP_2
PE3TP_1
PE3TP_0
PE3TN_3
PE3TN_2
PE3TN_1
PE3TN_0

PE4TP_3
PE4TP_2
PE4TP_1
PE4TP_0
PE4TN_3
PE4TN_2
PE4TN_1
PE4TN_0

PE5TP_3
PE5TP_2
PE5TP_1
PE5TP_0
PE5TN_3
PE5TN_2
PE5TN_1
PE5TN_0

PE6TP_3
PE6TP_2
PE6TP_1
PE6TP_0
PE6TN_3
PE6TN_2
PE6TN_1
PE6TN_0

PE7TP_3
PE7TP_2
PE7TP_1
PE7TP_0
PE7TN_3
PE7TN_2
PE7TN_1
PE7TN_0

AA8
AB4
AA3
Y7
AA9
AB5
AA2
Y6

R2
N1
U4
T8
T2
P1
T4
T7

V8
U6
W5
U3
V9
U7
W4
V3

J11
C11
C12
H12
K11
D11
B12
J12

D7
D8
F9
J9
E7
C8
E9
H9

H6
C3
D5
M9
J6
C2
D4
M8

J5
K7
G2
G5
K5
L7
G1
G4

MOD_MCH_EXP_MCH_0_SB_3_P_C
MOD_MCH_EXP_MCH_0_SB_2_P_C
MOD_MCH_EXP_MCH_0_SB_1_P_C
MOD_MCH_EXP_MCH_0_SB_0_P_C
MOD_MCH_EXP_MCH_0_SB_3_N_C
MOD_MCH_EXP_MCH_0_SB_2_N_C
MOD_MCH_EXP_MCH_0_SB_1_N_C
MOD_MCH_EXP_MCH_0_SB_0_N_C

MOD_MCH_EXP_MCH_2_SB_3_P_C
MOD_MCH_EXP_MCH_2_SB_2_P_C
MOD_MCH_EXP_MCH_2_SB_1_P_C
MOD_MCH_EXP_MCH_2_SB_0_P_C
MOD_MCH_EXP_MCH_2_SB_3_N_C
MOD_MCH_EXP_MCH_2_SB_2_N_C
MOD_MCH_EXP_MCH_2_SB_1_N_C
MOD_MCH_EXP_MCH_2_SB_0_N_C

MOD_MCH_EXP_MCH_3_SB_3_P_C
MOD_MCH_EXP_MCH_3_SB_2_P_C
MOD_MCH_EXP_MCH_3_SB_1_P_C
MOD_MCH_EXP_MCH_3_SB_0_P_C
MOD_MCH_EXP_MCH_3_SB_3_N_C
MOD_MCH_EXP_MCH_3_SB_2_N_C
MOD_MCH_EXP_MCH_3_SB_1_N_C
MOD_MCH_EXP_MCH_3_SB_0_N_C

MOD_MCH_EXP_MCH_4_SB_3_P_C
MOD_MCH_EXP_MCH_4_SB_2_P_C
MOD_MCH_EXP_MCH_4_SB_1_P_C
MOD_MCH_EXP_MCH_4_SB_0_P_C
MOD_MCH_EXP_MCH_4_SB_3_N_C
MOD_MCH_EXP_MCH_4_SB_2_N_C
MOD_MCH_EXP_MCH_4_SB_1_N_C
MOD_MCH_EXP_MCH_4_SB_0_N_C

MOD_MCH_EXP_MCH_5_SB_3_P_C
MOD_MCH_EXP_MCH_5_SB_2_P_C
MOD_MCH_EXP_MCH_5_SB_1_P_C
MOD_MCH_EXP_MCH_5_SB_0_P_C
MOD_MCH_EXP_MCH_5_SB_3_N_C
MOD_MCH_EXP_MCH_5_SB_2_N_C
MOD_MCH_EXP_MCH_5_SB_1_N_C
MOD_MCH_EXP_MCH_5_SB_0_N_C

MOD_MCH_EXP_MCH_6_SB_3_P_C
MOD_MCH_EXP_MCH_6_SB_2_P_C
MOD_MCH_EXP_MCH_6_SB_1_P_C
MOD_MCH_EXP_MCH_6_SB_0_P_C
MOD_MCH_EXP_MCH_6_SB_3_N_C
MOD_MCH_EXP_MCH_6_SB_2_N_C
MOD_MCH_EXP_MCH_6_SB_1_N_C
MOD_MCH_EXP_MCH_6_SB_0_N_C

MOD_MCH_EXP_MCH_7_SB_3_P_C
MOD_MCH_EXP_MCH_7_SB_2_P_C
MOD_MCH_EXP_MCH_7_SB_1_P_C
MOD_MCH_EXP_MCH_7_SB_0_P_C
MOD_MCH_EXP_MCH_7_SB_3_N_C
MOD_MCH_EXP_MCH_7_SB_2_N_C
MOD_MCH_EXP_MCH_7_SB_1_N_C
MOD_MCH_EXP_MCH_7_SB_0_N_C

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

29
29
29
29
29
29
29
29

24,126

SYSTEM_PWRGOOD_MCH

126

52,95,129
52,95,129
52,95,129

NC_MOD_MCH_RSVD_D29
NC_MOD_MCH_RSVD_H1
NC_MOD_MCH_RSVD_J3
NC_MOD_MCH_RSVD_L3
NC_MOD_MCH_RSVD_L6
NC_MOD_MCH_RSVD_M2
NC_MOD_MCH_RSVD_M3
NC_MOD_MCH_RSVD_M5
NC_MOD_MCH_RSVD_M6
NC_MOD_MCH_RSVD_M11
NC_MOD_MCH_RSVD_M12
NC_MOD_MCH_RSVD_N2
NC_MOD_MCH_RSVD_N5
NC_MOD_MCH_RSVD_N7
NC_MOD_MCH_RSVD_N8
NC_MOD_MCH_RSVD_N10
NC_MOD_MCH_RSVD_P6
NC_MOD_MCH_RSVD_P7
NC_MOD_MCH_RSVD_P9
NC_MOD_MCH_RSVD_P10
NC_MOD_MCH_RSVD_R6
NC_MOD_MCH_RSVD_R8
NC_MOD_MCH_RSVD_R9
NC_MOD_MCH_RSVD_T37
NC_MOD_MCH_RSVD_W1
NC_MOD_MCH_RSVD_Y1
NC_MOD_MCH_RSVD_AE8
NC_MOD_MCH_RSVD_AG2
NC_MOD_MCH_RSVD_AG6
NC_MOD_MCH_RSVD_AH7

NC_MOD_MCH_RSVD_AJ1
NC_MOD_MCH_RSVD_AK17
NC_MOD_MCH_RSVD_AK23
NC_MOD_MCH_RSVD_AM7
NC_MOD_MCH_RSVD_AM24
NC_MOD_MCH_RSVD_AM31
NC_MOD_MCH_RSVD_AN23
NC_MOD_MCH_RSVD_AP28
NC_MOD_MCH_RSVD_AP32
NC_MOD_MCH_RSVD_AR15
NC_MOD_MCH_RSVD_AR16
NC_MOD_MCH_RSVD_AR33
NC_MOD_MCH_RSVD_AV27

PLT_RST_MCH_N

MCH_ESB_ERR_2_N
MCH_ESB_ERR_1_N
MCH_ESB_ERR_0_N

H17
G17

D2
A5
E6

D29

H1
J3
L3
L6
M2
M3
M5

M6
M11
M12

N2

N5

N7

N8
N10

P6

P7

P9
P10

R6

R8

R9
T37

W1

Y1
AE8
AG2
AG6
AH7

AJ1

AK17
AK23

AM7

AM24
AM31
AN23
AP28
AP32
AR15
AR16
AR33
AV27

PWRGOOD
RESETI_N

ERR_2_N
ERR_1_N
ERR_0_N

RSVD_D29
RSVD_H1
RSVD_J3
RSVD_L3
RSVD_L6
RSVD_M2
RSVD_M3
RSVD_M5
RSVD_M6
RSVD_M11
RSVD_M12
RSVD_N2
RSVD_N5
RSVD_N7
RSVD_N8
RSVD_N10
RSVD_P6
RSVD_P7
RSVD_P9
RSVD_P10
RSVD_R6
RSVD_R8
RSVD_R9
RSVD_T37
RSVD_W1
RSVD_Y1
RSVD_AE8
RSVD_AG2
RSVD_AG6
RSVD_AH7

RSVD_AJ1
RSVD_AK17
RSVD_AK23
RSVD_AM7
RSVD_AM24
RSVD_AM31
RSVD_AN23
RSVD_AP28
RSVD_AP32
RSVD_AR15
RSVD_AR16
RSVD_AR33
RSVD_AV27

U_MCH

MOD_MCH_I2C_CHIPSET_SCL_R

MOD_MCH_I2C_CHIPSET_SDA_R

MOD_MCH_I2C_ESB2_SEG3_SCL_R
MOD_MCH_I2C_ESB2_SEG3_SDA_R

MOD_MCH_XDP0_TCK1_R
MOD_MCH_XDP0_TDI_MCH
MOD_MCH_XDP0_TDO_MCH
MOD_MCH_XDP0_TMS_R

MOD_MCH_SYSPWR_XDP0_TRST_N

NC_TDIOANODE
NC_TDIOCATHODE

MOD_MCH_XDP1_D_15_N
MOD_MCH_XDP1_D_14_N
MOD_MCH_XDP1_D_13_N
MOD_MCH_XDP1_D_12_N
MOD_MCH_XDP1_D_11_N
MOD_MCH_XDP1_D_10_N
MOD_MCH_XDP1_D_9_N
MOD_MCH_XDP1_D_8_N
MOD_MCH_XDP1_D_7_N
MOD_MCH_XDP1_D_6_N
MOD_MCH_XDP1_D_5_N
MOD_MCH_XDP1_D_4_N
MOD_MCH_XDP1_D_3_N
MOD_MCH_XDP1_D_2_N
MOD_MCH_XDP1_D_1_N
MOD_MCH_XDP1_D_0_N

MOD_MCH_XDP1_DSTBP_N
MOD_MCH_XDP1_DSTBN_N

MOD_MCH_XDP1_RDY_N

MOD_MCH_XDP1_ODTCRES
MOD_MCH_XDP1_SLWCRES
MOD_MCH_XDP1_COMCRES

MOD_MCH_TESTHI_AC36

TCK
TDI
TDO
TMS

K14
J14

K13
L12

A6
B7
B6
A7
A8

A4
B4

E16
D16
A15
C16
A16
A14
B15
D15
B14
B13
E14
A12
D13
A10
B10
A11

C14
C13

A17

G14
J15
F14

AC36

W10
W11
Y12
AA11

SM BUS 0
Slave

SM BUS 6
HP CTRL

Intel confirmed, leave MCH TDIODE floatingDT_ID#1915

See table on PP25 regarding AC36 pull-up

CFGSMBCLK

CFGSMBDATA

GPIOSMBCLK

GPIOSMBDATA

TRST_N

TDIOANODE

TDIOCATHODE

XDPD_15_N
XDPD_14_N
XDPD_13_N
XDPD_12_N
XDPD_11_N
XDPD_10_N

XDPD_9_N
XDPD_8_N
XDPD_7_N
XDPD_6_N
XDPD_5_N
XDPD_4_N
XDPD_3_N
XDPD_2_N
XDPD_1_N
XDPD_0_N

XDPDSTBP_N
XDPDSTBN_N

XDPRDY_N

XDPODTCRES
XDPSLWCRES
XDPCOMCRES

TESTHI_AC36

PEWIDTH_3_W10
PEWIDTH_2_W11
PEWIDTH_1_Y12

PEWIDTH_0_AA11

MOD_MCH_PEWIDTH_3
MOD_MCH_PEWIDTH_2

PEWIDTH_1

PEWIDTH_0

R4271

X

30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30

30
30

30

30
30
30

R4273

1 2

4.7K-5%

NP

13,17,21

X

R4272

X

1 2

24
21,24
21
24
24

21,24

21

PEWIDTH[3:0] Port0(ESI) Port2 Port3 Port4 Port5 Port6 Port7
0000 x4 x4 x4 x4 x4 x4 x4
0001 x4 x4 x4 x4 x4 |-- x8 --|
0010 x4 x4 x4 |-- x8 --| x4 x4
0011 x4 x4 x4 |-- x8 --| |-- x8 --|
0100 x4 x4 x4 |----- x16 ---------|
others Reserved
1000 x4 |-- x8 --| x4 x4 x4 x4
1001 x4 |-- x8 --| x4 x4 |-- x8 --|
1010 x4 |-- x8 --| |-- x8 --| x4 x4
1011 x4 |-- x8 --| |-- x8 --| |-- x8 --|
1100 x4 |-- x8 --| |------ x16 --------|
others Reserved
1111 All port widths determined by link

4.7K-5%

1 2

NP

R4274

4.7K-5%

X

MOD_MCH_XDP0_TMS

From XDP0

MOD_MCH_XDP0_TCK1

PEWIDTH

negotiation.<don't work 10/24/04>

4.7K-5%

1 2

R3603

1 2

R3604

1 2

0-5%

R3605

1 2

0-5%

MOD_MCH_XDP0_TDI_MCH

0-5%

R3606

1 2

0-5%

NP

1 2

NP

1 2

+1.5V

NP

R4747

X

I2C_CHIPSET_SCL

I2C_CHIPSET_SDA

I2C_ESB2_SEG3_SCL

I2C_ESB2_SEG3_SDA

+CPU_VTT

21

R4824

R5760

X

0-5%

R5759

X

0-5%

1K-1%

1 2

R5089

1 2

21

51-5%

R5761

MOD_MCH_XDP0_TCK1_R

1K-1%

R4840

1 2

72

51-5%

MOD_MCH_XDP0_TMS_R

21

R5762

1K-1%

71

21,30,53,63,71,72,91,96

21,30,53,63,71,72,91,96

63,96

63,96

To MCH

51-5%

+3.3V

1

24

24

2

3

4

45
45

28
28

24,126

CK_100M_MCH_P
CK_100M_MCH_N

MOD_MCH_PE_VCCA
MOD_MCH_PE_VSSA

SYSTEM_PWRGOOD_MCH

J2

PECLKP

K2

PECLKN

K1

PEVCCA

L1

PEVSSA

GREENCREEK REV 3.1

HETERO 3 OF 11

ECAD: Note special routing for PEVSSBG

+CPU_VTT

NP

21

NP

330-5%

Q3910

3904

NP

1K-1%

R5442

12

X

NP

Q3909

3904

1

X

R5463

X

3

2

PEICOMPI
PERCOMPO

PEVCCBG
PEVSSBG

1

X

+CPU_VTT

NP

R5460

X

3

2

R12
P12

R11
N11

1 2

51-5%

MOD_MCH_PE_COMP

MOD_MCH_PE_VCCBG

13,17,21

Depop R1006 when R5508 is populated

MOD_MCH_XDP0_TRST_N

28

28

P18_DT9082_jp

0-5%

R5508

21

1K-1%

1 2

R4350

1 2

R4351

5.1K-5%

5.1K-5%

TESTHI_V3REF_G16
TESTHI_V3REF_F17

GREENCREEK REV 3.1

HETERO 6 OF 11

G16
F17

MOD_MCH_TESTHI_V3REF_G16
MOD_MCH_TESTHI_V3REF_F17

1K-1%

R5091

1 2

M2LB_Change_Note:
PEWIDTH_0 connected to lower-left riser
to indicate if Ports 6 and 7 are bifricated. They are never bifricated
with the present risers.
PEWIDTH_1 connected to center (a.k.a. right) riser
to indicate if Ports 4 and 5 are bifricated. They are never bifricated

with the present risers, but would be bifricated in a 4-slot London configuration.

R5090

1 2

R5657

1K-1%

P18_DT9079_jp

MCH & PCI EXPRESS

MOD_MCH_SYSPWR_XDP0_TRST_N

21

24

PROPRIETARY NOTE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

NP

R5464

X

1 2

20K-5%

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

TITLE

DWG NO.

DATE

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

HX601

SHEET

REV.

A00

9/7/2007 24 OF 136

MCH

211

4

C

DBA

A B C

D

1

2

3

4

+3.3V

Thermal Sensor VCC in

+1.5V +1.5V

U_MCH

L16
L17
L18
L19
M16
M17
M18
N17
N19
P16
P18
P20
P22
P24
R15
R17
R19
R21
R23
T16
T18
T20
T22
T24
U15
U17
U19
U21
U23
V16
V18
V20
V22
V24
W15
W17
W19
W21
W23
Y16
Y18
Y20
Y22

Y24
AA15
AA17
AA19
AA21
AA23
AB16
AB18
AB20
AB22
AB24
AC15
AC17
AC19
AC21
AC23
AL17

AA13
AB13
AB14
AC25
AC26
AD26
AE35
AH10

L24

F13

VCC_L16
VCC_L17
VCC_L18
VCC_L19
VCC_M16
VCC_M17
VCC_M18
VCC_N17
VCC_N19
VCC_P16
VCC_P18
VCC_P20
VCC_P22
VCC_P24
VCC_R15
VCC_R17
VCC_R19
VCC_R21
VCC_R23
VCC_T16
VCC_T18
VCC_T20
VCC_T22
VCC_T24
VCC_U15
VCC_U17
VCC_U19
VCC_U21
VCC_U23
VCC_V16
VCC_V18
VCC_V20
VCC_V22
VCC_V24
VCC_W15
VCC_W17
VCC_W19
VCC_W21
VCC_W23
VCC_Y16
VCC_Y18
VCC_Y20
VCC_Y22
VCC_Y24
VCC_AA15
VCC_AA17
VCC_AA19
VCC_AA21
VCC_AA23
VCC_AB16
VCC_AB18
VCC_AB20
VCC_AB22
VCC_AB24
VCC_AC15
VCC_AC17
VCC_AC19
VCC_AC21
VCC_AC23
VCC_AL17

VCCSF_AA13
VCCSF_AB13
VCCSF_AB14
VCCSF_AC25
VCCSF_AC26
VCCSF_AD26
VCCSF_AE35
VCCSF_AH10

VCCSEN_L24

V3REF_F13

VCCFBD_A20
VCCFBD_E20
VCCFBD_E23
VCCFBD_F25
VCCFBD_H20
VCCFBD_H23
VCCFBD_K21
VCCFBD_K22
VCCFBD_K23
VCCFBD_L20
VCCFBD_L21
VCCFBD_L22
VCCFBD_L23
VCCFBD_M20
VCCFBD_M21
VCCFBD_M22
VCCFBD_M23
VCCFBD_M24
VCCFBD_M25
VCCFBD_N20
VCCFBD_N21
VCCFBD_N22
VCCFBD_N23
VCCFBD_N24
VCCFBD_N25
VCCFBD_N26
VCCFBD_P25
VCCFBD_P26
VCCFBD_R25
VCCFBD_T25
VCCFBD_T26
VCCFBD_T27
VCCFBD_U25
VCCFBD_U26
VCCFBD_V25
VCCFBD_V26
VCCFBD_W25
VCCFBD_W26
VCCFBD_Y25

VCCFBD_Y26
VCCFBD_AA25
VCCFBD_AA26
VCCFBD_AA27
VCCFBD_AB25
VCCFBD_AB26

VCCPE_G12
VCCPE_J10

VCCPE_L2

VCCPE_L8
VCCPE_L13
VCCPE_L14
VCCPE_L15
VCCPE_M13
VCCPE_M14
VCCPE_M15

VCCPE_N6
VCCPE_N12
VCCPE_N13
VCCPE_N14
VCCPE_N15
VCCPE_P13
VCCPE_P14

VCCPE_R4
VCCPE_R10
VCCPE_R13
VCCPE_R14
VCCPE_T13
VCCPE_T14

VCCPE_U2

VCCPE_U8
VCCPE_U13
VCCPE_U14
VCCPE_V13
VCCPE_V14

VCCPE_W6
VCCPE_W12
VCCPE_W13
VCCPE_W14
VCCPE_Y13
VCCPE_Y14

GREENCREEK REV 3.1

HETERO 7 OF 11

A20
E20
E23
F25
H20
H23
K21
K22
K23
L20
L21
L22
L23
M20
M21
M22
M23
M24
M25
N20
N21
N22
N23
N24
N25
N26
P25
P26
R25
T25
T26
T27
U25
U26
V25
V26
W25
W26
Y25
Y26
AA25
AA26
AA27
AB25
AB26

G12
J10
L2
L8
L13
L14
L15
M13
M14
M15
N6
N12
N13
N14
N15
P13
P14
R4
R10
R13
R14
T13
T14
U2
U8
U13
U14
V13
V14
W6
W12
W13
W14
Y13
Y14

+CPU_VTT

AC13
AC14
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF18
AF19
AF20
AF21
AG18
AG19
AG20
AG21
AH18
AH19
AH20
AH21
AJ18
AJ19
AJ20
AJ21
AK18
AK19
AK20
AK21
AL18
AL19
AL20
AL21
AM18
AM19
AM20
AM21
AN18
AN19
AN20
AN21
AP18
AP19
AP20
AP21
AR18
AR19
AR20
AR21
AT18
AT19
AT20
AT21
AU18
AU19
AU20
AU21
AV18
AV19
AV20
AV21

VTT_AC13
VTT_AC14
VTT_AD13
VTT_AD14
VTT_AD15
VTT_AD16
VTT_AD17
VTT_AD18
VTT_AD19
VTT_AD20
VTT_AD21
VTT_AD22
VTT_AD23
VTT_AD24
VTT_AD25
VTT_AE13
VTT_AE14
VTT_AE15
VTT_AE16
VTT_AE17
VTT_AE18
VTT_AE19
VTT_AE20
VTT_AE21
VTT_AE22
VTT_AE23
VTT_AE24
VTT_AE25
VTT_AE26
VTT_AF18
VTT_AF19
VTT_AF20
VTT_AF21
VTT_AG18
VTT_AG19
VTT_AG20
VTT_AG21
VTT_AH18
VTT_AH19
VTT_AH20
VTT_AH21
VTT_AJ18
VTT_AJ19
VTT_AJ20
VTT_AJ21
VTT_AK18
VTT_AK19
VTT_AK20
VTT_AK21
VTT_AL18
VTT_AL19
VTT_AL20
VTT_AL21
VTT_AM18
VTT_AM19
VTT_AM20
VTT_AM21
VTT_AN18
VTT_AN19
VTT_AN20
VTT_AN21
VTT_AP18
VTT_AP19
VTT_AP20
VTT_AP21
VTT_AR18
VTT_AR19
VTT_AR20
VTT_AR21
VTT_AT18
VTT_AT19
VTT_AT20
VTT_AT21
VTT_AU18
VTT_AU19
VTT_AU20
VTT_AU21
VTT_AV18
VTT_AV19
VTT_AV20
VTT_AV21

U_MCH

GREENCREEK REV 3.1

HETERO 8 OF 11

VSS_C30
VSS_C32
VSS_C33
VSS_C35
VSS_C38

VSS_D3
VSS_D6

VSS_D9
VSS_D12
VSS_D14
VSS_D18
VSS_D21
VSS_D24
VSS_D27
VSS_D30
VSS_D33
VSS_D36

VSS_E2

VSS_E5

VSS_E8
VSS_E11
VSS_E13
VSS_E17
VSS_E21
VSS_E26
VSS_E29
VSS_E32
VSS_E35

VSS_F1

VSS_F4

VSS_F7
VSS_F10
VSS_F16
VSS_F19
VSS_F21
VSS_F22
VSS_F26
VSS_F28
VSS_F31
VSS_F34
VSS_F38

VSS_G3

VSS_G6

VSS_G9
VSS_G15
VSS_G18
VSS_G21
VSS_G24
VSS_G27
VSS_G30
VSS_G31
VSS_G32
VSS_G33
VSS_G36
VSS_G37

VSS_H2

VSS_H5

VSS_H8
VSS_H11
VSS_H14
VSS_H26
VSS_H27
VSS_H28
VSS_H29
VSS_H30
VSS_H31
VSS_H32
VSS_H35

VSS_J1

VSS_J4

VSS_J7
VSS_J13
VSS_J17
VSS_J19
VSS_J22
VSS_J25
VSS_J26
VSS_J27
VSS_J28
VSS_J29
VSS_J30
VSS_J31
VSS_J34
VSS_J38

VSS_K3

VSS_K6

VSS_K9
VSS_K12
VSS_K16
VSS_K17
VSS_K20
VSS_K24
VSS_K25
VSS_K26
VSS_K27

C30
C32
C33
C35
C38
D3
D6
D9
D12
D14
D18
D21
D24
D27
D30
D33
D36
E2
E5
E8
E11
E13
E17
E21
E26
E29
E32
E35
F1
F4
F7
F10
F16
F19
F21
F22
F26
F28
F31
F34
F38
G3
G6
G9
G15
G18
G21
G24
G27
G30
G31
G32
G33
G36
G37
H2
H5
H8
H11
H14
H26
H27
H28
H29
H30
H31
H32
H35
J1
J4
J7
J13
J17
J19
J22
J25
J26
J27
J28
J29
J30
J31
J34
J38
K3
K6
K9
K12
K16
K17
K20
K24
K25
K26
K27

U_MCH

AM5

AM8
AM11
AM14
AM17
AM23
AM26
AM29
AM32
AM35
AM36

AN1

AN4

AN7
AN10
AN13
AN16
AN22
AN25
AN28
AN31
AN34
AN37
AN38

AP3

AP6

AP9
AP12
AP15
AP24
AP27
AP30
AP33

AR2

AR5

AR8
AR11
AR14
AR17
AR23
AR26
AR29
AR32
AR35
AR36

AT1

AT4

AT7
AT10
AT13
AT15
AT16
AT22
AT25
AT28
AT31
AT34
AT38

AU2

AU6

AU9
AU12
AU13
AU14
AU15
AU24
AU27
AU30
AU33
AU37

AV3

AV5

AV8
AV11
AV14
AV15
AV16
AV17
AV23
AV26
AV29
AV32
AV35
AV36

VSS_AM5
VSS_AM8
VSS_AM11
VSS_AM14
VSS_AM17
VSS_AM23
VSS_AM26
VSS_AM29
VSS_AM32
VSS_AM35
VSS_AM36
VSS_AN1
VSS_AN4
VSS_AN7
VSS_AN10
VSS_AN13
VSS_AN16
VSS_AN22
VSS_AN25
VSS_AN28
VSS_AN31
VSS_AN34
VSS_AN37
VSS_AN38
VSS_AP3
VSS_AP6
VSS_AP9
VSS_AP12
VSS_AP15
VSS_AP24
VSS_AP27
VSS_AP30
VSS_AP33
VSS_AR2
VSS_AR5
VSS_AR8
VSS_AR11
VSS_AR14
VSS_AR17
VSS_AR23
VSS_AR26
VSS_AR29
VSS_AR32
VSS_AR35
VSS_AR36
VSS_AT1
VSS_AT4
VSS_AT7
VSS_AT10
VSS_AT13
VSS_AT15
VSS_AT16
VSS_AT22
VSS_AT25
VSS_AT28
VSS_AT31
VSS_AT34
VSS_AT38
VSS_AU2
VSS_AU6
VSS_AU9
VSS_AU12
VSS_AU13
VSS_AU14
VSS_AU15
VSS_AU24
VSS_AU27
VSS_AU30
VSS_AU33
VSS_AU37
VSS_AV3
VSS_AV5
VSS_AV8
VSS_AV11
VSS_AV14
VSS_AV15
VSS_AV16
VSS_AV17
VSS_AV23
VSS_AV26
VSS_AV29
VSS_AV32
VSS_AV35
VSS_AV36

GREENCREEK REV 3.1

HETERO 9 OF 11

VSS_AD36
VSS_AD37
VSS_AD38

VSS_AE12
VSS_AE27
VSS_AE30
VSS_AE33

VSS_AF10
VSS_AF11
VSS_AF14
VSS_AF17
VSS_AF23
VSS_AF24
VSS_AF26
VSS_AF27
VSS_AF29
VSS_AF32
VSS_AF35
VSS_AF36

VSS_AG13
VSS_AG16
VSS_AG17
VSS_AG22
VSS_AG25
VSS_AG28
VSS_AG31
VSS_AG34
VSS_AG37
VSS_AG38

VSS_AH12
VSS_AH15
VSS_AH24
VSS_AH27
VSS_AH30
VSS_AH33

VSS_AJ11
VSS_AJ14
VSS_AJ17
VSS_AJ23
VSS_AJ26
VSS_AJ29
VSS_AJ32
VSS_AJ35
VSS_AJ36

VSS_AK10
VSS_AK13
VSS_AK16
VSS_AK22
VSS_AK25
VSS_AK28
VSS_AK31
VSS_AK34
VSS_AK37
VSS_AK38

VSS_AL12
VSS_AL15
VSS_AL24
VSS_AL27
VSS_AL30
VSS_AL33

VSS_AH17

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

VSS_AE3
VSS_AE6
VSS_AE9

VSS_AF2
VSS_AF5
VSS_AF8

VSS_AG1
VSS_AG4
VSS_AG7

VSS_AH3
VSS_AH6
VSS_AH9

VSS_AJ2
VSS_AJ5
VSS_AJ8

VSS_AK1
VSS_AK4
VSS_AK7

VSS_AL3
VSS_AL6
VSS_AL9

VSS_AM2

AD36
AD37
AD38
AE3
AE6
AE9
AE12
AE27
AE30
AE33
AF2
AF5
AF8
AF10
AF11
AF14
AF17
AF23
AF24
AF26
AF27
AF29
AF32
AF35
AF36
AG1
AG4
AG7
AG13
AG16
AG17
AG22
AG25
AG28
AG31
AG34
AG37
AG38
AH3
AH6
AH9
AH12
AH15
AH24
AH27
AH30
AH33
AJ2
AJ5
AJ8
AJ11
AJ14
AJ17
AJ23
AJ26
AJ29
AJ32
AJ35
AJ36
AK1
AK4
AK7
AK10
AK13
AK16
AK22
AK25
AK28
AK31
AK34
AK37
AK38
AL3
AL6
AL9
AL12
AL15
AL24
AL27
AL30
AL33
AM2
AH17

Perlim MCH current numbers

(02/01/05-AR#500):

Core = 13.14A
PCIe = 2.02A
FBD = 5.71A
Snoop = 2.15A

Current PDG indicates this should be PU. However, if early
samples are received, AC36 is still cared and requires a PD.
If the parts are not early samples, then this pin is NC'ed
internally to the MCH and it doesn't matter.
M/L/B have this PD with email permission from Intel in
case early samples are received in the future. Barcelona
has this PU. Both are OK.

P19_DT9172_rt_added_AC36_explanation

TESTHI_AC36 use

ProcessorVersion
GC-LE
GC-LE
BNB-LE/A0
BNB-LE/A0
BNB-B0
BNB-B0

GC-B1

BNB-B2 + Don't care (PU/PD)

GC-B2 +

Nocona/DempseyT

Dempsey

Nocona/DempseyT

Dempsey

Nocona/DempseyT

Dempsey

Dempsey, WC/CL

Dempsey, WC/CL

Dempsey, WC/CL

MCH Power & Ground

INC.

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

HX601

DATE

9/7/2007 25 OF 136

AC36
pulled to 1.5V
Must Float
pulled to 1.5V
Must Float
Must Float
pulled to 1.5V
PD to GND

Don't care (PU/PD)

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

ROUND ROCK,TEXAS

REV.

A00

SHEET

1

2

3

MCH

211

4

C

DBA

A B C

U_MCH

D

1

2

3

4

V17
V19
V21
V23
V28
V31
V34
V37

W3

W9
W16
W18
W20
W22
W24
W27
W30
W33
W36
W37

Y2

Y5

Y8
Y11
Y15
Y17
Y19
Y21
Y23
Y29
Y32
Y35
Y38
AA1
AA4
AA7

AA10
AA14
AA16
AA18
AA20
AA22
AA24
AA28
AA29
AA30
AA31
AA34
AA37

AB3
AB6
AB9

AB12
AB15
AB17
AB19
AB21
AB23
AB27
AB28
AB29
AB30
AB33
AB36

AC2
AC5
AC8

AC11
AC16
AC18
AC20
AC22
AC24
AC27
AC28
AC29
AC32
AC35
AC38

AD1
AD4
AD7

AD10
AD27
AD28
AD31
AD34

VSS_V17
VSS_V19
VSS_V21
VSS_V23
VSS_V28
VSS_V31
VSS_V34
VSS_V37
VSS_W3
VSS_W9
VSS_W16
VSS_W18
VSS_W20
VSS_W22
VSS_W24
VSS_W27
VSS_W30
VSS_W33
VSS_W36
VSS_W37
VSS_Y2
VSS_Y5
VSS_Y8
VSS_Y11
VSS_Y15
VSS_Y17
VSS_Y19
VSS_Y21
VSS_Y23
VSS_Y29
VSS_Y32
VSS_Y35
VSS_Y38
VSS_AA1
VSS_AA4
VSS_AA7
VSS_AA10
VSS_AA14
VSS_AA16
VSS_AA18
VSS_AA20
VSS_AA22
VSS_AA24
VSS_AA28
VSS_AA29
VSS_AA30
VSS_AA31
VSS_AA34
VSS_AA37
VSS_AB3
VSS_AB6
VSS_AB9
VSS_AB12
VSS_AB15
VSS_AB17
VSS_AB19
VSS_AB21
VSS_AB23
VSS_AB27
VSS_AB28
VSS_AB29
VSS_AB30
VSS_AB33
VSS_AB36
VSS_AC2
VSS_AC5
VSS_AC8
VSS_AC11
VSS_AC16
VSS_AC18
VSS_AC20
VSS_AC22
VSS_AC24
VSS_AC27
VSS_AC28
VSS_AC29
VSS_AC32
VSS_AC35
VSS_AC38
VSS_AD1
VSS_AD4
VSS_AD7
VSS_AD10
VSS_AD27
VSS_AD28
VSS_AD31
VSS_AD34

VSS_K28
VSS_K29
VSS_K30
VSS_K33
VSS_K36
VSS_K37

VSS_L5
VSS_L11
VSS_L26
VSS_L29
VSS_L32
VSS_L35

VSS_M1

VSS_M4

VSS_M7
VSS_M10
VSS_M19
VSS_M28
VSS_M31
VSS_M34
VSS_M37
VSS_M38

VSS_N3

VSS_N9
VSS_N16
VSS_N18
VSS_N27
VSS_N30
VSS_N31
VSS_N33
VSS_N36

VSS_P2

VSS_P5

VSS_P8
VSS_P11
VSS_P15
VSS_P17
VSS_P19
VSS_P21
VSS_P23
VSS_P29
VSS_P30
VSS_P31
VSS_P32
VSS_P35
VSS_P38

VSS_R1

VSS_R7
VSS_R16
VSS_R18
VSS_R20
VSS_R22
VSS_R24
VSS_R26
VSS_R27
VSS_R28
VSS_R29
VSS_R30
VSS_R31
VSS_R34
VSS_R37

VSS_T3

VSS_T6

VSS_T9
VSS_T10
VSS_T11
VSS_T12
VSS_T15
VSS_T17
VSS_T19
VSS_T21
VSS_T23
VSS_T29
VSS_T30
VSS_T33
VSS_T36

VSS_U5
VSS_U11
VSS_U12
VSS_U16
VSS_U18
VSS_U20
VSS_U22
VSS_U24
VSS_U29
VSS_U32
VSS_U35
VSS_U38

VSS_V1

VSS_V4

VSS_V7
VSS_V10
VSS_V11
VSS_V12
VSS_V15

K28
K29
K30
K33
K36
K37
L5
L11
L26
L29
L32
L35
M1
M4
M7
M10
M19
M28
M31
M34
M37
M38
N3
N9
N16
N18
N27
N30
N31
N33
N36
P2
P5
P8
P11
P15
P17
P19
P21
P23
P29
P30
P31
P32
P35
P38
R1
R7
R16
R18
R20
R22
R24
R26
R27
R28
R29
R30
R31
R34
R37
T3
T6
T9
T10
T11
T12
T15
T17
T19
T21
T23
T29
T30
T33
T36
U5
U11
U12
U16
U18
U20
U22
U24
U29
U32
U35
U38
V1
V4
V7
V10
V11
V12
V15

A3

A9
A13
A18
A21
A23
A25
A28
A31
A34
A36

B2

B3

B5

B8
B11
B16
B17
B20
B23
B37

C1

C4

C7
C10
C15
C19
C22
C24
C26
C27
C29

VSS_A3
VSS_A9
VSS_A13
VSS_A18
VSS_A21
VSS_A23
VSS_A25
VSS_A28
VSS_A31
VSS_A34
VSS_A36
VSS_B2
VSS_B3
VSS_B5
VSS_B8
VSS_B11
VSS_B16
VSS_B17
VSS_B20
VSS_B23
VSS_B37
VSS_C1
VSS_C4
VSS_C7
VSS_C10
VSS_C15
VSS_C19
VSS_C22
VSS_C24
VSS_C26
VSS_C27
VSS_C29

U_MCH

GREENCREEK REV 3.1

HETERO 11 OF 11

NC_MCH_REG_1

VSSSEN_L25

VSSQUIET_L9

L25

L9

MCH_REG

1 2

COMMON NEG

REG07 A NGO
COUPON TEST

NC_MCH_REG_2

TITLE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

1

2

3

MCH

211

4

GREENCREEK REV 3.1

HETERO 10 OF 11

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 26 OF 136

DCBA

+1.5V

A B C

ROOM = MCH

D

+CPU_VTT

1

C2563

1 2

21

C2608

C2617

1 2

21

C2562

1uF 6.3V

C2609

1 2

1uF 6.3V

21

C2616

1uF 6.3V

C2564

1 2

1uF 6.3V

21

C2607

1uF 6.3V

C2618

1 2

1uF 6.3V

21

C2561

1uF 6.3V

C2610

1 2

1uF 6.3V

21

C2615

1uF 6.3V

21

C2559

1uF 6.3V

C2605

1 2

1uF 6.3V

21

C2620

1uF 6.3V

C2560

1 2

1uF 6.3V

21

C2606

1uF 6.3V

C2619

1 2

1uF 6.3V

21

C2604

1uF 6.3V

C2611

1 2

1uF 6.3V

21

C2614

1uF 6.3V

C2603

1 2

1uF 6.3V

21

C2612

1uF 6.3V

C2613

1 2

1uF 6.3V

ROOM = MCH_CAPS_CORE_1UF

1uF 6.3V

1uF 6.3V

1uF 6.3V

21

C2767

1 2

C2768

10uF 6.3V

ROOM = MCH_CAPS_CORE_10UF

10uF 6.3V

+1.5V

D1071

2 1

MBRS130LT3

+3.3V

Room = MCH_CAPS_VTT_1UF

Room = MCH_CAPS_VTT_10UF

21

C2663

C2670

1 2

C2664

1 2

1uF 6.3V

21

C2669

1uF 6.3V

21

C2782

21

C2662

1uF 6.3V

C2671

1 2

1uF 6.3V

1 2

C2781

10uF 6.3V

C2665

1 2

1uF 6.3V

21

C2668

1uF 6.3V

1 2

C2780

10uF 6.3V

C2660

1 2

1uF 6.3V

21

C2673

1uF 6.3V

21

C2779

10uF 6.3V

21

C2661

1uF 6.3V

C2672

1 2

1uF 6.3V

10uF 6.3V

C2666

1 2

1uF 6.3V

21

C2667

1uF 6.3V

1uF 6.3V

1

1uF 6.3V

2

+1.5V

C2635

1 2

21

21

C2634

1uF 6.3V

MCH VCC caps

21

C2638

1uF 6.3V

C2636

1 2

1uF 6.3V

21

21

C2633

1uF 6.3V

C2637

1 2

1uF 6.3V

21

21

C2632

1uF 6.3V

C2631

1 2

1uF 6.3V

21

21

C2640

1uF 6.3V

21

C2639

1 2

1uF 6.3V

1uF 6.3V

MCH FSB VTT caps

+3.3V

C2674

1 2

2

1uF 6.3V

3

C2626

C2622

1 2

C2627

1 2

1uF 6.3V

21

C2621

1uF 6.3V

C2625

1uF 6.3V

1uF 6.3V

C2628

1 2

1uF 6.3V

1 2

C2774

C2623

1uF 6.3V

C2773

10uF 6.3V

MCH FBD caps

1 2

1uF 6.3V

1 2

10uF 6.3V

C2624

1 2

C2771

C2629

1 2

1uF 6.3V

21

C2772

10uF 6.3V

C2630

1uF 6.3V

21

C2770

10uF 6.3V

C2642

1uF 6.3V

1 2

C2769

10uF 6.3V

C2641

1 2

1uF 6.3V

10uF 6.3V

Room = MCH_CAPS_FBD_1UF

1uF 6.3V

Room = MCH_CAPS_FBD_10UF

Intel indicates these can be depoped for BNB.

MCH MISC Decoupling

3

Encourage keeping all caps regardless of BNB or GrnCrk

4

+1.5V

Room = MCH_CAPS_PCIE_1UF

21

C2648

1uF 6.3V

1 2

C2775

10uF 6.3V

C2647

1 2

1uF 6.3V

1uF 6.3V

Room = MCH_CAPS_PCIE_10UF

10uF 6.3V

C2651

1 2

C2645

1 2

21

C2650

1uF 6.3V1uF 6.3V

21

C2644

C2652

1 2

1uF 6.3V

C2646

1 2

1uF 6.3V

21

C2649

1uF 6.3V

21

C2643

1uF 6.3V

21

C2654

1uF 6.3V

1uF 6.3V

C2653

1 2

1uF 6.3V

21

C2776

MCH EXPRESS caps

TODO: Place final decoupling when Intel gets it done.

+1.5V

Room = MCH_CAPS_SF_1UF

21

C2657

1 2

C2777

C2658

1 2

1uF 6.3V

21

C2778

10uF 6.3V

21

C2656

1uF 6.3V

C2659

1uF 6.3V

ROOM = MCH_CAPS_SF_10UF

10uF 6.3V

MCH VCC Snoop Filter Caps

1 2

C2655

1 2

1uF 6.3V

1uF 6.3V

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF
LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST
AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF
THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT
THE PRIOR WRITTEN CONSENT OF DELL INC.

MCH DECOUPLING

TITLE

SCHEM, PLN, SV, PE2950, MLK

DWG NO.

HX601

DATE

9/7/2007 27 OF 136

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

REV.

A00

SHEET

MCH

211

4

C

DBA

1

+1.5V

R4358

1 2

ECAD: ROUTE CORE_VSSA BETWEEN CORE_VCCA AND FSB_VCCA (SPACE 10MIL)

.499-1%

A B C

MOD_MCH_CORE_VCCA_L

PROPAGATION_DELAY=L:S::200

NET_PHYSICAL_TYPE=25MIL

L1760

1 2

4.7uH 80mA

28.9mA

D

ROOM=MCH_VREF_FSB0

R4357

+CPU_VTT

+1.5V

MOD_MCH_CORE_VCCA

PROPAGATION_DELAY=L:S::700

NET_PHYSICAL_TYPE=25MIL

21

21

22

R4841

1 2

PDG 5.7.3.4

R4376

1 2

649-1%

21

R4381

MOD_MCH_FSB_CRES

PROPAGATION_DELAY=L:S::1000

49.9-1%

22

R4383

1 2

49.9-1%

R4392

1 2

680-5%

SUB=NP0

MOD_MCH_FSB0_VREF_R

NET_PHYSICAL_TYPE=50MILS

21

100-1%

NC_TP_MOD_MCH_FSB0_VREF_R

NET_PHYSICAL_TYPE=30MIL

R4335

1 2

0-5%

21

C2676

1uF 6.3V

MOD_MCH_FSB0_VREF

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MILS

ECAD: Route <1.5" trace.

ECAD: Route at 30-50mils

22

1

+1.5V

21

R4359

+1.5V

.499-1%

MOD_MCH_FSB_VCCA_L

PROPAGATION_DELAY=L:S::200

NET_PHYSICAL_TYPE=25MIL

L1761

21

4.7uH 80mA

28.9mA

ROOM=MCH_FILTER_FSB

ECAD: ROUTE EACH FBD VCCA/VSSA AS DIFF PAIR (SPACE 10MIL)

C2755

C2763

1 2

C2754

22uF 6.3V22uF 6.3V

C2762

.1uF

10V-10%

MOD_MCH_CORE_VSSA

NET_PHYSICAL_TYPE=25MIL

21

.1uF

10V-10%

MOD_MCH_FSB_VCCA

PROPAGATION_DELAY=L:S::700

NET_PHYSICAL_TYPE=25MIL

22

22

MCH - FSB/CORE PLL/COMP/VREF CKTS

NP

R4992

X

MOD_MCH_FSB_ODTCRES

PROPAGATION_DELAY=L:S::1000

MOD_MCH_FSB_SLWCRES

PROPAGATION_DELAY=L:S::1000

MOD_MCH_FSB_SLWCTRL

PROPAGATION_DELAY=L:S::1000

Could pull-down MOD_MCH_FSB_SLWCTRL for debug

1K-1% 1K-1%

1 2

TODO: get guidance on max lengths, not in PDG

+1.5V

22

22

22

This one was actually routed to 121 mils, so I bumped it to 130

+CPU_VTT

R4382

1 2

49.9-1%

R4391

R4356

680-5%

SUB=NP0

MOD_MCH_FSB1_VREF_R

NET_PHYSICAL_TYPE=50MILS
PROPAGATION_DELAY=L:S::130

100-1%

1 2

NC_TP_MOD_MCH_FSB1_VREF_R

21

NET_PHYSICAL_TYPE=30MIL

21

C2675

R4334

1 2

0-5%

1uF 6.3V

ROOM=MCH_VREF_FSB1

MOD_MCH_FSB1_VREF

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MILS

ECAD: Route <1.5" trace.

ECAD: Route at 30-50mils

22

2

R4360

1 2

0.402-1%

MOD_MCH_FBD_BRANCH0_VCCA_L

PROPAGATION_DELAY=L:S::200

NET_PHYSICAL_TYPE=25MIL

ROOM=MCH_FILTER_FBD_01

+1.5V

R4361

1 2

0.402-1%

MOD_MCH_FBD_BRANCH1_VCCA_L

PROPAGATION_DELAY=L:S::200

NET_PHYSICAL_TYPE=25MIL

ROOM=MCH_FILTER_FBD_23

L1762

1 2

4.7uH 80mA

60mA

L1763

4.7uH 80mA

60mA

MOD_MCH_FBD_BRANCH0_VCCA

PROPAGATION_DELAY=L:S::1200

10uF 6.3V

1 2

21

10uF 6.3V

1 2

10uF 6.3V

C3353

10uF 6.3V

C3354

21

21

C2756

C2758

21

C2757

21

C2759

.1uF

10V-10%

.1uF

10V-10%

NET_PHYSICAL_TYPE=50MIL

MOD_MCH_FBD_BRANCH0_VSSA

PROPAGATION_DELAY=L:S::1200

NET_PHYSICAL_TYPE=50MIL

MOD_MCH_FBD_BRANCH1_VCCA

PROPAGATION_DELAY=L:S::1200

NET_PHYSICAL_TYPE=50MIL

MOD_MCH_FBD_BRANCH1_VSSA

PROPAGATION_DELAY=L:S::1200

NET_PHYSICAL_TYPE=50MIL

23

23

23

23

R4388

1 2

21

R4349

100-1%

51.1-1%

21

R4389

R4337

1 2

R4390

100-1%

121-1%

100-1%

1 2

MOD_MCH_FBD_RESIN

PROPAGATION_DELAY=L:S::1000

MOD_MCH_FBD_BGBIAS_EXT

PROPAGATION_DELAY=L:S::1000

MOD_MCH_FBD_ICOMP_BIAS

PROPAGATION_DELAY=L:S::1000

ROOM = MCH

2

23

23

23

3

Derating for L = 90

+1.5V

21

R4362

.499-1%

ECAD: ROUTE PE VCCA/VSSA AS DIFF PAIR (SPACE 10MIL)

MOD_MCH_PE_VCCA_L

PROPAGATION_DELAY=L:S::200

NET_PHYSICAL_TYPE=25MIL

ROOM = MCH_FILTER_PCIE

L1764

4.7uH 80mA

30.9mA

MCH - FBD PLL/COMP CKTS

2.5V 0.6mA Reference Voltage off 3.3V supply

TODO: Evaulate putting in a lower mA Inductor (trio)

ECAD: ROUTE PE VCCA/VSSA AS DIFF PAIR (SPACE 10MIL)

ROOM = MCH

+1.5V

21

21

C2760

22uF 6.3V

21

C2761

.1uF

10V-10%

MOD_MCH_PE_VCCA

PROPAGATION_DELAY=L:S::700

NET_PHYSICAL_TYPE=50MIL

MOD_MCH_PE_VSSA

PROPAGATION_DELAY=L:S::700

NET_PHYSICAL_TYPE=50MIL

24

24

R4323

24.9-1%

1 2

MOD_MCH_PE_COMP

PROPAGATION_DELAY=L:S::1000

24

NET_PHYSICAL_TYPE=20MIL

P2V5_VREF

56

21

C3321

22uF 6.3V

+3.3V

R5121

1 2

1

TL431ACD

6

7

160-5%

(2.5V)

D1085

2

3

R5128

1 2

.499-1%

8

dell p/n = 1X621

NET_PHYSICAL_TYPE=15MIL

MOD_MCH_PE_VCCBG_L

L1811

4.7uH 80mA

0.6mA

21

C3209

1 2

C3210

22uF 6.3V

(0.6mA)

outputs 2.5V

MOD_MCH_PE_VCCBG

PROPAGATION_DELAY=L:S::1200

NET_PHYSICAL_TYPE=15MIL

21

.1uF

16V-10%

ECAD:PROPAGATION_DELAY=L:S::700
ECAD: NET_PHYSICAL_TYPE=15mil

MOD_MCH_PE_VSSBG0

24

3

4

MCH - PE PLL/COMP/BAND GAP CKTS

Filter implemented per 0.7 PDG pag275-280, 10.4.2.1

MCH - Analog/ BandGap/ Comp Ckts

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

ROOM = MCH_VREF_PCIE

M2LB_Change_Note:

ROOM = MCH

Removed constraint on MOD_MCH_FSB0_VREF_R.

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 28 OF 136

DCBA

MCH

211

4

A B C

C885

MOD_MCH_EXP_MCH_0_SB_0_N_C

24

21

EXP_MCH_0_SB_0_N

49

D

1

2

MCH TO ESB2

ROOM = LAI_MCH

MOD_MCH_EXP_MCH_0_SB_0_P_C

24

MOD_MCH_EXP_MCH_0_SB_1_N_C

24

MOD_MCH_EXP_MCH_0_SB_1_P_C

24

MOD_MCH_EXP_MCH_0_SB_2_N_C

24

MOD_MCH_EXP_MCH_0_SB_2_P_C

24

MOD_MCH_EXP_MCH_0_SB_3_N_C

24

MOD_MCH_EXP_MCH_0_SB_3_P_C

24

MOD_MCH_EXP_MCH_2_SB_0_N_C

24

MOD_MCH_EXP_MCH_2_SB_0_P_C

24

MOD_MCH_EXP_MCH_2_SB_1_N_C

24

MOD_MCH_EXP_MCH_2_SB_1_P_C

24

MOD_MCH_EXP_MCH_2_SB_2_N_C

24

MOD_MCH_EXP_MCH_2_SB_2_P_C

24

MOD_MCH_EXP_MCH_2_SB_3_N_C

24

MOD_MCH_EXP_MCH_2_SB_3_P_C

24

.1uF

10V-10%

C883

21

.1uF

10V-10%

C887

21

.1uF

10V-10%

C889

21

.1uF

10V-10%

C877

.1uF

10V-10%

C875

.1uF

10V-10%

C879

.1uF

10V-10%

C881

.1uF

10V-10%

C884

21

EXP_MCH_0_SB_0_P

49

.1uF

10V-10%

EXP_MCH_0_SB_1_N

49

C886

21

.1uF

10V-10%

EXP_MCH_0_SB_1_P

EXP_MCH_0_SB_2_N

49

1

49

C888

21

EXP_MCH_0_SB_2_P

49

.1uF

10V-10%

EXP_MCH_0_SB_3_N

49

C890

21

EXP_MCH_0_SB_3_P

49

.1uF

10V-10%

ROMB X4

21

C876

21

.1uF

21

10V-10%

C878

21

.1uF

21

10V-10%

C880

21

.1uF

21

10V-10%

C882

21

.1uF

10V-10%

EXP_MCH_2_SB_0_N

EXP_MCH_2_SB_0_P

EXP_MCH_2_SB_1_N

EXP_MCH_2_SB_1_P

EXP_MCH_2_SB_2_N

EXP_MCH_2_SB_2_P

EXP_MCH_2_SB_3_N

EXP_MCH_2_SB_3_P

49

49

49

49

49

49

49

49

ROOM = PCIE_ROMB_X4

MOD_MCH_EXP_MCH_3_SB_0_N_C

24

MOD_MCH_EXP_MCH_3_SB_0_P_C

24

MOD_MCH_EXP_MCH_3_SB_1_N_C

24

MOD_MCH_EXP_MCH_3_SB_1_P_C

24

MOD_MCH_EXP_MCH_3_SB_2_N_C

24

MOD_MCH_EXP_MCH_3_SB_2_P_C

24

MOD_MCH_EXP_MCH_3_SB_3_N_C

24

MOD_MCH_EXP_MCH_3_SB_3_P_C

24

C869

21

.1uF

10V-10%

C867

21

.1uF

10V-10%

C871

21

.1uF

10V-10%

C873

21

.1uF

10V-10%

C868

21

.1uF

10V-10%

C870

21

.1uF

10V-10%

C872

21

.1uF

10V-10%

C874

21

.1uF

10V-10%

EXP_MCH_3_SB_0_N

EXP_MCH_3_SB_0_P

EXP_MCH_3_SB_1_N

EXP_MCH_3_SB_1_P

EXP_MCH_3_SB_2_N

EXP_MCH_3_SB_2_P

EXP_MCH_3_SB_3_N

EXP_MCH_3_SB_3_P

70

70

70

70

70

70

70

70

2

3

X8 SLOT

ROOM = PCIE_RISER2_X8

MOD_MCH_EXP_MCH_4_SB_0_N_C

24

MOD_MCH_EXP_MCH_4_SB_0_P_C

24

MOD_MCH_EXP_MCH_4_SB_1_N_C

24

MOD_MCH_EXP_MCH_4_SB_1_P_C

24

MOD_MCH_EXP_MCH_4_SB_2_N_C

24

MOD_MCH_EXP_MCH_4_SB_2_P_C

24

MOD_MCH_EXP_MCH_4_SB_3_N_C

24

MOD_MCH_EXP_MCH_4_SB_3_P_C

24

C917

21

.1uF

10V-10%

C915

21

.1uF

10V-10%

C919

21

.1uF

10V-10%

C921

21

.1uF

10V-10%

C916

21

.1uF

10V-10%

C918

21

.1uF

10V-10%

C920

21

.1uF

10V-10%

C922

21

.1uF

10V-10%

EXP_MCH_4_SB_0_N

EXP_MCH_4_SB_0_P

EXP_MCH_4_SB_1_N

EXP_MCH_4_SB_1_P

EXP_MCH_4_SB_2_N

EXP_MCH_4_SB_2_P

EXP_MCH_4_SB_3_N

EXP_MCH_4_SB_3_P

72

72

72

72

72

72

72

72

MOD_MCH_EXP_MCH_5_SB_0_N_C

24

MOD_MCH_EXP_MCH_5_SB_0_P_C

24

MOD_MCH_EXP_MCH_5_SB_1_N_C

24

MOD_MCH_EXP_MCH_5_SB_1_P_C

24

MOD_MCH_EXP_MCH_5_SB_2_N_C

24

MOD_MCH_EXP_MCH_5_SB_2_P_C

24

MOD_MCH_EXP_MCH_5_SB_3_N_C

24

MOD_MCH_EXP_MCH_5_SB_3_P_C

24

C909

21

.1uF

10V-10%

C907

21

.1uF

10V-10%

C911

21

.1uF

10V-10%

C913

21

.1uF

10V-10%

C908

21

.1uF

10V-10%

C910

21

.1uF

10V-10%

C912

21

.1uF

10V-10%

C914

21

.1uF

10V-10%

EXP_MCH_5_SB_0_N

EXP_MCH_5_SB_0_P

EXP_MCH_5_SB_1_N

EXP_MCH_5_SB_1_P

EXP_MCH_5_SB_2_N

EXP_MCH_5_SB_2_P

EXP_MCH_5_SB_3_N

EXP_MCH_5_SB_3_P

72

72

72

72

72

72

72

72

3

4

x8 Slot

ROOM = PCIE_RISER1_X8

C901

MOD_MCH_EXP_MCH_6_SB_0_N_C

24

MOD_MCH_EXP_MCH_6_SB_0_P_C

24

MOD_MCH_EXP_MCH_6_SB_1_N_C

24

MOD_MCH_EXP_MCH_6_SB_1_P_C

24

MOD_MCH_EXP_MCH_6_SB_2_N_C

24

MOD_MCH_EXP_MCH_6_SB_2_P_C

24

MOD_MCH_EXP_MCH_6_SB_3_N_C

24

MOD_MCH_EXP_MCH_6_SB_3_P_C

24

21

.1uF

10V-10%

C899

21

.1uF

10V-10%

C903

21

.1uF

10V-10%

C905

21

.1uF

10V-10%

C900

21

.1uF

10V-10%

C902

21

.1uF

10V-10%

C904

21

.1uF

10V-10%

C906

21

EXP_MCH_6_SB_0_N

EXP_MCH_6_SB_0_P

EXP_MCH_6_SB_1_N

EXP_MCH_6_SB_1_P

EXP_MCH_6_SB_2_N

EXP_MCH_6_SB_2_P

EXP_MCH_6_SB_3_N

EXP_MCH_6_SB_3_P

71

71

71

71

71

71

71

71

.1uF

10V-10%

Only the PCIe caps for the TX side are contained within the Sub-System Mod

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

MCH - PCIE TX CAPS

MOD_MCH_EXP_MCH_7_SB_0_N_C

24

MOD_MCH_EXP_MCH_7_SB_0_P_C

24

MOD_MCH_EXP_MCH_7_SB_1_N_C

24

MOD_MCH_EXP_MCH_7_SB_1_P_C

24

MOD_MCH_EXP_MCH_7_SB_2_N_C

24

MOD_MCH_EXP_MCH_7_SB_2_P_C

24

MOD_MCH_EXP_MCH_7_SB_3_N_C

24

MOD_MCH_EXP_MCH_7_SB_3_P_C

24

M2LB_Change_Note:
Changed ROOM names, boxes, and text.

C893

.1uF

10V-10%

C891

.1uF

10V-10%

C895

.1uF

10V-10%

C897

.1uF

10V-10%

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

1 21

SEC

21

21

21

21

MCH

C892

.1uF

10V-10%

C894

.1uF

10V-10%

C896

.1uF

10V-10%

C898

.1uF

10V-10%

TITLE

DWG NO.

DATE

EXP_MCH_7_SB_0_N

21

EXP_MCH_7_SB_0_P

EXP_MCH_7_SB_1_N

21

EXP_MCH_7_SB_1_P

EXP_MCH_7_SB_2_N

21

EXP_MCH_7_SB_2_P

EXP_MCH_7_SB_3_N

21

EXP_MCH_7_SB_3_P

71

71

71

71

71

71

71

71

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

A00

SHEET

9/7/2007 29 OF 136

4

DCBA

A B C

D

1

2

+3.3V

21

R3686

R3687

1 2

330-5%330-5%

MOD_MCH_XDP1_CLKREF

21

C1981

Note: .0052W > 1/32W. Need 1/16W resistor

21,24,53,63,71,72,91,96

21,24,53,63,71,72,91,96

.1uF

16V-10%

126

SYSTEM_PWRGOOD_XDP1

I2C_CHIPSET_SDA

I2C_CHIPSET_SCL

30

NP0

NP0

NP0

R5279

1 2

0-5%

R5278

0-5%

R5277

1 2

0-5%

MOD_MCH_SYSTEM_PWRGOOD

21

24
24

24
24

24
24

24
24

24
24

45
30

MOD_MCH_XDP1_DSTBP_N
MOD_MCH_XDP1_RDY_N

MOD_MCH_XDP1_D_0_N
MOD_MCH_XDP1_D_1_N

MOD_MCH_XDP1_D_2_N
MOD_MCH_XDP1_D_3_N

NC_MOD_MCH_XDP1_21
NC_MOD_MCH_XDP1_23 NC_MOD_MCH_XDP1_24

MOD_MCH_XDP1_D_4_N
MOD_MCH_XDP1_D_5_N

MOD_MCH_XDP1_D_6_N
MOD_MCH_XDP1_D_7_N

NC_ESB_TP0

CK_33M_XDP1
MOD_MCH_XDP1_CLKREF

MOD_MCH_XDP1_SDA_R
MOD_MCH_XDP1_SCL_R
NC_MOD_MCH_XDP1_55
NC_MOD_MCH_XDP1_57

J_XDP1_MCH

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

+1.5V

MOD_MCH_XDP1_DSTBN_N

NC_MOD_MCH_XDP1_6

MOD_MCH_XDP1_D_8_N
MOD_MCH_XDP1_D_9_N

MOD_MCH_XDP1_D_10_N
MOD_MCH_XDP1_D_11_N

NC_MOD_MCH_XDP1_22

MOD_MCH_XDP1_D_12_N
MOD_MCH_XDP1_D_13_N

MOD_MCH_XDP1_D_14_N
MOD_MCH_XDP1_D_15_N

CK_333M_XDP1_P
CK_333M_XDP1_N

NC_MOD_MCH_XDP1_52
NC_MOD_MCH_XDP1_54
NC_MOD_MCH_XDP1_56
NC_MOD_MCH_XDP1_58

549-1%

R4336

1 2

R4384

1 2

24

24
24

24
24

ROOM = MCH

24
24

24
24

46,47

XDP_BCLK

46,47

MOD_MCH_PLT_RST_XDP1_N PLT_RST_XDP1_N

RESET_BTN_N

ECAD: Place series resistor at split from the rest of the trace

R5276

1 2

21,54,58,95,128

P46 is an input and should be tied to the system reset

P48 is an output from the XDP to reset the systemb

0-5%

NP0

MOD_MCH_XDP1_COMCRES

NET_PHYSICAL_TYPE=15MIL
PROPAGATION_DELAY=L:S::1200

49.9-1%

MOD_MCH_XDP1_ODTCRES

MOD_MCH_XDP1_SLWCRES

NET_PHYSICAL_TYPE=15MIL
PROPAGATION_DELAY=L:S::1200

NET_PHYSICAL_TYPE=15MIL
PROPAGATION_DELAY=L:S::1200

126

24

1

24

24

2

2X30 MICRO-SOCKET CONN

NP0

ROOM = XDP1

3

3

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

MCH - XDP

TITLE

DWG NO.

DATE

MODULE:
DESC:
REV: OF

CPUS,FSB,NB,XDP0,XDP1

SEC

INC.

ROUND ROCK,TEXAS

SCHEM, PLN, SV, PE2950, MLK

REV.

HX601

SHEET

A00

9/7/2007 30 OF 136

DCBA

MCH

211

4