MSI MS-9154 Schematic 020

A B C

Dell Controlled Print

D

REVISIONS

1

2

3

REV

A00-00

A01-00

A02-00

A03-00

ECO161177

ECO168386

ECO168401

ECO173798

DESCRIPTIONECO DATE

RELEASE FOR P1355 TO J9621 CAPACITOR CHANGE

TABLE OF CONTENTS

Page 1.
Page 2.
Page 3.
Page 4.
Page 5.
Page 6.
Page 7.
Page 8.
Page 9.
Page 10.
Page 11.
Page 12.
Page 13.
Page 14.
Page 15.
Page 16.
Page 17.
Page 18.
Page 19.
Page 20.
Page 21.
Page 22.
Page 23.
Page 24.
Page 25.
Page 26.
Page 27.
Page 28.
Page 29.
Page 30.
Page 31.
Page 32.
Page 33.
Page 34.
Page 35.
Page 36.
Page 37.
Page 38.
Page 39.
Page 40.
Page 41.
Page 42.
Page 43.
Page 44.
Page 45.
Page 46.
Page 47.
Page 48.
Page 49.
Page 50.
Page 51.
Page 52.
Page 53.
Page 54.
Page 55. FWH
Page 56.
Page 57.
Page 58.
Page 59.

BLOCK DIAGRAM
CLOCK DIAGRAM
Clock Synth.
Differential Buffer DB800
System CPLD
Voltage Regulators
VRD
VRD
VRD

---blank--­Processors
Processors
Processors

---blank--­ITP 32 & Level Translation Circuits
MCH, memory
MCH, GTL, Exp, Hub-link
MCH, power
Decoupling Caps
DDR2
DDR2
DDR2, routing diagram
DDR2, VRef
Gigabit Ethernet
Gigabit Ethernet
Gigabit Ethernet
PXH
PXH
PXH
PXH
Connectors
Connectors
ICH5
ICH5
Keyboard, Mouse, COM Ports, I2C MUX/Table
Radeon Video
Radeon Video
Radeon Video
Radeon Video
Super I/O, 373
Battery / Intrusion Detect / RAID Key / VAux Pwrgood
Fans and fan LED's
Parallel Port / ID Button / Rear Cyclops / Speaker
BMC
BMC
BMC
BMC
BMC, Serial Port Muxing
BMC - Serial Port MUXing Diagram
RAC

1.2V Vtt generation
Fan PWM Controllers
MicroVu
VAux reset

USB / Buttons
Spares / Coupons / Hardware
PCI bus p/u's / PCI Debug Slot
Debug Features

06/23/2004RELEASE FOR PRODUCTION

10/21/2004RELEASE Q4/2004 BLOCK

12/17/2004

APPROVED

JIM HUNT

JIM HUNT

1

2

3

4

1U PWA assembly

2U/5U PWA assembly

P# D8266
P# H1754

XLBOM Build Options

1U, Production
2U/5U Production

0
1
21U, Debug

2U/5U Debug

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

3

PWB/Silk Color

Red White
Blue x01

White

x00

Clear White x02
Green Yellow x03

White x03Green

Green White a00

Big Bend, Kobuk, Corvette

PWA: H1754

PWB:

SCHEM:

ASSY DWG:

THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC.,
EXCEPT AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY
OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN
WHOLE OR IN PART AND MUST BE RETURNED TO DELL INC.
UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE
OF THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED
FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE
LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

D1656
D1660
D1657

PROPRIETARY NOTE

UNIPLANAR

aka LINDY PLANAR

DRAWN

Uniplanar Team:

DESIGNED

CHECKED

APPROVED

-Shawn Dube

APPROVED

-Jinsaku Masuyama

APPROVED

-Garnett Thompson

APPROVED

-TJ Thompson

RELEASED

XLBOM Build option table

0 Production Build
9 Prototype Build

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO
ECO

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

INC.

D1660

DATE

12/16/2004 1 OF 60

4

ROUND ROCK,TEXAS

REV.

A03-00

SHEET

DCBA

B D

CA

CLOCK DISTRIBUTION

BLOCK DIAGRAM

12-16-2004_19:50

1

1

2

2

3

3

4 4

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

2 OF 60

DC

A B

B D

V_3P3_CLK

3

21

CA

12-16-2004_19:50

1

+3.3V

1 2

C1093

BLM18BD601SN1

BLM18BD601SN1

0.1uF 16V

L103

L105

R1476

R1420

21

4,35

4,35

21

V_3P3_CLK

3

21

21

1 2

C1094

0.1uF 16V

C1209

C1103

10uF 6.3V

1 2

0.1uF 16V

1 2

C1102

C1101

0.1uF 16V

1 2

0.1uF 16V

1 2

C1100

C1104

0.1uF 16V

1 2

0.1uF 16V

1 2

C1099

1 2

C1098

0.1uF 16V

C1096

0.1uF 16V

1 2

0.1uF 16V

1 2

C1097

0.1uF 16V

ICH_SEG2_SDA

ICH_SEG2_SCL

0-5%

R1421

1 2

0-5%

ICH_SEG2_409_SDA

ICH_SEG2_409_SCL

4.7K

NP*

R1477

4.7K

1 2

NP*

3

ECAD Note:

VCC routing should be from plane, through high-f cap, to pin

3

1

2

3

U1084
300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V
KOA CZB2BFL-301P

3

May need to tune caps during UT

V_3P3_CLK

C757

21

0.1uF 16V

50V-10%

27pF

x03_tj_121503

NP

2 1

C1090

R606

21

2.2-5%

X10

1 2

14.31818MHz

R947

2 1

1M-5%

X

50V-10%

C756

27pF

21

0.1uF 16V

12

C759

C1091

21

+3.3V

1 2

C1105

0.1uF 16V

10uF 6.3V

x00_tj_050503

SUB*_U1084

L129

1 2

ILB_1206

300OHM, 300 mA

5

CK_FSB

5

1 2

C1092

V_3P3_CLK_VDD48

CK_FSA

V_3P3_CLK_VDDA

C758

1 2

0.1uF 16V

PROPAGATION_DELAY=L:S::1000

NET_PHYSICAL_TYPE=50MIL

10uF 6.3V

R1419

21

0-5%

R1002

R1022

1 2

0-5%

4,5,59

12

475-1%

IREF = 2.32mA

x02_sd

21

R46

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MIL

5,59

4.7K

R1008

1 2

CK_VTT_PWRGD_N
CK_PWRDWN_N

21

C1326

X

0.1uF 16V

NP*

4.7K

R1018

1 2

NP*

R1007

x00_tj_051203

R1475

4.7K
1 2

3
3

21

1K-1%

C778

1 2

PART_NUMBER=79015

4.7K

21

C779

PART_NUMBER=79015

CK_XTAL_IN
CK_XTAL_OUT

CK_FSA_R
CK_FSB_R
CK_IREF

ICH_SEG2_409_SDA
ICH_SEG2_409_SCL

C777

1000pF

50V-10%

1000pF

50V-10%

PART_NUMBER=79015

C780

21

1000pF

50V-10%

3
10
16
24
55
34
42
48
36

1000pF

1 2

PART_NUMBER=79015

50V-10%

4

5

51
56
52
35
21

30
28

6
11
17
25
39
33
53
45
54

x00_tj_052003

CK409B

VDD_REF
VDD_PCI_1
VDD_PCI_2
VDD_3V66
VDD_ANLG
VDD_48MHZ
VDD_CPU_1
VDD_CPU_2
VDD_SRC

XTALIN
XTALOUT

FS_A
FS_B
IREF
VTT_PWRGD
PWR_DOWN

SDATA
SCLK

GND_REF
GND_PCI_1
GND_PCI_2
GND_3V66
GND_SRC
GND_48MHZ
GND_IREF
GND_CPU
GND_ANLG

CK409 - TSSOP56

SMBus address = D2h

SUB*_W7296

x00c4_tj_090304

REF0
REF1

PCI_F0
PCI_F1
PCI_F2

PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6

USB
DOT

SRC_P
SRC_N

3V66_0
3V66_1
3V66_2
3V66_3

3V66_4/VCH

CPU_P0
CPU_N0
CPU_P1
CPU_N1
CPU_P2
CPU_N2
CPU_P3
CPU_N3

1
2

7
8
9
12
13
14
15
18
19
20

31
32

38
37

22
23
26
27
29

41
40
44
43
47
46
50
49

CK_14M_ICHS_R
CK_14M_SIO_R

CK_33M_ICHS_R
CK_33M_SIO_R
CK_33M_FWH_R
CK_33M_SLOT3_R
CK_33M_PCI0_DEBUG_R
CK_33M_BMC_R
CK_33M_CPLD_R
CK_33M_DBG_LPC_R
CK_33M_VIDEO_R
CK_33M_RAC_R

CK_48M_USB_ICHS_R
CK_48M_SIO_R

CK_66M_MCH_R
CK_66M_ICH_R
CK_66M_3V66_2
CK_66M_LAI_R

CK_167M_CPU1_P_R
CK_167M_CPU1_N_R
CK_167M_CPU2_P_R
CK_167M_CPU2_N_R
CK_167M_MCH_P_R
CK_167M_MCH_N_R
CK_167M_ITP_P_R
CK_167M_ITP_N_R

CK_100M_DB800_P_R
CK_100M_DB800_N_R

1 2

R1017

21

1K-1%

R1417

1K-1%

R956

1 2

33-5%

R957

1 2

33-5%

R1361

1 2

33-5%

+3.3V

NP*

R593

1K-1%

R964

CK_14M_ICHS

CK_14M_SIO

33

40

33-5%

R955

33-5%

R954

33-5%

R1362

1 2

33-5%

R949

33-5%

R1416

21

21

21

21

21

CK_33M_ICHS

CK_33M_SIO

CK_33M_FWH

CK_33M_SLOT1

CK_33M_PCI0_DEBUG

55

33

40

x00_tj_051503

31

58

2

1K-1%
R1363

33-5%

R959

21

NC_CK_48M_SIO

R962

21

33-5%

R963

21

33-5%

21

CK-409 support
Place close to ICH

21

R1429

1 2

33-5%

21

R1712

49.9-1%

CK_100M_DB800_P
CK_100M_DB800_N

49.9-1%

33-5%

R965

33-5%

R966

33-5%

R967

33-5%

CK_48M_USB_ICHS

R960

33-5%

R961

21

R952

33-5%

21

R968

33-5%

21

R969

33-5%

21

R1036

21

21

21

21

21

49.9-1%

33

4
4

21

R1039

49.9-1%

21

21

21

R1038

49.9-1%

21

R1364

1 2

33-5%

R1366

33-5%

R1367

1 2

33-5%

33-5%

R38

NP*

21

21

21

CK_33M_BMC

CK_33M_CPLD

CK_33M_SMARTVU

CK_33M_VIDEO

CK_33M_RAC

CK_66M_MCH

CK_66M_ICH

CK_167M_CPU1_P

CK_167M_CPU1_N

CK_167M_CPU2_P

CK_167M_CPU2_N

CK_167M_MCH_P

CK_167M_MCH_N

44

5,59

59

36

50

To CPLD and Mictor header

17

33

11

11

11

11

17

17

3

Spread spectrum Controlled through I2C

CK409B / CK409 Operation

FSA

FSB SPEEDFSB

All clk _R nets have a hidden prop-delay max of 500mil

R1473

1 2

4.7K

POP01

R1474

4.7K

POP01

CPU_STOP#

PCI_STOP#

Pop 33ohm, 49.9ohm if CK409B used

NP01

Populate with CK409B (ITP diferential pair)

Differential pair routing guideline:

6 mil traces / 14 mil spacing

Spacing to other traces: 5W

NP01

R950

33-5%

R1034

1 2

R1040

49.9-1%

49.9-1%

CK_167M_ITP_P

CK_167M_ITP_N

15

15

R1037

49.9-1%

R951

21

33-5%

21

NP01

R1035

49.9-1%

21

R1033

49.9-1%

NP01

0

1

0

10

0

11

100 MHz

200 MHz

133 MHz

166 MHz

4 4

ROOM=CLOCK1

Freq. latched on VTT_PWRGD

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

REV.

A03-00

SHEET

3 OF 60

subsys done

Clock CK409B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

A B

DC

B D

CA

12-16-2004_19:50

1

3,35

3,35

ICH_SEG2_SDA

ICH_SEG2_SCL

R1423

0-5%

R1422

1 2

0-5%

4

21

ICH_SEG2_800_SDA

ICH_SEG2_800_SCL

V_3P3_SRC

21

R1479

4.7K

NP*

R1478

1 2

1

4.7K

NP*

4

4

2

3

V_3P3_SRC

4

DB800_OE0

4

DB800_OE4

4

DB800_OE5

4
4,31
4,31

x00_sd_051703

SLOT7_PWRGD
SLOT6_PWRGD

21

R111

NP

R100

X

1 2

21

R112

8.2K-5%

NP

21

R101

1K-1%

X

R113

8.2K-5%
1 2

NP

R103

1K-1%

X

1 2

21

R114

8.2K-5%

NP

21

R105

1K-1%

X

4

R115

8.2K-5%
1 2

NP

R107

1K-1%

X

1 2

V_3P3_SRC

8.2K-5%1K-1%

4

V_3P3_SRC

21

R592

+3.3V

1 2

C1114

R996

R591

8.2K-5%
1 2

0.1uF 16V

x00_tj_051203

21

10K-1%

21

R590

8.2K-5%

L108

BLM18BD601SN1

L107

BLM18BD601SN1

R999

10K-1%

1 2

8.2K-5%

21

21

R998

1 2

NP*

1 2

C1111

21

R997

10K-1%

X

C1327

21

0.1uF 16V

0.1uF 16V

NP

R1480

X

10K-1%

1 2

3,5,59

21

C1210

4.7K

x00_sd_051703

10uF 6.3V

1 2

C1110

CK_100M_DB800_N

3

CK_100M_DB800_P

3

ICH_SEG2_800_SCL

4

ICH_SEG2_800_SDA

4

CK_PWRDWN_N

DB800_OE0

4

DB800_OE4

4

DB800_OE5

4
4,31
4,31

SLOT7_PWRGD
SLOT6_PWRGD

1 2

C1109

0.1uF 16V

SRC_BYPASS/PLL

SRC_PLL_LOW_BW

SRC_STOP_N
SRC_DIV2_N

NC_SRC_LOCK

C1108

0.1uF 16V

1 2

0.1uF 16V

1 2

C1112

0.1uF 16V

1 2

C1113

C784

0.1uF 16V
PART_NUMBER=79015

DB800

5

SRC_IN

4

SRC_IN

23

SCLK

24

SDATA

22

BYPASS/PLL

28

PLL_BW

27

SRC_STOP

1

SRC_DIV2

26

PWRDWN

45

LOCK

6

OE_0

14

OE_1

15

OE_2

7

OE_3

43

OE_4

35

OE_5

36

OE_6

44

OE_7

3

GND_3

10

GND_10

18

GND_18

25

GND_25

32

GND_32

40

OE_INV/GND

47

GNDA

ICS9DB108

SMBus address = DCh

21

1000pF

50V-10%

x00_tj_051203

C786

1000pF

1 2

PART_NUMBER=79015

50V-10%

DIF_0
DIF_0

DIF_1
DIF_1

DIF_2
DIF_2

DIF_3
DIF_3

DIF_4
DIF_4

DIF_5
DIF_5

DIF_6
DIF_6

DIF_7
DIF_7

IREF

VDD_2
VDD_11
VDD_19
VDD_31
VDD_39

VDDA

8
9

12
13

16
17

20
21

30
29

34
33

38
37

42
41

46

2
11
19
31
39

48

Note: If clock ordering changes, BIOS requirements must change

V_3P3_SRC

CK_100M_SATA_P_R
CK_100M_SATA_N_R

CK_100M_MCH_P_R
CK_100M_MCH_N_R

CK_100M_PXH_PLANAR_P_R
CK_100M_PXH_PLANAR_N_R

CK_100M_DOBSON_P_R
CK_100M_DOBSON_N_R

CK_100M_PXH_P_R
CK_100M_PXH_N_R

CK_100M_EXP_LAI_P_R
CK_100M_EXP_LAI_N_R

CK_100M_SLOT1_P_R
CK_100M_SLOT1_N_R

CK_100M_SLOT2_P_R
CK_100M_SLOT2_N_R

R1003

1 2

475-1%

V_3P3_SRC

DB800_VDDA

21

0.1uF 16V

C1202

10uF 6.3V

4

4

x00_tj_050103

SUB*_U1084

1 2

ILB_1206

300OHM, 300 mA

C1107

12

L130

IREF = 2.32mA

+3.3V

0.1uF 16V

12

NP

1 2

33-5%

R977

1 2

33-5%

R980

1 2

33-5%

R975

1 2

33-5%

1 2

33-5%

1 2

33-5%

R1368

33-5%

R1370

33-5%

C1106

R976

R973

R971

X

NP

21

21

R978

1 2

X

33-5%

R979

1 2

33-5%

R981

1 2

33-5%

R974

1 2

33-5%

R972

1 2

33-5%

R970

1 2

33-5%

R1369

33-5%

R1371

21

33-5%

2

CK_100M_SATA_P

CK_100M_SATA_N

CK_100M_MCH_P

CK_100M_MCH_N

CK_100M_PXH_PLANAR_P

CK_100M_PXH_PLANAR_N

CK_100M_DOBSON_P

CK_100M_DOBSON_N

CK_100M_PXH_P

CK_100M_PXH_N

CK_100M_EXP_SPARE_P

CK_100M_EXP_SPARE_N

CK_100M_SLOT7_P

21

CK_100M_SLOT7_N

CK_100M_SLOT6_P

CK_100M_SLOT6_N

33

33

17

17

27

27

31

31

31

31

31

31

31

31

31

31

3

R1051

1 2

49.9-1%

R1052

1 2

R1050

1 2

49.9-1%

49.9-1%

R1049

1 2

R1048

1 2

49.9-1%

49.9-1%

R1047

1 2

R1046

1 2

49.9-1%

49.9-1%

R1045

1 2

R1044

1 2

49.9-1%

49.9-1%

R1043

1 2

R1042

1 2

49.9-1%

49.9-1%

R1041

1 2

21

R1434

49.9-1%

R1433

49.9-1%

21

21

R1432

49.9-1%

49.9-1%

21

R1431

49.9-1%

PROPAGATION_DELAY=L:S::500
NET_PHYSICAL_TYPE=50MIL

U1084
300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V
KOA CZB2BFL-301P

1U Prod 2U/5U Prod 1U Proto 2U/5U Proto

SATAOE0

XXXX

OE1 MCH

X X X X

OE2

Planar PXH

X X X X

OE3

Dobson

X X

4 4

OE4
OE5

PXH
LAI

X X

ROOM=CLOCK2

X X

OE6

Slot1 ***Note--BIOS should disable for 2U

X X

OE7

Slot2

***Note--BIOS should disable for 2U

DB800 Differential buffer

INC.

ROUND ROCK,TEXAS

TITLE

subsys done

A B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

DC

REV.

A03-00

SHEET

4 OF 60

1

2

3

5,59

5,59

5,59

5,59

5,59

5,59

46

SYSTEM_PWRGOOD_PXH_R

5

5

5

5

5

5,59

PCI_RST_RAC_N_R

5

PCI_RST_MCH_N_R

5

PCI_RST_PLANAR_N_R

5

PCI_RST_RISER_N_R

5

PCI_RST_BACKPLANE_N_R

5

SHIFTY_RISER_CLK_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_LATCH_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_DATA_DN_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_BCKPLN_CLK_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_LATCH_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_DATA_DN_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_CLK_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_LATCH_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_DN_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_UP_R

PROPAGATION_DELAY=L:S::2200

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_NIC_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_FETS_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_BACKPLANE_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_RISER_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_CHIPSET_R

PROPAGATION_DELAY=L:S::2000

PROPAGATION_DELAY=L:S::2000

PROPAGATION_DELAY=L:S::2000

PROPAGATION_DELAY=L:S::2000

PROPAGATION_DELAY=L:S::2000

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

5

PROPAGATION_DELAY=L:S::2000

1 2

x03_GT_012604

1 2

33-5%

33-5%

1 2

33-5%

1 2

33-5%

33-5%

R6016

1 2

33-5%

R6017

1 2

33-5%

R1541

R1542

R1543

R1545

R1544

R1546

R6003

R6004

R6002

R6005

33-5%

1 2

33-5%

1K-5%

1 2

33-5%

33-5%

1 2

33-5%

R1381

R1377

21

R1378

R1379

R1380

21

50V-10%

470pF

33-5%

1 2

33-5%

33-5%

1 2

33-5%

33-5%

1 2

33-5%

33-5%

1 2

33-5%

33-5%

1 2

33-5%

R129

21

R1376

R1353

R1375

R1374

21

R1373

50V-10%

470pF

50V-10%

21

C1345

x03_GT_012604

x03b_GT_012204

PCI_RST_PXH_N

PCI_RST_DEBUG_N

21

SHIFTY_RISER_CLK

SHIFTY_RISER_LATCH

21

SHIFTY_RISER_DATA_DN

SHIFTY_BCKPLN_CLK

21

SHIFTY_BCKPLN_LATCH

SHIFTY_BCKPLN_DATA_DN

21

SHIFTY_BMC_CLK

SHIFTY_BMC_LATCH

21

SHIFTY_BMC_DATA_DN

SHIFTY_BMC_DATA_UP

point-to-point, no cap needed

50V-10%

470pF

21 C900

470pF

21 C1341

point-to-point, no cap needed

point-to-point, no cap needed

50V-10%

470pF

21

C1346

50V-10%

470pF

50V-10%

470pF

21

C1347

50V-10%

21 C1342

21

470pF

C1349

27

58,59

50V-10%

470pF

21 C1343

31

31

31

32

32

32

46

46

46

5

21 C1344

PCI_RST_RAC_N

PCI_RST_MCH_N

PCI_RST_SIO_FWH_N

PCI_RST_RISER_N

PCI_RST_BACKPLANE_N

x02_sd

SYSTEM_PWRGOOD_PXH

SYSTEM_PWRGOOD_NIC

SYSTEM_PWRGOOD_FETS

SYSTEM_PWRGOOD_BACKPLANE

SYSTEM_PWRGOOD_RISER

SYSTEM_PWRGOOD_CHIPSET

50

17

x03b_GT_012204

40,55

31

32

PROG-PART SPEC 14967
DISK PROG
BLANK PART

27,28

24,25

24,35,41

32

31

17,33

B D

todo check ich_pme will be driven or floated high in time

x02_tj_092203

+3.3V_AUX

1K-5%

SYSTEM_PWRGOOD_ESM
SYSTEM_PWRGOOD_NIC_R

5

SYSTEM_PWRGOOD_FETS_R

5

SYSTEM_PWRGOOD_BACKPLANE_R

5

SYSTEM_PWRGOOD_RISER_R

5

SYSTEM_PWRGOOD_CHIPSET_R
SYSTEM_PWRGOOD_PXH_R

5

PCI_RST_MCH_N_R

5

PCI_RST_PLANAR_N_R

5

PCI_RST_RISER_N_R

5

PCI_RST_BACKPLANE_N_R

5

PCI_RST_RAC_N_R

5

BACKPLANE_PRES_N
RISER_PRES_N
SHIFTY_RISER_DATA_UP
CK_FSA

3

SHIFTY_RISER_DATA_DN_R
SHIFTY_RISER_CLK_R
SHIFTY_RISER_LATCH_R
CK_FSB

3

BUF_CK_CPLD

5

CK_33M_CPLD
INTRUSION_COVER_VAUX_N

41

CK_32K_VAUX_SYSCPLD

33

SHIFTY_BMC_DATA_UP

5

SHIFTY_BMC_DATA_DN_R

5

CPLD_DDR2_RESET

3.3VAUX_PWRGOOD

41

H2_PROCHOT_3V

15

H1_PROCHOT_3V

15

H2_THERMTRIP_3V
H1_THERMTRIP_3V
H2_IERR_3V
H1_IERR_3V
ITP_DBR_N

15

SHIFTY_BMC_CLK_R

5

SHIFTY_BMC_LATCH_R

5

ICH_THRMTRIP

5

SHIFTY_BCKPLN_CLK_R
SHIFTY_BCKPLN_LATCH_R
SHIFTY_BCKPLN_DATA_DN_R
SHIFTY_BCKPLN_DATA_UP
5V_PWRGOOD
5V_RISER_PWRGOOD

6

RISER_PWRGOOD
DC2DC_CPUVTT_EN
DC2DC_1V5_EN
DC2DC_1V8_EN
DC2DC_3V3_EN
DC2DC_5V_EN

21

0.1uF 16V

C13

1 2

C14

0.1uF 16V

NC_SC_NC18
NC_SC_NC20
NC_SC_NC31
NC_SC_NC33
NC_SC_NC34
NC_SC_NC42
NC_SC_NC44
NC_SC_NC46
NC_SC_NC48
NC_SC_NC66
NC_SC_NC75
NC_SC_NC106
NC_SC_NC107
NC_SC_NC114

0.1uF 16V
C16

21

P3975SYSTEM_CPLD

P3976
1Y852

x00_sd_051903
x00_sd_051903

just for dumbview
just for dumbview

+3.3V_AUX

22uF 6.3V

C742

21

44,46,50

5,59

5,32,46

5,31

31,59

5,59
5,59
5,59

3,59

x03b_sd

5,59

15,46
15,46
15,46
15,46

5,59
5,59
5,59

32,59

6,59

31,59

6,51,59

6,59
6,59
6,59

6,42,59

0.1uF 16V

1 2

C15

1 2

R1382

1uF 6.3V

21

17
16
15
14
13
12
11
10

9
7
6
5

19
21
22
23
24
25
26
28
30
32
35
38

4
3

2
143
140
138
136
134
133
132
131
130
129

39
40
41
43
45
49
50
51
52
53
54
56
57

18
20
31
33
34
42
44
46
48
66

75
106
107
114

29

36

47

62

72

89

90

99
108
123
144

1uF 6.3V

C277

IO_1_1
IO_1_2
IO_1_3
IO_1_4
IO_1_5
IO_1_6
IO_1_11
IO_1_12
IO_1_13
IO_1_14
IO_1_15_GTS1
IO_1_16_GTS0

IO_2_1
IO_2_2
IO_2_3
IO_2_4
IO_2_5
IO_2_6
IO_2_11
IO_2_12
IO_2_13_GCK0
IO_2_14_GCK1
IO_2_15_CDRST
IO_2_16_GCK2

IO_3_1
IO_3_2_GTS3
IO_3_3_GTS2
IO_3_4_GSR
IO_3_5
IO_3_6
IO_3_7
IO_3_11
IO_3_12
IO_3_13
IO_3_14
IO_3_15
IO_3_16

IO_4_1_DGE
IO_4_2
IO_4_3
IO_4_4
IO_4_5
IO_4_6
IO_4_7
IO_4_11
IO_4_12
IO_4_13
IO_4_14
IO_4_15
IO_4_16

NC_18
NC_20
NC_31
NC_33
NC_34
NC_42
NC_44
NC_46
NC_48
NC_66
NC_75
NC_106
NC_107
NC_114

GND_29
GND_36
GND_47
GND_62
GND_72
GND_89
GND_90
GND_99
GND_108
GND_123
GND_144

1uF 6.3V

1 2

C278

21

1uF 6.3V

C279

SYSTEM_CPLD

XC2C128 TQFP144

SUB*_P3975

256 macrocell flavor

1 2

C659

IO_5_1
IO_5_2
IO_5_3
IO_5_4
IO_5_5
IO_5_6

IO_5_7
IO_5_11
IO_5_12
IO_5_13
IO_5_14
IO_5_15
IO_5_16

IO_6_1

IO_6_2

IO_6_3

IO_6_4

IO_6_5

IO_6_6
IO_6_11
IO_6_12
IO_6_13
IO_6_14
IO_6_15
IO_6_16

IO_7_1

IO_7_2

IO_7_3

IO_7_4

IO_7_5

IO_7_6

IO_7_7
IO_7_11
IO_7_12
IO_7_13
IO_7_14
IO_7_15
IO_7_16

IO_8_1

IO_8_2

IO_8_3

IO_8_4

IO_8_5

IO_8_6
IO_8_11
IO_8_12
IO_8_13
IO_8_14
IO_8_15
IO_8_16

TCK
TDI
TDO
TMS

VCC_JTAG

VCC_1
VCC_37
VCC_84

VCCIO1_27
VCCIO1_55
VCCIO1_73
VCCIO1_93

VCCIO2_109
VCCIO2_127
VCCIO2_141

NC_135
NC_137
NC_139
NC_142

94
95
96
97
98
100
101
102
103
104
105
110
111

92
91
88
87
86
85
83
82
81
80
79
78

112
113
115
116
117
118
119
120
121
124
125
126
128

77
76
74
71
70
69
68
64
61
60
59
58

67
63
122
65
8

1
37
84

27
55
73
93

109
127
141

135
137
139
142

CPLD_TCK
CPLD_TDI
CPLD_TD1
CPLD_TMS

NC_SC_NC135
NC_SC_NC137
NC_SC_NC139
NC_SC_NC142

PS1_PWRGOOD

PS2_PWRGOOD
DEBUG_JUMPER_1
DEBUG_JUMPER_0

DEBUG_LED_3

DEBUG_LED_2

DEBUG_LED_1

DEBUG_LED_0

ICH_PWRBTN_N

ICH_PME_N

PFAULT_LATCH_N_R

PFAULT_RESET

RISER_EXP_PME_N

VRD1_THERMTRIP_N

PCI_RST_ICH_N

VCORE_EN_R VCORE_EN
VCORE1_PWRGOOD
VCORE2_PWRGOOD
CPLD_H_FORCEPR

VRD2_THERMTRIP_N

ICH_PWR_ON_REQ

RESET_BTN_N
PS1_ENABLE_N
PS2_ENABLE_N

B_1U_2U5U

LPC_LFRAME_N

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

CPLD_H_VID_PWRGOOD_N

PME_NIC_CPLD_N

H2_CPU_PRES_N
H1_CPU_PRES_N

H2_VTT_EN
H1_VTT_EN

RISER_PCI_PME_N

CK_VTT_PWRGD_N

DC2DC_5V_RISER_EN

H1_BSEL0_3V_N
H1_BSEL1_3V_N
H2_BSEL0_3V_N
H2_BSEL1_3V_N

CPU_VTT_PWRGOOD

1V5_PWRGOOD

1V8_PWRGOOD

3V3_PWRGOOD

CK_PWRDWN_N

5,40,46
5,40
46
5,31,32,40,46

CA

44,46

31,59
31,59
59
59
59
59
59
59
33,41,44,56,59
33
5
5

x03b_sd

31

9,46
33,59

7,59
8,59
5
9,46
33,40,41,44,59
56
31,59
31,59

33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
5,59
28
5,12,46
5,12,46
5,12
5,12
31
3,59

6

15
15
15
15
6,51
6,59
6,59
6,59
3,4,59

33-5%

x02_sd

x03b_sd

+3.3V_AUX

+3.3V_AUX

PFAULT_LATCH_N_R

5

x00_sd_52903 - removed 2 leds

1 2

R1790

1 2

21

R1791

PROPAGATION_DELAY=L:S::2000

PFAULT_RESET_R

PROPAGATION_DELAY=L:S::2500

21

R1865

+3.3V_AUX

1 2

8.2K-5%

8.2K-5%

R1920

0-5%

R1921

0-5%

2

8.2K-5%8.2K-5%

NP*

NP*

R1769

R1770

21

1 2

NP*

21

NP*

GND

TPS72118DBV

7,8,59

NP13

NP02

R6021

0-5%

+3.3V

1 2

33-5%

U64

x02_sd

1 2

ICH_THRMTRIP

5

X04_GT_032904

I2C_SEG2_VAUX_SDA
I2C_SEG2_VAUX_SCL

R1922

51

OUTIN

43

NCEN

R6006

33-5%
R6007

21

33-5%

21

C559

1000pF

PART_NUMBER=79015

SHUNT_1V5_N

NET_PHYSICAL_TYPE=PWR

+1.8V_AUX

0.1uF 16V
C1624

21

PFAULT_LATCH_N

+3.3V_AUX

142U38

1

R575

1 2

100-1%

50V-10%

1 2

2.7K-5%

28

44,45,59
44,45,59

10V-10%

1uF

21

PFAULT_RESET

R92

0.1uF 16V

C1625

21

44,46

5

Q104

3904

1

C1626

+3.3V_AUX

CK_CPLD

3

RC = 0.1 us

F = 2.0MHz

ICH_THRMTRIP_N

3

2

todo....need to check that 3904 has drive strength and gain

x00_tj_042803

5,12,46
5,12,46

5,12
5,12

ROOM=SYSCPLD

144U38

VHC14VHC14

5,59

5,59

H2_CPU_PRES_N
H1_CPU_PRES_N
H2_VTT_EN
H1_VTT_EN

CPLD_H_VID_PWRGOOD_N

CPLD_H_FORCEPR

5

BUF_CK_CPLD

CPLD_DDR2_RESET

33

+3.3V_AUX

7

8

RN87

2

1

12-16-2004_19:50

1

5

todo, consider slew rate limiting

+1.8V

1 2

R1439

1 2

2.7K-5%

R1438

2.7K-5%

R426

1 2

2.7K-5%

301-1%

Q66

3904

1

R583

21

2.7K-5%

Q65

3904

21

1

Q84

3904

1

3

2

3

2

3

2

R1359

301-1%

Q11

3904

1

H_VTT_PWRGOOD

+1.8V

R1

21

3

2

H_FORCEPR_N

DDR2_RESET_N_1

DDR2_RESET_N_2

12

+3.3V_AUX

20,21

20,21

2

11,12

3

5

6

4.7K

21

R1835

4.7K

4.7K

4

3

5,32,46

5,31

BACKPLANE_PRES_N
RISER_PRES_N

x00_sd_052203
x00_tj_052903

R1834

1 2

+3.3V_AUX

J14

1

5,40,46
5,32,40

5,40

4 4

5,31,32,40,46

CPLD_TCK
CPLD_TDO
CPLD_TDI
CPLD_TMS

2
3
4
5
6

SIO

Header

CPLD_TDI CPLD_TD1 CPLD_TD2

CPLD JTAG Chain

Planar ESM Riser Backplane

CPLD_TD3

Gated by ~SPG Gated by ~SPG

Jumper

NP*

CPLD_TD0

CPLD_BYPASS

p/u for TCK at SIO

31,46

CPLD_TD2

1 2

NP*

CPLD_TDO

5,32,40

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

5 OF 60

A B

DC

B D

CA

12-16-2004_19:51

1

2

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_1P8V

+12V

R73

8.2K-5%

1 2

C1805

12

+

1V8_PWRGOOD

1 2

0.1uF 16V

270uF

16V-20%

R132

1 2

+12V

+

2 1

X04_GT_031904

+1.8V

3.01K-1%

C606

270uF

16V-20%

5,59

Enable is driven to required state
from CPLD at all times.

C605

70W VERTICAL
+12V
+1.8V
DDR II, MCH

+1.8V DC2DC

x04_tj_031904

SUB=SUB*_0K260

R290

1 2

422-1%

442-1%

DC2DC_1V8_EN

C588

NP

1 2

R463

1 2

0-5%

R546

0-5%

5,59

R547

0-5%

1 2

NC_DC2DC_1P8V_2

+1.8V

21

1000pF

50V-10%

PART_NUMBER=79015

+12V

DC2DC_1P8V

1

+RS

2

RSVD

3

-RS

4

PWRGD

5

PWRGD_SET

K

7

VSS_0

8

VSS_1

9

OUTEN

10

-SENCE

11

+SENSE

12

12V_IN_0

13

12V_IN_1

14

12V_IN_2

15

VOUT_0

16

VOUT_1

17

VSS_2

18

VOUT_2

19

VSS_3

20

VOUT_3

21

VSS_4

22

VOUT_4

23

VSS_5

24

VOUT_5

MH1

GND_MH1

MH2

GND_MH2

DC/DC CONVERTER

MOD., 24 PIN, 72W, VERTICAL

x00_gt_062603

+1.8V

16V-10%

4.7uF

21

+1.8V

12

C268

C600

+

16V-10%

4.7uF

680uF

6.3V-20%

C601

21

C269

25V-20%

.1uF

21

x00_tj_051203

x02_tj_121503

12

+

680uF

C611

C270

6.3V-20%

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_3P3V

100W HORIZONTAL
+12V
+3.3V
RISER's

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_5V

+12V

100W VERTICAL
+12V
+5V
BACKPLANE

+5V DC2DC

1

DC2DC_5V

+RS

K

-RS
PWRGD
RSVD_1
RSVD_2
VSS_0
VSS_1
OUTEN

-SENCE
+SENSE
12V_IN_0
12V_IN_1
12V_IN_2
VOUT_0
VOUT_1
VSS_2
VOUT_2
VSS_3
VOUT_3
VSS_4
VOUT_4
VSS_5
VOUT_5

GND_MH1
GND_MH2

DC/DC CONVERTER

MOD. 073_20821_03

VCC

16V-10%

4.7uF

VCC

C271

VCC

NP

C604

21

12

+

DC2DC_5V_1U

16V-10%

4.7uF

680uF

6.3V-20%

x00_tj_051203

25V-20%

C607

.1uF

21

12

+

C272

C620

21

680uF

6.3V-20%

2

+12V

R74

8.2K-5%

1 2

todo should this really be NC? -shawn

5,6,59

X04_GT_031904

3V3_PWRGOOD

R133

3.01K-1%

1 2

3P3V_RISER_SENSE

31

x00_sd_051703

Enable is driven to required state
from CPLD at all times.

RISER

+3.3V DC2DC

R1572

1 2

21.5K-1%

+3.3V

5,59

R1580

21

2-1%

R1430

1 2

2-1%

+3.3V

DC2DC_3V3_EN

21

R301

0-5%

NC_DC2DC_3P3V_6

+3.3V

C1501

1 2

1000pF

50V-10%

PART_NUMBER=79015

NP

R1488

10K-1%

21

+12V

DC2DC_3P3V

1

+RS

K

3

-RS

4

PWRGD

5

PWRGD_SET

6

RESERVED

7

VSS_7

8

VSS_8

9

OUTEN

10

-SENSE

11

+SENSE

12

12VIN_12

13

12VIN_13

14

12VIN_14

15

VCC_15

16

VCC_16

17

VSS_17

18

VCC_18

19

VSS_19

20

VCC_20

21

VSS_21

22

VCC_22

23

VSS_23

24

VCC_24

100W-25A DC-DC

MOD.-25 pin, HORIZONTAL

+3.3V

16V-10%

4.7uF

21

C602

16V-10%

4.7uF

21

25V-20%

C603

x00_tj_051203

.1uF

C619

21

X04_GT_031904

5,6,59

X04_GT_031904

SENSE_5V_BACKPLANE_1U

32

SENSE_5V_BACKPLANE_2U5U

32

VCC

1 2

5V_PWRGOOD

R1752

20-1%

R562

0-5%

R75

1 2

Enable is driven to required state
from CPLD at all times.

R134

1.5K-5% 4.75K-1%

1 2

x03b_sd

NP13

R1750

1 2

0-5%

R1751

1 2

20-1%

R273

0-5%

21

511-1%

VCC

1 2

R274

10K-1%

21

x03_sd_sense

21

R275

5,6,42,59

NP*

DC2DC_5V_SENSE_GND

R462

12

0-5%

NC_DC2DC_5V_6

DC2DC_5V_EN

DC2DC_5V_SENSE_GND

6

DC2DC_5V_SENSE

6

C590

NP

DC2DC_5V_SENSE

21

1000pF

6

6

R466

1 2

0-5%

VCC

50V-10%

+12V

1

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

MH1
MH2

SUB=SUB*_G6740

BACKPLANE

1

VCC_1

+12V

U24

+12V

1 2

C1627

12

+

680uF

6.3V-20%

C1568

+

270uF

2 1

16V-20%

X00_GT_052203

0.1uF 16V

VCC

GND

DS1818

2

RESET

3

SUB=SUB*_Y1351

1

3V3_PWRGOOD

5,6,59

+3.3V

4V-20%

820uF

x04b_tj_032404

12

+

1 2

C287

+

4V-20%

820uF

+

1 2

C288

C610

270uF

16V-20%

1 2

C1650

0.1uF 16V

Sub to DS1811R-5 (+5V, 5% part)

DS1818

2

VCC

GND

3

U59

RESET

1

SUB=SUB*_1F826

5V_PWRGOOD

5,6,59

NP

R1848

X

1 2

5,6,42,59

5,6,59

309-1%

+12V

DC2DC_5V_EN

5V_PWRGOOD

NP

R1849

1 2

X

0-5%

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

X

12VIN_10

11

12VIN_11

40W-15A DC-DC

SIP11

X00_GT_061203

3

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_CPU_VTT

Enable is driven to required state
from CPLD at all times.

+12V

NP

R1137

X

1 2

CPU_VTT_PWRGOOD

NP

R1148

X

1 2

ECAD: Place 1 560uF cap by each CPU

+12V

NP

16V-20%

270uF

5,51

x04b_tj_032404

1 2

C138

+

40W VERTICAL
+12V
+1.2V
CPU1, CPU2, MCH

8.2K-5%2.7K-5%

5,51,59

DC2DC_CPUVTT_EN

NP*

R543

1 2

x02_tj_091903

+12V

27.4K-1%

& one by regulator

+CPU_VTT

CPU VTT

R225

NP*

1 2

26.7-1%

X

NP

DC2DC_CPUVTT

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

X

12VIN_10

11

12VIN_11

40W-15A DC-DC

SIP11

+CPU_VTT

.1uF

C349

2 1

+

2 1

10V-10%

+CPU_VTT

16V-10%

C591

560uF

4V-20%

4.7uF

21

C350

C608

+

2 1

560uF

4V-20%

TYPE

40W HORIZONTAL
INPUT +12V
OUTPUT
DESTINATION

+1.5V

MCH, ICH5

ROOM=DC2DC_1P5V

Enable is driven to required state
from CPLD at all times.

+12V

R77

8.2K-5%

1 2

5,59

1V5_PWRGOOD

R136

3.01K-1%

1 2

Substitute from 3.92K to 3.74K to tweak 1.5V to 1.514V

x03_tj_010904
x03b_tj_012604

+12V

16V-20%

270uF

5,59

X04_GT_031904

1 2

+

C1566

DC2DC_1V5_EN

R70

1 2

+12V

3.74K-1%

+1.5V DC2DC

+1.5V

R1489

21

26.7K-1%

SUB*_5N443

Substitute 26.1K, 1%

DC2DC_1P5V

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

12VIN_10

11

12VIN_11

40W-15A DC-DC

MOD.-13 pin, HORIZONTAL

+1.5V

4V-20%

820uF

TYPE
INPUT
OUTPUT
DESTINATION

40W HORIZONTAL
+12V
+5V
MCH, ICH5

ROOM=DC2DC_RISER5V

5V DC2DC

Enable is driven to required state

+5.0V Riser

from CPLD at all times.

U34

+5.0V Riser

+12V

DC2DC_RISER5V

1 2

C1651

X04_GT_031904

5,6

+12V

16V-20%

270uF

+

1 2

C1497

+

10V-10%

.1uF

2 1

16V-10%

C1575

4.7uF

C1585

21

5V_RISER_PWRGOOD

X04_GT_031904

1 2

C1569

R76

1 2

5

R135

1 2

4.75K-1%

DC2DC_5V_RISER_EN

1.5K-5%

R32

+12V

309-1%

1 2

R106

1 2

0-5%

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

12VIN_10

11

12VIN_11

40W-15A DC-DC

MOD.-13 pin, HORIZONTAL

Sub to DS1811R-5 (+5V, 5% part)

0.1uF 16V

VCC

GND

DS1818

2

3

RESET

+5.0V Riser

1

5V_RISER_PWRGOOD

SUB=SUB*_1F826

12

+

C633

680uF

6.3V-20%

10V-10%

.1uF

2 1

16V-10%

C1576

5,6

4.7uF

C1586

21

3

4 4

INC.

ROUND ROCK,TEXAS

TITLE

DC2DC REGULATORS

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

A B

DWG NO.

DATE

DC

D1660

12/16/2004

REV.

A03-00

SHEET

6 OF 60

B D

+12V +12V

SUB=SUB*_J9621

CA

12-16-2004_20:22

SUB=SUB*_J9621

1

7

7

VRD BOM Changes:

X02_TJ_081803

VRD1_PWM3A

VRD1_PWM4A

+3.3V

8.2K-5%
R4502

21

X02_TJ_081803

VCORE1_PWRGOOD

21

R1972

220K

21

R1973

VRD1_VCC

220K

5,7,59

7

X03_GT_011804

X02_TJ_110503

x00c4_tj_090804

SUB*_16155

Q86

3

FT2N7002LT1

1

2

7
7

SUB=SUB*_G7300

5.1-5%

2 1

R260

R1985

1 2

1K-5%

1N914

2-1%

VRD1_PWM1A

DRV1_OD

.22uF 25V

20%

X03_GT_012604

1 3

D9

R240

21

1
2
3
4

C484

21

.22uF 25V

20%

BST
IN
OD
VCC

Phase 1

ROOM = VRD1_PHASE1

1 2

50V-10%

C491

VRD1_DRV1

ADP3418

VRD1_PHASE1B_SENSE

7

x03_sd

1000pF

C852

NP*

21

C466

21

.1uF

25V-20%

8

DRVH

7

SW

6

PGND

5

DRVL

R433

VRD1_UGATE1

VRD1_LGATE1

4.7K

1 2

R451

1 2

4.7K

Q41

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

Q21

4

3

2

1

9

D

G

S

NC

FDS7066SN3

SUB*_T1564

25V-20%

.1uF

21

.22uF 25V

1 2

20%

5

6

7

8

PKG_TYPE=SO8_P9DR_FRCHLD

C488

25V-20%

C1680

.1uF

16V-10%

4.7uF

C1682

21

21

C1681

Q24

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

Q20

4

3

2

1

FDS7066SN3

D

G

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

9

D

S

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

25V-20%

.1uF

C489

21

A03_121704_GT

C1683

21

25V-20%

.1uF

C336

16V-10%

4.7uF

C1684

21

SUB*_16155

12

16V-10%

+

560uF

4V-20%

4.7uF

2 1

C303

X02_TJ_110503

Q88

3

FT2N7002LT1

1

2

R1986

1 2

1K-5%

Phase 2

ROOM = VRD1_PHASE2

VRD1_PHASE2B_SENSE

7

A03_121704_GT

C343

16V-10%

12

+

560uF

4V-20%

4.7uF

2 1

C308

X03_GT_012604

21

C1685

+CPU_VID1

0.6uH, 27Amp

Q36

9

D

G

S

NC

5

6

7

8

20%

16V-10%

.22uF 25V

1 2

C581

4.7uF

2 1

C1686

25V-20%

.1uF

25V-20%

.1uF

2 1

C1687

2 1

C1688

SUB=SUB*_N1453

1N914

.22uF 25V

1 2

20%

1 3

D11

C579

C471

50V-10%

1000pF

21

x03_sd

C853

NP*

4

3

2

1

21

FDS7096N3

L3

2-1%

12

7
7

R244

21

VRD1_PWM2A

DRV1_OD

1

BST

2

IN

3

OD

4

VCC

.1uF

25V-20%

VRD1_PHASE2

DRVH

SW
PGND
DRVL

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

8
7
6
5

Q27

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

C580

21

4.7uF

2 1

C1689

25V-20%

.1uF

25V-20%

.1uF

2 1

C1690

2 1

C1691

1

+CPU_VID1

L2

0.6uH, 27Amp

1 2

SUB=SUB*_N1453

SUB=SUB*_G7300

ADP3418

Q26

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

R163

C281

3-5%

1 2

1 2

.001UF

50V-10%

R152

C276

Q37

4

3

2

3-5%

VRD1_LGATE2

5.1-5%

1 2

2 1

1

R258

.22uF 25V

1 2

.001UF

50V-10%

20%

C482

21

R434

1 2

4.7K

R454

1 2

4.7K

FDS7066SN3

9

D

G

S

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

+12V

+12V

SUB=SUB*_J9621

SUB=SUB*_J9621

2

DRV1_OD_R

7

PWM Control Circuitry

ROOM = VRD1_CTRL

X04_GT_031904

H1_VSSSENSE

12

VRD1_VSSSENSE_MID

3

x00_sd_061603 - providing sensing

0-5%

R1851

21

SUB=SUB*_4053P

SUB=SUB*_75EEC

R304

1 2

1K-5%

DRV1_OD_R

7

X04_GT_031904

C1728

1 2

5,8,59

R1820

1 2

0-5%

VRD1_VSSSENSE

50V-10%

1000pF

1uF

25V-10%

VCORE_EN

C1727

21

R1980

220K

100-5%

X03_GT_011804

21

C1807

1 2

R1846

21

5,7,59

DRV1_OD

x03b_GT_012204

27pF

50V-10%

21

C462

VCORE1_PWRGOOD

.1uF

7

25V-20%

15

7

11

10

12

VRD1_VCC

EN

PWRGD

ILIMIT

DELAY

X02_TJ_110503

VRD1_CTRL

SUB*_16155

+12V

1 2

10-5%

RAMPADJ

R13

VCC

RT

PWM1

Q87

3

FT2N7002LT1

2

28

14
13

27
26

1

7
7

5.1-5%

2 1

R261

1 2

487K-1%

R271

VRD1_PWM1A

VRD1_PWM2A

R1987

1 2

1K-5%

X03_GT_012604

1 3

1N914

1 2

2-1%

VRD1_PWM3A

DRV1_OD

R299

1 2

200K-1%

.22uF 25V

20%

D7

R243

SUB=SUB*_G7300

16V-10%

.47uF

21

7

50V-10%

C490

21

C467

.1uF

25V-20%

VRD1_DRV3

C9

Phase 3

ROOM = VRD1_PHASE3

x03_sd

1000pF

21

1
2
3
4

C854

NP*

21

VRD1_PHASE3B_SENSE

7

BST
IN
OD
VCC

DRVH

SW
PGND
DRVL

ADP3418

.22uF 25V

1 2

20%

C483

X00_GT_062103
Redraw Only- NEED INDEPENDENT CHECK before MODEM!

A03_121704_GT

C338

12

+

16V-10%

4.7uF

2 1

C305

A03_121704_GT

C337

SUB*_16155

12

+

X02_TJ_110503

560uF

4V-20%

Q89

3

FT2N7002LT1

1

2

R1988

1 2

1K-5%

Phase 4

ROOM = VRD1_PHASE4

VRD1_PHASE4B_SENSE

7

X03_GT_012604

.22uF 25V

Q38

4

3

2

1

9

D

G

S

NC

5

6

7

8

.22uF 25V

16V-10%

1 2

20%

4.7uF

C481

2 1

C1692

25V-20%

.1uF

25V-20%

2 1

C1693

.1uF

2 1

C1694

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

8

VRD1_UGATE3

Redraw Only- NEED INDEPENDENT CHECK before MODEM!

Q39

4

3

2

1

9

G

S

FDS7096N3

D

SUB*_N1930

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

C487

21

4.7uF

2 1

C1695

25V-20%

.1uF

25V-20%

2 1

C1696

.1uF

2 1

C1697

+CPU_VID1

L1

1 2

SUB=SUB*_N1453

0.6uH, 27Amp

1N914

D10

31

1 2

7
7

2-1%

VRD1_PWM4A

DRV1_OD

R236

SUB=SUB*_G7300

20%

1

VRD1_UGATE4

BST

2

IN

3

OD

4

VCC

21

7

50V-10%

C578

C465

1 2

.1uF

25V-20%

VRD1_DRV4

ADP3418

1000pF

21

DRVH

PGND
DRVL

C855

x03_sd

SW

NP*

8
7
6
5

VRD1_LGATE4

6
5

VRD1_LGATE3

R457

1 2

4.7K

R437

4.7K

1 2

Q40

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

Q25

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

R171

C282

5.1-5%

12

R257

3-5%

1 2

21

.001UF

50V-10%

.22uF 25V

20%

C8

21

21

R430

4.7K

21

R428

4.7K

Q34

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

4

3

2

1

FDS7066SN3

.22uF 25V

20%

Q33

G

SUB*_T1564

16V-10%

1 2

9

D

S

NC

PKG_TYPE=SO8_P9DR_FRCHLD

4.7uF

C485

5

6

7

8

2 1

C1698

25V-20%

.1uF

25V-20%

.1uF

C1699

12

C1700

12

Q35

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

Q32

4

3

2

1

9

D

G

S

NC

FDS7066SN3

SUB*_T1564

16V-10%

4.7uF

.22uF 25V

20%

C486

21

5

6

7

8

PKG_TYPE=SO8_P9DR_FRCHLD

2 1

C1701

25V-20%

.1uF

25V-20%

.1uF

C1702

12

C1703

12

FDS7066N3 is local. Waiting on library symbol.

16V-10%

560uF

4V-20%

2 1

4.7uF

C302

+CPU_VID1

L4

1 2

21

R153

21

C280

SUB=SUB*_N1453

0.6uH, 27Amp

3-5%

.001UF

50V-10%

2

3

VID Termination

R303

0-5%

75K-1%

1 2

4700pF

7
7
7

1 2

21

75K-1%

R291

21

X04_GT_031904

C710

1 2

29.4K-1%

R306

1 2

0-5%15.8K-1%

R315

0-5%

R85

75K-1%

R286

21

X04_GT_031904

R314

21

0-5%

75K-1%

R284

21

R81

75K-1%

X04_GT_031904

R285

21

NP

21

VRD1_PHASE1B_SENSE

VRD1_PHASE2B_SENSE

VRD1_PHASE3B_SENSE

VRD1_PHASE4B_SENSE

X04_GT_031904

3

D

1

X

2

G

S

7

VRD1_PWM1A

7

7

7

+CPU_VID1

7

X04_GT_032204

1 2

C6007

.01uF 16V

R407

1 2

0-5%

C334

NP

1 2

21

X

X

ALT_LLINE

7,8

2N7002

NP

Q7

.047uF

16V-10%

R484

4.7K

If this FET is populated, you must verify Vgs(th) is met!

X03_GT_011904

R1717

NP

1 2

68K-5%

R1718

NP

68K-5%

GPO_ALT_LLINE_N

33

X

21

X

VRD1_PWM3A

VRD1_PWM4A

U61

7

7

+3.3V_AUX

14

13

VHC14

x00_sd_052903

12

ALT_LLINE

7,8

x04b_tj_032404

Input Filtering

+12V

A03_121704_GT

SUB=SUB*_J9621

C582

12

C725

12

+

560uF

x04b_tj_032404

4V-20%

C2

.1uF

1 2

50V-20%

+

270uF

16V-20%

C3

21

.1uF

SUB=SUB*_4053P

50V-20%

C21

1uF

1 2

25V-10%

C12

1 2

SUB=SUB*_4053P

INTEGRATED VRD 10.1 VOLTAGE

REGULATOR FOR PROC_1

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

1uF

25V-10%

+CPU_VTT

R28

1 2

499-1%

R27

1 2

499-1%

R26

1 2

499-1%

R25

1 2

499-1%

R16

1 2

499-1%

R15

1 2

499-1%

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

SHEET

H1_VID0

H1_VID1

H1_VID2

H1_VID3

H1_VID4

H1_VID5

7 OF 60

7,12

7,12

7,12

7,12

7,12

7,12

REV.

A03-00

CSSUM
CSREF

CSCOMP

300-5%

NP

50V-10%

1000pF

X

PWM2

25

PWM3

24

PWM4

23

SW1

22

SW2

21

SW3

20

SW4

17
16
18

8

FB

X04_GT_031904

NP

C1810

100-5%

21

X

50V-10%

1 2

R1992

VRD1_PWM3A

VRD1_PWM4A

R310

1 2

0-5%

1 2

2700pF

SUB*_1U388

R147

C720

50V-10%

21

THERMISTOR

.047uF 25V

1 2

20%

C714

4 4

+CPU_VID1

1 2

249K-1%

R255

1 2

127K-1%

R233

X04_GT_031904

7,12
7,12
7,12
7,12
7,12
7,12

C300

100pF 50V

R250

2 1

10.7K-1% 680pF 50V

X04_GT_031904

H1_VID0

H1_VID1

H1_VID2

H1_VID3

H1_VID4

H1_VID5

12

X04_GT_031904

100K-1%

21

C708

12

VRD1_VSSSENSE

R289

NP*

X04_GT_032204

NP

(1.33K)

SUB=NP

9

COMP

7

FBRTN

5

VID0

4

VID1

3

VID2

2

VID3

1

VID4

6

VID5

19

GND

C479

12

680pF 50V

R278

1 2

1.3K-1%

R288

1 2

ADP3168

SUB*_H5002

X04_GT_031904

X

NP

R305

X

X04_GT_031904

SUB*_X5828

1 2

R311

X

12

H1_VCCSENSE

1 2

1K-5%

R1821

1 2

VRD1_VCCSENSE

X04_GT_031904

100K-1%

R6019

1 2

0-5% 0-5%

X04_GT_031904

X04_GT_031904

A B

DC

+12V

B D

CA

SUB=SUB*_J9621

1

8

8

VRD BOM Changes:

VRD2_PWM3A

VRD2_PWM4A

+3.3V

8.2K-5%

X02_TJ_081803

R1970

R4503

21

21

220K

X02_TJ_081803

21

R1971

VRD2_VCC

220K

+12V

Q92

3

FT2N7002LT1

2

SUB=SUB*_J9621

A03_121704_GT

C440

C1715

12

+

Phase 2

R1990

1

1 2

1K-5%

X03_GT_012604

VRD2_PHASE2B_SENSE

8

.22uF 25V

20%

1 3

1N914

2-1%

D38

R249

ROOM = VRD2_PHASE2

x03_sd

C857

NP*

21

1 2

50V-10%

C650

C478

.1uF

25V-20%

1000pF

Q52

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

1 2

C652

4.7uF

2 1

C1710

25V-20%

.1uF

25V-20%

.1uF

2 1

C1711

2 1

C1712

Q47

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

21

16V-10%

4.7uF

C651

2 1

C1713

25V-20%

.1uF

25V-20%

.1uF

2 1

C1714

2 1

560uF

4V-20%

16V-10%

4.7uF

2 1

+CPU_VID2

C333

1

.1uF

C1708

A03_121704_GT

2 1

C1709

12

+

C344

+CPU_VID2

0.6uH, 27Amp

16V-10%

560uF

4V-20%

12

4.7uF

L17

2 1

C326

SUB=SUB*_N1453

SUB*_16155

X02_TJ_110503

Q90

SUB*_16155

X02_TJ_110503

8

3

FT2N7002LT1

1

2

R1989

1 2

1K-5%

1N914

2-1%

VRD2_PWM1A

X03_GT_012604

8

1 3

D25

20%

R247

21

1

BST

2

ROOM = VRD2_PHASE1

VRD2_PHASE1B_SENSE

.22uF 25V

1 2

VRD2_DRV1

C648

50V-10%

1000pF

DRVH

Phase 1

x03_sd

C856

NP*

21

C476

21

.1uF

25V-20%

8

VRD2_UGATE1

7

Q70

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

1 2

C624

4.7uF

2 1

C1704

25V-20%

.1uF

25V-20%

.1uF

2 1

C1705

2 1

C1706

Q44

4

3

2

1

9

G

S

FDS7096N3

D

SUB*_N1930

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

1 2

C646

4.7uF

2 1

C1707

25V-20%

.1uF

25V-20%

2 1

L16

x00c4_tj_090804

8

DRV2_OD

8

SUB=SUB*_G7300

5.1-5%

2 1

R264

.22uF 25V

20%

C599

21

IN

3

OD

4

VCC

ADP3418

SW
PGND
DRVL

6
5

VRD2_LGATE1

Q43

4

3

2

1

9

D

G

S

NC

5

6

7

8

FDS7066SN3

SUB*_T1564

Q42

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

NC

5

6

7

8

R172

3-5%

1 2

5.1-5%

2 1

PKG_TYPE=SO8_P9DR_FRCHLD

C283

1 2

R263

.001UF

50V-10%

R487

1 2

4.7K

R494

1 2

4.7K

PKG_TYPE=SO8_P9DR_FRCHLD

21

VRD2_PWM2A

8

DRV2_OD

8

SUB=SUB*_G7300

.22uF 25V

20%

C595

21

VRD2_DRV2

1

BST

2

IN

3

OD

4

VCC

ADP3418

DRVH

SW
PGND
DRVL

8
7
6
5

Q56

9

D

G

S

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

R490

1 2

VRD2_LGATE2

4.7K

R495

1 2

4

3

2

1

FDS7066SN3

4.7K

Q46

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

R179

C285

0.6uH, 27Amp

1 2

3-5%

1 2

1 2

.001UF

SUB=SUB*_N1453

50V-10%

VCORE2_PWRGOOD

5,8,59

+12V

A03_121704_GT

SUB=SUB*_J9621

2

+12V

Q91

2

SUB=SUB*_J9621

3

H2_VSSSENSE

12

R318

1 2

1K-5%

SUB=SUB*_4053P

8

DRV2_OD_R

8

X04_GT_031904

X04_GT_031904

C1729

DRV2_OD_R

X03_GT_011804

R1981

21

DRV2_OD

220K

x03b_GT_012204

21

C1808

27pF

50V-10%

PWM Control Circuitry

ROOM = VRD2_CTRL

0-5%

21

VCORE_EN

C1730

1 2

100-5%

R1847

C473

5,8,59

21

.1uF

VCORE2_PWRGOOD

VRD2_VSSSENSE

1uF

1 2

5,7,59

1 2

50V-10%

1000pF

25V-10%

R1822

PART_NUMBER=79015

25V-20%

SUB*_16155

X02_TJ_110503

8

3

FT2N7002LT1

1

2

R6018

1 2

1K-5%

1N914

2-1%

X03_GT_012604

8

1 3

D12

20%

1 2

R248

Phase 3

ROOM = VRD2_PHASE3

VRD2_PHASE3B_SENSE

.22uF 25V

C647

21

50V-10%

1000pF

C477

.1uF

25V-20%

x03_sd

C858

NP*

21

21

Q62

4

3

2

1

9

G

S

FDS7096N3

SUB*_N1930

D

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

1 2

16V-10%

4.7uF

C594

2 1

C1732

25V-20%

.1uF

25V-20%

.1uF

2 1

C1722

2 1

C1723

Q63

4

3

2

1

9

G

S

FDS7096N3

D

SUB*_N1930

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

C623

21

4.7uF

2 1

C1724

25V-20%

.1uF

25V-20%

.1uF

2 1

C1725

2 1

12

C424

C1726

+

VRD2_DRV3

15

11

10

EN

PWRGD

ILIMIT

VRD2_VCC

8

VRD2_CTRL

VCC

RAMPADJ

RT

28

14
13

27

+12V

10-5%

1 2

R14

487K-1%

VRD2_PWM1A

VRD2_PWM2A

8
8

SUB=SUB*_G7300

5.1-5%

2 1

R267

1 2

R272

R300

1 2

200K-1%

8

VRD2_PWM3A

DRV2_OD

16V-10%

.47uF

1

BST

2

IN

3

OD

4

VCC

ADP3418

.22uF 25V

1 2

20%

C598

C11

21

DRVH

SW
PGND
DRVL

8
7
6
5

VRD2_UGATE3

VRD2_LGATE3

R500

1 2

4.7K

R493

1 2

4.7K

Q67

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

Q45

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

560uF

4V-20%

2 1

4.7uF

C328

+CPU_VID2

L5

1 2

R182

1 2

21

C299

SUB*_16155

X02_TJ_110503

0.6uH, 27Amp

3-5%

.001UF

SUB=SUB*_N1453

50V-10%

Q93

3

FT2N7002LT1

1

2

5.1-5%

R262

R1991

1 2

1K-5%

X03_GT_012604

20%

1N914

D34

31

1 2

8
8

2-1%

VRD2_PWM4A

DRV2_OD

R246

SUB=SUB*_G7300

12

.22uF 25V

20%

C10

21

.22uF 25V

C649

21

1

BST

2

IN

3

OD

4

VCC

Phase 4

ROOM = VRD2_PHASE4

VRD2_PHASE4B_SENSE

8

50V-10%

1000pF

VRD2_DRV4

ADP3418

x03_sd

C859

21

C475

1 2

.1uF

25V-20%

NP*21

DRVH

SW
PGND
DRVL

8
7
6
5

21

R486

VRD2_LGATE4

R485

4.7K

Q50

4

3

2

1

9

G

S

FDS7096N3

D

SUB*_N1930

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

1 2

16V-10%

4.7uF

C617

2 1

C1716

25V-20%

.1uF

25V-20%

.1uF

C1717

12

12

C1718

Q51

4

3

2

1

9

G

S

FDS7096N3

D

SUB*_N1930

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

C618

21

4.7uF

A03_121704_GT

2 1

C1719

25V-20%

.1uF

25V-20%

.1uF

C1720

12

12

C425

C1721

12

+

16V-10%

560uF

4V-20%

2 1

4.7uF

C309

+CPU_VID2

L18

SUB=SUB*_N1453

0.6uH, 27Amp

1 2

VRD2_UGATE4

Q49

4

3

2

1

9

D

G

S

NC

5

6

7

8

21

FDS7066SN3

4.7K

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

Q48

4

3

2

1

9

D

G

S

FDS7066SN3

SUB*_T1564

5

6

7

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

R178

C284

21

3-5%

21

.001UF

50V-10%

3

VID Termination

R316

0-5%

1 2

8
8
8

R350

1 2

21

75K-1%

0-5%

R298

75K-1%

21

C721

50V-10%

SUB*_1U388

1 2

4700pF

C711

R148

21

15.8K-1% 0-5%

THERMISTOR

R349

0-5%

21

75K-1%

R295

R293

21

X04_GT_031904

R87

1 2

29.4K-1%

R332

1 2

21

75K-1%

21

X04_GT_031904

X04_GT_031904

VRD2_PHASE1B_SENSE

VRD2_PHASE2B_SENSE

VRD2_PHASE3B_SENSE

VRD2_PHASE4B_SENSE

R294

R86

75K-1%

X03_GT_011904

+CPU_VTT

R1715

NP

1 2

68K-5%

R1716

NP

68K-5%

7

X

21

X

VRD2_PWM3A

VRD2_PWM4A

8

FDS7066N3 is local. Waiting on library symbol.

R79

1 2

8

Input Filtering

499-1%

H2_VID0

8,12

R78

+12V

C583

1 2

499-1%

SUB=SUB*_J9621

A03_121704_GT

+

270uF

2 1

16V-20%

C820

12

+

560uF

4V-20%

C6

.1uF

1 2

50V-20%

C7

21

.1uF

50V-20%

C23

1uF

1 2

25V-10%

C22

1uF

1 2

25V-10%

R72

1 2

499-1%

R71

1 2

499-1%

H2_VID1

H2_VID2

H2_VID3

8,12

8,12

8,12

R69

SUB*_4053P

SUB*_4053P

1 2

499-1%

H2_VID4

8,12

R68

1 2

H2_VID5

8,12

499-1%

NP

3

X

2

8

8

8

8

VRD2_PWM1A

+CPU_VID2

8

X04_GT_032204

1 2

C6008

.01uF 16V

R418

1 2

0-5%

D

Q8

2N7002

R501

1

G

S

NP

4.7K

21

X

NP

C335

1 2

.047uF

16V-10%

X

ALT_LLINE

21

INTEGRATED VRD 10.1 VOLTAGE

INC.

ROUND ROCK,TEXAS

If this FET is populated, you must verify Vgs(th) is met!

TITLE

REGULATOR FOR PROC_2

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

8 OF 60

SUB*_75EEC

.047uF 25V

20%

12

DELAY

1 2

C715

249K-1%

R256

1 2

1 2

127K-1%

R235

8,12
8,12
8,12
8,12
8,12
8,12

VRD2_VSSSENSE

H2_VID0

H2_VID1

H2_VID2

H2_VID3

H2_VID4

H2_VID5

100K-1%

X04_GT_031904 X04_GT_031904

C301

21

12

100pF 50V

R297

NP*

19

9

7

5
4
3
2
1
6

COMP

FBRTN

VID0
VID1
VID2
VID3
VID4
VID5

GND

ADP3168

NP

680pF 50V

C480

12

X

X04_GT_031904

X04_GT_032204

R252

2 1

C709

12

R279

1 2

PWM1

26

PWM2

25

PWM3

24

PWM4

23

SW1

22

SW2

21

SW3

20

SW4

FB

17
16
18

8

CSSUM
CSREF

CSCOMP

SUB*_H5002
X04_GT_031904

NP

R328

X

1 2

X04_GT_031904

X04_GT_031904

300-5%

VRD2_PWM3A

VRD2_PWM4A

R347

1 2

0-5%

50V-10%

2700pF

4 4

(1.33K)

NP

R1993

1.3K-1%

R296

1 2

100K-1%

X

SUB*_X5828

50V-10%

1000pF

NP

X

21

NP

C1811

100-5%

X

1 2

R1994

+CPU_VID2

12

H2_VCCSENSE

X00_GT_052203

10.7K-1% 680pF 50V

X04_GT_031904

X04_GT_031904

R348

1 2

1K-5%

VRD2_VCCSENSE

X04_GT_031904

R1823

1 2

0-5% 0-5%

1 2

X04_GT_031904

subsys done

A B

DC

B D

CA

12-16-2004_19:51

1

1

+12V

R427

1 2

+3.3V

100-1%

2

100K-5%

T

Locate near hot component in P1 core regulator.

R90

21

10K-1%

0.1uF 16V

1 2

R104

21

C719

0.1uF 16V

1 2

C716

10K-1%

3.32K-1%

R102

21

21

R281

1 2

1K-1%

R183

.22uF 25V

20%

10K-1% 25.5K-1%

1 2

C653

U17

3

V+

V-

LM339

2

12

5

+

4

-

21

21

R140

R254

8.2K-5%

U17

3

V+

V-

LM339

14

12

9

+

8

-

21

R1704

VRD1_THERMTRIP_N

5,46

2

3

100K-5%

T

1 2

10K-1%

1 2

R89

0.1uF 16V

1 2

R141

0.1uF 16V

C718

1 2

C717

10K-1%

3.32K-1%

R149

21

1 2

1K-1%

R192

R280

U17

21

7

6

3

V+

V-

LM339

1

12

+

-

1 2

10K-1% 25.5K-1%

R142

1 2

R253

11

10

+3.3V

8.2K-5%

U17

3

V+

V-

LM339

13

12

+

-

21

R1705

VRD2_THERMTRIP_N

5,46

3

Locate near hot component in P2 core regulator.

VRD Over Temperature Detect Circuit

ROOM=VRD_THERM

4 4

INC.

VRD THERMTRIP

TITLE

ROUND ROCK,TEXAS

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

9 OF 60

DC

A B

B D

CA

12-16-2004_19:51

1

1

2

2

3

3

4 4

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

10 OF 60

DC

A B

B D

CA

12-16-2004_19:51

1

2

3

x00_tj_061403

Alternate PLL filter circuit recommended by Intel until
on-die version validated.

+1.5V

R1583NP

1 2

X

0-5%

2.5V-20%-2STACK

680uF

NP

1 2

+

X

C1588

NP

C1570

X

1 2

4.7uF

C1371

6.3V-10%

NP

X

+CPU_VTT

1 2

0.1uF 16V

R1556

1 2

220

R1558

1 2

220

R1562

1 2

220

R1563

1 2

220

R1506

51

R1493

51

R1497

51

R1499

51

R1501

51

R1503

51

R1494

NP

1 2

51

R1508

1 2

100-5%

x00_GT_010704

x04_tj_031604

V_1P5_H1_VCCPLL

NP

21

X

C1370

0.1uF 16V

ROOM=PROC_1

ROOM=PROC_2

TO DO - MECHANICAL ADD'S NOT CORRECT

Heat Sink Clips

Heat Sink RM

PROC_1

A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13

A9

B8
E13
D12
C11

B7

A6

A7

C9

C8

E10

D9

D19
F17
F14

B19
B21
C21
C20
B22

D20
F12
E11
D10

F20
D23
A17
F11

E21
D22
F21

C6
E19

A23
E22
C23

F27
C27
E27
C26

E5

D7

AE6

D4

Y8

D6

B24
G23

Y4

W5

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

AP0
AP1

ADS
ADSTB0
ADSTB1

REQ0
REQ1
REQ2
REQ3
REQ4

BR0
BR1
BR2
BR3

BNR
BPRI
LOCK
BINIT

RS0
RS1
RS2
RSP
TRDY

HITM
HIT
DEFER

A20M
SMI
FERR/PBE
IGNNE
IERR
MCERR

SLP
STPCLK
RESET
INIT

LINT0
LINT1

BCLK0
BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

DSTBN0
DSTBN1
DSTBN2
DSTBN3

DSTBP0
DSTBP1
DSTBP2
DSTBP3

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

11

15

3
3

H_A3_N
H_A4_N
H_A5_N
H_A6_N
H_A7_N
H_A8_N
H_A9_N
H_A10_N
H_A11_N
H_A12_N
H_A13_N
H_A14_N
H_A15_N
H_A16_N
H_A17_N
H_A18_N
H_A19_N
H_A20_N
H_A21_N
H_A22_N
H_A23_N
H_A24_N
H_A25_N
H_A26_N
H_A27_N
H_A28_N
H_A29_N
H_A30_N
H_A31_N
H_A32_N
H_A33_N
H_A34_N
H_A35_N

H_AP0_N
H_AP1_N

H_ADS_N
H_ADSTB0_N
H_ADSTB1_N

H_REQ0_N
H_REQ1_N
H_REQ2_N
H_REQ3_N
H_REQ4_N

H_BREQ0_N
H_BREQ1_N
H1_BREQ23_N

H_BNR_N
H_BPRI_N
H_LOCK_N
H_BINIT_N

H_RS0_N
H_RS1_N
H_RS2_N
H_RSP_N
H_TRDY_N

H_HITM_N
H_HIT_N
H_DEFER_N

H_A20M_N
H_SMI_N
H_FERR_N
H_IGNNE_N
H1_IERR_N
H_MCERR_N

H_SLP_N
H_STPCLK_N
H_RST_N
H_INIT_N

H_INTR
H_NMI

CK_167M_CPU1_P
CK_167M_CPU1_N

Place @ CPU1 Place @ CPU2

R1559

R1557

1 2

R1560

1 2

R1561

1 2

R1504

1 2

R1505

1 2

21

R1496

21

301-1%

21

R1498

21

R1500

21

R1502

21

R1495

NP

1 2

220

220

220

220

51

51

51

R1554

51

51

51

51

21

21

21

21

21

21

X

H_A20M_N

H_SLP_N

H_NMI

H_INTR

H_SMI_N

H_INIT_N

H_IGNNE_N

H_STPCLK_N

H_FERR_N

H_BREQ0_N

H_BREQ1_N

H1_BREQ23_N

H1_ODTEN

H_PWRGOOD

H1_TESTHI0

H1_TESTHI1

H1_TESTHI2

H1_TESTHI3

H1_TESTHI4

H1_TESTHI5

H1_TESTHI6

H1_TESTHI7

H1_TESTHI8

11,33

11,33

11,33

11,33

11,33

11,33,55

11,33

11,33

11,33

11,17

11,17

11

12

12,33

12

12

12

12

12

12

12

12

12

X

R1492

NP

1 2

X

51

NP*

H1_BOOTSEL

H_RST_N

12

12

11,15,17

11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17

11,17
11,17

11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17
11,17
11,17

11,33
11,33
11,33
11,33

11,15,17

11,33

11,33
11,15,17
11,33,55

11,33

11,33

SUB=SUB*_4M319

10 - 12 mil traces

Heat Sink RM screws

Y26

D0

AA27

D1

Y24

D2

AA25

D3

AD27

D4

Y23

D5

AA24

D6

AB26

D7

AB25

D8

AB23

D9

AA22

D10

AA21

D11

AB20

D12

AB22

D13

AB19

D14

AA19

D15

AE26

D16

AC26

D17

AD25

D18

AE25

D19

AC24

D20

AD24

D21

AE23

D22

AC23

D23

AA18

D24

AC20

D25

AC21

D26

AE22

D27

AE20

D28

AD21

D29

AD19

D30

AB17

D31

AB16

D32

AA16

D33

AC17

D34

AE13

D35

AD18

D36

AB15

D37

AD13

D38

AD14

D39

AD11

D40

AC12

D41

AE10

D42

AC11

D43

AE9

D44

AD10

D45

AD8

D46

AC9

D47

AA13

D48

AA14

D49

AC14

D50

AB12

D51

AB13

D52

AA11

D53

AA10

D54

AB10

D55

AC8

D56

AD7

D57

AE7

D58

AC6

D59

AC5

D60

AA8

D61

Y9

D62

AB6

D63

AC18

DP0

AE19

DP1

AC15

DP2

AE17

DP3

Y21
Y18
Y15
Y12

Y20
Y17
Y14
Y11

AC27
AD22
AE12
AB9
F18
E18

H_D0_N
H_D1_N
H_D2_N
H_D3_N
H_D4_N
H_D5_N
H_D6_N
H_D7_N
H_D8_N

H_D9_N
H_D10_N
H_D11_N
H_D12_N
H_D13_N
H_D14_N
H_D15_N
H_D16_N
H_D17_N
H_D18_N
H_D19_N
H_D20_N
H_D21_N
H_D22_N
H_D23_N
H_D24_N
H_D25_N
H_D26_N
H_D27_N
H_D28_N
H_D29_N
H_D30_N
H_D31_N
H_D32_N
H_D33_N
H_D34_N
H_D35_N
H_D36_N
H_D37_N
H_D38_N
H_D39_N
H_D40_N
H_D41_N
H_D42_N
H_D43_N
H_D44_N
H_D45_N
H_D46_N
H_D47_N
H_D48_N
H_D49_N
H_D50_N
H_D51_N
H_D52_N
H_D53_N
H_D54_N
H_D55_N
H_D56_N
H_D57_N
H_D58_N
H_D59_N
H_D60_N
H_D61_N
H_D62_N
H_D63_N

H_DP0_N
H_DP1_N
H_DP2_N
H_DP3_N

H_DSTBN0_N
H_DSTBN1_N
H_DSTBN2_N
H_DSTBN3_N

H_DSTBP0_N
H_DSTBP1_N
H_DSTBP2_N
H_DSTBP3_N

H_DBI0_N
H_DBI1_N
H_DBI2_N
H_DBI3_N
H_DBSY_N
H_DRDY_N

11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17
11,17

Swizzled

11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17

11,17
11,17

11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17
11,17

11

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17
11,17
11,17

11,33
11,33
11,33
11,33

15

11,15,17

11,33

11,33
11,15,17
11,33,55

11,33

11,33

H_A3_N
H_A4_N
H_A5_N
H_A6_N
H_A7_N
H_A8_N
H_A9_N
H_A10_N
H_A11_N
H_A12_N
H_A13_N
H_A14_N
H_A15_N
H_A16_N
H_A17_N
H_A18_N
H_A19_N
H_A20_N
H_A21_N
H_A22_N
H_A23_N
H_A24_N
H_A25_N
H_A26_N
H_A27_N
H_A28_N
H_A29_N
H_A30_N
H_A31_N
H_A32_N
H_A33_N
H_A34_N
H_A35_N

H_AP0_N
H_AP1_N

H_ADS_N
H_ADSTB0_N
H_ADSTB1_N

H_REQ0_N
H_REQ1_N
H_REQ2_N
H_REQ3_N
H_REQ4_N

H_BREQ1_N
H_BREQ0_N
H2_BREQ23_N

H_BNR_N
H_BPRI_N
H_LOCK_N
H_BINIT_N

H_RS0_N
H_RS1_N
H_RS2_N
H_RSP_N
H_TRDY_N

H_HITM_N
H_HIT_N
H_DEFER_N

H_A20M_N
H_SMI_N
H_FERR_N
H_IGNNE_N
H2_IERR_N
H_MCERR_N

H_SLP_N
H_STPCLK_N
H_RST_N
H_INIT_N

H_INTR
H_NMI

CK_167M_CPU2_P

3

CK_167M_CPU2_N

3

SUB=SUB*_4M319

A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13

A9

B8
E13
D12
C11

B7

A6

A7

C9

C8

E10

D9

D19
F17
F14

B19
B21
C21
C20
B22

D20
F12
E11
D10

F20
D23
A17
F11

E21
D22
F21

C6
E19

A23
E22
C23

F27
C27
E27
C26

E5

D7

AE6

D4

Y8

D6

B24
G23

Y4

W5

PROC_2

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

AP0
AP1

ADS
ADSTB0
ADSTB1

REQ0
REQ1
REQ2
REQ3
REQ4

BR0
BR1
BR2
BR3

BNR
BPRI
LOCK
BINIT

RS0
RS1
RS2
RSP
TRDY

HITM
HIT
DEFER

A20M
SMI
FERR/PBE
IGNNE
IERR
MCERR

SLP
STPCLK
RESET
INIT

LINT0
LINT1

BCLK0
BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

DSTBN0
DSTBN1
DSTBN2
DSTBN3

DSTBP0
DSTBP1
DSTBP2
DSTBP3

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

Y26
AA27
Y24
AA25
AD27
Y23
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
AD10
AD8
AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
AD7
AE7
AC6
AC5
AA8
Y9
AB6

AC18
AE19
AC15
AE17

Y21
Y18
Y15
Y12

Y20
Y17
Y14
Y11

AC27
AD22
AE12
AB9
F18
E18

H_D0_N
H_D1_N
H_D2_N
H_D3_N
H_D4_N
H_D5_N
H_D6_N
H_D7_N
H_D8_N

H_D9_N
H_D10_N
H_D11_N
H_D12_N
H_D13_N
H_D14_N
H_D15_N
H_D16_N
H_D17_N
H_D18_N
H_D19_N
H_D20_N
H_D21_N
H_D22_N
H_D23_N
H_D24_N
H_D25_N
H_D26_N
H_D27_N
H_D28_N
H_D29_N
H_D30_N
H_D31_N
H_D32_N
H_D33_N
H_D34_N
H_D35_N
H_D36_N
H_D37_N
H_D38_N
H_D39_N
H_D40_N
H_D41_N
H_D42_N
H_D43_N
H_D44_N
H_D45_N
H_D46_N
H_D47_N
H_D48_N
H_D49_N
H_D50_N
H_D51_N
H_D52_N
H_D53_N
H_D54_N
H_D55_N
H_D56_N
H_D57_N
H_D58_N
H_D59_N
H_D60_N
H_D61_N
H_D62_N
H_D63_N

H_DP0_N
H_DP1_N
H_DP2_N
H_DP3_N

H_DSTBN0_N
H_DSTBN1_N
H_DSTBN2_N
H_DSTBN3_N

H_DSTBP0_N
H_DSTBP1_N
H_DSTBP2_N
H_DSTBP3_N

H_DBI0_N
H_DBI1_N
H_DBI2_N
H_DBI3_N
H_DBSY_N
H_DRDY_N

11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17
11,17

+CPU_VTT

+CPU_VTT

R1570

1 2

39-5%

R1566

1 2

39-5%

R1569

1 2

39-5%

R1567

1 2

39-5%

R1568

1 2

39-5%

R1518

1 2

R1516

1 2

R1514

1 2

R1512

1 2

R1520

R1511

NP

R1509

51

51

51

51

51

51

51

1 2

1 2

1 2

1 2

21

21

X

21

C1448

47pF

50V-5%

C1444

1 2

47pF

50V-5%

C1445

2 1

47pF

50V-5%

C1446

47pF

50V-5%

C1447

47pF

50V-5%

R1521

51

R1517

51

R1515

51

R1513

51

R1519

51

R1565

51

ECAD: Route trace from L128 to pin AB4

Route trace from L127 to pin AD4

ECAD: Route trace from L125 to pin AB4

Route trace from L126 to pin AD4

21

12

12

21

21

H_BINIT_N

H_BNR_N

H_HIT_N

H_HITM_N

H_MCERR_N

H2_BREQ23_N

H2_TESTHI0

H2_TESTHI1

H2_TESTHI2

H2_TESTHI3

H2_TESTHI4

H2_TESTHI5

H2_TESTHI6

H2_TESTHI7

H2_TESTHI8

H_FORCEPR_N

H2_BOOTSEL

H_TEST_BUS

11,17

11,17

11,17

11,17

11,15,17

11

12

12

12

12

12

12

12

12

12

5,12

12

12

775mV

x04_sd

775mV

x04_sd

754mV

754mV

+CPU_VTT

21

R1592

R370

1 2

+CPU_VTT

21

R1593

21

R371

+CPU_VTT

21

R1594

R372

1 2

+CPU_VTT

21

R1595

21

R373

+CPU_VTT

L136

10uH 165MA

to pin AD4

L137

1 2

10uH 165MA

to pin AB4

+CPU_VTT

L138

1 2

10uH 165MA

to pin AD4

L139

10uH 165MA

to pin AB4

CPU1 GTL VREF

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

49.9-1%

NET_PHYSICAL_TYPE=50MIL

C1451

90.9-1%90.9-1%

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

49.9-1%

NET_PHYSICAL_TYPE=50MIL

C1454

1uF

1 2

1 2

10V-10%

1uF

10V-10%

CPU2 GTL VREF

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

49.9-1%49.9-1%
NET_PHYSICAL_TYPE=50MIL

1 2

C1452

1 2

1uF

10V-10%

1uF

10V-10%

84.5-1%

NET_PHYSICAL_TYPE=50MIL

84.5-1%

C1453

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

X02_tj_091603

X03_tj_121503

21

21

R1824

1 2

0-5%

R1825 NET_PHYSICAL_TYPE=50MIL

1 2

0-5%

R1826

1 2

1 2

ROOM=PROC_1

V_VTT_H1_VCCA

cap between AB4 and AA5

C1492

1 2

22uF 6.3V22uF 6.3V

V_VTT_H1_VSSA

V_VTT_H2_VCCA

21

C1491

NET_PHYSICAL_TYPE=50MIL

C1581

NET_PHYSICAL_TYPE=50MIL

0-5%

R1827

0-5%

cap between AB4 and AA5

V_VTT_H2_VSSA

21

220pF

50V-10%

NC_H1_GTLREF01

21

C1579

NC_H1_GTLREF23

NET_PHYSICAL_TYPE=50MIL

NET_PHYSICAL_TYPE=50MIL

C1578

NET_PHYSICAL_TYPE=50MIL

NET_PHYSICAL_TYPE=50MIL

C1583

NET_PHYSICAL_TYPE=50MIL

220pF

21

220pF

NC_H2_GTLREF01

21

220pF

NC_H2_GTLREF23

21

C1582

C1580

50V-10%

C1577

50V-10%

C1584

50V-10%

220pF

50V-10%

21

21

21

220pF

50V-10%

220pF

50V-10%

220pF

50V-10%

12

12

12

12

H1_GTLREF01

2 1

750-1%

H1_GTLREF23

750-1%

H2_GTLREF01

750-1%

H2_GTLREF23

750-1%

1

12

2

R323

NP01

12

R321

12

NP01

12

3

R319

12

NP01

12

2 1

R320

NP01

Retention Screws

ADD1=ADD*_89JJP_RETSCRW1
ADD2=ADD*_89JJP_RETSCRW2
ADD3=ADD*_89JJP_RETSCRW3

Dangling 750 ohm resistors are there to help fine-tune
VREF's using a variable powr supply during margin testing

ADD4=ADD*_89JJP_RETSCRW4
ADD5=ADD*_89JJP_RETSCRW5

+1.5V

4 4

ADD6=ADD*_89JJP_RETSCRW6
ADD7=ADD*_89JJP_RETSCRW7

R1522

1 2

51

H2_ODTEN

12

ADD8=ADD*_89JJP_RETSCRW8

R1584NP

PROCESSORS 1 & 2

21

X

0-5%

2.5V-20%-2STACK

680uF

1 2

+

X

NP

C1587

NP

21

C1571

X

4.7uF

C1372

6.3V-10%

NP

21

X

NP

X

C1373

0.1uF 16V

V_1P5_H2_VCCPLL

1 2

0.1uF 16V

x00_sd_061703

12

NC_ST1_2

RETENTION SUPPORT, W/CLIP

NC_ST2_2

RETENTION SUPPORT, W/CLIP

x03b_tj_012004

SUB*_X4108

ST1

1

GND

2

NC

GROUND, BRACKET

ST2

1

GND

2

NC

GROUND, BRACKET

SUB*_X4108

1U Bottom Support Bracket

2U/5U Bottom Support Bracket

proc heatsink RM boat

two of the boats are represented here

ADD7=ADD02_Y1255_BRKT1
ADD8=ADD02_Y1255_BRKT2

ADD1=ADD13_W1578_BRKT3
ADD2=ADD13_W1578_BRKT4

ADD3=ADD*_X4108_RETMOD1
ADD4=ADD*_X4108_RETMOD2
ADD5=ADD*_X4108_RETMOD3

ADD1=ADD*_H3668_RMCLIP1
ADD2=ADD*_H3668_RMCLIP2

ADD3=ADD*_H3668_RMCLIP3
ADD4=ADD*_H3668_RMCLIP4

ADD5=ADD*_X4108_RETMOD5
ADD6=ADD*_X4108_RETMOD6
ADD7=ADD*_X4108_RETMOD7

proc heatsink RM clip

x03b_tj_012004

proc heatsink RM boat

x03b_tj_012004

PROCESSOR 1 & 2

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

INC.

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

ROUND ROCK,TEXAS

REV.

A03-00

SHEET

11 OF 60

subsys done

A B

DC

B D

CA

12-16-2004_19:51

1

2

3

SUB=SUB*_4M319

A5
A11
A21
A27
A29
A31

B2

B9
B15
B17
B23
B28
B30

C7
C13
C19
C25
C29
C31

D2

D5
D11
D21
D27
D28
D30

E9
E15
E17
E23
E29
E31

F2

F7
F13
F19
F25
F28
F30

G1

G3

G5

G9
G25
G27
G29
G31

H2

H4

H6

H8
H24
H26
H28
H30

J1

J3

J5

J7

J9
J23
J25
J27
J29
J31

K2

K4

K6

K8
K24
K26
K28
K30

L1

L3

L5

L7

L9
L23
L25
L27
L29
L31

M2

M4

M6

M8
M24
M26
M28
M30

N2

N4

PROC_1

VSS_A5
VSS_A11
VSS_A21
VSS_A27
VSS_A29
VSS_A31
VSS_B2
VSS_B9
VSS_B15
VSS_B17
VSS_B23
VSS_B28
VSS_B30
VSS_C7
VSS_C13
VSS_C19
VSS_C25
VSS_C29
VSS_C31
VSS_D2
VSS_D5
VSS_D11
VSS_D21
VSS_D27
VSS_D28
VSS_D30
VSS_E9
VSS_E15
VSS_E17
VSS_E23
VSS_E29
VSS_E31
VSS_F2
VSS_F7
VSS_F13
VSS_F19
VSS_F25
VSS_F28
VSS_F30
VSS_G1
VSS_G3
VSS_G5
VSS_G9
VSS_G25
VSS_G27
VSS_G29
VSS_G31
VSS_H2
VSS_H4
VSS_H6
VSS_H8
VSS_H24
VSS_H26
VSS_H28
VSS_H30
VSS_J1
VSS_J3
VSS_J5
VSS_J7
VSS_J9
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_K2
VSS_K4
VSS_K6
VSS_K8
VSS_K24
VSS_K26
VSS_K28
VSS_K30
VSS_L1
VSS_L3
VSS_L5
VSS_L7
VSS_L9
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31
VSS_M2
VSS_M4
VSS_M6
VSS_M8
VSS_M24
VSS_M26
VSS_M28
VSS_M30
VSS_N2
VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13
VSS_Y19
VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB1
VSS_AB5

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC2
VSS_AC7

VSS_AC13
VSS_AC19
VSS_AC25

VSS_AD3
VSS_AD9

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE2

VSS_AE11
VSS_AE21
VSS_AE27

N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13
Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

SUB=SUB*_4M319

A5
A11
A21
A27
A29
A31

B2

B9
B15
B17
B23
B28
B30

C7
C13
C19
C25
C29
C31

D2

D5
D11
D21
D27
D28
D30

E9
E15
E17
E23
E29
E31

F2

F7
F13
F19
F25
F28
F30

G1

G3

G5

G9
G25
G27
G29
G31

H2

H4

H6

H8
H24
H26
H28
H30

J1

J3

J5

J7

J9
J23
J25
J27
J29
J31

K2

K4

K6

K8
K24
K26
K28
K30

L1

L3

L5

L7

L9
L23
L25
L27
L29
L31

M2

M4

M6

M8
M24
M26
M28
M30

N2

N4

PROC_2

VSS_A5
VSS_A11
VSS_A21
VSS_A27
VSS_A29
VSS_A31
VSS_B2
VSS_B9
VSS_B15
VSS_B17
VSS_B23
VSS_B28
VSS_B30
VSS_C7
VSS_C13
VSS_C19
VSS_C25
VSS_C29
VSS_C31
VSS_D2
VSS_D5
VSS_D11
VSS_D21
VSS_D27
VSS_D28
VSS_D30
VSS_E9
VSS_E15
VSS_E17
VSS_E23
VSS_E29
VSS_E31
VSS_F2
VSS_F7
VSS_F13
VSS_F19
VSS_F25
VSS_F28
VSS_F30
VSS_G1
VSS_G3
VSS_G5
VSS_G9
VSS_G25
VSS_G27
VSS_G29
VSS_G31
VSS_H2
VSS_H4
VSS_H6
VSS_H8
VSS_H24
VSS_H26
VSS_H28
VSS_H30
VSS_J1
VSS_J3
VSS_J5
VSS_J7
VSS_J9
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_K2
VSS_K4
VSS_K6
VSS_K8
VSS_K24
VSS_K26
VSS_K28
VSS_K30
VSS_L1
VSS_L3
VSS_L5
VSS_L7
VSS_L9
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31
VSS_M2
VSS_M4
VSS_M6
VSS_M8
VSS_M24
VSS_M26
VSS_M28
VSS_M30
VSS_N2
VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13
VSS_Y19
VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB1
VSS_AB5

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC2
VSS_AC7

VSS_AC13
VSS_AC19
VSS_AC25

VSS_AD3
VSS_AD9

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE2

VSS_AE11
VSS_AE21
VSS_AE27

N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13
Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

11
12
11
12

5,46

15
15

12
12
12
12

11
11
11
11
11
11
11
11
11

11

11

45
45

15

5,11,12

15

12,15
12,15
12,15
12,15
12,15
12,15

12,15

15

15
12,15
12,15

H1_ODTEN
H1_SLEW_CTRL
H1_BOOTSEL
H1_OPTIMIZED

H1_CPU_PRES_N
H1_BSEL0
H1_BSEL1

H1_COMP0
H1_COMP1
H1_COMP2
H1_COMP3

H1_TESTHI0
H1_TESTHI1
H1_TESTHI2
H1_TESTHI3
H1_TESTHI4
H1_TESTHI5
H1_TESTHI6
H1_TESTHI7
H1_TESTHI8

H1_GTLREF01

H1_GTLREF23

H1_THRM_AN
H1_THRM_CA
NC_H1_PKG_ID

H1_PROCHOT_N
H_FORCEPR_N
H1_THERMTRIP_N

H_BPM0_N
H_BPM1_N
H_BPM2_N
H_BPM3_N
H_BPM4_N
H_BPM5_N

ITP_TCK
ITP_TDI_H1
ITP_TDO_H1
ITP_TMS
ITP_TRST_N

+CPU_VTT

+CPU_VTT

SUB=SUB*_4M319

Place @ CPU1

R1526

1 2

51

1 2

R1528

R1530

1 2

R1601

100-1%

R1597

49.9-1%

R60

301-1%

51

51

21

1 2

21

1 2

49.9-1%

21

21

H_VTT_PWRGOOD

R1531

51

R1527

51

R1529

51

R1600

100-1%

R1596

PROC_1

B5

ODTEN

AC30

AD16

AC28

21

21

SLEW_CTRL

G7

BOOT_SELECT

C1

OPTIMIZED/COMPAT

A3

SKTOCC

AA3

BSEL0

AB3

BSEL1

COMP0

E16

COMP1
COMP2

D25

COMP3

W6

TESTHI0

W7

TESTHI1

W8

TESTHI2

Y6

TESTHI3

AA7

TESTHI4

AD5

TESTHI5

AE5

TESTHI6

A26

TESTHI7

Y29

TESTHI8

W23

GTLREF0

W9

GTLREF1

F23

GTLREF2

F9 AA28

GTLREF3 NC_AA28

Y27

THERMDA

Y28

THERMDC

AE4

SMB_PRT

B25

PROCHOT

A15

FORCEPR

F26

THRMTRIP

F6

BPM0

F8

BPM1

E7

BPM2

F5

BPM3

E8

BPM4

E4

BPM5

E24

TCK

C24

TDI

E25

TDO

A25

TMS

F24

TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

H_BPM0_N

H_BPM1_N

H_BPM2_N

H_BPM3_N

H_BPM4_N

H_BPM5_N

H1_COMP2

H1_COMP3

H1_COMP0

H1_COMP1

5,12

12,15

12,15

12,15

12,15

12,15

12,15

12

12

12

12

12

12

VID0
VID1
VID2
VID3
VID4
VID5

VCCPLL

VCCIOPLL

VCCA
VSSA

VCCSENSE
VSSSENSE

PWRGOOD

RSVD_A16

RSVD_W3
RSVD_Y3

RSVD_AC1
RSVD_AE15
RSVD_AE16
RSVD_AE28
RSVD_AE29

NC_AA29
NC_AB28
NC_AB29
NC_AC29
NC_AD28
NC_AD29

VTTEN

VIDPWRGD

VTT_A4
VTT_B4

VTT_B12

VTT_C5
VTT_C10
VTT_E12
VTT_F10
VTT_Y10

VTT_AA12
VTT_AC10
VTT_AD12

H1_SLEW_CTRL

H1_OPTIMIZED

F3
E3
D3
C3
B3
A1

AD1
AD4

AB4
AA5

B27
D26

AB7

A16
W3
Y3
AC1
AE15
AE16
AE28
AE29

AA29
AB28
AB29
AC29
AD28
AD29

E1
B1

A4
B4
B12
C5
C10
E12
F10
Y10
AA12
AC10
AD12

H1_VID0
H1_VID1
H1_VID2
H1_VID3
H1_VID4
H1_VID5

V_1P5_H1_VCCPLL

V_VTT_H1_VCCA
V_VTT_H1_VSSA

H1_VCCSENSE
H1_VSSSENSE

H_PWRGOOD

H_TEST_BUS
NC_H1_W3
NC_H1_Y3
NC_H1_AC1
NC_H1_AE15
NC_H1_AE16
NC_H1_AE28
NC_H1_AE29

NC_H1_AA28
NC_H1_AA29
NC_H1_AB28
NC_H1_AB29
NC_H1_AC29
NC_H1_AD28
NC_H1_AD29

H1_VTT_EN
H_VTT_PWRGOOD

+CPU_VTT

+CPU_VTT

51

0-5%

NP

21

R1524

X

NP

21

R1525

X

NP

21

R1523

X

NP

21

R1585

X

5151

7
7
7
7
7
7

11

11
11

X00_GT_052203

7

X00_TJ_061803

7

X00_GT_052203

11,12,33

11,12

5
5,12

11
12
11
12

5,46

15
15

12
12
12
12

11
11
11
11
11
11
11
11
11

11

11

45
45

15

5,11,12

15

12,15
12,15
12,15
12,15
12,15
12,15

12,15

15

15
12,15
12,15

+CPU_VTT

H2_ODTEN
H2_SLEW_CTRL
H2_BOOTSEL
H2_OPTIMIZED

H2_CPU_PRES_N
H2_BSEL0
H2_BSEL1

H2_COMP0
H2_COMP1
H2_COMP2
H2_COMP3

H2_TESTHI0
H2_TESTHI1
H2_TESTHI2
H2_TESTHI3
H2_TESTHI4
H2_TESTHI5
H2_TESTHI6
H2_TESTHI7
H2_TESTHI8

H2_GTLREF01

H2_GTLREF23

H2_THRM_AN
H2_THRM_CA
NC_H2_PKG_ID

H2_PROCHOT_N
H_FORCEPR_N
H2_THERMTRIP_N

H_BPM0_N
H_BPM1_N
H_BPM2_N
H_BPM3_N
H_BPM4_N
H_BPM5_N

ITP_TCK
ITP_TDI_H2
ITP_TDO_H2
ITP_TMS
ITP_TRST_N

SUB=SUB*_4M319

Place @ CPU2

R1602

1 2

100-1%

R1599

1 2

49.9-1%

100-1%

49.9-1%

R1603

R1598

21

21

B5

AC30

G7
C1

A3
AA3
AB3

AD16

E16

AC28

D25

W6

W7

W8

Y6
AA7
AD5
AE5
A26
Y29

W23

W9
F23

Y27
Y28
AE4

B25
A15
F26

F6

F8

E7

F5

E8

E4

E24
C24
E25
A25
F24

PROC_2

ODTEN
SLEW_CTRL
BOOT_SELECT
OPTIMIZED/COMPAT

SKTOCC
BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

GTLREF0
GTLREF1
GTLREF2
GTLREF3 NC_AA28

THERMDA
THERMDC
SMB_PRT

PROCHOT
FORCEPR
THRMTRIP

BPM0
BPM1
BPM2
BPM3
BPM4
BPM5

TCK
TDI
TDO
TMS
TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

H2_COMP2

H2_COMP3

H2_COMP0

H2_COMP1

12

12

12

12

VID0
VID1
VID2
VID3
VID4
VID5

VCCPLL

VCCIOPLL

VCCA
VSSA

VCCSENSE
VSSSENSE

PWRGOOD

RSVD_A16

RSVD_W3
RSVD_Y3

RSVD_AC1
RSVD_AE15
RSVD_AE16
RSVD_AE28
RSVD_AE29

NC_AA29
NC_AB28
NC_AB29
NC_AC29
NC_AD28
NC_AD29

VTTEN

VIDPWRGD

VTT_A4
VTT_B4

VTT_B12

VTT_C5
VTT_C10
VTT_E12
VTT_F10
VTT_Y10

VTT_AA12
VTT_AC10
VTT_AD12

12

12

F3
E3
D3
C3
B3
A1

AD1
AD4

AB4
AA5

B27
D26

AB7

A16
W3
Y3
AC1
AE15
AE16
AE28
AE29

AA28F9
AA29
AB28
AB29
AC29
AD28
AD29

E1
B1

A4
B4
B12
C5
C10
E12
F10
Y10
AA12
AC10
AD12

H2_SLEW_CTRL

H2_OPTIMIZED

H2_VID0
H2_VID1
H2_VID2
H2_VID3
H2_VID4
H2_VID5

V_1P5_H2_VCCPLL

V_VTT_H2_VCCA
V_VTT_H2_VSSA

H2_VCCSENSE
H2_VSSSENSE

H_PWRGOOD

H_TEST_BUS
NC_H2_W3
NC_H2_Y3
NC_H2_AC1
NC_H2_AE15
NC_H2_AE16
NC_H2_AE28
NC_H2_AE29

NC_H2_AA28
NC_H2_AA29
NC_H2_AB28
NC_H2_AB29
NC_H2_AC29
NC_H2_AD28
NC_H2_AD29

H2_VTT_EN
H_VTT_PWRGOOD

+CPU_VTT

+CPU_VTT

NP

R1540

X

1 2

R1586

1 2

51

0-5%

NP

R1539

X

1 2

NP

R1538

X

1 2

8
8
8
8
8
8

11

11
11

X00_GT_052203

8

X00_TJ_061803

8

X00_GT_052203

11,12,33

11,12

5
5,12

51 51

1

2

3

4 4

INC.

ROUND ROCK,TEXAS

PROCESSOR 1 & 2

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

ECAD: place resistor near processor

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

12 OF 60

DC

subsys done

A B

B D

+CPU_VID1

CA

+CPU_VID1

ROOM=PROC_1

12-16-2004_19:51

x00_tj_041003

1

2

3

+CPU_VID1

SUB=SUB*_4M319

A2

A8
A14
A18
A24
A28
A30

B6
B20
B26
B29
B31

C2

C4
C16
C22
C28
C30

D1

D8
D14
D18
D24
D29
D31

E2

E6
E20
E26
E28
E30

F1

F4
F16
F22
F29
F31

G2

G4

G6

G8
G24
G26
G28
G30

H1

H3

H5

H7

H9
H23
H25
H27
H29
H31

J2

J4

J6

J8
J24
J26
J28
J30

K1

K3

K5

K7

K9
K23
K25
K27
K29
K31

L2

L4

L6

L8
L24
L26
L28
L30

M1

M3

M5

M7

M9
M23
M25
M27
M29
M31

PROC_1

VCC_A2
VCC_A8
VCC_A14
VCC_A18
VCC_A24
VCC_A28
VCC_A30
VCC_B6
VCC_B20
VCC_B26
VCC_B29
VCC_B31
VCC_C2
VCC_C4
VCC_C16
VCC_C22
VCC_C28
VCC_C30
VCC_D1
VCC_D8
VCC_D14
VCC_D18
VCC_D24
VCC_D29
VCC_D31
VCC_E2
VCC_E6
VCC_E20
VCC_E26
VCC_E28
VCC_E30
VCC_F1
VCC_F4
VCC_F16
VCC_F22
VCC_F29
VCC_F31
VCC_G2
VCC_G4
VCC_G6
VCC_G8
VCC_G24
VCC_G26
VCC_G28
VCC_G30
VCC_H1
VCC_H3
VCC_H5
VCC_H7
VCC_H9
VCC_H23
VCC_H25
VCC_H27
VCC_H29
VCC_H31
VCC_J2
VCC_J4
VCC_J6
VCC_J8
VCC_J24
VCC_J26
VCC_J28
VCC_J30
VCC_K1
VCC_K3
VCC_K5
VCC_K7
VCC_K9
VCC_K23
VCC_K25
VCC_K27
VCC_K29
VCC_K31
VCC_L2
VCC_L4
VCC_L6
VCC_L8
VCC_L24
VCC_L26
VCC_L28
VCC_L30
VCC_M1
VCC_M3
VCC_M5
VCC_M7
VCC_M9
VCC_M23
VCC_M25
VCC_M27
VCC_M29
VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 3 OF 4

VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y16
VCC_Y22
VCC_Y30
VCC_AA1
VCC_AA4

VCC_AA6
VCC_AA20
VCC_AA26
VCC_AA31

VCC_AB2

VCC_AB8
VCC_AB14
VCC_AB18
VCC_AB24
VCC_AB30

VCC_AC3

VCC_AC4
VCC_AC16
VCC_AC22
VCC_AC31

VCC_AD2

VCC_AD6
VCC_AD20
VCC_AD26
VCC_AD30

VCC_AE3

VCC_AE8
VCC_AE14
VCC_AE18
VCC_AE24

VCC_N1
VCC_N3
VCC_N5
VCC_N7
VCC_N9

VCC_P2
VCC_P4
VCC_P6
VCC_P8

VCC_R1
VCC_R3
VCC_R5
VCC_R7
VCC_R9

VCC_T2
VCC_T4
VCC_T6
VCC_T8

VCC_U1
VCC_U3
VCC_U5
VCC_U7
VCC_U9

VCC_V2
VCC_V4
VCC_V6
VCC_V8

VCC_W1

VCC_Y2

N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y16
Y22
Y30
AA1
AA4
AA6
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC16
AC22
AC31
AD2
AD6
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24

+CPU_VID1

+CPU_VID2 +CPU_VID2

PROC_2

N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y16
Y22
Y30
AA1
AA4
AA6
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC16
AC22
AC31
AD2
AD6
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24

SUB=SUB*_4M319

A2

A8
A14
A18
A24
A28
A30

B6
B20
B26
B29
B31

C2

C4
C16
C22
C28
C30

D1

D8
D14
D18
D24
D29
D31

E2

E6
E20
E26
E28
E30

F1

F4
F16
F22
F29
F31

G2

G4

G6

G8
G24
G26
G28
G30

H1

H3

H5

H7

H9
H23
H25
H27
H29
H31

J2

J4

J6

J8
J24
J26
J28
J30

K1

K3

K5

K7

K9
K23
K25
K27
K29
K31

L2

L4

L6

L8
L24
L26
L28
L30

M1

M3

M5

M7

M9
M23
M25
M27
M29
M31

VCC_A2
VCC_A8
VCC_A14
VCC_A18
VCC_A24
VCC_A28
VCC_A30
VCC_B6
VCC_B20
VCC_B26
VCC_B29
VCC_B31
VCC_C2
VCC_C4
VCC_C16
VCC_C22
VCC_C28
VCC_C30
VCC_D1
VCC_D8
VCC_D14
VCC_D18
VCC_D24
VCC_D29
VCC_D31
VCC_E2
VCC_E6
VCC_E20
VCC_E26
VCC_E28
VCC_E30
VCC_F1
VCC_F4
VCC_F16
VCC_F22
VCC_F29
VCC_F31
VCC_G2
VCC_G4
VCC_G6
VCC_G8
VCC_G24
VCC_G26
VCC_G28
VCC_G30
VCC_H1
VCC_H3
VCC_H5
VCC_H7
VCC_H9
VCC_H23
VCC_H25
VCC_H27
VCC_H29
VCC_H31
VCC_J2
VCC_J4
VCC_J6
VCC_J8
VCC_J24
VCC_J26
VCC_J28
VCC_J30
VCC_K1
VCC_K3
VCC_K5
VCC_K7
VCC_K9
VCC_K23
VCC_K25
VCC_K27
VCC_K29
VCC_K31
VCC_L2
VCC_L4
VCC_L6
VCC_L8
VCC_L24
VCC_L26
VCC_L28
VCC_L30
VCC_M1
VCC_M3
VCC_M5
VCC_M7
VCC_M9
VCC_M23
VCC_M25
VCC_M27
VCC_M29
VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 3 OF 4

VCC_AA20
VCC_AA26
VCC_AA31

VCC_AB14
VCC_AB18
VCC_AB24
VCC_AB30

VCC_AC16
VCC_AC22
VCC_AC31

VCC_AD20
VCC_AD26
VCC_AD30

VCC_AE14
VCC_AE18
VCC_AE24

VCC_N1
VCC_N3
VCC_N5
VCC_N7

VCC_N9
VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8
VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9
VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8
VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9
VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8
VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W1
VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y2
VCC_Y16
VCC_Y22
VCC_Y30
VCC_AA1
VCC_AA4
VCC_AA6

VCC_AB2
VCC_AB8

VCC_AC3
VCC_AC4

VCC_AD2
VCC_AD6

VCC_AE3
VCC_AE8

X00_GT_052803

12

+

C536

+CPU_VID2

12

C294

ECAD: Place 7 caps on each side of the each CPU

+CPU_VID1

+CPU_VID2

+CPU_VTT

SUB*_K1098

560uF

4V-20%

SUB*_K1098

+

560uF

4V-20%

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

1 2

10uF 6.3V

21

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

21

C537

C547

C1526

C1546

C1539

C1510

C1540

C1545

SUB*_K1098

12

+

12

+

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

12

+

SUB*_K1098

4V-20%

C540

560uF

12

+

560uF

4V-20%

C538

SUB*_K1098

12

+

560uF

4V-20%

C539

ROOM=PROC_2

SUB*_K1098

560uF

ECAD: Place on back side of planar

10uF 6.3V

C548

4V-20%

SUB*_D2341

C1520

21

ECAD: Place these 12 caps in CPU socket cavity

C1547

1 2

ECAD: Place on back side of planar

C1538

21

SUB*_D2341

C1509

21

ECAD: Place these 12 caps in CPU socket cavity

C1534

21

ECAD: Place on back side of planar

C1516

21

ECAD: Place on back side of planar

SUB*_K1098

12

+

560uF

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

C542

4V-20%

SUB*_D2341

C1525

21

C1548

1 2

C1528

21

SUB*_D2341

C1508

21

C1535

21

C1517

21

SUB*_K1098

12

+

560uF

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

C543

4V-20%

SUB*_D2341

C1521

21

C1549

1 2

C1529

21

SUB*_D2341

C1507

21

C1541

21

C1518

21

12

+

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

SUB*_K1098

560uF

SUB*_K1098

560uF

21

21

21

21

C545

4V-20%

4V-20%

SUB*_D2341

C1522

21

C1519

C1506

SUB*_D2341

C1530

C1536

C1515

1 2

SUB*_K1098

12

+

12

+

C549

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

21

10uF 6.3V

12

C546

560uF

4V-20%

SUB*_K1098

4V-20%

C1527

C1544

C1502

C1531

C1537

C1511

C544

560uF

SUB*_D2341

21

21

21

SUB*_D2341

21

1 2

SUB*_K1098

+

560uF

4V-20%

SUB*_K1098

12

+

560uF

SUB*_D2341

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

C1523

21

10uF 6.3V

21

21

SUB*_D2341

21

C1556

21

10uF 6.3V

1 2

C550

4V-20%

C1550

C1505

C1532

C1514

SUB*_K1098

12

+

12

+

C541

10uF 6.3V

21

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

21

10uF 6.3V

4V-20%

4V-20%

C1524

C1551

C1542

C1533

C1557

C1512

C551

C552

560uF

SUB*_K1098

560uF

SUB*_D2341

21

21

SUB*_D2341

21

1 2

SUB*_K1098

12

+

560uF

4V-20%

SUB*_K1098

12

+

560uF

4V-20%

SUB*_D2341

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

C732

21

10uF 6.3V

21

C1504

21

SUB*_D2341

C737

21

C1558

21

10uF 6.3V

1 2

X00_GT_052203

C290

12

+

C553

10uF 6.3V

C1552

C1513

10uF 6.3V

X00_GT_052203

10uF 6.3V

10uF 6.3V

10uF 6.3V

10uF 6.3V

SUB*_K1098

12

+

560uF

4V-20%

SUB*_K1098

560uF

4V-20%

SUB*_D2341

C733

21

C1553

21

C1503

21

SUB*_D2341

C738

21

C1559

21

C1543

1 2

C292

12

+

C297

10uF 6.3V

10uF 6.3V

10uF 6.3V

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

SUB*_K1098

12

+

560uF

4V-20%

SUB*_K1098

12

C296

560uF

4V-20%

SUB*_D2341

C734

21

C1554

21

C500

21

C739

C1560

21

10uF 6.3V

C511

12

+

C291

SUB*_K1098

+

560uF

4V-20%

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

21

SUB*_D2341

10uF 6.3V

C736

21

C1561

21

10uF 6.3V

21

SUB*_K1098

560uF

C735

C1555

C499

C507

C289

4V-20%

12

+

C295

10uF 6.3V

10uF 6.3V

10uF 6.3V

21

10uF 6.3V

SUB*_K1098

12

+

SUB*_K1098

560uF

4V-20%

C1656

21

C497

21

C1657

C508

21

560uF

4V-20%

C293

12

+

C298

10uF 6.3V

21

10uF 6.3V

SUB*_K1098

12

+

560uF

4V-20%

SUB*_K1098

560uF

4V-20%

C498

21

10uF 6.3V

C509

C496

21

10uF 6.3V

1 2

C506

10uF 6.3V

C492

21

10uF 6.3V

1 2

C502

10uF 6.3V

C495

21

10uF 6.3V

1 2

C505

10uF 6.3V

C501

21

10uF 6.3V

1 2

C503

10uF 6.3V

C494

21

10uF 6.3V

1 2

C504

4.0V-20%

4.0V-20%

10uF 6.3V

C493

21

10uF 6.3V

1 2

1 2

330uF

+

+CPU_VID2

330uF

+

21

C510

C413

C428

4.0V-20%
330uF

+

4.0V-20%
330uF

+

4.0V-20%

C414

21

330uF

1 2

C415

+

1

1 2

C516

4.0V-20%
330uF

+

C517

21

2

3

21

4 4

C1496

1 2

C1495

22uF 6.3V

SUB*_C5127

x03b_tj_011903

C1494

1 2

22uF 6.3V

21

C1493

22uF 6.3V

22uF 6.3V

21

C286

C1450

22uF 6.3V

1 2

C1449

1uF 6.3V

1 2

C1391

1uF 6.3V

1 2

21

C1374

0.1uF 16V

0.1uF 16V

C1785

21

0.1uF 16V

X00_GT_062003

INC.

ROUND ROCK,TEXAS

TITLE

PROCESSOR 1 & 2

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

A B

DWG NO.

DATE

DC

D1660

12/16/2004

REV.

A03-00

SHEET

13 OF 60

B D

CA

12-16-2004_19:51

1

1

2

2

3

3

4 4

INC.

ROUND ROCK,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

DWG NO.

DATE

D1660

12/16/2004

REV.

A03-00

SHEET

14 OF 60

DC

A B

1

+CPU_VTT

C76

1 2

C304

1 2

0.1uF 16V

1uF

10V-10%

x00_GT_010704

R1913

1 2

100-5%

21

R568

x00_tj_051203

R550

40.2-0.5%

1 2

21

R219

40.2-0.5%

R220

40.2-0.5%

1 2

21

R221

40.2-0.5%

ITP PORT

R222

40.2-0.5%

40.2-0.5%

1 2

a00_tj_052604

ITP_CONN

NP

ROOM=ITP

21

R218

40.2-0.5%

R367

1 2

R4

1.5K-5%
1 2

x00_tj_051203

+3.3V_AUX

75-1%

R1756

1 2

B D

CA

ITP_TDI_H1

FOR JTDO:

+CPU_VTT

Install 1-2 for TWO processor system
Install 2-3 for UNI processor system

x00_tj_091603

21

150-5%

R6001

150-5%

(UNI-PROCESSOR IS WITH PROC_1 INSTALLED ONLY!)

12-16-2004_19:51

ROOMS COMPLETE

1

11,17

H_RST_N

x02_tj_081803

R80

1 2

0-5%

H_BPM0_N

12

H_BPM1_N

12

H_BPM2_N

12

H_BPM3_N

12

H_BPM4_N

12

H_BPM5_N

12

H_RST_ITP_N

CK_167M_ITP_P

3

CK_167M_ITP_N

3

(BPM5DR#)

x00_tj_060403

(FBO)

1
3 4
5 6
7 8

9
11 12
13 14
15 16
17 18
19

X

21 22
23
25

2MM SMT

KEY 26

2

10

20

24
26

K

21

R125

ITP_PWR

680-5%

R160

1 2

27.4-1%

NC_ITP_DBA_N

ITP_DBR_N

ITP_TDI_H1

ITP_TMS

ITP_TRST_N

ITP_TCK

NC_ITP_FBI

ITP_TDO_H2

NC_ITP_26_KEY

12
12
12
12

12,15

PROC_1 PROC_2

ITP_TDO_H1

5

ITP_TDI_H2

TDITDI

JTDO

1

2

3

2

a00_tj_052604

ITP_JPR

NP

1
2
3

X

+CPU_VTT

R126

x00_tj_060403

150-5%

1 2

ITP_TDI_H2
ITP_TDO_H1
ITP_TDO_H2

12
12
12,15

TDO

ITP_TD0_H2

TDO

2

ITP ROUTING DRAWING

H1_THERMTRIP_N

12

+CPU_VTT

21

R277

51

R554

2.7K-5%

x02_tj_092203

Q28

3904

1

21

+3.3V_AUX

21

R374

3

2

1K-1%

H1_THERMTRIP_3V

ROOM=PROC_1

5,46

12

H1_PROCHOT_N

+CPU_VTT

R308

1 2

51

R556

2.7K-5%

+3.3V

+CPU_VTT

21

21

R266

R419

2.7K-5%

Q68

3904

1

21

R376

1K-1%

H1_PROCHOT_3V

Q30

3904

1

21

3

2

5

H1_IERR_N

11

51

+3.3V

21

R415

1K-1%

H1_IERR_3V

3

2

11,17

5,46

H_MCERR_N

NP*

R423

1 2

2.7K-5%

NP*

Q71

3904

1

NP*

+3.3V

R417

1 2

R586

1K-1%

NC_H_MCERR_3V

3

x03b_sd

2

12

H1_BSEL0

511-1%

1 2

R603

2.7K-5%

ROOM = PROC_1

+CPU_VTT +3.3V+CPU_VTT +3.3V

21

R595

Q61

3904 3904

1

21

1K-1%

H1_BSEL0_3V_N

3

2

5

H1_BSEL1

12

R585

1 2

511-1%

R602

2.7K-5%

21

R594

Q53

1

21

1K-1%

H1_BSEL1_3V_N

3

2

5

3

H2_THERMTRIP_N

12

ECAD: the components within each circuit need to stay clumped

+CPU_VTT

ROOM=PROC_2

x02_tj_092203

+CPU_VTT

R292

1 2

51

R555

1 2

2.7K-5%

Q29

3904

1

+3.3V_AUX

R375

1 2

3

2

1K-1%

H2_THERMTRIP_3V

5,46

H2_PROCHOT_N

12

51

R1510

21

R557

1 2

2.7K-5%

Q31

3904

1

+3.3V

R377

1K-1%

1 2

H2_PROCHOT_3V

3

2

3

+CPU_VTT

+3.3V

ROOM=PROC_2

21

51

R312

5

H2_IERR_N

11

1 2

Q69

R420

2.7K-5%

3904

21

R416

1

1K-1%

H2_IERR_3V

3

2

5,46

R588

1 2

511-1%

ROOM = PROC_2

21

R597

1K-1%

H2_BSEL0_3V_N

5

+CPU_VTT +3.3V+CPU_VTT +3.3V

R587

1 2

511-1%

21

R596

1K-1%

H2_BSEL1_3V_N

5

12

H2_BSEL0

R605

2.7K-5%

Q102

1

21

3

R604

H2_BSEL1

12

2.7K-5%

2

Q64

39043904

1

21

3

2

INVERTING LEVEL TRANSLATION

4 4

INC.

ROUND ROCK,TEXAS

TITLE

ITP & GTL LEVEL TRANSLATION

subsys done

A B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

DC

REV.

A03-00

SHEET

15 OF 60

B D

CA

+1.8V

19

ROOM = DDR_TERM

21
21

C360

21

.1uF

10V-10%

C359

1

RN28

2
3

71.5

4

8
7
6
5

DDR2B_A0

DDR2B_A0
DDR2B_A10
DDR2B_A10

16,21
16,21
16,21
16,21

1%

1

1

RN29

2
3

71.5

4

8
7
6
5

DDR2B_A1

DDR2B_A1

DDR2B_A2

DDR2B_A2

16,21
16,21
16,21
16,21

1%

1

RN30

2
3

71.5

4

8
7
6
5

DDR2B_A5

DDR2B_A5

DDR2B_A6

DDR2B_A6

16,21
16,21
16,21
16,21

1%

1

RN31

2
3

71.5

4

8
7
6
5

DDR2B_A7

DDR2B_A7

DDR2B_A8

DDR2B_A8

16,21
16,21
16,21
16,21

1%

1

RN32

2
3

71.5

4

8
7
6
5

DDR2B_A4

DDR2B_A4

DDR2B_A3

DDR2B_A3

16,21
16,21
16,21
16,21

1%

1

RN33

2
3

71.5

4

8
7
6
5

DDR2B_A11
DDR2B_A11

DDR2B_A9

DDR2B_A9

16,21
16,21
16,21
16,21

1%

1

RN36

2
3

71.5

4

8
7
6
5

DDR2B_BA2
DDR2B_BA2
DDR2B_A12
DDR2B_A12

16,21
16,21
16,21
16,21

1%

1

RN34

2
3

71.5

4

8
7
6
5

DDR2B_BA1
DDR2B_BA1
DDR2B_BA0
DDR2B_BA0

16,21
16,21
16,21
16,21

1%

2

1

RN35

2
3

71.5

4

8
7
6
5

DDR2B_CS0_N
DDR2B_CS0_N

DDR2B_CAS_N
DDR2B_CAS_N

16,21
16,21

16,21
16,21

1%

1

RN39

2
3

71.5

4

8
7
6
5

DDR2B_RAS_N
DDR2B_RAS_N

DDR2B_A13
DDR2B_A13

16,21
16,21
16,21
16,21

1%

DDR2B_CS3_N
DDR2B_CS3_N
DDR2B_CS2_N
DDR2B_CS2_N

x00_tj_061903

DDR2B_CS7_N
DDR2B_CS7_N

DDR2B_WE_N
DDR2B_WE_N

16,21
16,21
16,21
16,21

16,21
16,21

16,21
16,21

x00_tj_051203

x00_tj_051203

1

RN37

2
3

71.5

4

8
7
6
5

1%

1

RN38

2
3

71.5

4

8
7
6
5

1%

1

RN43

2
3

71.5

4

8
7
6
5

DDR2B_CS1_N
DDR2B_CS1_N
DDR2B_CS6_N
DDR2B_CS6_N

16,21
16,21
16,21
16,21

1%

x00_tj_051203

1

RN42

2
3

71.5

4

8
7
6
5

DDR2B_CS5_N
DDR2B_CS5_N
DDR2B_CS4_N
DDR2B_CS4_N

16,21
16,21
16,21
16,21

1%

1

RN41

2
3

71.5

4

8
7
6
5

DDR2_CKE4
DDR2_CKE4
DDR2_CKE2
DDR2_CKE2

16,20
16,20
16,20
16,20

1%

DDR2_CKE6
DDR2_CKE6
DDR2_CKE0
DDR2_CKE0

16,20
16,20
16,20
16,20

3

1

RN40

2
3

71.5

4

8
7
6
5

1%

R380

1 2

100-1%

R382

1 2

100-1%

R385

1 2

100-1%

R387

1 2

100-1%

R389

R381

21

100-1%

R383

21

100-1%

R386

21

100-1%

R388

21

100-1%

1 2

NP*

NP*

R390

100-1%

R392

100-1%

R394

100-1%

R396

100-1%

21

21

21

NP*

21

NP*

100-1%

R391

1 2

100-1%

R393

1 2

100-1%

R395

1 2

100-1%

4 4

CK_200M_DIMMB3_P

CK_200M_DIMMB3_P

CK_200M_DIMMB3_N

CK_200M_DIMMB3_N

CK_200M_DIMMB1_P

CK_200M_DIMMB1_P

CK_200M_DIMMB1_N

CK_200M_DIMMB1_N

CK_200M_DIMMB2_P

CK_200M_DIMMB2_P

CK_200M_DIMMB2_N

CK_200M_DIMMB2_N

CK_200M_DIMMB0_P

CK_200M_DIMMB0_P

CK_200M_DIMMB0_N

CK_200M_DIMMB0_N

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16

16

16

16

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

RN59

71.5
1%

RN58

71.5
1%

RN57

71.5
1%

RN56

71.5
1%

RN55

71.5
1%

RN54

71.5
1%

RN53

71.5
1%

RN52

71.5
1%

RN51

71.5
1%

RN44

71.5
1%

RN45

71.5
1%

RN46

71.5
1%

RN47

71.5
1%

RN50

71.5
1%

RN49

71.5
1%

RN48

71.5
1%

R397

100-1%

R399

100-1%

R401

100-1%

R403

100-1%

R405

100-1%

R409

100-1%

R411

100-1%

R413

100-1%

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

21

1 2

21

1 2

21

1 2

21

1 2

21

1 2

21

1 2

21

NP*

1 2

21

NP*

1 2

R398

100-1%

R400

100-1%

R402

100-1%

R404

100-1%

R408

100-1%

R410

100-1%

R412

100-1%

R414

100-1%

NP*

NP*

DDR2A_A10
DDR2A_A10

DDR2A_A0
DDR2A_A0

DDR2A_A2
DDR2A_A2
DDR2A_A1
DDR2A_A1

DDR2A_A6
DDR2A_A6
DDR2A_A5
DDR2A_A5

DDR2A_A8
DDR2A_A8
DDR2A_A7
DDR2A_A7

DDR2A_A3
DDR2A_A3
DDR2A_A4
DDR2A_A4

DDR2A_A9

DDR2A_A9
DDR2A_A11
DDR2A_A11

DDR2A_A12
DDR2A_A12
DDR2A_BA2
DDR2A_BA2

DDR2A_BA0
DDR2A_BA0
DDR2A_BA1
DDR2A_BA1

DDR2A_CAS_N
DDR2A_CAS_N
DDR2A_CS0_N
DDR2A_CS0_N

DDR2A_WE_N

DDR2A_WE_N
DDR2A_RAS_N
DDR2A_RAS_N

DDR2A_CS3_N
DDR2A_CS3_N
DDR2A_CS2_N
DDR2A_CS2_N

DDR2A_CS7_N
DDR2A_CS7_N

DDR2A_A13
DDR2A_A13

DDR2A_CS6_N
DDR2A_CS6_N

DDR2A_CS1_N
DDR2A_CS1_N

DDR2A_CS5_N
DDR2A_CS5_N
DDR2A_CS4_N
DDR2A_CS4_N

DDR2_CKE1
DDR2_CKE1
DDR2_CKE7
DDR2_CKE7

DDR2_CKE5
DDR2_CKE5
DDR2_CKE3
DDR2_CKE3

CK_200M_DIMMA3_P

CK_200M_DIMMA3_P

CK_200M_DIMMA3_N

CK_200M_DIMMA3_N

CK_200M_DIMMA1_P

CK_200M_DIMMA1_P

CK_200M_DIMMA1_N

CK_200M_DIMMA1_N

CK_200M_DIMMA2_P

CK_200M_DIMMA2_P

CK_200M_DIMMA2_N

CK_200M_DIMMA2_N

CK_200M_DIMMA0_P

CK_200M_DIMMA0_P

CK_200M_DIMMA0_N

CK_200M_DIMMA0_N

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20
16,20
16,20

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16

16

16

16

21

.1uF

10V-10%

C364

21

.1uF

10V-10%

C357

21

.1uF

10V-10%

C355

21

.1uF

10V-10%

C353

21

.1uF

10V-10%

C418

21

.1uF

10V-10%

C313

21

.1uF

10V-10%

C351

21

.1uF

10V-10%

C341

21

.1uF

10V-10%

C339

21

.1uF

10V-10%

C322

21

.1uF

10V-10%

C325

21

.1uF

10V-10%

C316

21

.1uF

10V-10%

C369

1 2

.1uF

10V-10%

C371

1 2

.1uF

10V-10%

C373

1 2

.1uF

10V-10%

C375

1 2

.1uF

10V-10%

C374

1 2

.1uF

10V-10%

C366

21

.1uF

10V-10%

CAD Notes:

1) Place one cap near every 2 signals

2) Place 10uF caps at each end of row

C358

.1uF

10V-10%

C361

.1uF

10V-10%

C362

.1uF

10V-10%

C356

.1uF

10V-10%

C354

.1uF

10V-10%

C352

.1uF

10V-10%

C419

.1uF

10V-10%

C312

.1uF

10V-10%

C342

.1uF

10V-10%

C340

.1uF

10V-10%

C321

.1uF

10V-10%

C363

.1uF

10V-10%

C323

.1uF

10V-10%

C315

.1uF

10V-10%

C370

1 2

.1uF

10V-10%

C372

1 2

.1uF

10V-10%

C314

1 2

.1uF

10V-10%

C368

1 2

.1uF

10V-10%

C365

1 2

.1uF

10V-10%

C367

1 2

.1uF

10V-10%

21

x00_tj_060503

C73

21

1 2

10uF 6.3V

21

C79

21

21

10uF 6.3V

21

21

21

21

21

21

21

21

21

21

16,21
16,21
16,21
16,21
16,21
16,21

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21

16,21
16,21
16,21

16,21
16,21
16,21

16,20
16,21
16,20
16,21

16,21
16,21
16,21
16,21
16,21
16,21
16,21
16,21

16
16

23

2U/5U Heatsink assembly

DDR2B_DQS0_P
DDR2B_DQS0_N
DDR2B_DQS1_P
DDR2B_DQS1_N
DDR2B_DQS2_P
DDR2B_DQS2_N
DDR2B_DQS3_P
DDR2B_DQS3_N
DDR2B_DQS4_P
DDR2B_DQS4_N
DDR2B_DQS5_P
DDR2B_DQS5_N
DDR2B_DQS6_P
DDR2B_DQS6_N
DDR2B_DQS7_P
DDR2B_DQS7_N
DDR2B_DQS8_P
DDR2B_DQS8_N
DDR2B_DQS9_P
DDR2B_DQS9_N
DDR2B_DQS10_P
DDR2B_DQS10_N
DDR2B_DQS11_P
DDR2B_DQS11_N
DDR2B_DQS12_P
DDR2B_DQS12_N
DDR2B_DQS13_P
DDR2B_DQS13_N
DDR2B_DQS14_P
DDR2B_DQS14_N
DDR2B_DQS15_P
DDR2B_DQS15_N
DDR2B_DQS16_P
DDR2B_DQS16_N
DDR2B_DQS17_P
DDR2B_DQS17_N

DDR2B_A0
DDR2B_A1
DDR2B_A2
DDR2B_A3
DDR2B_A4
DDR2B_A5
DDR2B_A6
DDR2B_A7
DDR2B_A8
DDR2B_A9
DDR2B_A10
DDR2B_A11
DDR2B_A12
DDR2B_A13

DDR2B_BA0
DDR2B_BA1
DDR2B_BA2

DDR2B_WE_N
DDR2B_CAS_N

DDR2B_RAS_N

DDR2_CKE4
DDR2_CKE5

DDR2_CKE6
DDR2_CKE7

DDR2B_CS0_N
DDR2B_CS1_N
DDR2B_CS2_N
DDR2B_CS3_N
DDR2B_CS4_N
DDR2B_CS5_N
DDR2B_CS6_N
DDR2B_CS7_N

CK_200M_DIMMB1_P
CK_200M_DIMMB1_N
CK_200M_DIMMB2_P
CK_200M_DIMMB2_N
CK_200M_DIMMB3_P
CK_200M_DIMMB3_N
CK_200M_DIMMB0_P
CK_200M_DIMMB0_N

DDR2B_MCH_VREF

SUB=SUB*_R7626

1U Heatsink assembly

AM28
AN29
AM22
AN23
AK17
AL17
AK11
AL11

AG2
AH2
AA3
AB4

P1
R2
H3

H1
AK5
AK6

AK29
AL29
AK23
AL23
AN18
AN17
AN12
AN11

AJ1
AH1
AB2
AB1

T2

R3

J3

J2
AM6
AN6

AF7

AE14
AN14
AK14
AD15
AH16
AG17
AD18
AL20
AJ21

AC4

AH22
AH23

U4

AA8
AE7

AM25

W4

W1

Y9

AH26
AJ27
AJ28
AH28

V9

V2

T7

P6

N4

M2

M6

L3

AH7
AJ6
AH6
AG6
AG8
AE8
AK9
AL8

AN4

B_DQS0_P
B_DQS0_N
B_DQS1_P
B_DQS1_N
B_DQS2_P
B_DQS2_N
B_DQS3_P
B_DQS3_N
B_DQS4_P
B_DQS4_N
B_DQS5_P
B_DQS5_N
B_DQS6_P
B_DQS6_N
B_DQS7_P
B_DQS7_N
B_DQS8_P
B_DQS8_N
B_DQS9_P
B_DQS9_N
B_DQS10_P
B_DQS10_N
B_DQS11_P
B_DQS11_N
B_DQS12_P
B_DQS12_N
B_DQS13_P
B_DQS13_N
B_DQS14_P
B_DQS14_N
B_DQS15_P
B_DQS15_N
B_DQS16_P
B_DQS16_N
B_DQS17_P
B_DQS17_N

B_MA0
B_MA1
B_MA2
B_MA3
B_MA4
B_MA5
B_MA6
B_MA7
B_MA8
B_MA9
B_MA10
B_MA11
B_MA12
B_MA13

B_BA0
B_BA1
B_BA2

B_WE
B_CAS
B_RAS

CKE4
CKE5
CKE6
CKE7

B_CS0
B_CS1
B_CS2
B_CS3
B_CS4
B_CS5
B_CS6
B_CS7

B_CMDCLK0_P
B_CMDCLK0_N
B_CMDCLK1_P
B_CMDCLK1_N
B_CMDCLK2_P
B_CMDCLK2_N
B_CMDCLK3_P
B_CMDCLK3_N

B_VREF

INTEL LINDENHURST MCH V0P21

x02_tj_041003
x03_tj_121503
x03b_tj_012004

x00c4_tj_090304

MCH

B_DQ0
B_DQ1
B_DQ2
B_DQ3
B_DQ4
B_DQ5
B_DQ6
B_DQ7

B_DQ8

B_DQ9
B_DQ10
B_DQ11
B_DQ12
B_DQ13
B_DQ14
B_DQ15

B_DQ16
B_DQ17
B_DQ18
B_DQ19
B_DQ20
B_DQ21
B_DQ22
B_DQ23

B_DQ24
B_DQ25
B_DQ26
B_DQ27
B_DQ28
B_DQ29
B_DQ30
B_DQ31

B_DQ32
B_DQ33
B_DQ34
B_DQ35
B_DQ36
B_DQ37
B_DQ38
B_DQ39

B_DQ40
B_DQ41
B_DQ42
B_DQ43
B_DQ44
B_DQ45
B_DQ46
B_DQ47

B_DQ48
B_DQ49
B_DQ50
B_DQ51
B_DQ52
B_DQ53
B_DQ54
B_DQ55

B_DQ56
B_DQ57
B_DQ58
B_DQ59
B_DQ60
B_DQ61
B_DQ62
B_DQ63

B_CB0

B_CB1

B_CB2

B_CB3

B_CB4

B_CB5

B_CB6

B_CB7

HETERO 3 OF 7

ADD=ADD02_W1549_MCHHTSNK1

ADD1=ADD13_X1306_MCHHTSNK2

AM30
AN30
AN27
AM27
AK30
AM31
AL28
AK27

AM24
AN24
AN21
AM21
AL25
AK24
AL22
AK21

AK18
AM18
AN15
AM15
AL19
AM19
AM16
AL16

AK12
AM12
AN9
AM9
AL13
AM13
AM10
AL10

AJ3
AJ4
AF1
AF4
AK3
AK2
AG3
AF3

AC3
AC1
Y3
Y4
AD2
AD3
AA2
Y1

T4
T1
N1
N2
U3
U1
P3
P4

K2
K1
F2
E1
L1
K4
G1
G2

AM7
AL7
AM4
AL4
AN8
AK8
AN5
AL5

x00_tj_041003

DDR2B_SD0_0
DDR2B_SD0_1
DDR2B_SD0_2
DDR2B_SD0_3
DDR2B_SD0_4
DDR2B_SD0_5
DDR2B_SD0_6
DDR2B_SD0_7

DDR2B_SD1_0
DDR2B_SD1_1
DDR2B_SD1_2
DDR2B_SD1_3
DDR2B_SD1_4
DDR2B_SD1_5
DDR2B_SD1_6
DDR2B_SD1_7

DDR2B_SD2_0
DDR2B_SD2_1
DDR2B_SD2_2
DDR2B_SD2_3
DDR2B_SD2_4
DDR2B_SD2_5
DDR2B_SD2_6
DDR2B_SD2_7

DDR2B_SD3_0
DDR2B_SD3_1
DDR2B_SD3_2
DDR2B_SD3_3
DDR2B_SD3_4
DDR2B_SD3_5
DDR2B_SD3_6
DDR2B_SD3_7

DDR2B_SD4_0
DDR2B_SD4_1
DDR2B_SD4_2
DDR2B_SD4_3
DDR2B_SD4_4
DDR2B_SD4_5
DDR2B_SD4_6
DDR2B_SD4_7

DDR2B_SD5_0
DDR2B_SD5_1
DDR2B_SD5_2
DDR2B_SD5_3
DDR2B_SD5_4
DDR2B_SD5_5
DDR2B_SD5_6
DDR2B_SD5_7

DDR2B_SD6_0
DDR2B_SD6_1
DDR2B_SD6_2
DDR2B_SD6_3
DDR2B_SD6_4
DDR2B_SD6_5
DDR2B_SD6_6
DDR2B_SD6_7

DDR2B_SD7_0
DDR2B_SD7_1
DDR2B_SD7_2
DDR2B_SD7_3
DDR2B_SD7_4
DDR2B_SD7_5
DDR2B_SD7_6
DDR2B_SD7_7

DDR2B_CB0
DDR2B_CB1
DDR2B_CB2
DDR2B_CB3
DDR2B_CB4
DDR2B_CB5
DDR2B_CB6
DDR2B_CB7

ROOM = MCH

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

16,20
16,20
16,20
16,20
16,20
16,20

16
16

23

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20

16,20
16,20
16,20

16,20
16,20
16,20

16,20
16,21
16,20
16,21

16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20

DDR2A_DQS0_P
DDR2A_DQS0_N
DDR2A_DQS1_P
DDR2A_DQS1_N
DDR2A_DQS2_P
DDR2A_DQS2_N
DDR2A_DQS3_P
DDR2A_DQS3_N
DDR2A_DQS4_P
DDR2A_DQS4_N
DDR2A_DQS5_P
DDR2A_DQS5_N
DDR2A_DQS6_P
DDR2A_DQS6_N
DDR2A_DQS7_P
DDR2A_DQS7_N
DDR2A_DQS8_P
DDR2A_DQS8_N
DDR2A_DQS9_P
DDR2A_DQS9_N
DDR2A_DQS10_P
DDR2A_DQS10_N
DDR2A_DQS11_P
DDR2A_DQS11_N
DDR2A_DQS12_P
DDR2A_DQS12_N
DDR2A_DQS13_P
DDR2A_DQS13_N
DDR2A_DQS14_P
DDR2A_DQS14_N
DDR2A_DQS15_P
DDR2A_DQS15_N
DDR2A_DQS16_P
DDR2A_DQS16_N
DDR2A_DQS17_P
DDR2A_DQS17_N

DDR2A_A0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_A7
DDR2A_A8
DDR2A_A9
DDR2A_A10
DDR2A_A11
DDR2A_A12
DDR2A_A13

DDR2A_BA0
DDR2A_BA1
DDR2A_BA2

DDR2A_WE_N
DDR2A_CAS_N
DDR2A_RAS_N

DDR2_CKE0
DDR2_CKE1
DDR2_CKE2
DDR2_CKE3

DDR2A_CS0_N
DDR2A_CS1_N
DDR2A_CS2_N
DDR2A_CS3_N
DDR2A_CS4_N
DDR2A_CS5_N
DDR2A_CS6_N
DDR2A_CS7_N

CK_200M_DIMMA1_P
CK_200M_DIMMA1_N
CK_200M_DIMMA2_P
CK_200M_DIMMA2_N
CK_200M_DIMMA3_P
CK_200M_DIMMA3_N
CK_200M_DIMMA0_P
CK_200M_DIMMA0_N

DDR2A_MCH_VREF

ROOM=MCH

AJ30
AJ31
AJ24
AJ25
AH19
AH20
AG14
AG15

AC6
AD6

W7
V8
N7
P7
G4

H4
AF9
AG9

AL32
AL31
AF25
AF24
AE20
AE19
AH14
AJ13

AD8
AC7

Y7

Y6
P10
N10

J6

H6
AH8
AJ7

AH5

AD14
AL14
AK15
AJ16
AH17
AF18
AN20
AK20
AJ22

AE4

AF22
AG23

U6

AB5
AF6

AE25

Y10

W8
AA6

AE26
AN26
AL26
AK26

W2

V3

T8
T10

N5

M5

M3

L4

AF13
AF12
AH11
AJ12
AH13
AG12
AC10

AD9
AM3

A_DQS0_P
A_DQS0_N
A_DQS1_P
A_DQS1_N
A_DQS2_P
A_DQS2_N
A_DQS3_P
A_DQS3_N
A_DQS4_P
A_DQS4_N
A_DQS5_P
A_DQS5_N
A_DQS6_P
A_DQS6_N
A_DQS7_P
A_DQS7_N
A_DQS8_P
A_DQS8_N
A_DQS9_P
A_DQS9_N
A_DQS10_P
A_DQS10_N
A_DQS11_P
A_DQS11_N
A_DQS12_P
A_DQS12_N
A_DQS13_P
A_DQS13_N
A_DQS14_P
A_DQS14_N
A_DQS15_P
A_DQS15_N
A_DQS16_P
A_DQS16_N
A_DQS17_P
A_DQS17_N

A_MA0
A_MA1
A_MA2
A_MA3
A_MA4
A_MA5
A_MA6
A_MA7
A_MA8
A_MA9
A_MA10
A_MA11
A_MA12
A_MA13

A_BA0
A_BA1
A_BA2

A_WE
A_CAS
A_RAS

CKE0
CKE1
CKE2
CKE3

A_CS0
A_CS1
A_CS2
A_CS3
A_CS4
A_CS5
A_CS6
A_CS7

A_CMDCLK0_P
A_CMDCLK0_N
A_CMDCLK1_P
A_CMDCLK1_N
A_CMDCLK2_P
A_CMDCLK2_N
A_CMDCLK3_P
A_CMDCLK3_N

A_VREF

INTEL LINDENHURST MCH V0P21

MCH

HETERO 4 OF 7

A_DQ0
A_DQ1
A_DQ2
A_DQ3
A_DQ4
A_DQ5
A_DQ6
A_DQ7

A_DQ8

A_DQ9
A_DQ10
A_DQ11
A_DQ12
A_DQ13
A_DQ14
A_DQ15

A_DQ16
A_DQ17
A_DQ18
A_DQ19
A_DQ20
A_DQ21
A_DQ22
A_DQ23

A_DQ24
A_DQ25
A_DQ26
A_DQ27
A_DQ28
A_DQ29
A_DQ30
A_DQ31

A_DQ32
A_DQ33
A_DQ34
A_DQ35
A_DQ36
A_DQ37
A_DQ38
A_DQ39

A_DQ40
A_DQ41
A_DQ42
A_DQ43
A_DQ44
A_DQ45
A_DQ46
A_DQ47

A_DQ48
A_DQ49
A_DQ50
A_DQ51
A_DQ52
A_DQ53
A_DQ54
A_DQ55

A_DQ56
A_DQ57
A_DQ58
A_DQ59
A_DQ60
A_DQ61
A_DQ62
A_DQ63

A_CB0

A_CB1

A_CB2

A_CB3

A_CB4

A_CB5

A_CB6

A_CB7

AK32
AH31
AH29
AF28
AJ33
AK33
AG30
AG29

AG27
AG26
AD24
AD23
AE28
AF27
AH25
AG24

AF21
AG21
AF19
AG18
AE22
AD21
AJ18
AG20

AF16
AF15
AE13
AD12
AE17
AJ15
AE16
AD17

AH4
AG5
AB8
AB7
AB10
AA9
AE5
AD5

U9
AA5
V6
U7
W10
U10
W5
V5

R6
R5
L7
L6
P9
T5
N8
M9

K5
J5
K8
K10
L9
L10
K7
H7

AJ9
AG11
AE11
AD11
AJ10
AH10
AF10
AE10

DDR2A_SD0_0
DDR2A_SD0_1
DDR2A_SD0_2
DDR2A_SD0_3
DDR2A_SD0_4
DDR2A_SD0_5
DDR2A_SD0_6
DDR2A_SD0_7

DDR2A_SD1_0
DDR2A_SD1_1
DDR2A_SD1_2
DDR2A_SD1_3
DDR2A_SD1_4
DDR2A_SD1_5
DDR2A_SD1_6
DDR2A_SD1_7

DDR2A_SD2_0
DDR2A_SD2_1
DDR2A_SD2_2
DDR2A_SD2_3
DDR2A_SD2_4
DDR2A_SD2_5
DDR2A_SD2_6
DDR2A_SD2_7

DDR2A_SD3_0
DDR2A_SD3_1
DDR2A_SD3_2
DDR2A_SD3_3
DDR2A_SD3_4
DDR2A_SD3_5
DDR2A_SD3_6
DDR2A_SD3_7

DDR2A_SD4_0
DDR2A_SD4_1
DDR2A_SD4_2
DDR2A_SD4_3
DDR2A_SD4_4
DDR2A_SD4_5
DDR2A_SD4_6
DDR2A_SD4_7

DDR2A_SD5_0
DDR2A_SD5_1
DDR2A_SD5_2
DDR2A_SD5_3
DDR2A_SD5_4
DDR2A_SD5_5
DDR2A_SD5_6
DDR2A_SD5_7

DDR2A_SD6_0
DDR2A_SD6_1
DDR2A_SD6_2
DDR2A_SD6_3
DDR2A_SD6_4
DDR2A_SD6_5
DDR2A_SD6_6
DDR2A_SD6_7

DDR2A_SD7_0
DDR2A_SD7_1
DDR2A_SD7_2
DDR2A_SD7_3
DDR2A_SD7_4
DDR2A_SD7_5
DDR2A_SD7_6
DDR2A_SD7_7

DDR2A_CB0
DDR2A_CB1
DDR2A_CB2
DDR2A_CB3
DDR2A_CB4
DDR2A_CB5
DDR2A_CB6
DDR2A_CB7

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

1

2

20
20
20
20
20
20
20
20

3

subsys done

These can be left floating

But BIOS must turn them off

A B

MCH & DDR TERM

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

INC.

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

DC

ROUND ROCK,TEXAS

REV.

A03-00

SHEET

16 OF 60

B D

CA

1

2

3

LINDENHURST MCH
MCH REFDES = MCH

MCH_HDACVREF

17

CK_167M_MCH_N

3

CK_167M_MCH_P

3

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

11
11

11
11

11

11
11

11
11
11
11
11
11

11
11
11
11

11
11
11
11
11

11

11
11

11,15

MCH_HCRES0

17

MCH_HODTCRES

17

MCH_HSLWCRES

17

H_ADS_N
H_A3_N
H_A4_N
H_A5_N
H_A6_N
H_A7_N
H_A8_N
H_A9_N
H_A10_N
H_A11_N
H_A12_N
H_A13_N
H_A14_N
H_A15_N
H_A16_N
H_A17_N
H_A18_N
H_A19_N
H_A20_N
H_A21_N
H_A22_N
H_A23_N
H_A24_N
H_A25_N
H_A26_N
H_A27_N
H_A28_N
H_A29_N
H_A30_N
H_A31_N
H_A32_N
H_A33_N
H_A34_N
H_A35_N

H_ADSTB0_N
H_ADSTB1_N

H_AP0_N
H_AP1_N

H_BPRI_N

H_BINIT_N
H_BNR_N

H_DRDY_N
H_DBSY_N
H_DEFER_N
H_HIT_N
H_HITM_N
H_LOCK_N

H_RS0_N
H_RS1_N
H_RS2_N
H_RSP_N

H_REQ0_N
H_REQ1_N
H_REQ2_N
H_REQ3_N
H_REQ4_N

H_TRDY_N

H_BREQ0_N
H_BREQ1_N

H_MCERR_N

ROOM=MCH

J11
K11
B27
K22
J20
G23
G22
H21
K19
H19
G19
E22
E21
F18
E19
F21
F20
D26
C26
A26
D22
B22
A25
B25
D25
C24
A22
B21
D23
A23
B24
A20
D19
C20
C21
D20

G20
C23

G25
H25

A28

G26
B31

B30
H27
B28
E30
D28
C30

F29
D31
G28
J26

K20
J21
J23
H22
K23

A30

F24
D29

H24

C27
E27
F26

E13
D13
F23

BCLKN
BCLKP
ADS
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

ADSTB0
ADSTB1

AP0
AP1

BPRI

BINIT
BNR

DRDY
DBSY
DEFER
HIT
HITM
LOCK

RS0
RS1
RS2
RSP

HREQ0
HREQ1
HREQ2
HREQ3
HREQ4

TRDY

BREQ0
BREQ1

MCERR

HCRES0
H0DTCRES
HSLWCRES

HDVREF1
HDVREF0
HACVREF

INTEL LINDENHURST MCH V0P21

MCH

HETERO 1 OF 7

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

DBINV0
DBINV1
DBINV2
DBINV3

DSTBN0
DSTBP0
DSTBN1
DSTBP1
DSTBN2
DSTBP2
DSTBN3
DSTBP3

C18
B19
C14
A17
A19
B16
C17
B18
D17
A16
B13
A14
A13
D14
C12
B12
E18
J18
H18
F17
G17
K17
E16
J17
J14
F14
F15
G16
K16
H16
G14
K14
E12
C11
H13
F11
G13
D11
E9
F12
G10
D8
H10
F8
J12
G11
K13
H12
B10
A10
A11
C9
B9
C8
B6
B7
E7
B4
A4
B3
D5
C6
D7
C5

C29
E28
E25
F27

D16
E15
F9
A5

B15
C15
H15
J15
D10
E10
A8
A7

H_DBI0_N
H_DBI1_N
H_DBI2_N
H_DBI3_N

H_DSTBN0_N
H_DSTBP0_N
H_DSTBN1_N
H_DSTBP1_N
H_DSTBN2_N
H_DSTBP2_N
H_DSTBN3_N
H_DSTBP3_N

H_D0_N
H_D1_N
H_D2_N
H_D3_N
H_D4_N
H_D5_N
H_D6_N
H_D7_N
H_D8_N

H_D9_N
H_D10_N
H_D11_N
H_D12_N
H_D13_N
H_D14_N
H_D15_N
H_D16_N
H_D17_N
H_D18_N
H_D19_N
H_D20_N
H_D21_N
H_D22_N
H_D23_N
H_D24_N
H_D25_N
H_D26_N
H_D27_N
H_D28_N
H_D29_N
H_D30_N
H_D31_N
H_D32_N
H_D33_N
H_D34_N
H_D35_N
H_D36_N
H_D37_N
H_D38_N
H_D39_N
H_D40_N
H_D41_N
H_D42_N
H_D43_N
H_D44_N
H_D45_N
H_D46_N
H_D47_N
H_D48_N
H_D49_N
H_D50_N
H_D51_N
H_D52_N
H_D53_N
H_D54_N
H_D55_N
H_D56_N
H_D57_N
H_D58_N
H_D59_N
H_D60_N
H_D61_N
H_D62_N
H_D63_N

H_DP0_N
H_DP1_N
H_DP2_N
H_DP3_N

11
11
11
11

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

11
11
11
11

11
11
11
11
11
11
11
11

ROOM = MCH

17
17
17
17
17

ITP_TMS_MCH
ITP_TDI_MCH
ITP_TDO_MCH
ITP_TRST_MCH_N
ITP_TCK1_MCH

+1.5V

R1313

1 2

43.2-1%

PROPAGATION_DELAY=L:S::750

+CPU_VTT

72

RN76

RN76

1K-5%

1K-5%

1 8

54

680-5%

RN76

R180

21

x00_tj_052003

1K-5%

EXP_A_UP_0P

31

EXP_A_UP_0N

31

EXP_A_UP_1P

31

EXP_A_UP_1N

31

EXP_A_UP_2P

31

EXP_A_UP_2N

31

EXP_A_UP_3P

31

EXP_A_UP_3N

31

EXP_A_UP_4P

31

EXP_A_UP_4N

31

EXP_A_UP_5P

31

EXP_A_UP_5N

31

EXP_A_UP_6P

31

EXP_A_UP_6N

31

EXP_A_UP_7P

31

EXP_A_UP_7N

31

EXP_B_UP_0P

31

EXP_B_UP_0N

31

EXP_B_UP_1P

31

EXP_B_UP_1N

31

EXP_B_UP_2P

31

EXP_B_UP_2N

31

EXP_B_UP_3P

31

EXP_B_UP_3N

31

EXP_B_UP_4P

29

EXP_B_UP_4N

29

EXP_B_UP_5P

29

EXP_B_UP_5N

29

EXP_B_UP_6P

29

EXP_B_UP_6N

29

EXP_B_UP_7P

29

EXP_B_UP_7N

29

EXP_C_UP_0P

31

EXP_C_UP_0N

31

EXP_C_UP_1P

31

EXP_C_UP_1N

31

EXP_C_UP_2P

31

EXP_C_UP_2N

31

EXP_C_UP_3P

31

EXP_C_UP_3N

31

EXP_C_UP_4P

31

EXP_C_UP_4N

31

EXP_C_UP_5P

31

EXP_C_UP_5N

31

EXP_C_UP_6P

31

EXP_C_UP_6N

31

EXP_C_UP_7P

31

EXP_C_UP_7N

31

RN76

3 6

1K-5%

11,15

33

33

33
33

18

18

5,33

17
17

CK_100M_MCH_P

4

CK_100M_MCH_N

4

NC_MCH_TESTIN_N
PCI_RST_MCH_N

5

H_RST_N

MCH_PME_N

MCH_GPE_N

HLA_STBS
HLA_STBF

HLA_MCH_SWING
CK_66M_MCH

3

HIRCOMP_MCH

HLA_MCH_VREF

SYSTEM_PWRGOOD_CHIPSET

ICH_SEG0_MCH_SCL
ICH_SEG0_MCH_SDA

ITP_TMS_MCH

17

ITP_TDI_MCH

17

ITP_TDO_MCH

17

ITP_TCK1_MCH

17

ITP_TRST_MCH_N

17

DDRCRES1

18

DDRCRES2

18

NC_MCH_AF30
NC_MCH_AE23
NC_MCH_AD20
NC_MCH_AJ19
NC_MCH_R10
NC_MCH_R9
NC_MCH_R8
NC_MCH_M8

ROOM=MCH

MCH

R33

EXP_A_RXP_0

P33

EXP_A_RXN_0

N28

EXP_A_RXP_1

N29

EXP_A_RXN_1

L31

EXP_A_RXP_2

L30

EXP_A_RXN_2

J33

EXP_A_RXP_3

J32

EXP_A_RXN_3

R26

EXP_A_RXP_4

R27

EXP_A_RXN_4

N25

EXP_A_RXP_5

N26

EXP_A_RXN_5

M27

EXP_A_RXP_6

M26

EXP_A_RXN_6

K29

EXP_A_RXP_7

K28

EXP_A_RXN_7

AG33
AF33

AE32
AD32

AC30
AD30

AC31
AB31
AD29

AE29

AC25
AC24

AB26
AB25

AA30
AA29

AF30
AE23
AD20
AJ19

EXP_B_RXP_0
EXP_B_RXN_0

EXP_B_RXP_1
EXP_B_RXN_1

EXP_B_RXP_2
EXP_B_RXN_2

EXP_B_RXP_3
EXP_B_RXN_3

EXP_B_RXP_4
EXP_B_RXN_4

EXP_B_RXP_5
EXP_B_RXN_5

EXP_B_RXP_6
EXP_B_RXN_6

Y25

EXP_B_RXP_7

Y24

EXP_B_RXN_7

Y28

EXP_C_RXP_0

Y27

EXP_C_RXN_0

Y30

EXP_C_RXP_1

Y31

EXP_C_RXN_1

EXP_C_RXP_2
EXP_C_RXN_2

V33

EXP_C_RXP_3

V32

EXP_C_RXN_3

T32

EXP_C_RXP_4

T31

EXP_C_RXN_4

R30

EXP_C_RXP_5

R29

EXP_C_RXN_5

V27

EXP_C_RXP_6

V26

EXP_C_RXN_6

V24

EXP_C_RXP_7

U24

EXP_C_RXN_7

T23 U33

EXP_CLK_P EXP_COMP0

R24

EXP_CLK_N

L12

TESTIN

C2

RESET_IN

J24

CPURST

M24

PME

L25

GPE

E31

HI_STBS

D32

HI_STBF

H31

HISWING

L24

HICLK

K25

HIRCOMP

F32

HIVREF

E3

PWRGOOD

C3

SMBCLK

D4

F3
G5
G6
D2
J9

AE2
AE1

R10

R9
R8
M8

SMBDATA

TMS
TDI
TDO
TCK
TRST

DDR_RES1
DDR_RES2
RESERVED_AF30
RESERVED_AE23
RESERVED_AD20
RESERVED_AJ19
RESERVED_R10
RESERVED_R9
RESERVED_R8
RESERVED_M8

3.3V

INTEL LINDENHURST MCH V0P21

HETERO 2 OR 7

EXP_A_TXP_0
EXP_A_TXN_0

EXP_A_TXP_1
EXP_A_TXN_1

EXP_A_TXP_2
EXP_A_TXN_2

EXP_A_TXP_3
EXP_A_TXN_3

EXP_A_TXP_4
EXP_A_TXN_4

EXP_A_TXP_5
EXP_A_TXN_5

EXP_A_TXP_6
EXP_A_TXN_6

EXP_A_TXP_7
EXP_A_TXN_7

EXP_B_TXP_0
EXP_B_TXN_0

EXP_B_TXP_1
EXP_B_TXN_1

EXP_B_TXP_2
EXP_B_TXN_2

EXP_B_TXP_3
EXP_B_TXN_3

EXP_B_TXP_4
EXP_B_TXN_4

EXP_B_TXP_5
EXP_B_TXN_5

EXP_B_TXP_6
EXP_B_TXN_6

EXP_B_TXP_7
EXP_B_TXN_7

EXP_C_TXP_0
EXP_C_TXN_0

EXP_C_TXP_1
EXP_C_TXN_1

EXP_C_TXP_2
EXP_C_TXN_2

EXP_C_TXP_3
EXP_C_TXN_3

EXP_C_TXP_4
EXP_C_TXN_4

EXP_C_TXP_5
EXP_C_TXN_5

EXP_C_TXP_6
EXP_C_TXN_6

EXP_C_TXP_7
EXP_C_TXN_7

EXP_COMP1

EXPHPINTR_N

VCCBGEXP
VSSBGEXP

V3REF

DDRSLWCRES

DDRCRES0

DDRIMPCRES

PLLSEL[1]
PLLSEL[0]

HI11
HI10

HI9
HI8
HI7
HI6
HI5
HI4
HI3
HI2
HI1
HI0

DEBUG7
DEBUG6
DEBUG5
DEBUG4
DEBUG3
DEBUG2
DEBUG1
DEBUG0

TDIOCATHODE

TDIOANODE

RESERVED_AA24

RESERVED_R32
RESERVED_L33

P30
P31

N31
N32

M33
M32

K32
K31

P24
P25

P27
P28

M30
M29

L28
L27

AG32
AH32

AF31
AE31

AC33
AD33

AB32
AA32

AD27
AD26

AC27
AC28

AB29
AB28

AA27
AA26

W26
W25

W28
W29

Y33
AA33

W32
W31

U31
U30

V30
V29

T29
T28

T26
T25

U25
E6
U27
U28

H33
AK1
AC9
AL2
A29
C31

G32
J29
E33
F30
J27
K26
H28
G29
G31
C32
H30
J30

D1
L11
D3
B2
H9
G8
G7
J8

F33
D33
AA24
R32
L33

(MCH_VSSBGEXP)

MCH_PLLSTRAP_1
MCH_PLLSTRAP_0

HLA_11
HLA_10

HLA_9
HLA_8
HLA_7
HLA_6
HLA_5
HLA_4
HLA_3
HLA_2
HLA_1
HLA_0

NC_ITP_MCH_DEBUG7
NC_ITP_MCH_DEBUG6
NC_ITP_MCH_DEBUG5
NC_ITP_MCH_DEBUG4
NC_ITP_MCH_DEBUG3
NC_ITP_MCH_DEBUG2
NC_ITP_MCH_DEBUG1
NC_ITP_MCH_DEBUG0

NC_MCH_TD_CATHODE

MCH_EXP_COMP

MCH_VCCBGEXP

DDRSLWCRES

DDRCRES0

DDRIMPCRES

33
33
33
33
33
33
33
33
33
33
33
33

NC_MCH_TD_ANODE
NC_MCH_RES_AA24

NC_MCH_RES_R32
NC_MCH_RES_L33

EXP_A_DN_0P_C
EXP_A_DN_0N_C

EXP_A_DN_1P_C
EXP_A_DN_1N_C

EXP_A_DN_2P_C
EXP_A_DN_2N_C

EXP_A_DN_3P_C
EXP_A_DN_3N_C

EXP_A_DN_4P_C
EXP_A_DN_4N_C

EXP_A_DN_5P_C
EXP_A_DN_5N_C

EXP_A_DN_6P_C
EXP_A_DN_6N_C

EXP_A_DN_7P_C
EXP_A_DN_7N_C

EXP_B_DN_0P_C
EXP_B_DN_0N_C

EXP_B_DN_1P_C
EXP_B_DN_1N_C

EXP_B_DN_2P_C
EXP_B_DN_2N_C

EXP_B_DN_3P_C
EXP_B_DN_3N_C

EXP_B_DN_4P_C
EXP_B_DN_4N_C

EXP_B_DN_5P_C
EXP_B_DN_5N_C

EXP_B_DN_6P_C
EXP_B_DN_6N_C

EXP_B_DN_7P_C
EXP_B_DN_7N_C

EXP_C_DN_0P_C
EXP_C_DN_0N_C

EXP_C_DN_1P_C
EXP_C_DN_1N_C

EXP_C_DN_2P_C
EXP_C_DN_2N_C

EXP_C_DN_3P_C
EXP_C_DN_3N_C

EXP_C_DN_4P_C
EXP_C_DN_4N_C

EXP_C_DN_5P_C
EXP_C_DN_5N_C

EXP_C_DN_6P_C
EXP_C_DN_6N_C

EXP_C_DN_7P_C
EXP_C_DN_7N_C

17

18
18
18

x02_tj_091903

+1.5V

NP

R1605

X

1 2

220

21

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

R1606

1K-5%

+1.5V+3.3V

NP

21

R1082

X

220

+1.5V

R1001

1 2

1K-5%

R1247

21

24.9-1%

4.7K

+3.3V

21

R1604

C1738

1 2

MCH_EXPHPINTR_N

.1uF

10V-10%

+3.3V

R5

2 1

220

D33

31

R12

C1119

EXP_A_DN_0P_C

17

EXP_A_DN_0N_C

17

EXP_A_DN_1P_C

17

EXP_A_DN_1N_C

17

EXP_A_DN_2P_C

17

EXP_A_DN_2N_C

17

EXP_A_DN_3P_C

17

EXP_A_DN_3N_C

17

EXP_A_DN_4P_C

17

EXP_A_DN_4N_C

17

EXP_A_DN_5P_C

17

EXP_A_DN_5N_C

17

EXP_A_DN_6P_C

17

EXP_A_DN_6N_C

17

EXP_A_DN_7P_C

17

EXP_A_DN_7N_C

17

21

.1uF

10V-10%

C1121

21

.1uF

10V-10%

C1126

21

.1uF

10V-10%

C1124

21

.1uF

10V-10%

C1134

21

.1uF

10V-10%

C1132

21

.1uF

10V-10%

C1130

21

.1uF

10V-10%

C1128

21

.1uF

10V-10%

C1120

21

.1uF

10V-10%

C1122

21

.1uF

10V-10%

C1125

21

.1uF

10V-10%

C1123

21

.1uF

10V-10%

C1133

21

.1uF

10V-10%

C1131

21

.1uF

10V-10%

C1129

21

.1uF

10V-10%

C1127

21

EXP_A_DN_0P

EXP_A_DN_0N

EXP_A_DN_1P

EXP_A_DN_1N

EXP_A_DN_2P

EXP_A_DN_2N

EXP_A_DN_3P

EXP_A_DN_3N

EXP_A_DN_4P

EXP_A_DN_4N

EXP_A_DN_5P

EXP_A_DN_5N

EXP_A_DN_6P

EXP_A_DN_6N

EXP_A_DN_7P

EXP_A_DN_7N

31

31

31

31

31

31

1

31

31

31

31

31

31

31

31

31

31

.1uF

10V-10%

C1150

EXP_B_DN_0P_C

17

EXP_B_DN_0N_C

17

EXP_B_DN_1P_C

17

EXP_B_DN_1N_C

17

EXP_B_DN_2P_C

17

EXP_B_DN_2N_C

17

EXP_B_DN_3P_C

17

EXP_B_DN_3N_C

17

EXP_B_DN_4P_C

17

EXP_B_DN_4N_C

17

EXP_B_DN_5P_C

17

EXP_B_DN_5N_C

17

EXP_B_DN_6P_C

17

EXP_B_DN_6N_C

17

EXP_B_DN_7P_C

17

EXP_B_DN_7N_C

17

21

.1uF

10V-10%

C1148

21

.1uF

10V-10%

C1146

21

.1uF

10V-10%

C1144

21

.1uF

10V-10%

C1142

21

.1uF

10V-10%

C1140

21

.1uF

10V-10%

C1138

21

.1uF

10V-10%

C1136

21

.1uF

10V-10%

C1149

21

.1uF

10V-10%

C1147

21

.1uF

10V-10%

C1145

21

.1uF

10V-10%

C1143

21

.1uF

10V-10%

C1141

21

.1uF

10V-10%

C1139

21

.1uF

10V-10%

C1137

21

.1uF

10V-10%

C1135

21

EXP_B_DN_0P

EXP_B_DN_0N

EXP_B_DN_1P

EXP_B_DN_1N

EXP_B_DN_2P

EXP_B_DN_2N

EXP_B_DN_3P

EXP_B_DN_3N

EXP_B_DN_4P

EXP_B_DN_4N

EXP_B_DN_5P

EXP_B_DN_5N

EXP_B_DN_6P

EXP_B_DN_6N

EXP_B_DN_7P

EXP_B_DN_7N

31

31

31

31

31

31

2

31

31

27

27

27

27

27

27

27

27

.1uF

10V-10%

C1151

EXP_C_DN_0P_C

17

EXP_C_DN_0N_C

17

EXP_C_DN_1P_C

17

EXP_C_DN_1N_C

17

EXP_C_DN_2P_C

17

EXP_C_DN_2N_C

17

EXP_C_DN_3P_C

17

EXP_C_DN_3N_C

17

EXP_C_DN_4P_C

17

EXP_C_DN_4N_C

17

EXP_C_DN_5P_C

17

EXP_C_DN_5N_C

17

EXP_C_DN_6P_C

17

EXP_C_DN_6N_C

17

EXP_C_DN_7P_C

17

EXP_C_DN_7N_C

17

21

.1uF

10V-10%

C1153

21

.1uF

10V-10%

C1155

21

.1uF

10V-10%

C1157

21

.1uF

10V-10%

C1159

21

.1uF

10V-10%

C1161

21

.1uF

10V-10%

C1163

21

.1uF

10V-10%

C1165

21

.1uF

10V-10%

C1152

21

.1uF

10V-10%

C1154

21

.1uF

10V-10%

C1156

21

.1uF

10V-10%

C1158

21

.1uF

10V-10%

C1160

21

.1uF

10V-10%

C1162

21

.1uF

10V-10%

C1164

21

.1uF

10V-10%

C1166

21

EXP_C_DN_0P

EXP_C_DN_0N

EXP_C_DN_1P

EXP_C_DN_1N

EXP_C_DN_2P

EXP_C_DN_2N

EXP_C_DN_3P

EXP_C_DN_3N

EXP_C_DN_4P

EXP_C_DN_4N

EXP_C_DN_5P

EXP_C_DN_5N

EXP_C_DN_6P

EXP_C_DN_6N

EXP_C_DN_7P

EXP_C_DN_7N

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

3

.1uF

10V-10%

NET_PHYSICAL_TYPE=PWR
PROPAGATION_DELAY=L:S::1200

R1833

1 2

1 2

1-1%

21

X00_TJ_060403

1K-1%1K-1%

x00_tt_052903

L131

4.7uH 80mA

MCH_VCCBGEXP

17

10uF 6.3V

1 2

C1661

10uF 6.3V

C823

21

0.1uF 16V
1 2

C195

+CPU_VTT

+3.3V

TLV431A

53

4

x00_tj_051203

100K-1%

R2

R181

4 4

12

2.5V Generation

INC.

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

12/16/2004

ROUND ROCK,TEXAS

REV.

A03-00

SHEET

17 OF 60

17

17
17

MCH_HCRES0

MCH_HODTCRES
MCH_HSLWCRES

21

R982

49.9-1%

48.7-1%
SUB*_X5575

x04_sdx04_sd

R1057

1 2

549-1%

442-1%

17

SUB*_0K260

MCH_HDACVREF

MRGN_MHDAC

1

1
3 4

TSM 2X2
SMT HDR

R983

1 2

49.9-1%

R1406

775mV

750-1%

21

R1547

C1198

2

2

43

12

NP01

220pF

50V-10%

21

C1191

1uF

10V-10%

R378

1 2

x04_sd

90.9-1%

27,31,35

27,31,35

ICH_SEG0_SDA

ICH_SEG0_SCL

NP*

R1425

1 2

220

R1424

220

x04_tj_031604

ICH_SEG0_MCH_SDA

21

ICH_SEG0_MCH_SCL

1 2

21

R1407

8.2K-5%

NP*

NET_PHYSICAL_TYPE=PWR
PROPAGATION_DELAY=L:S::1200

8.2K-5%

NP*

17

MCH & PCI EXPRESS CAPS

17

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

1 2

subsys done

A B

DC

B D

CA

+CPU_VTT

18

PROPAGATION_DELAY=L:S::700
NET_PHYSICAL_TYPE=50MIL

MCH_VCCA_VCORE

L113

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

MCH_VCCA_VCORE_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

R1173

1 2

1-1%

+1.5V

LINDENHURST MCH

21

ROOM = MCH

+1.8V

+1.5V

MCH

MCH REFDES = MCH

F1

VDDR_F1

H5

VDDR_H5

K3

MCH

A21

GND-A21

A24

GND-A24

A27

1

2

3

4 4

GND-A27

B5

GND-B5

B8

GND-B8

B11

GND-B11

B14

GND-B14

B17

GND-B17

B20

GND-B20

B23

GND-B23

B26

GND-B26

B29

GND-B29

C1

GND-C1

C4

GND-C4

C7

GND-C7

C10

GND-C10

C13

GND-C13

C16

GND-C16

C19

GND-C19

C22

GND-C22

C25

GND-C25

C28

GND-C28

B32

GND-B32

D6

GND-D6

D9

GND-D9

D12

GND-D12

D15

GND-D15

D18

GND-D18

D21

GND-D21

D24

GND-D24

E2

GND-E2

E5

GND-E5

E24

GND-E24

E26

GND-E26

E29

GND-E29

E32

GND-E32

F4

GND-F4

F7

GND-F7

F10

GND-F10

F13

GND-F13

F16

GND-F16

F19

GND-F19

F22

GND-F22

F25

GND-F25

F28

GND-F28

F31

GND-F31

G3

GND-G3

G9

GND-G9

G12

GND-G12

G15

GND-G15

G18

GND-G18

G21

GND-G21

G24

GND-G24

G27

GND-G27

G30

GND-G30

H2

GND-H2

H8

GND-H8

H11

GND-H11

H14

GND-H14

H17

GND-H17

H20

GND-H20

H32

GND-H32

J1

GND-J1

J4

GND-J4

J7

GND-J7

J10

GND-J10

J22

GND-J22

J25

GND-J25

J28

GND-J28

J31

GND-J31

K6

GND-K6

K12

GND-K12

K15

GND-K15

K18

GND-K18

K21

GND-K21

K24

GND-K24

L2

GND-L2

L5

GND-L5

L8

GND-L8

L14

GND-L14

L16

GND-L16

L18

GND-L18

L20

GND-L20

L22

GND-L22

L26

GND-L26

L29

GND-L29

L32

GND-L32

M4

GND-M4

M10

GND-M10

M11

GND-M11

M13

GND-M13

M15

GND-M15

M17

GND-M17

M19

GND-M19

M21

GND-M21

M23

GND-M23

M25

GND-M25

M31

GND-M31

N3

GND-N3

N6

GND-N6

N9

GND-N9

N12

GND-N12

N14

GND-N14

N16

GND-N16

N18

GND-N18

N20

GND-N20

N22

GND-N22

N24

GND-N24

N27

GND-N27

N30

GND-N30

P2

GND-P2

P8

GND-P8

P11

GND-P11

P13

GND-P13

P15

GND-P15

ROOM=MCH

INTEL LINDENHURST MCH V0P21

HETERO 7 OF 7

GND-P17
GND-P19
GND-P23
GND-P26
GND-P32

GND-R1
GND-R4

GND-R7
GND-R12
GND-R14
GND-R16
GND-R18
GND-R20
GND-R22
GND-R25
GND-R28
GND-R31

GND-T6
GND-T11
GND-T13
GND-T15
GND-T17
GND-T19
GND-T21
GND-T30

GND-U2

GND-U5

GND-U8
GND-U12
GND-U14
GND-U16
GND-U18
GND-U20
GND-U22
GND-U26
GND-U32

GND-V4
GND-V10
GND-V11
GND-V13
GND-V15
GND-V17
GND-V19
GND-V21
GND-V25
GND-V28
GND-V31

GND-W3

GND-W6

GND-W9
GND-W12
GND-W14
GND-W16
GND-W18
GND-W20
GND-W22
GND-W24
GND-W30

GND-Y2

GND-Y8
GND-Y11
GND-Y13
GND-Y15
GND-Y17
GND-Y19
GND-Y21
GND-Y23
GND-Y26
GND-Y32
GND-AA1
GND-AA4
GND-AA7

GND-AA10
GND-AA12
GND-AA14
GND-AA16
GND-AA18
GND-AA20
GND-AA22
GND-AA25
GND-AA28
GND-AA31

GND-AB6

GND-AB11

GND-AB13
GND-AB15
GND-AB17
GND-AB19
GND-AB21
GND-AB23
GND-AB30

GND-AC2
GND-AC5
GND-AC8

GND-AC12
GND-AC14
GND-AC16
GND-AC18
GND-AC20
GND-AC22
GND-AC26
GND-AC32

GND-AD4

GND-AD10
GND-AD13
GND-AD16
GND-AD19
GND-AD22
GND-AD25
GND-AD28
GND-AD31

GND-AE3
GND-AE6
GND-AE9

VSSA_CORE

VSSA_HI

VSSA_EXP

P17
P19
P23
P26
P32
R1
R4
R7
R12
R14
R16
R18
R20
R22
R25
R28
R31
T6
T11
T13
T15
T17
T19
T21
T30
U2
U5
U8
U12
U14
U16
U18
U20
U22
U26
U32
V4
V10
V11
V13
V15
V17
V19
V21
V25
V28
V31
W3
W6
W9
W12
W14
W16
W18
W20
W22
W24
W30
Y2
Y8
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y26
Y32
AA1
AA4
AA7
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AA28
AA31
AB6
AB11

AB13
AB15
AB17
AB19
AB21
AB23
AB30
AC2
AC5
AC8
AC12
AC14
AC16
AC18
AC20
AC22
AC26
AC32
AD4
AD10
AD13
AD16
AD19
AD22
AD25
AD28
AD31
AE3
AE6
AE9

F5
P21
V23

MCH_VSSA_SB
MCH_VSSA_HI
MCH_VSSA_EXP

18
18
18

AE15
AE21
AE27

AF2
AF8

AF11

AF14
AF17
AF20
AF23
AF26
AF29
AF32

AG1
AG4

AG7
AG13
AG19
AG25
AG31

AH9
AH12
AH15
AH18
AH21
AH24
AH27
AH30

AJ2

AJ5
AJ11

ROOM=MCH

MCH

GND-AE15
GND-AE21
GND-AE27
GND-AF2
GND-AF8
GND-AF11

GND-AF14
GND-AF17
GND-AF20
GND-AF23
GND-AF26
GND-AF29
GND-AF32
GND-AG1
GND-AG4
GND-AG7
GND-AG13
GND-AG19
GND-AG25
GND-AG31
GND-AH9
GND-AH12
GND-AH15
GND-AH18
GND-AH21
GND-AH24
GND-AH27
GND-AH30
GND-AJ2
GND-AJ5
GND-AJ11

INTEL LINDENHURST MCH V0P21

HETERO 6 OF 7

GND-AJ17
GND-AJ23
GND-AJ29
GND-AJ32

GND-AK4

GND-AK7
GND-AK10
GND-AK13
GND-AK16
GND-AK19
GND-AK22
GND-AK25
GND-AK28
GND-AK31

GND-AL3

GND-AL9
GND-AL15

GND-AL21
GND-AL27
GND-AL33

GND-AM2

GND-AM5

GND-AM8
GND-AM11
GND-AM14
GND-AM17
GND-AM20
GND-AM23
GND-AM26
GND-AM29
GND-AM32

GND-AN7
GND-AN13
GND-AN19
GND-AN25
GND-AN31

AJ17
AJ23
AJ29
AJ32
AK4
AK7
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK31
AL3
AL9
AL15

AL21
AL27
AL33
AM2
AM5
AM8
AM11
AM14
AM17
AM20
AM23
AM26
AM29
AM32
AN7
AN13
AN19
AN25
AN31

+1.5V

N11

P12
R11

T12
U11

V12
W11

Y12

AA11

AB3

AB9
AB12
AB14
AB16
AB18
AB20
AB22
AC11
AC13
AC15
AC17
AC19
AC21
AC23

AD1

AD7
AE12
AE18
AE24

AF5
AG10
AG16
AG22
AG28

AH3

AJ8
AJ14
AJ20
AJ26

AL1

AL6
AL12
AL18
AL24
AL30

AN3
AN10
AN16
AN22
AN28

K30

K33

M28

N33

P29

R23

T22

T24

T27

T33

U29

V22

W23

W27

W33

Y22

Y29
AA23
AB24
AB27
AB33
AC29
AE30
AE33
AH33

M1
M7

P5

T3
T9

V1
V7

Y5

VDDR_K3
VDDR_M1
VDDR_M7
VDDR_N11
VDDR_P5
VDDR_P12
VDDR_R11
VDDR_T3
VDDR_T9
VDDR_T12
VDDR_U11
VDDR_V1
VDDR_V7
VDDR_V12
VDDR_W11
VDDR_Y5
VDDR_Y12
VDDR_AA11
VDDR_AB3
VDDR_AB9
VDDR_AB12
VDDR_AB14
VDDR_AB16
VDDR_AB18
VDDR_AB20
VDDR_AB22
VDDR_AC11
VDDR_AC13
VDDR_AC15
VDDR_AC17
VDDR_AC19
VDDR_AC21
VDDR_AC23
VDDR_AD1
VDDR_AD7
VDDR_AE12
VDDR_AE18
VDDR_AE24
VDDR_AF5
VDDR_AG10
VDDR_AG16
VDDR_AG22
VDDR_AG28
VDDR_AH3
VDDR_AJ8
VDDR_AJ14
VDDR_AJ20
VDDR_AJ26
VDDR_AL1
VDDR_AL6
VDDR_AL12
VDDR_AL18
VDDR_AL24
VDDR_AL30
VDDR_AN3
VDDR_AN10
VDDR_AN16
VDDR_AN22
VDDR_AN28

VEXP_K30
VEXP_K33
VEXP_M28
VEXP_N33
VEXP_P29
VEXP_R23
VEXP_T22
VEXP_T24
VEXP_T27
VEXP_T33
VEXP_U29
VEXP_V22
VEXP_W23
VEXP_W27
VEXP_W33
VEXP_Y22
VEXP_Y29
VEXP_AA23
VEXP_AB24
VEXP_AB27
VEXP_AB33
VEXP_AC29
VEXP_AE30
VEXP_AE33
VEXP_AH33

INTEL LINDENHURST MCH V0P21

HETERO 5 OF 7

ROOM=MCH

VCORE_C33
VCORE_G33
VCORE_H29

VCORE_K9
VCORE_K27
VCORE_L23
VCORE_M12
VCORE_M22
VCORE_N13
VCORE_N15
VCORE_N17
VCORE_N19
VCORE_N21
VCORE_N23
VCORE_P14
VCORE_P16
VCORE_P18
VCORE_P22
VCORE_R13
VCORE_R15
VCORE_R17
VCORE_R19
VCORE_R21
VCORE_T14
VCORE_T16
VCORE_T18
VCORE_T20

VCORE-U13
VCORE-U15
VCORE_U17
VCORE_U19
VCORE_U21
VCORE_V14
VCORE_V16
VCORE_V18
VCORE_V20
VCORE_W13
VCORE_W15
VCORE_W17
VCORE_W19
VCORE_W21
VCORE_Y14
VCORE_Y16
VCORE_Y18
VCORE_Y20

VCORE_AA13
VCORE_AA15
VCORE_AA17
VCORE_AA19
VCORE_AA21

VTT_A3
VTT_A6

VTT_A9
VTT_A12
VTT_A15
VTT_A18
VTT_A31
VTT_D27
VTT_D30

VTT_E8
VTT_E11
VTT_E14
VTT_E17
VTT_E20
VTT_E23
VTT_H23
VTT_H26
VTT_J13
VTT_J16
VTT_J19
VTT_L13
VTT_L15
VTT_L17
VTT_L19
VTT_L21
VTT_M14
VTT_M16
VTT_M18
VTT_M20

VCCA_CORE

VCCA_DDR
VCCA_EXP

VCCA_HI

C33
G33
H29
K9
K27
L23
M12
M22
N13
N15
N17
N19
N21
N23
P14
P16
P18
P22
R13
R15
R17
R19
R21
T14
T16
T18
T20

U13
U15
U17
U19
U21
V14
V16
V18
V20
W13
W15
W17
W19
W21
Y14
Y16
Y18
Y20
AA13
AA15
AA17
AA19
AA21

A3
A6
A9
A12
A15
A18
A31
D27
D30
E8
E11
E14
E17
E20
E23
H23
H26
J13
J16
J19
L13
L15
L17
L19
L21
M14
M16
M18
M20

F6
E4
U23
P20

+1.5V

+CPU_VTT

MCH_VCCA_VCORE
MCH_VCCA_DDR
MCH_VCCA_EXP
MCH_VCCA_HI

18
18
18
18

To be placed near hub link on MCH

C636

1 2

MCH POWER

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL INC. ROUND ROCK, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL INC. EXCEPT
AS AUTHORIZED BY DELL INC., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL INC. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL INC.

21

C1169

21

C401

.01uF 50V

C1170

1 2

0.1uF 16V

C142

0.1uF 16V

1
3 4

1 2

MRGN_MHVS

1
3 4

21

C1171

0.1uF 16V

C637

0.1uF 16V

TSM 2X2
SMT HDR

0.1uF 16V

@MCH

1 2

.01uF 50V

2

2

NP*

+1.5V

R234

1 2

21

R551

2.7K-5%

21

43.2-1%49.9-1%

NP01R582

MCH HLA VREF
& VSWING

R276

1 2

NET_PHYSICAL_TYPE=PWR

NET_PHYSICAL_TYPE=PWR

R537

1 2

24.3-1% 78.7-1%

MRGN_MHVR

1

1
3 4

TSM 2X2
SMT HDR

HLA_MCH_SWING

(804mv)

HLA_MCH_VREF

(353mv)

2.7K-5%

2

2

43

NP*

17

1 2

17

R553

NP01

18

18

PROPAGATION_DELAY=L:S::600
NET_PHYSICAL_TYPE=50MIL

18

PROPAGATION_DELAY=L:S::600
NET_PHYSICAL_TYPE=50MIL

18

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=50MIL

18

PROPAGATION_DELAY=L:S::1400
NET_PHYSICAL_TYPE=50MIL

18

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MIL

18

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_SB

MCH_VCCA_DDR

MCH_VSSA_SB

MCH_VCCA_EXP

MCH_VSSA_EXP

MCH_VCCA_HI

MCH_VSSA_HI

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1000

1 2

C1589

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1300

PROPAGATION_DELAY=L:S::1000

10uF 6.3V

x00_tj_042903

17

17

C1236

1 2

C1238

21

C1240

1 2

C1242

17

17

17

C1226

10uF 6.3V

C1225

10uF 6.3V

C1227

10uF 6.3V

C1228

10uF 6.3V

DDRCRES2

DDRCRES1

1 2

0.1uF 16V0.1uF 16V

21

21

0.1uF 16V

1 2

0.1uF 16V

DDRIMPCRES

DDRCRES0

DDRSLWCRES

L112

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

L111

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

L110

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

23.4mA

MCH_VCCA_DDR_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

23.4mA

21

MCH_VCCA_EXP_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

21.3mA

MCH_VCCA_HI_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

24.7mA

PN 7H671

ESR = 300mohm

Max current = 80mA
Inductance = 4.7uH

R1031

1 2

287-1%

R1004

1 2

1.05K-1%

976-1%

x04_tj_032904

R1573

40.2-0.5%

C1173

1 2

R1574

1 2

40.2-0.5%

21

C1172

0.1uF 16V 0.1uF 16V

MCH Power & Ground

D1660

12/16/2004

21

INC.

x00_tj_051203
x00_tj_052903
x02_tj_100703

x00_tj_052903

1 2

1 2

x00_tj_052903

SUB=SUB*_C6435

+1.8V

ROUND ROCK,TEXAS

SHEET

18 OF 60

R1174

1-1%

R1175

.499-1%

R1176

1-1%

REV.

+1.5V

21

1

+1.5V

+1.5V

2

3

A03-00

subsys done

A B

DC