MSI MS-9154 Schematic 00

A B C

Dell Controlled Print

REVISIONS

REV

A00-00

ECO161177

DESCRIPTIONECO DATE

RELEASE FOR PRODUCTION 06/23/2004

TABLE OF CONTENTS

Page 1. Page 2. Page 3. Page 4. Page 5. Page 6. Page 7. Page 8. Page 9. Page 10. Page 11. Page 12. Page 13. Page 14. Page 15. Page 16. Page 17. Page 18. Page 19. Page 20. Page 21. Page 22. Page 23. Page 24. Page 25. Page 26. Page 27. Page 28. Page 29. Page 30. Page 31. Page 32. Page 33. Page 34. Page 35. Page 36. Page 37. Page 38. Page 39. Page 40. Page 41. Page 42. Page 43. Page 44. Page 45. Page 46. Page 47. Page 48. Page 49. Page 50. Page 51. Page 52. Page 53. Page 54. Page 55. FWH Page 56. Page 57. Page 58. Page 59.

BLOCK DIAGRAM CLOCK DIAGRAM Clock Synth. Differential Buffer DB800 System CPLD Voltage Regulators VRD VRD VRD

---blank--Processors Processors Processors

---blank--ITP 32 & Level Translation Circuits MCH, memory MCH, GTL, Exp, Hub-link MCH, power Decoupling Caps DDR2 DDR2 DDR2, routing diagram DDR2, VRef Gigabit Ethernet Gigabit Ethernet Gigabit Ethernet PXH PXH PXH PXH Connectors Connectors ICH5 ICH5 Keyboard, Mouse, COM Ports, I2C MUX/Table Radeon Video Radeon Video Radeon Video Radeon Video Super I/O, 373 Battery / Intrusion Detect / RAID Key / VAux Pwrgood Fans and fan LED's Parallel Port / ID Button / Rear Cyclops / Speaker BMC BMC BMC BMC BMC, Serial Port Muxing BMC - Serial Port MUXing Diagram RAC

1.2V Vtt generation Fan PWM Controllers MicroVu VAux reset

USB / Buttons Spares / Coupons / Hardware PCI bus p/u's / PCI Debug Slot Debug Features

APPROVED

JIM HUNT

1U PWA assembly

2U/5U PWA assembly

P# F1667 P# H1754

XLBOM Build Options

1U, Production 2U/5U Production

0 1 21U, Debug

2U/5U Debug

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

PWB/Silk Color

Red White Blue x01

White

x00

Clear White x02 Green Yellow x03

White x03Green

Green White a00

Big Bend, Kobuk, Corvette

PWA: H1754

PWB:

SCHEM:

ASSY DWG:

THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

D1656 D1660 D1657

PROPRIETARY NOTE

UNIPLANAR

aka LINDY PLANAR

DRAWN

Uniplanar Team:

DESIGNED

CHECKED

APPROVED

-Shawn Dube

APPROVED

-Jinsaku Masuyama

APPROVED

-Garnett Thompson

APPROVED

-TJ Thompson

RELEASED

XLBOM Build option table

0 Production Build 9 Prototype Build

A CURRENT ISSUE OF THIS DRAWING MUST INCLUDE A COPY OF THE FOLLOWING ECO'S: ECO

ECO ECO ECO ECO ECO ECO ECO

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

DATE DATE DATE DATE DATE DATE DATE DATE

COMPUTER CORPORATION AUSTIN,TEXAS

SHEET

7/14/2004

REV.

A00-00D1660

1 OF 60

DCBA

B D

CLOCK DISTRIBUTION

BLOCK DIAGRAM

7-14-2004_10:52

4 4

USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH

OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE

AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

D1660

SHEET

7/14/2004

REV.

A00-00

2 OF 60

A B

B D

V_3P3_CLK

7-14-2004_10:52

+3.3V

1 2

C1093

L103

BLM18BD601SN1

L105

BLM18BD601SN1

0.1uF 16V

R1476

R1420

4,35

V_3P3_CLK

1 2

C1094

0.1uF 16V

C1209

C1103

10uF 6.3V

1 2

0.1uF 16V

1 2

C1102

C1101

0.1uF 16V

1 2

0.1uF 16V

1 2

C1100

1 2

C1104

0.1uF 16V

1 2

C1099

0.1uF 16V

1 2

C1098

0.1uF 16V

1 2

C1096

0.1uF 16V

1 2

C1097

0.1uF 16V

ICH_SEG2_SDA

ICH_SEG2_SCL

0-5%

R1421

1 2

0-5%

ICH_SEG2_409_SDA

ICH_SEG2_409_SCL

4.7K

R1477

NP*

4.7K

1 2

NP*

ECAD Note:

VCC routing should be from plane, through high-f cap, to pin

U1084 300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V KOA CZB2BFL-301P

May need to tune caps during UT

V_3P3_CLK

C757

50V-10%

x03_tj_121503

0.1uF 16V

2 1

27pF

C1090

R606

2.2-5%

X10

1 2

14.31818MHz

R947

2 1

1M-5%

50V-10%

C756

27pF

C759

0.1uF 16V

C1091

+3.3V

1 2

C1105

0.1uF 16V

10uF 6.3V

x00_tj_050503

SUB*_U1084

L129

1 2

ILB_1206

300OHM, 300 mA

CK_FSB

1 2

C1092

V_3P3_CLK_VDD48

CK_FSA

C758

0.1uF 16V

PROPAGATION_DELAY=L:S::1000

NET_PHYSICAL_TYPE=50MIL

R1419

0-5%

V_3P3_CLK_VDDA

1 2

10uF 6.3V

1 2

R1002

x02_sd

PROPAGATION_DELAY=L:S::1000 NET_PHYSICAL_TYPE=50MIL

R1022

0-5%

5,59

4,5,59

475-1%

IREF = 2.32mA

R46

4.7K

R1008

1 2

CK_VTT_PWRGD_N CK_PWRDWN_N

C1326

0.1uF 16V

NP*

4.7K

R1018

x00_tj_051203

4.7K

1 2

NP*

R1007

C778

1 2

PART_NUMBER=79015

4.7K

R1475

1 2

C779

PART_NUMBER=79015

CK_XTAL_IN CK_XTAL_OUT

CK_FSA_R CK_FSB_R CK_IREF

ICH_SEG2_409_SDA

ICH_SEG2_409_SCL

1K-1%

C777

1000pF

50V-10%

1000pF

50V-10%

1000pF

50V-10%

PART_NUMBER=79015

C780

1 2

1000pF

50V-10%

PART_NUMBER=79015

CK409B for Proto builds

VDD_REF

VDD_PCI_1

VDD_PCI_2

VDD_3V66

VDD_ANLG

VDD_48MHZ

VDD_CPU_1

VDD_CPU_2

VDD_SRC

XTALIN

XTALOUT

FS_A

FS_B

IREF

VTT_PWRGD

PWR_DOWN

SDATA

SCLK

GND_REF

GND_PCI_1

GND_PCI_2

GND_3V66

GND_SRC

GND_48MHZ

GND_IREF

GND_CPU

GND_ANLG

x00_tj_052003

CK409B

REF0 REF1

PCI_F0 PCI_F1 PCI_F2

PCI0 PCI1 PCI2 PCI3 PCI4 PCI5 PCI6

SRC_P SRC_N

3V66_0 3V66_1 3V66_2 3V66_3

3V66_4/VCH

CPU_P0 CPU_N0 CPU_P1 CPU_N1 CPU_P2 CPU_N2 CPU_P3 CPU_N3

CK409 - TSSOP56

SMBus address = D2h

USB DOT

1 2

7 8 9 12 13 14 15 18 19 20

31 32

38 37

22 23 26 27 29

41 40 44 43 47 46 50 49

CK_14M_ICHS_R CK_14M_SIO_R

CK_33M_ICHS_R CK_33M_SIO_R CK_33M_FWH_R CK_33M_SLOT3_R CK_33M_PCI0_DEBUG_R CK_33M_BMC_R CK_33M_CPLD_R CK_33M_DBG_LPC_R CK_33M_VIDEO_R CK_33M_RAC_R

CK_48M_USB_ICHS_R CK_48M_SIO_R

CK_66M_MCH_R CK_66M_ICH_R CK_66M_3V66_2 CK_66M_LAI_R

CK_167M_CPU1_P_R CK_167M_CPU1_N_R CK_167M_CPU2_P_R CK_167M_CPU2_N_R CK_167M_MCH_P_R CK_167M_MCH_N_R CK_167M_ITP_P_R CK_167M_ITP_N_R

CK_100M_DB800_P_R CK_100M_DB800_N_R

R1417

1 2

R1017

1K-1%

R956

1 2

33-5%

R957

1 2

33-5%

R1361

1 2

33-5%

+3.3V

NP*

R593

1K-1%

R964

CK_14M_ICHS

CK_14M_SIO

33-5%

R955

33-5%

R954

33-5%

R1362

1 2

33-5%

R949

33-5%

R1416

CK_33M_ICHS

CK_33M_SIO

CK_33M_FWH

CK_33M_SLOT1

CK_33M_PCI0_DEBUG

x00_tj_051503

1K-1% R1363

33-5%

R959

NC_CK_48M_SIO

R962

33-5%

R963

33-5%

CK-409 support Place close to ICH

R142921R1712

1 2

33-5%

49.9-1%

CK_100M_DB800_P CK_100M_DB800_N

49.9-1%

33-5%

R965

33-5%

R966

33-5%

R967

33-5%

CK_48M_USB_ICHS

R960

33-5%

R961

R952

33-5%

R968

33-5%

R969

33-5%

R1036

4 4

49.9-1%

R1039

49.9-1%

R1038

49.9-1%

R1364

1 2

33-5%

R1366

33-5%

R1367

1 2

33-5%

R38

NP*

CK_33M_BMC

CK_33M_CPLD

CK_33M_SMARTVU

CK_33M_VIDEO

CK_33M_RAC

CK_66M_MCH

CK_66M_ICH

CK_167M_CPU1_P

CK_167M_CPU1_N

CK_167M_CPU2_P

CK_167M_CPU2_N

CK_167M_MCH_P

CK_167M_MCH_N

5,59

To CPLD and Mictor header

Spread spectrum Controlled through I2C

CK409B / CK409 Operation

FSA

FSB SPEEDFSB

All clk _R nets have a hidden prop-delay max of 500mil

R1473

1 2

4.7K

POP01

R1474

4.7K

POP01

CPU_STOP#

PCI_STOP#

Pop 33ohm, 49.9ohm if CK409B used

NP01

Populate with CK409B (ITP diferential pair)

Differential pair routing guideline:

6 mil traces / 14 mil spacing

Spacing to other traces: 5W

NP01

R950

33-5%

R1037

49.9-1%

R951

33-5%

NP01

R1035

49.9-1%

R1033

49.9-1%

NP01

R1040

R1034

1 2

49.9-1%

CK_167M_ITP_P

CK_167M_ITP_N

100 MHz

200 MHz

133 MHz

166 MHz

4 4

ROOM=CLOCK1

TITLE

DWG NO.

DATE

COMPUTER CORPORATION

AUSTIN,TEXAS

SCHEM,PLN,SV,PE2800/2850/1850

REV.

D1660

SHEET

7/14/2004

3 OF 60

A00-00

subsys done

Freq. latched on VTT_PWRGD

Clock CK409B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

B D

7-14-2004_10:52

3,35

ICH_SEG2_SDA

ICH_SEG2_SCL

R1423

0-5%

R1422

1 2

0-5%

V_3P3_SRC

ICH_SEG2_800_SDA

ICH_SEG2_800_SCL

R1479

4.7K

R1478

NP*

4.7K

1 2

NP*

V_3P3_SRC

DB800_OE0

DB800_OE4

DB800_OE5

4 4,31 4,31

x00_sd_051703

SLOT7_PWRGD SLOT6_PWRGD

R111

R100

1 2

R112

8.2K-5%

R101

1K-1%

R113

8.2K-5%

1 2

R103

1K-1%

1 2

R114

8.2K-5%

R105

1K-1%

R115

8.2K-5%

1 2

R107

1K-1%

1 2

V_3P3_SRC

8.2K-5%1K-1%

V_3P3_SRC

R592

+3.3V

1 2

C1114

R996

R591

8.2K-5%

1 2

BLM18BD601SN1

0.1uF 16V

x00_tj_051203

10K-1%

R590

8.2K-5%

L108

L107

R999

1 2

8.2K-5%

R998

10K-1%

1 2

0.1uF 16V

NP*

C1111

R997

10K-1%

C1327

1 2

0.1uF 16V

10K-1%

R1480

1 2

3,5,59

C1210

4.7K

x00_sd_051703

10uF 6.3V

3 3

4 4

4,31 4,31

1 2

C1110

0.1uF 16V

CK_100M_DB800_N CK_100M_DB800_P

ICH_SEG2_800_SCL ICH_SEG2_800_SDA

CK_PWRDWN_N

DB800_OE0

DB800_OE4

DB800_OE5

SLOT7_PWRGD SLOT6_PWRGD

C1109

SRC_BYPASS/PLL

SRC_PLL_LOW_BW

SRC_STOP_N SRC_DIV2_N

NC_SRC_LOCK

1 2

0.1uF 16V

1 2

C1108

1 2

C1112

0.1uF 16V

1 2

C1113

C784

0.1uF 16V

DB800

SRC_IN

SCLK

SDATA

BYPASS/PLL

PLL_BW

SRC_STOP

SRC_DIV2

PWRDWN

LOCK

OE_0

OE_1

OE_2

OE_3

OE_4

OE_5

OE_6

OE_7

GND_3

GND_10

GND_18

GND_25

GND_32

GND_40

GNDA

ICS9DB108

SMBus address = DCh

C786

1000pF

PART_NUMBER=79015

x00_tj_051203

1 2

50V-10%

1000pF

PART_NUMBER=79015

50V-10%

DIF_0 DIF_0

DIF_1 DIF_1

DIF_2 DIF_2

DIF_3 DIF_3

DIF_4 DIF_4

DIF_5 DIF_5

DIF_6 DIF_6

DIF_7 DIF_7

IREF

VDD_2 VDD_11 VDD_19 VDD_31 VDD_39

VDDA

8 9

12 13

16 17

20 21

30 29

34 33

38 37

42 41

2 11 19 31 39

DB800_VDDA

Note: If clock ordering changes, BIOS requirements must change

V_3P3_SRC

CK_100M_SATA_P_R CK_100M_SATA_N_R

CK_100M_MCH_P_R CK_100M_MCH_N_R

CK_100M_PXH_PLANAR_P_R CK_100M_PXH_PLANAR_N_R

CK_100M_DOBSON_P_R CK_100M_DOBSON_N_R

CK_100M_PXH_P_R CK_100M_PXH_N_R

CK_100M_EXP_LAI_P_R CK_100M_EXP_LAI_N_R

CK_100M_SLOT1_P_R CK_100M_SLOT1_N_R

CK_100M_SLOT2_P_R CK_100M_SLOT2_N_R

R1003

1 2

475-1%

V_3P3_SRC

10uF 6.3V

C1202

x00_tj_050103

SUB*_U1084

0.1uF 16V

300OHM, 300 mA

C1107

L130

1 2

ILB_1206

IREF = 2.32mA

+3.3V

0.1uF 16V

C1106

R976

1 2

33-5%

R977

1 2

33-5%

R980

1 2

33-5%

R975

1 2

33-5%

R973

1 2

33-5%

R971

1 2

33-5%

R1368

33-5%

R1370

33-5%

R978

1 2

33-5%

1 2

33-5%

1 2

33-5%

1 2

33-5%

R1371

33-5%

R979

R981

R974

1 2

33-5%

R972

1 2

33-5%

R970

R1369

33-5%

CK_100M_SATA_P

CK_100M_SATA_N

CK_100M_MCH_P

CK_100M_MCH_N

CK_100M_PXH_PLANAR_P

CK_100M_PXH_PLANAR_N

CK_100M_DOBSON_P

CK_100M_DOBSON_N

CK_100M_PXH_P

CK_100M_PXH_N

CK_100M_EXP_SPARE_P

CK_100M_EXP_SPARE_N

CK_100M_SLOT7_P

CK_100M_SLOT7_N

CK_100M_SLOT6_P

CK_100M_SLOT6_N

R1051

1 2

49.9-1%

R1052

1 2

R1050

49.9-1%

1 2

49.9-1%

R1049

1 2

R1048

49.9-1%

1 2

49.9-1%

R1047

1 2

R1046

49.9-1%

1 2

R1045

49.9-1%

1 2

R1044

1 2

49.9-1%

R1042

49.9-1%

R1043

49.9-1%

1 2

49.9-1%

R1041

49.9-1%

1 2

R1434

49.9-1%

R1433

R1432

49.9-1%

R1431

49.9-1%

PROPAGATION_DELAY=L:S::500 NET_PHYSICAL_TYPE=50MIL

U1084 300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V KOA CZB2BFL-301P

1U Prod 2U/5U Prod 1U Proto 2U/5U Proto

SATAOE0

XXXX

OE1 MCH

X X X X

OE2

Planar PXH

X X X X

OE3

Dobson

X X

4 4

OE4 OE5

PXH LAI

X X

ROOM=CLOCK2

X X

OE6

Slot1 ***Note--BIOS should disable for 2U

X X

OE7

Slot2

***Note--BIOS should disable for 2U

DB800 Differential buffer

TITLE

COMPUTER CORPORATION

AUSTIN,TEXAS

subsys done

A B

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

4 OF 60

5,59

SYSTEM_PWRGOOD_PXH_R

5,59

PCI_RST_RAC_N_R

PCI_RST_MCH_N_R

PCI_RST_PLANAR_N_R

PCI_RST_RISER_N_R

PCI_RST_BACKPLANE_N_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_NIC_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_FETS_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_BACKPLANE_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_RISER_R

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_CHIPSET_R

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_CLK_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_LATCH_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_DATA_DN_R

PROPAGATION_DELAY=L:S::2000

SHIFTY_BCKPLN_CLK_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_LATCH_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_DATA_DN_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_CLK_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_LATCH_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_DN_R

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_UP_R

PROPAGATION_DELAY=L:S::2200

33-5%

1 2

33-5%

1 2

1K-5%

1 2

33-5%

1 2

33-5%

x03_GT_012604

1 2

33-5%

1 2

33-5%

1 2

33-5%

R6016

1 2

33-5% R6017

1 2

33-5%

R1541

33-5%

R1542

1 2

33-5%

R1543

33-5%

R1545

1 2

33-5%

R1544

33-5%

R1546

1 2

33-5%

R6003

33-5%

R6004

1 2

33-5%

R6002

33-5%

R6005

1 2

33-5%

50V-10%

R1381

R1377

R1378

R1379

R1380

50V-10%

470pF

R129

point-to-point, no cap needed

R1376

R1353

R1375

R1374

R1373

470pF

50V-10%

470pF

C1345

50V-10%

470pF

21 C900

C1346

50V-10%

470pF

21 C1341

point-to-point, no cap needed

50V-10%

470pF

50V-10%

470pF

C1347

x03_GT_012604

x03b_GT_012204

PCI_RST_PXH_N

PCI_RST_DEBUG_N

SHIFTY_RISER_CLK

SHIFTY_RISER_LATCH

SHIFTY_RISER_DATA_DN

SHIFTY_BCKPLN_CLK

SHIFTY_BCKPLN_LATCH

SHIFTY_BCKPLN_DATA_DN

SHIFTY_BMC_CLK

SHIFTY_BMC_LATCH

SHIFTY_BMC_DATA_DN

SHIFTY_BMC_DATA_UP

50V-10%

470pF

21 C1342

C1349

58,59

SYSTEM_PWRGOOD_BACKPLANE

50V-10%

470pF

21 C1343

21 C1344

PCI_RST_RAC_N

PCI_RST_MCH_N

PCI_RST_SIO_FWH_N

PCI_RST_RISER_N

PCI_RST_BACKPLANE_N

x02_sd

SYSTEM_PWRGOOD_PXH

SYSTEM_PWRGOOD_NIC

SYSTEM_PWRGOOD_FETS

SYSTEM_PWRGOOD_RISER

SYSTEM_PWRGOOD_CHIPSET

x03b_GT_012204

40,55

PROG-PART SPEC 14967 DISK PROG BLANK PART

27,28

24,25

24,35,41

17,33

B D

todo check ich_pme will be driven or floated high in time

x02_tj_092203

+3.3V_AUX

1 2

P3975SYSTEM_CPLD

P3976 1Y852

+3.3V_AUX

44,46,50

5,32,46

x03b_sd

x00_sd_051903 x00_sd_051903

just for dumbview just for dumbview

6,51,59

6,42,59

22uF 6.3V

0.1uF 16V

C742

5,59

5,31

31,59

5,59 5,59 5,59

3,59

5,59

15,46 15,46 15,46 15,46

5,59 5,59 5,59

32,59

6,59

31,59

6,59 6,59 6,59

1 2

C15

SYSTEM_PWRGOOD_ESM SYSTEM_PWRGOOD_NIC_R

SYSTEM_PWRGOOD_FETS_R

SYSTEM_PWRGOOD_BACKPLANE_R

SYSTEM_PWRGOOD_RISER_R

SYSTEM_PWRGOOD_CHIPSET_R SYSTEM_PWRGOOD_PXH_R

PCI_RST_MCH_N_R

PCI_RST_PLANAR_N_R

PCI_RST_RISER_N_R

PCI_RST_BACKPLANE_N_R

PCI_RST_RAC_N_R

BACKPLANE_PRES_N RISER_PRES_N SHIFTY_RISER_DATA_UP CK_FSA

SHIFTY_RISER_DATA_DN_R SHIFTY_RISER_CLK_R SHIFTY_RISER_LATCH_R CK_FSB

BUF_CK_CPLD

CK_33M_CPLD INTRUSION_COVER_VAUX_N

CK_32K_VAUX_SYSCPLD

SHIFTY_BMC_DATA_UP

SHIFTY_BMC_DATA_DN_R

CPLD_DDR2_RESET

3.3VAUX_PWRGOOD

H2_PROCHOT_3V

H1_PROCHOT_3V

H2_THERMTRIP_3V H1_THERMTRIP_3V H2_IERR_3V H1_IERR_3V ITP_DBR_N

SHIFTY_BMC_CLK_R

SHIFTY_BMC_LATCH_R

ICH_THRMTRIP

SHIFTY_BCKPLN_CLK_R SHIFTY_BCKPLN_LATCH_R SHIFTY_BCKPLN_DATA_DN_R SHIFTY_BCKPLN_DATA_UP 5V_PWRGOOD 5V_RISER_PWRGOOD

RISER_PWRGOOD DC2DC_CPUVTT_EN DC2DC_1V5_EN DC2DC_1V8_EN DC2DC_3V3_EN DC2DC_5V_EN

NC_SC_NC18 NC_SC_NC20 NC_SC_NC31 NC_SC_NC33 NC_SC_NC34 NC_SC_NC42 NC_SC_NC44 NC_SC_NC46 NC_SC_NC48 NC_SC_NC66 NC_SC_NC75 NC_SC_NC106 NC_SC_NC107 NC_SC_NC114

0.1uF 16V C13

0.1uF 16V 1 2

C14

0.1uF 16V

1K-5%

C16

R1382

143 140 138 136 134 133 132 131 130 129

106 107 114

108 123 144

1uF 6.3V

C277

IO_1_1

IO_1_2

IO_1_3

IO_1_4

IO_1_5

IO_1_6

IO_1_11

IO_1_12

IO_1_13

IO_1_14

IO_1_15_GTS1

IO_1_16_GTS0

IO_2_1

IO_2_2

IO_2_3

IO_2_4

IO_2_5

IO_2_6

IO_2_11

IO_2_12

IO_2_13_GCK0

IO_2_14_GCK1

IO_2_15_CDRST

IO_2_16_GCK2

IO_3_1

IO_3_2_GTS3

IO_3_3_GTS2 IO_3_4_GSR IO_3_5 IO_3_6 IO_3_7 IO_3_11 IO_3_12 IO_3_13 IO_3_14 IO_3_15 IO_3_16

IO_4_1_DGE

IO_4_2

IO_4_3

IO_4_4

IO_4_5

IO_4_6

IO_4_7

IO_4_11

IO_4_12

IO_4_13

IO_4_14

IO_4_15

IO_4_16

NC_18

NC_20

NC_31

NC_33

NC_34

NC_42

NC_44

NC_46

NC_48

NC_66

NC_75 NC_106 NC_107 NC_114

GND_29

GND_36

GND_47

GND_62

GND_72

GND_89

GND_90

GND_99 GND_108 GND_123 GND_144

1uF 6.3V

1 2

C278

1uF 6.3V

C279

SYSTEM_CPLD

XC2C128 TQFP144

SUB*_P3975

1uF 6.3V

1 2

C659

IO_5_1 IO_5_2 IO_5_3 IO_5_4 IO_5_5 IO_5_6

IO_5_7 IO_5_11 IO_5_12 IO_5_13 IO_5_14 IO_5_15 IO_5_16

IO_6_1

IO_6_2

IO_6_3

IO_6_4

IO_6_5

IO_6_6 IO_6_11 IO_6_12 IO_6_13 IO_6_14 IO_6_15 IO_6_16

IO_7_1

IO_7_2

IO_7_3

IO_7_4

IO_7_5

IO_7_6

IO_7_7 IO_7_11 IO_7_12 IO_7_13 IO_7_14 IO_7_15 IO_7_16

IO_8_1

IO_8_2

IO_8_3

IO_8_4

IO_8_5

IO_8_6 IO_8_11 IO_8_12 IO_8_13 IO_8_14 IO_8_15 IO_8_16

VCC_JTAG

VCC_1 VCC_37 VCC_84

VCCIO1_27 VCCIO1_55 VCCIO1_73 VCCIO1_93

VCCIO2_109 VCCIO2_127 VCCIO2_141

NC_135 NC_137 NC_139 NC_142

256 macrocell flavor

TCK TDI TDO TMS

94 95 96 97 98 100 101 102 103 104 105 110 111

92 91 88 87 86 85 83 82 81 80 79 78

112 113 115 116 117 118 119 120 121 124 125 126 128

77 76 74 71 70 69 68 64 61 60 59 58

67 63 122 65 8

1 37 84

27 55 73 93

109 127 141

135 137 139 142

PS1_PWRGOOD

PS2_PWRGOOD DEBUG_JUMPER_1 DEBUG_JUMPER_0

DEBUG_LED_3

DEBUG_LED_2

DEBUG_LED_1

DEBUG_LED_0

ICH_PWRBTN_N

ICH_PME_N

PFAULT_LATCH_N_R

PFAULT_RESET

RISER_EXP_PME_N

VRD1_THERMTRIP_N

PCI_RST_ICH_N

VCORE_EN_R VCORE_EN VCORE1_PWRGOOD VCORE2_PWRGOOD CPLD_H_FORCEPR

VRD2_THERMTRIP_N

ICH_PWR_ON_REQ

RESET_BTN_N PS1_ENABLE_N PS2_ENABLE_N

LPC_LFRAME_N

CPLD_H_VID_PWRGOOD_N

PME_NIC_CPLD_N

H2_CPU_PRES_N H1_CPU_PRES_N

RISER_PCI_PME_N

CK_VTT_PWRGD_N

DC2DC_5V_RISER_EN

H1_BSEL0_3V_N H1_BSEL1_3V_N H2_BSEL0_3V_N H2_BSEL1_3V_N

CPU_VTT_PWRGOOD

1V5_PWRGOOD

1V8_PWRGOOD

3V3_PWRGOOD

CK_PWRDWN_N

CPLD_TCK CPLD_TDI CPLD_TD1 CPLD_TMS

NC_SC_NC135 NC_SC_NC137 NC_SC_NC139 NC_SC_NC142

B_1U_2U5U

LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0

H2_VTT_EN H1_VTT_EN

5,40,46 5,40 46 5,31,32,40,46

44,46

31,59 31,59 59 59 59 59 59 59 33,41,44,56,59 33 5 5

x03b_sd

9,46 33,59

7,59 8,59 5 9,46 33,40,41,44,59 56 31,59 31,59

33,40,44,55,59 33,40,44,55,59 33,40,44,55,59 33,40,44,55,59 33,40,44,55,59 5,59 28 5,12,46 5,12,46 5,12 5,12

x03b_sd

31 3,59

15 15 15 15 6,51 6,59 6,59 6,59 3,4,59

+3.3V_AUX

x00_sd_52903 - removed 2 leds

33-5%

x02_sd

+3.3V_AUX

R1790

R1791

PFAULT_LATCH_N_R

PROPAGATION_DELAY=L:S::2000

PFAULT_RESET_R

PROPAGATION_DELAY=L:S::2500

R1865

+3.3V_AUX

1 2

8.2K-5%

R1920

1 2

0-5%

R1921

0-5%

NP*

GND

TPS72118DBV

8.2K-5%8.2K-5%

NP*

1 2

NP*

R1769

NP13

R1770

NP02

R6021

1 2

0-5%

NP*

+3.3V

33-5%

U64

x02_sd

7,8,59

X04_GT_032904

I2C_SEG2_VAUX_SDA I2C_SEG2_VAUX_SCL

1 2

R1922

OUTIN

NCEN

R6006

1 2

33-5% R6007

33-5%

C559

PART_NUMBER=79015

ICH_THRMTRIP

SHUNT_1V5_N

NET_PHYSICAL_TYPE=PWR

0.1uF 16V

+3.3V_AUX

1 2

100-1%

1000pF

50V-10%

+1.8V_AUX

10V-10%

C1624

1uF

PFAULT_LATCH_N

PFAULT_RESET

142U38

R575

R92

1 2

2.7K-5%

44,45,59 44,45,59

0.1uF 16V

C1625

44,46

Q104

3904

C1626

+3.3V_AUX

144U38

CK_CPLD

BUF_CK_CPLD

VHC14VHC14

RC = 0.1 us

F = 2.0MHz

5,59

ICH_THRMTRIP_N

5,59

todo....need to check that 3904 has drive strength and gain

x00_tj_042803

5,12,46 5,12,46

5,12 5,12

H2_CPU_PRES_N H1_CPU_PRES_N H2_VTT_EN H1_VTT_EN

CPLD_DDR2_RESET

CPLD_H_VID_PWRGOOD_N

CPLD_H_FORCEPR

+3.3V_AUX

RN87

4.7K

ROOM=SYSCPLD

R1439

1 2

2.7K-5%

R1438

2.7K-5%

R426

1 2

2.7K-5%

5,32,46

5,31

+1.8V

1 2

301-1%

Q66

R1359

3904

R583

3904

2.7K-5%

Q65

3904

Q84

3904

BACKPLANE_PRES_N RISER_PRES_N

x00_sd_052203 x00_tj_052903

7-14-2004_10:52

todo, consider slew rate limiting

DDR2_RESET_N_1

+1.8V

301-1%

DDR2_RESET_N_2

Q11

H_VTT_PWRGOOD

H_FORCEPR_N

+3.3V_AUX

R1834

11,12

4.7K

R1835

4.7K

1 2

20,21

+3.3V_AUX

J14

SIO

CPLD_TDI CPLD_TD1 CPLD_TD2

5,40,46 5,32,40

5,40

4 4

5,31,32,40,46

CPLD_TCK CPLD_TDO CPLD_TDI CPLD_TMS

2 3 4 5

Header

CPLD JTAG Chain

Planar ESM Riser Backplane

CPLD_TD3

Gated by ~SPG Gated by ~SPG

Jumper

NP*

COMPUTER

CPLD_TD0

p/u for TCK at SIO

31,46

CPLD_TD2

CPLD_BYPASS

1 2

NP*

CPLD_TDO

5,32,40

TITLE

CORPORATION

AUSTIN,TEXAS

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

5 OF 60

A B

B D

7-14-2004_10:52

TYPE INPUT OUTPUT DESTINATION

70W VERTICAL +12V +1.8V DDR II, MCH

ROOM=DC2DC_1P8V

+12V

R73

8.2K-5%

1 2

C1805

1V8_PWRGOOD

1 2

0.1uF 16V

270uF

16V-20%

+12V

2 1

X04_GT_031904

+1.8V

R132

3.01K-1%

1 2

C606

270uF

16V-20%

R463

1 2

0-5%

5,59

Enable is driven to required state from CPLD at all times.

C605

R546

1 2

0-5%

5,59

R547

TYPE INPUT OUTPUT DESTINATION

ROOM=DC2DC_3P3V

100W HORIZONTAL +12V +3.3V RISER's

TYPE INPUT OUTPUT DESTINATION

ROOM=DC2DC_5V

+12V

100W VERTICAL +12V +5V BACKPLANE

+5V DC2DC

+1.8V DC2DC

+12V

x04_tj_031904

SUB=SUB*_0K260

R290

1 2

422-1%

442-1%

DC2DC_1V8_EN

C588

0-5%

1 2

PART_NUMBER=79015

NC_DC2DC_1P8V_2

+1.8V

1000pF

50V-10%

+12V

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MH1 MH2

MOD., 24 PIN, 72W, VERTICAL

DC2DC_1P8V

+RS

RSVD

-RS

PWRGD

PWRGD_SET

VSS_0

VSS_1

OUTEN

-SENCE +SENSE 12V_IN_0 12V_IN_1 12V_IN_2 VOUT_0 VOUT_1 VSS_2 VOUT_2 VSS_3 VOUT_3 VSS_4 VOUT_4 VSS_5 VOUT_5

GND_MH1 GND_MH2

DC/DC CONVERTER

x00_gt_062603

+1.8V

16V-10%

4.7uF

C600

+1.8V

C268

16V-10%

4.7uF

680uF

C269

6.3V-20%

25V-20%

C601

.1uF

x00_tj_051203

x02_tj_121503

C611

680uF

C270

6.3V-20%

R74

8.2K-5%

1 2

todo should this really be NC? -shawn

5,6,59

X04_GT_031904

3V3_PWRGOOD

R133

3.01K-1%

1 2

3P3V_RISER_SENSE

x00_sd_051703

Enable is driven to required state from CPLD at all times.

RISER

+12V

2 1

270uF

16V-20%

C1568

680uF

6.3V-20%

+3.3V DC2DC

+3.3V

5,59

R1580

2-1%

R1430

1 2

C1627

X00_GT_052203

1 2

2-1%

0.1uF 16V

DS1818

+3.3V

U24

VCC

RESET

GND

SUB=SUB*_Y1351

R301

R1572

1 2

21.5K-1%

DC2DC_3V3_EN

C1501

0-5%

3V3_PWRGOOD

R1488

10K-1%

NC_DC2DC_3P3V_6

+3.3V

1 2

1000pF

50V-10%

PART_NUMBER=79015

+12V

5,6,59

DC2DC_3P3V

+RS

-RS

PWRGD

PWRGD_SET

RESERVED

VSS_7

VSS_8

OUTEN

-SENSE

+SENSE

12VIN_12

12VIN_13

12VIN_14

VCC_15

VCC_16

VSS_17

VCC_18

VSS_19

VCC_20

VSS_21

VCC_22

VSS_23

VCC_24

100W-25A DC-DC

MOD.-25 pin, HORIZONTAL

+3.3V

16V-10%

4.7uF

+3.3V

4V-20%

820uF

1 2

C602

C287

16V-10%

4.7uF

4V-20%

820uF

x00_tj_051203

25V-20%

C603

.1uF

1 2

C288

C619

R75

X04_GT_031904

5,6,59

X04_GT_031904

SENSE_5V_BACKPLANE_1U

SENSE_5V_BACKPLANE_2U5U

VCC

5V_PWRGOOD

R134

R1752

20-1%

R562

1 2

0-5%

BACKPLANE

+12V

x04b_tj_032404

C610

270uF

16V-20%

1 2

Enable is driven to required state from CPLD at all times.

1.5K-5% 4.75K-1%

x03b_sd

NP13

R1750

1 2

0-5%

R1751

1 2

20-1%

R273

1 2

0-5%

x03_sd_sense

1 2

C1650

0.1uF 16V

Sub to DS1811R-5 (+5V, 5% part)

511-1%

VCC

GND

DS1818

R274

U59

RESET

5,6,42,59

10K-1%

SUB=SUB*_1F826

R275

NP*

5V_PWRGOOD

DC2DC_5V_SENSE_GND

R462

0-5%

NC_DC2DC_5V_6

DC2DC_5V_EN

DC2DC_5V_SENSE_GND

DC2DC_5V_SENSE

C590

DC2DC_5V_SENSE

5,6,59

1 2

VCC

1000pF

50V-10%

R466

0-5%

+12V

R1848

1 2

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MH1 MH2

SUB=SUB*_G6740

5,6,42,59

5,6,59

+12V

309-1%

DC2DC_5V

+RS

-RS PWRGD RSVD_1 RSVD_2 VSS_0 VSS_1 OUTEN

-SENCE +SENSE 12V_IN_0 12V_IN_1 12V_IN_2 VOUT_0 VOUT_1 VSS_2 VOUT_2 VSS_3 VOUT_3 VSS_4 VOUT_4 VSS_5 VOUT_5

GND_MH1 GND_MH2

DC/DC CONVERTER

MOD. 073_20821_03

DC2DC_5V_EN

5V_PWRGOOD

R1849

1 2

0-5%

VCC

16V-10%

4.7uF

VCC

C271

VCC

16V-10%

C604

4.7uF

680uF

6.3V-20%

DC2DC_5V_1U

VCC_1

VCC_2

VCC_3

TRIM

OUTEN

PWRGD

VSS_7

VSS_8

PWRGD_SET

12VIN_10

12VIN_11

40W-15A DC-DC

SIP11

x00_tj_051203

25V-20%

C607

.1uF

C272

680uF

X00_GT_061203

C620

6.3V-20%

TYPE INPUT OUTPUT DESTINATION

40W VERTICAL +12V +1.2V CPU1, CPU2, MCH

ROOM=DC2DC_CPU_VTT

Enable is driven to required state from CPLD at all times.

+12V

R1137

+12V

16V-20%

270uF

1 2

x04b_tj_032404

C138

5,51

CPU_VTT_PWRGOOD

1 2

5,51,59

R1148

1 2

8.2K-5%2.7K-5%

DC2DC_CPUVTT_EN

NP*

x02_tj_091903

R543

1 2

+CPU_VTT

+12V

27.4K-1%

CPU VTT

NP*

R225

1 2

26.7-1%

DC2DC_CPUVTT

VCC_1

VCC_2

VCC_3

TRIM

OUTEN

PWRGD

VSS_7

VSS_8

PWRGD_SET

12VIN_10

12VIN_11

40W-15A DC-DC

SIP11

+CPU_VTT

10V-10%

+CPU_VTT

.1uF

C349

2 1

16V-10%

C591

4.7uF

560uF

4V-20%

C608

C350

2 1

560uF

4V-20%

TYPE

40W HORIZONTAL INPUT +12V OUTPUT DESTINATION

+1.5V

MCH, ICH5

ROOM=DC2DC_1P5V

Enable is driven to required state from CPLD at all times.

+12V

R77

8.2K-5%

1 2

5,59

1V5_PWRGOOD

R136

1 2

3.01K-1%

+12V

16V-20%

270uF

5,59

X04_GT_031904

1 2

C1566

DC2DC_1V5_EN

R70

1 2

+12V

3.74K-1%

+1.5V DC2DC

+1.5V

R1489

26.7K-1%

SUB*_5N443

MOD.-13 pin, HORIZONTAL

DC2DC_1P5V

VCC_1

VCC_2

VCC_3

TRIM

OUTEN

PWRGD

VSS_7

VSS_8

PWRGD_SET

12VIN_10

12VIN_11

40W-15A DC-DC

+1.5V

4V-20%

820uF

1 2

C1497

10V-10%

2 1

.1uF

16V-10%

C1575

4.7uF

C1585

TYPE INPUT OUTPUT DESTINATION

40W HORIZONTAL +12V +5V MCH, ICH5

ROOM=DC2DC_RISER5V

Enable is driven to required state from CPLD at all times.

+12V

5,6

+12V

16V-20%

270uF

X04_GT_031904

5V_RISER_PWRGOOD

X04_GT_031904

1 2

C1569

R76

1 2

R135

1 2

4.75K-1%

DC2DC_5V_RISER_EN

1.5K-5%

R32

1 2

+12V

309-1%

+5.0V Riser

R106

1 2

0-5%

5V DC2DC

DC2DC_RISER5V

VCC_1

VCC_2

VCC_3

TRIM

OUTEN

PWRGD

VSS_7

VSS_8

PWRGD_SET

12VIN_10

12VIN_11

40W-15A DC-DC

MOD.-13 pin, HORIZONTAL

+5.0V Riser

U34

VCC

RESET

GND

1 2

C1651

Sub to DS1811R-5 (+5V, 5% part)

0.1uF 16V

DS1818

SUB=SUB*_1F826

+5.0V Riser

5V_RISER_PWRGOOD

10V-10%

.1uF

2 1

C1576

5,6

16V-10%

4.7uF

C1586

ECAD: Place 1 560uF cap by each CPU

Substitute 26.1K, 1%

Substitute from 3.92K to 3.74K to tweak 1.5V to 1.514V

x03_tj_010904 x03b_tj_012604

C633

680uF

6.3V-20%

& one by regulator

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

DC2DC REGULATORS

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

6 OF 60

A B

B D

+12V +12V

SUB=SUB*_P1355

7-14-2004_10:52

SUB=SUB*_P1355

VRD1_PWM3A

VRD1_PWM4A

VRD BOM Changes:

X02_TJ_081803

220K

+3.3V

8.2K-5% R4502

R1972

X02_TJ_081803

VCORE1_PWRGOOD

R1973

5,7,59

VRD1_VCC

220K

X03_GT_011804

SUB*_16155

X02_TJ_110503

Q86

FT2N7002LT1

7 7

5.1-5%

2 1

R260

R1985

1 2

1K-5%

1N914

2-1%

VRD1_PWM1A DRV1_OD

.22uF 25V

20%

X03_GT_012604

.22uF 25V

20%

1 3

R240

BST

VCC

C484

Phase 1

ROOM = VRD1_PHASE1

50V-10%

C491

1000pF

1 2

VRD1_DRV1

ADP3418

VRD1_PHASE1B_SENSE

x03_sd

C852

NP*

C466

.1uF

25V-20%

DRVH

SW PGND DRVL

7 6 5

VRD1_UGATE1

R433

VRD1_LGATE1

4.7K

1 2

R451

1 2

4.7K

Q41

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

Q21

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

25V-20%

.1uF

1 2

C488

C1680

25V-20%

.1uF

16V-10%

4.7uF

C1682

C1681

Q24

FDS7096N3

SUB*_N1930

Q20

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

x04b_tj_032404

25V-20%

.1uF

C489

C1683

25V-20%

.1uF

C336

16V-10%

4.7uF

C1684

16V-10%

4.7uF

560uF

4V-20%

C1685

+CPU_VID1

0.6uH, 27Amp

R152

C276

1 2

2 1

C303

3-5%

.001UF

SUB=SUB*_N1453

50V-10%

SUB*_16155

X02_TJ_110503

Q88

FT2N7002LT1

1N914

2-1%

VRD1_PWM2A

DRV1_OD

5.1-5%

2 1

R258

R1986

1 2

1K-5%

1 3

D11

R244

.22uF 25V

20%

X03_GT_012604

.22uF 25V

20%

1 2

VRD1_PHASE2

BST

VCC

ADP3418

C482

Phase 2

ROOM = VRD1_PHASE2

VRD1_PHASE2B_SENSE

50V-10%

1000pF

C579

C471

.1uF

25V-20%

DRVH

SW PGND DRVL

C853

x03_sd

8 7 6 5

NP*

R434

1 2

VRD1_LGATE2

4.7K

R454

1 2

4.7K

Q36

FDS7096N3

SUB*_N1930

FDS7066SN3

PKG_TYPE=SO8_P9DR_FRCHLD

20%

Q37

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

4.7uF

.22uF 25V

1 2

C581

2 1

C1686

25V-20%

.1uF

25V-20%

.1uF

2 1

C1687

2 1

C1688

Q27

FDS7096N3

SUB*_N1930

Q26

FDS7066SN3

PKG_TYPE=SO8_P9DR_FRCHLD

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

2 1

4.7uF

C580

C1689

25V-20%

.1uF

2 1

x04b_tj_032404

C343

25V-20%

.1uF

2 1

C1690

C1691

16V-10%

4.7uF

560uF

4V-20%

+CPU_VID1

C281

2 1

1 2

R163

1 2

C308

0.6uH, 27Amp

SUB=SUB*_N1453

3-5%

.001UF

50V-10%

+12V

SUB=SUB*_P1355

16V-10%

4.7uF

560uF

4V-20%

+CPU_VID1

C280

2 1

1 2

R153

C302

0.6uH, 27Amp

SUB=SUB*_N1453

3-5%

.001UF

50V-10%

DRV1_OD_R

PWM Control Circuitry

ROOM = VRD1_CTRL

X04_GT_031904

H1_VSSSENSE

x00_sd_061603 - providing sensing

VRD1_VSSSENSE_MID

R304

X04_GT_031904

1 2

0-5%

R1851

1K-5%

C1728

SUB=SUB*_4053P

DRV1_OD_R

SUB=SUB*_75EEC

1 2

1uF

1 2

25V-10%

5,8,59

VCORE_EN

R1820

0-5%

VRD1_VSSSENSE

50V-10%

1000pF

R1980

220K

C1727

100-5%

X03_GT_011804

C1807

1 2

R1846

5,7,59

DRV1_OD

x03b_GT_012204

27pF

50V-10%

VCORE1_PWRGOOD

C462

.1uF

25V-20%

VRD1_VCC

PWRGD

ILIMIT

DELAY

SUB*_16155

X02_TJ_110503

VRD1_CTRL

+12V

10-5%

VCC

RAMPADJ

PWM1

1 2

Q87

FT2N7002LT1

R13

14 13

27 26

7 7

5.1-5%

2 1

R261

1 2

487K-1%

R271

VRD1_PWM1A VRD1_PWM2A

R1987

1 2

1K-5%

X03_GT_012604

1 3

1N914

1 2

2-1%

VRD1_PWM3A DRV1_OD

R299

1 2

200K-1%

R243

.22uF 25V

20%

16V-10%

.47uF

50V-10%

1000pF

C490

C467

.1uF

25V-20%

VRD1_DRV3

1 2 3 4

Phase 3

ROOM = VRD1_PHASE3

x03_sd

C854

NP*

VRD1_PHASE3B_SENSE

8 7 6 5

R457

BST

DRVH IN OD VCC

PGND

DRVL

ADP3418

.22uF 25V

1 2

20%

C483

X00_GT_062103 Redraw Only- NEED INDEPENDENT CHECK before MODEM!

x04b_tj_032404

C338

16V-10%

2 1

4.7uF

X04b_tj_032404

C305

C337

560uF

SUB*_16155

X02_TJ_110503

4V-20%

Q89

FT2N7002LT1

R1988

1 2

1K-5%

Phase 4

ROOM = VRD1_PHASE4

VRD1_PHASE4B_SENSE

X03_GT_012604

.22uF 25V

Q38

16V-10%

.22uF 25V

20%

1 2

4.7uF

C481

2 1

C1692

25V-20%

.1uF

25V-20%

.1uF

2 1

C1693

2 1

C1694

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

VRD1_UGATE3

Redraw Only- NEED INDEPENDENT CHECK before MODEM!

Q40

VRD1_LGATE3

FDS7066SN3

R437

4.7K

1 2

4.7K

SUB*_T1564

1 2

PKG_TYPE=SO8_P9DR_FRCHLD

Q39

FDS7096N3

SUB*_N1930

Q25

FDS7066SN3

SUB*_T1564

20%

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

4.7uF

.22uF 25V

C487

2 1

C1695

25V-20%

.1uF

25V-20%

.1uF

2 1

C1696

2 1

C1697

+CPU_VID1

1 2

R171

1 2

C282

0.6uH, 27Amp

SUB=SUB*_N1453

3-5%

.001UF

50V-10%

7 7

5.1-5%

R257

1N914

1 2

2-1%

VRD1_PWM4A DRV1_OD

.22uF 25V

20%

D10

R236

20%

VRD1_UGATE4

BST

VCC

VRD1_DRV4

50V-10%

C578

C465

1 2

.1uF

25V-20%

ADP3418

1000pF

x03_sd

DRVH

SW PGND DRVL

C855

NP*

8 7 6 5

VRD1_LGATE4

R430

4.7K

R428

4.7K

Q34

FDS7096N3

SUB*_N1930

.22uF 25V

PKG_TYPE=SO8_P9DR_FRCHLD

20%

Q33

FDS7066SN3

SUB*_T1564

16V-10%

1 2

PKG_TYPE=SO8_P9DR_FRCHLD

4.7uF

C485

2 1

C1698

25V-20%

.1uF

25V-20%

.1uF

C1699

C1700

Q35

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

20%

Q32

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

.22uF 25V

C486

2 1

4.7uF

C1701

25V-20%

.1uF

25V-20%

.1uF

C1702

C1703

FDS7066N3 is local. Waiting on library symbol.

VID Termination

.047uF 25V

20%

1 2

C714

1 2

249K-1%

R255

1 2

127K-1%

R233

7,12 7,12 7,12 7,12 7,12 7,12

H1_VID0 H1_VID1 H1_VID2 H1_VID3 H1_VID4 H1_VID5

VRD1_VSSSENSE

5 4 3 2 1 6

COMP

FBRTN

VID0 VID1 VID2 VID3 VID4 VID5

GND

PWM2 PWM3 PWM4

SW1 SW2 SW3 SW4

CSSUM CSREF

CSCOMP

25 24

23 22 21 20

17 16 18

VRD1_PWM3A VRD1_PWM4A

R310

1 2

0-5%

100K-1%

R289

NP*

X04_GT_031904

C300

100pF 50V

X04_GT_031904

4 4

R250

2 1

+CPU_VID1

10.7K-1% 680pF 50V

C708

X04_GT_032204

C479

680pF 50V

R278

1 2

1.3K-1%

(1.33K)

X04_GT_031904

SUB=NP

R288

1 2

R311

100K-1%

H1_VCCSENSE

1 2

1K-5%

R1821

1 2

VRD1_VCCSENSE

X04_GT_031904

R6019

1 2

ADP3168

SUB*_H5002

X04_GT_031904

R305

X04_GT_031904

SUB*_X5828

300-5%

1 2

50V-10%

1000pF

X04_GT_031904

1 2

C1810

100-5%

50V-10%

2700pF

SUB*_1U388

R147

R1992

1 2

C720

50V-10%

THERMISTOR

0-5% 0-5%

X04_GT_031904

7 7 7

R303

0-5%

75K-1%

4700pF

1 2

R315

1 2

0-5%

75K-1%

R291

R28621R284

X04_GT_031904

C710

R85

1 2

29.4K-1%

R306

0-5%15.8K-1%

R314

0-5%

75K-1%

X04_GT_031904

R81

75K-1%

X04_GT_031904

R285

VRD1_PHASE1B_SENSE

VRD1_PHASE2B_SENSE

VRD1_PHASE3B_SENSE

VRD1_PHASE4B_SENSE

X04_GT_031904

X03_GT_011904

+CPU_VID1

VRD1_PWM1A

R1717

1 2

68K-5%

R1718

68K-5%

X04_GT_032204

1 2

C6007

.01uF 16V

R407

1 2

0-5%

C334

1 2

ALT_LLINE

7,8

GPO_ALT_LLINE_N

2N7002

.047uF

16V-10%

R484

4.7K

If this FET is populated, you must verify Vgs(th) is met!

VRD1_PWM3A

VRD1_PWM4A

U61

+3.3V_AUX

VHC14

x00_sd_052903

ALT_LLINE

7,8

x04b_tj_032404

Input Filtering

+12V

SUB=SUB*_P1355

C582

270uF

16V-20%

C725

560uF

4V-20%

x04b_tj_032404

.1uF

1 2

50V-20%

.1uF

SUB=SUB*_4053P

50V-20%

C21

1uF

1 2

25V-10%

C12

1uF

1 2

SUB=SUB*_4053P

25V-10%

INTEGRATED VRD 10.1 VOLTAGE

REGULATOR FOR PROC_1

+CPU_VTT

R28

1 2

499-1%

R27

1 2

499-1%

R26

1 2

499-1%

R25

1 2

499-1%

R16

1 2

499-1%

R15

1 2

499-1%

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

SHEET

7/14/2004

H1_VID0

H1_VID1

H1_VID2

H1_VID3

H1_VID4

H1_VID5

7 OF 60

7,12

REV.

A00-00

A B

VRD2_PWM3A

VRD2_PWM4A

VRD BOM Changes:

X02_TJ_081803

220K

R1970

+3.3V

8.2K-5% R4503

X02_TJ_081803

R1971

VRD2_VCC

220K

X03_GT_011804

SUB*_16155

X02_TJ_110503

+12V

Q90

FT2N7002LT1

5.1-5%

2 1

R264

8 8

20%

R1989

1 2

1K-5%

1N914

2-1%

VRD2_PWM1A DRV2_OD

.22uF 25V

X03_GT_012604

VRD2_PHASE1B_SENSE

.22uF 25V

1 3

D25

20%

R247

BST

VCC

C599

ROOM = VRD2_PHASE1

1 2

VRD2_DRV1

50V-10%

C648

ADP3418

1000pF

C476

.1uF

25V-20%

DRVH

SW PGND DRVL

Phase 1

x03_sd

C856

NP*

VRD2_UGATE1

7 6 5

VRD2_LGATE1

R487

4.7K

1 2

R494

1 2

4.7K

Q70

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

20%

Q43

FDS7066SN3

SUB*_T1564

16V-10%

.22uF 25V

1 2

C624

PKG_TYPE=SO8_P9DR_FRCHLD

2 1

4.7uF

C1704

25V-20%

.1uF

25V-20%

.1uF

2 1

C1705

B D

SUB=SUB*_P1355

+12V

2 1

C1706

Q44

FDS7096N3

SUB*_N1930

.22uF 25V

20%

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

4.7uF

1 2

C646

2 1

C1707

25V-20%

.1uF

25V-20%

.1uF

2 1

C1708

2 1

C1709

16V-10%

C344

560uF

4V-20%

+CPU_VID2

0.6uH, 27Amp

4.7uF

L17

2 1

C326

SUB=SUB*_N1453

SUB*_16155

X02_TJ_110503

Q92

FT2N7002LT1

1 2

1N914

2-1%

R1990

1K-5%

1 3

D38

R249

ROOM = VRD2_PHASE2

X03_GT_012604

VRD2_PHASE2B_SENSE

.22uF 25V

20%

1 2

50V-10%

C650

C478

.1uF

25V-20%

Phase 2

1000pF

x03_sd

C857

NP*

Q52

FDS7096N3

SUB*_N1930

.22uF 25V

20%

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

4.7uF

1 2

C652

2 1

C1710

25V-20%

.1uF

25V-20%

.1uF

2 1

C1711

2 1

C1712

Q47

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

VRD2_DRV2

Q42

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

R172

1 2

C283

1 2

3-5%

.001UF

50V-10%

8 8

5.1-5%

2 1

R263

20%

VRD2_PWM2A DRV2_OD

.22uF 25V

C595

BST

VCC

DRVH

PGND DRVL

ADP3418

8 7 6 5

R490

1 2

VRD2_LGATE2

4.7K

R495

1 2

4.7K

Q56

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

Q46

FDS7066SN3

SUB*_T1564

.22uF 25V

20%

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

2 1

4.7uF

C651

C1713

25V-20%

.1uF

2 1

x04b_tj_032404

25V-20%

.1uF

2 1

C1714

SUB=SUB*_P1355

16V-10%

C440

C1715

560uF

4V-20%

+CPU_VID2

4.7uF

L16

R179

1 2

C285

1 2

2 1

C333

0.6uH, 27Amp

1 2

3-5%

.001UF

50V-10%

SUB=SUB*_N1453

VCORE2_PWRGOOD

5,8,59

+12V

SUB=SUB*_P1355

+12V

X03_GT_011804

SUB*_16155

X02_TJ_110503

DRV2_OD_R

220K

R1981

C1808

DRV2_OD

x03b_GT_012204

27pF

50V-10%

Q91

FT2N7002LT1

R6018

1 2

1K-5%

1N914

2-1%

Phase 3

ROOM = VRD2_PHASE3

X03_GT_012604

VRD2_PHASE3B_SENSE

.22uF 25V

1 3

1 2

D12

R248

20%

50V-10%

C647

C477

.1uF

25V-20%

1000pF

x03_sd

C858

NP*

Q62

FDS7096N3

SUB*_N1930

20%

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

.22uF 25V

1 2

C594

2 1

4.7uF

C1732

25V-20%

.1uF

2 1

25V-20%

.1uF

2 1

C1722

C1723

Q63

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

16V-10%

C623

2 1

4.7uF

C1724

25V-20%

.1uF

2 1

25V-20%

.1uF

2 1

C1725

C424

C1726

16V-10%

560uF

4V-20%

+CPU_VID2

4.7uF

2 1

C328

SUB*_16155

X02_TJ_110503

Q93

FT2N7002LT1

R1991

1 2

1K-5%

X03_GT_012604

20%

1N914

D34

1 2

2-1%

R246

.22uF 25V

C649

Phase 4

ROOM = VRD2_PHASE4

VRD2_PHASE4B_SENSE

50V-10%

1000pF

x03_sd

C859

NP*21

C475

1 2

.1uF

25V-20%

Q50

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

.22uF 25V

20%

1 2

C617

16V-10%

2 1

4.7uF

C1716

25V-20%

.1uF

25V-20%

.1uF

C1717

C1718

Q51

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

20%

16V-10%

4.7uF

.22uF 25V

C618

2 1

C1719

25V-20%

.1uF

SUB=SUB*_P1355

C425

25V-20%

.1uF

C1721

C1720

16V-10%

560uF

4V-20%

4.7uF

2 1

C309

+CPU_VID2

L18

SUB=SUB*_4053P

H2_VSSSENSE

R318

1 2

1K-5%

DRV2_OD_R

PWM Control Circuitry

ROOM = VRD2_CTRL

0-5%

VCORE_EN

C1730

100-5%

1 2

R1847

C473

5,8,59

X04_GT_031904

VRD2_VSSSENSE

50V-10%

C1729

1uF

1 2

25V-10%

5,7,59

R1822

1 2

1000pF

PART_NUMBER=79015

.1uF

25V-20%

VCORE2_PWRGOOD

PWRGD

ILIMIT

VRD2_VCC

VRD2_CTRL

VCC

RAMPADJ

14 13

+12V

10-5%

1 2

R14

487K-1%

VRD2_PWM1A VRD2_PWM2A

8 8

5.1-5%

2 1

R267

1 2

R272

R300

1 2

200K-1%

VRD2_PWM3A DRV2_OD

16V-10%

1 2 3 4

.47uF

BST IN OD VCC

C11

VRD2_DRV3

ADP3418

.22uF 25V

20%

1 2

DRVH

SW PGND DRVL

C598

8 7 6 5

VRD2_UGATE3

VRD2_LGATE3

R500

4.7K

1 2

R493

1 2

4.7K

Q67

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

Q45

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

R182

1 2

C299

0.6uH, 27Amp

1 2

3-5%

.001UF

50V-10%

SUB=SUB*_N1453

8 8

5.1-5%

R262

VRD2_PWM4A DRV2_OD

.22uF 25V

20%

C10

VRD2_DRV4

VRD2_UGATE4

Q49

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

Q48

FDS7066SN3

SUB*_T1564

R178

C284

PKG_TYPE=SO8_P9DR_FRCHLD

8 7 6 5

R486

VRD2_LGATE4

R485

4.7K

BST

VCC

DRVH

PGND DRVL

ADP3418

0.6uH, 27Amp

1 2

3-5%

.001UF

SUB=SUB*_N1453

50V-10%

VID Termination

R316

0-5%

1 2

8 8 8

R350

1 2

75K-1%

0-5%

R298

75K-1%

50V-10%

4700pF

1 2

C721

SUB*_1U388

C711

R148

15.8K-1% 0-5%

THERMISTOR

R349

0-5%

75K-1%

R295

R293

X04_GT_031904

R87

1 2

29.4K-1%

R332

1 2

VRD2_PHASE1B_SENSE

VRD2_PHASE2B_SENSE

VRD2_PHASE3B_SENSE

VRD2_PHASE4B_SENSE

75K-1%

R294

X04_GT_031904

R86

75K-1%

X04_GT_031904

X03_GT_011904

+CPU_VTT

R1715

VRD2_PWM1A

+CPU_VID2

X04_GT_032204

1 2

C6008

.01uF 16V

R418

1 2

0-5%

2N7002

R501

4.7K

16V-10%

C335

1 2

.047uF

ALT_LLINE

1 2

68K-5%

R1716

68K-5%

VRD2_PWM3A

VRD2_PWM4A

FDS7066N3 is local. Waiting on library symbol.

R79

1 2

Input Filtering

499-1%

H2_VID0

8,12

R78

+12V

C583

2 1

270uF

16V-20%

SUB=SUB*_P1355

x04b_tj_032404

C820

560uF

4V-20%

1 2

499-1%

R72

1 2

499-1%

.1uF

1 2

50V-20%

.1uF

50V-20%

C23

1uF

1 2

25V-10%

C22

1uF

1 2

25V-10%

R71

1 2

499-1%

H2_VID1

H2_VID2

H2_VID3

8,12

R69

SUB*_4053P

1 2

499-1%

H2_VID4

8,12

R68

1 2

H2_VID5

8,12

499-1%

COMPUTER

INTEGRATED VRD 10.1 VOLTAGE

CORPORATION

AUSTIN,TEXAS

If this FET is populated, you must verify Vgs(th) is met!

TITLE

REGULATOR FOR PROC_2

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

REV.

D1660

A00-00

SHEET

7/14/2004 8 OF 60

SUB*_75EEC

.047uF 25V

20%

1 2

C715

1 2

249K-1%

R256

1 2

127K-1%

R235

8,12 8,12 8,12 8,12 8,12 8,12

VRD2_VSSSENSE

H2_VID0 H2_VID1 H2_VID2 H2_VID3 H2_VID4 H2_VID5

5 4 3 2 1 6

DELAY

COMP

FBRTN

VID0 VID1 VID2 VID3 VID4 VID5

GND

PWM1 PWM2 PWM3 PWM4

SW1 SW2 SW3 SW4

CSSUM CSREF

CSCOMP

26 25 24

23 22 21 20

17 16 18

VRD2_PWM3A VRD2_PWM4A

R347

1 2

0-5%

100K-1%

R297

ADP3168

NP*

X04_GT_031904 X04_GT_031904

C301

100pF 50V

C480

680pF 50V

X04_GT_031904

X04_GT_032204

R252

2 1

C709

R279

1 2

SUB*_H5002 X04_GT_031904

R328

1 2

X04_GT_031904

300-5%

X04_GT_031904

50V-10%

2700pF

4 4

+CPU_VID2

H2_VCCSENSE

X00_GT_052203

10.7K-1% 680pF 50V

X04_GT_031904

1 2

X04_GT_031904

R348

VRD2_VCCSENSE

1K-5%

X04_GT_031904

R1823

1 2

0-5% 0-5%

1.3K-1%

(1.33K)

R296

1 2

100K-1%

R1993

X04_GT_031904

SUB*_X5828

50V-10%

1000pF

C1811

100-5%

1 2

R1994

subsys done

A B

B D

7-14-2004_10:52

+12V

R427

1 2

+3.3V

100-1%

100K-5%

Locate near hot component in P1 core regulator.

R90

10K-1%

0.1uF 16V

1 2

R104

C719

0.1uF 16V 1 2

C716

10K-1%

3.32K-1%

R102

1 2

R183

R281

1K-1%

.22uF 25V

20%

1 2

C653

10K-1% 25.5K-1%

U17

V+ V-

LM339

R140

R254

8.2K-5%

U17

V+ V-

LM339

R1704

VRD1_THERMTRIP_N

5,46

100K-5%

1 2

10K-1%

1 2

R89

0.1uF 16V 1 2

R141

0.1uF 16V

C718

1 2

C717

10K-1%

3.32K-1%

R149

1 2

R192

R280

1K-1%

U17

V+ V-

LM339

1 2

10K-1% 25.5K-1%

R142

1 2

R253

+3.3V

8.2K-5%

U17

V+ V-

LM339

R1705

VRD2_THERMTRIP_N

5,46

Locate near hot component in P2 core regulator.

VRD Over Temperature Detect Circuit

ROOM=VRD_THERM

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

VRD THERMTRIP

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

9 OF 60

A B

B D

7-14-2004_10:52

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

10 OF 60

A B

B D

7-14-2004_10:52

ROOM=PROC_1

ROOM=PROC_2

ROOM=PROC_1

X02_tj_091603

+CPU_VTT

X03_tj_121503

L136

TO DO - MECHANICAL ADD'S NOT CORRECT

ECAD: Route trace from L128 to pin AB4

Route trace from L127 to pin AD4

10uH 165MA

to pin AD4

L137

1 2

C1492

1 2

V_VTT_H1_VCCA

cap between AB4 and AA5

22uF 6.3V22uF 6.3V

V_VTT_H1_VSSA

10uH 165MA

to pin AB4

+CPU_VTT

L138

+CPU_VTT

x00_tj_061403

Alternate PLL filter circuit recommended by Intel until on-die version validated.

+1.5V

R1583NP

1 2

0-5%

2.5V-20%-2STACK

680uF

1 2

C1588

C1570

1 2

4.7uF

C1371

6.3V-10%

1 2

0.1uF 16V

C1370

Place @ CPU1 Place @ CPU2

R1559

R1556

1 2

220

R1558

1 2

220

R1562

1 2

220

R1563

1 2

220

R1506

R1493

R1497

R1499

R1501

R1503

R1494

1 2

R1508

1 2

100-5%

x00_GT_010704

x04_tj_031604

V_1P5_H1_VCCPLL

0.1uF 16V

R1557

1 2

R1560

1 2

R1561

1 2

R1504

1 2

R1505

1 2

R1496

301-1%

R1498

R1500

R1502

R1495

1 2

R1492

1 2

NP*

10 - 12 mil traces

220

R1554

X X

H_A20M_N

H_SLP_N

H_NMI

H_INTR

H_SMI_N

H_INIT_N

H_IGNNE_N

H_STPCLK_N

H_FERR_N

H_BREQ0_N

H_BREQ1_N

H1_BREQ23_N

H1_ODTEN

H_PWRGOOD

H1_TESTHI0

H1_TESTHI1

H1_TESTHI2

H1_TESTHI3

H1_TESTHI4

H1_TESTHI5

H1_TESTHI6

H1_TESTHI7

H1_TESTHI8

H1_BOOTSEL

H_RST_N

11,33

11,33,55

11,33

11,17

12,33

11,15,17

Heat Sink Clips

Heat Sink RM

11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17

11,17 11,17

11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17

11,17 11,17

11,17 11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17

11,17 11,17 11,17

11,33 11,33 11,33 11,33

11,15,17

11,33

11,33 11,15,17 11,33,55

11,33

H_A3_N H_A4_N H_A5_N H_A6_N H_A7_N H_A8_N H_A9_N H_A10_N H_A11_N H_A12_N H_A13_N H_A14_N H_A15_N H_A16_N H_A17_N H_A18_N H_A19_N H_A20_N H_A21_N H_A22_N H_A23_N H_A24_N H_A25_N H_A26_N H_A27_N H_A28_N H_A29_N H_A30_N H_A31_N H_A32_N H_A33_N H_A34_N H_A35_N

H_AP0_N H_AP1_N

H_ADS_N H_ADSTB0_N H_ADSTB1_N

H_REQ0_N H_REQ1_N H_REQ2_N H_REQ3_N H_REQ4_N

H_BREQ0_N H_BREQ1_N H1_BREQ23_N

H_BNR_N H_BPRI_N H_LOCK_N H_BINIT_N

H_RS0_N H_RS1_N H_RS2_N H_RSP_N H_TRDY_N

H_HITM_N H_HIT_N H_DEFER_N

H_A20M_N H_SMI_N H_FERR_N H_IGNNE_N H1_IERR_N H_MCERR_N

H_SLP_N H_STPCLK_N H_RST_N H_INIT_N

H_INTR H_NMI

CK_167M_CPU1_P

CK_167M_CPU1_N

SUB=SUB*_4M319

Retention Screws

PROC_1

A22 A20 B18 C18 A19 C17 D17 A13 B16 B14 B13 A12 C15 C14 D16 D15 F15 A10 B10 B11 C12 E14 D13

E13 D12 C11

E10

D19 F17 F14

B19 B21 C21 C20 B22

D20 F12 E11 D10

F20 D23 A17 F11

E21 D22 F21

E19

A23 E22 C23

F27 C27 E27 C26

AE6

B24 G23

A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25

A26

A27 A28 A29 A30

A31

A32

A33

A34

A35

AP0

AP1

ADS ADSTB0 ADSTB1

REQ0 REQ1 REQ2 REQ3 REQ4

BR0 BR1 BR2 BR3

BNR BPRI LOCK BINIT

RS0 RS1 RS2

RSP TRDY

HITM HIT DEFER

A20M SMI FERR/PBE IGNNE

IERR

MCERR

SLP

STPCLK

RESET

INIT

LINT0 LINT1

BCLK0

BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

ADD1=ADD*_89JJP_RETSCRW1 ADD2=ADD*_89JJP_RETSCRW2 ADD3=ADD*_89JJP_RETSCRW3

D0 D1 D2 D3 D4 D5 D6 D7 D8

D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

DP0 DP1 DP2 DP3

DSTBN0 DSTBN1 DSTBN2 DSTBN3

DSTBP0 DSTBP1 DSTBP2 DSTBP3

DBI0 DBI1 DBI2 DBI3 DBSY DRDY

Heat Sink RM screws

Y26 AA27 Y24 AA25 AD27 Y23 AA24 AB26 AB25 AB23 AA22 AA21 AB20 AB22 AB19 AA19 AE26 AC26 AD25 AE25 AC24 AD24 AE23 AC23 AA18 AC20 AC21 AE22 AE20 AD21 AD19 AB17 AB16 AA16 AC17 AE13 AD18 AB15 AD13 AD14 AD11 AC12 AE10 AC11 AE9 AD10 AD8 AC9 AA13 AA14 AC14 AB12 AB13 AA11 AA10 AB10 AC8 AD7 AE7 AC6 AC5 AA8 Y9 AB6

AC18 AE19 AC15 AE17

Y21 Y18 Y15 Y12

Y20 Y17 Y14 Y11

AC27 AD22 AE12 AB9 F18 E18

H_D10_N H_D11_N H_D12_N H_D13_N H_D14_N H_D15_N H_D16_N H_D17_N H_D18_N H_D19_N H_D20_N H_D21_N H_D22_N H_D23_N H_D24_N H_D25_N H_D26_N H_D27_N H_D28_N H_D29_N H_D30_N H_D31_N H_D32_N H_D33_N H_D34_N H_D35_N H_D36_N H_D37_N H_D38_N H_D39_N H_D40_N H_D41_N H_D42_N H_D43_N H_D44_N H_D45_N H_D46_N H_D47_N H_D48_N H_D49_N H_D50_N H_D51_N H_D52_N H_D53_N H_D54_N H_D55_N H_D56_N H_D57_N H_D58_N H_D59_N H_D60_N H_D61_N H_D62_N H_D63_N

H_DP0_N H_DP1_N H_DP2_N H_DP3_N

H_DSTBN0_N H_DSTBN1_N H_DSTBN2_N H_DSTBN3_N

H_DSTBP0_N H_DSTBP1_N H_DSTBP2_N H_DSTBP3_N

H_DBI0_N H_DBI1_N H_DBI2_N H_DBI3_N H_DBSY_N H_DRDY_N

H_D0_N H_D1_N H_D2_N H_D3_N H_D4_N H_D5_N H_D6_N H_D7_N H_D8_N H_D9_N

11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17

11,17 11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17 11,17

Swizzled

11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17 11,17

11,17 11,17

11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17

11,17 11,17

11,17 11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17

11,17 11,17 11,17

11,33 11,33 11,33 11,33

11,15,17

11,33

11,33 11,15,17 11,33,55

11,33

H_AP0_N H_AP1_N

H_ADS_N H_ADSTB0_N H_ADSTB1_N

H_REQ0_N H_REQ1_N H_REQ2_N H_REQ3_N H_REQ4_N

H_BREQ1_N H_BREQ0_N H2_BREQ23_N

H_BNR_N H_BPRI_N H_LOCK_N H_BINIT_N

H_RS0_N H_RS1_N H_RS2_N H_RSP_N H_TRDY_N

H_HITM_N H_HIT_N H_DEFER_N

H_A20M_N H_SMI_N H_FERR_N H_IGNNE_N H2_IERR_N H_MCERR_N

H_SLP_N H_STPCLK_N H_RST_N H_INIT_N

H_INTR H_NMI

CK_167M_CPU2_P

CK_167M_CPU2_N

SUB=SUB*_4M319

A22 A20 B18 C18 A19 C17 D17 A13 B16 B14 B13 A12 C15 C14 D16 D15 F15 A10 B10 B11 C12 E14 D13

B8 E13 D12 C11

E10

D19 F17 F14

B19 B21 C21 C20 B22

D20 F12 E11 D10

F20 D23 A17 F11

E21 D22 F21

C6 E19

A23 E22 C23

F27 C27 E27 C26

AE6

B24 G23

PROC_2

A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35

AP0 AP1

ADS ADSTB0 ADSTB1

REQ0 REQ1 REQ2 REQ3 REQ4

BR0 BR1 BR2 BR3

BNR BPRI LOCK BINIT

RS0 RS1 RS2 RSP TRDY

HITM HIT DEFER

A20M SMI FERR/PBE IGNNE IERR MCERR

SLP STPCLK RESET INIT

LINT0 LINT1

BCLK0 BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63

DP0 DP1 DP2 DP3

DSTBN0 DSTBN1 DSTBN2 DSTBN3

DSTBP0 DSTBP1 DSTBP2 DSTBP3

DBI0 DBI1 DBI2 DBI3 DBSY DRDY

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

AC18 AE19 AC15 AE17

Y21 Y18 Y15 Y12

Y20 Y17 Y14 Y11

AC27 AD22 AE12 AB9 F18 E18

H_D0_N H_D1_N H_D2_N H_D3_N H_D4_N H_D5_N H_D6_N H_D7_N H_D8_N

H_D9_N H_D10_N H_D11_N H_D12_N H_D13_N H_D14_N H_D15_N H_D16_N H_D17_N H_D18_N H_D19_N H_D20_N H_D21_N H_D22_N H_D23_N H_D24_N H_D25_N H_D26_N H_D27_N H_D28_N H_D29_N H_D30_N H_D31_N H_D32_N H_D33_N H_D34_N H_D35_N H_D36_N H_D37_N H_D38_N H_D39_N H_D40_N H_D41_N H_D42_N H_D43_N H_D44_N H_D45_N H_D46_N H_D47_N H_D48_N H_D49_N H_D50_N H_D51_N H_D52_N H_D53_N H_D54_N H_D55_N H_D56_N H_D57_N H_D58_N H_D59_N H_D60_N H_D61_N H_D62_N H_D63_N

H_DP0_N H_DP1_N H_DP2_N H_DP3_N

H_DSTBN0_N H_DSTBN1_N H_DSTBN2_N H_DSTBN3_N

H_DSTBP0_N H_DSTBP1_N H_DSTBP2_N H_DSTBP3_N

H_DBI0_N H_DBI1_N H_DBI2_N H_DBI3_N H_DBSY_N H_DRDY_N

11,17 11,17 11,17 11,17

11,17 11,17 11,17 11,17 11,17 11,17

+CPU_VTT

R1570

1 2

39-5%

R1566

1 2

39-5%

R1569

1 2

39-5%

R1567

1 2

39-5%

R1568

1 2

39-5%

R1518

1 2

R1516

1 2

R1514

1 2

R1512

1 2

R1520

R1511

R1509

1 2

C1448

47pF

50V-5% C1444

1 2

47pF

50V-5%

C1445

2 1

47pF

50V-5%

C1446

47pF

50V-5%

C1447

47pF

50V-5%

R1521

R1517

R1515

R1513

R1519

R1565

ECAD: Route trace from L125 to pin AB4

Route trace from L126 to pin AD4

H_BINIT_N

H_BNR_N

H_HIT_N

H_HITM_N

H_MCERR_N

H2_BREQ23_N

H2_TESTHI0

H2_TESTHI1

H2_TESTHI2

H2_TESTHI3

H2_TESTHI4

H2_TESTHI5

H2_TESTHI6

H2_TESTHI7

H2_TESTHI8

H_FORCEPR_N

H2_BOOTSEL

H_TEST_BUS

11,17

11,15,17

5,12

Dangling 750 ohm resistors are there to help fine-tune VREF's using a variable powr supply during margin testing

775mV

x04_sd

775mV

x04_sd

754mV

+CPU_VTT

R1592

R370

1 2

+CPU_VTT

R1593

R371

+CPU_VTT

R1594

R372

84.5-1%

1 2

+CPU_VTT

R1595

R373

84.5-1%

1 2

10uH 165MA

to pin AD4

L139

10uH 165MA

to pin AB4

CPU1 GTL VREF

ECAD: Route <1.5" trace. ECAD: Place 220pf caps under CPU

49.9-1%

NET_PHYSICAL_TYPE=50MIL

C1451

90.9-1%90.9-1%

ECAD: Route <1.5" trace. ECAD: Place 220pf caps under CPU

49.9-1%

1uF

1 2

10V-10%

NET_PHYSICAL_TYPE=50MIL

C1454

1uF

1 2

10V-10%

CPU2 GTL VREF

ECAD: Route <1.5" trace. ECAD: Place 220pf caps under CPU

49.9-1%49.9-1% NET_PHYSICAL_TYPE=50MIL

1 2

C1452

1 2

1uF

10V-10%

1uF

10V-10%

C1453

ECAD: Route <1.5" trace. ECAD: Place 220pf caps under CPU

NET_PHYSICAL_TYPE=50MIL

C1491

R1824

NET_PHYSICAL_TYPE=50MIL

1 2

0-5%

C1581

NET_PHYSICAL_TYPE=50MIL

R1825 NET_PHYSICAL_TYPE=50MIL

1 2

0-5%

NET_PHYSICAL_TYPE=50MIL

R1826

1 2

0-5%

R1827

1 2

0-5%

V_VTT_H2_VCCA

cap between AB4 and AA5

V_VTT_H2_VSSA

220pF

50V-10%

NC_H1_GTLREF01

C1582

C1579

NC_H1_GTLREF23

220pF

50V-10%

C1580

220pF

50V-10%

220pF

50V-10%

NET_PHYSICAL_TYPE=50MIL

C1578

220pF

50V-10%

NC_H2_GTLREF01

C1577

220pF

50V-10%

NET_PHYSICAL_TYPE=50MIL

C1583

NC_H2_GTLREF23

220pF

50V-10%

C1584

220pF

50V-10%

NET_PHYSICAL_TYPE=50MIL

H1_GTLREF01

2 1

750-1%

R323

NP01

H1_GTLREF23

750-1%

R321

NP01

H2_GTLREF01

750-1%

R319

NP01

H2_GTLREF23

2 1

750-1%

R320

NP01

ADD4=ADD*_89JJP_RETSCRW4 ADD5=ADD*_89JJP_RETSCRW5

+1.5V

4 4

ADD6=ADD*_89JJP_RETSCRW6 ADD7=ADD*_89JJP_RETSCRW7

R1522

1 2

H2_ODTEN

ADD8=ADD*_89JJP_RETSCRW8

R1584NP

PROCESSORS 1 & 2

0-5%

2.5V-20%-2STACK

680uF

1 2

C1587

C1571

4.7uF

C1372

6.3V-10%

0.1uF 16V

C1373

V_1P5_H2_VCCPLL

x00_sd_061703

1 2

0.1uF 16V

x03b_tj_012004

SUB*_X4108

ST1

GND

NC_ST1_2

GROUND, BRACKET

RETENTION SUPPORT, W/CLIP

SUB*_X4108

ST2

GND

NC_ST2_2

GROUND, BRACKET

RETENTION SUPPORT, W/CLIP

1U Bottom Support Bracket

2U/5U Bottom Support Bracket

proc heatsink RM boat

two of the boats are represented here

ADD7=ADD02_Y1255_BRKT1 ADD8=ADD02_Y1255_BRKT2

ADD1=ADD13_W1578_BRKT3 ADD2=ADD13_W1578_BRKT4

ADD3=ADD*_X4108_RETMOD1 ADD4=ADD*_X4108_RETMOD2 ADD5=ADD*_X4108_RETMOD3

ADD1=ADD*_H3668_RMCLIP1 ADD2=ADD*_H3668_RMCLIP2

ADD3=ADD*_H3668_RMCLIP3 ADD4=ADD*_H3668_RMCLIP4

ADD5=ADD*_X4108_RETMOD5 ADD6=ADD*_X4108_RETMOD6 ADD7=ADD*_X4108_RETMOD7

proc heatsink RM clip

x03b_tj_012004

proc heatsink RM boat

x03b_tj_012004

PROCESSOR 1 & 2

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

SHEET

7/14/2004

REV.

A00-00

11 OF 60

subsys done

A B

B D

7-14-2004_10:52

SUB=SUB*_4M319

PROC_1

VSS_A5

A11

VSS_A11

A21

VSS_A21

A27

VSS_A27

A29

VSS_A29

A31

VSS_A31

VSS_B2

VSS_B9

B15

VSS_B15

B17

VSS_B17

B23

VSS_B23

B28

VSS_B28

B30

VSS_B30

VSS_C7

C13

VSS_C13

C19

VSS_C19

C25

VSS_C25

C29

VSS_C29

C31

VSS_C31

VSS_D2

VSS_D5

D11

VSS_D11

D21

VSS_D21

D27

VSS_D27

D28

VSS_D28

D30

VSS_D30

VSS_E9

E15

VSS_E15

E17

VSS_E17

E23

VSS_E23

E29

VSS_E29

E31

VSS_E31

VSS_F2

VSS_F7

F13

VSS_F13

F19

VSS_F19

F25

VSS_F25

F28

VSS_F28

F30

VSS_F30

VSS_G1

VSS_G3

VSS_G5

VSS_G9

G25

VSS_G25

G27

VSS_G27

G29

VSS_G29

G31

VSS_G31

VSS_H2

VSS_H4

VSS_H6

VSS_H8

H24

VSS_H24

H26

VSS_H26

H28

VSS_H28

H30

VSS_H30

VSS_J1

VSS_J3

VSS_J5

VSS_J7

VSS_J9

J23

VSS_J23

J25

VSS_J25

J27

VSS_J27

J29

VSS_J29

J31

VSS_J31

VSS_K2

VSS_K4

VSS_K6

VSS_K8

K24

VSS_K24

K26

VSS_K26

K28

VSS_K28

K30

VSS_K30

VSS_L1

VSS_L3

VSS_L5

VSS_L7

VSS_L9

L23

VSS_L23

L25

VSS_L25

L27

VSS_L27

L29

VSS_L29

L31

VSS_L31

VSS_M2

VSS_M4

VSS_M6

VSS_M8

M24

VSS_M24

M26

VSS_M26

M28

VSS_M28

M30

VSS_M30

VSS_N2

VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8 VSS_N24 VSS_N26 VSS_N28 VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9 VSS_P23 VSS_P25 VSS_P27 VSS_P29 VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8 VSS_R24 VSS_R26 VSS_R28 VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9 VSS_T23 VSS_T25 VSS_T27 VSS_T29 VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8 VSS_U24 VSS_U26 VSS_U28 VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9 VSS_V23 VSS_V25 VSS_V27 VSS_V29 VSS_V31

VSS_W2

VSS_W4 VSS_W24 VSS_W26 VSS_W28 VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7 VSS_Y13 VSS_Y19 VSS_Y25 VSS_Y31 VSS_AA2 VSS_AA9

VSS_AA15 VSS_AA17 VSS_AA23 VSS_AA30

VSS_AB1 VSS_AB5

VSS_AB11 VSS_AB21 VSS_AB27 VSS_AB31

VSS_AC2 VSS_AC7

VSS_AC13 VSS_AC19 VSS_AC25

VSS_AD3 VSS_AD9

VSS_AD15 VSS_AD17 VSS_AD23 VSS_AD31

VSS_AE2

VSS_AE11 VSS_AE21 VSS_AE27

N6 N8 N24 N26 N28 N30 P1 P3 P5 P7 P9 P23 P25 P27 P29 P31 R2 R4 R6 R8 R24 R26 R28 R30 T1 T3 T5 T7 T9 T23 T25 T27 T29 T31 U2 U4 U6 U8 U24 U26 U28 U30 V1 V3 V5 V7 V9 V23 V25 V27 V29 V31 W2 W4 W24 W26 W28 W30 Y1 Y5 Y7 Y13 Y19 Y25 Y31 AA2 AA9 AA15 AA17 AA23 AA30 AB1 AB5 AB11 AB21 AB27 AB31 AC2 AC7 AC13 AC19 AC25 AD3 AD9 AD15 AD17 AD23 AD31 AE2 AE11 AE21 AE27

SUB=SUB*_4M319

PROC_2

VSS_A5

A11

VSS_A11

A21

VSS_A21

A27

VSS_A27

A29

VSS_A29

A31

VSS_A31

VSS_B2

VSS_B9

B15

VSS_B15

B17

VSS_B17

B23

VSS_B23

B28

VSS_B28

B30

VSS_B30

VSS_C7

C13

VSS_C13

C19

VSS_C19

C25

VSS_C25

C29

VSS_C29

C31

VSS_C31

VSS_D2

VSS_D5

D11

VSS_D11

D21

VSS_D21

D27

VSS_D27

D28

VSS_D28

D30

VSS_D30

VSS_E9

E15

VSS_E15

E17

VSS_E17

E23

VSS_E23

E29

VSS_E29

E31

VSS_E31

VSS_F2

VSS_F7

F13

VSS_F13

F19

VSS_F19

F25

VSS_F25

F28

VSS_F28

F30

VSS_F30

VSS_G1

VSS_G3

VSS_G5

VSS_G9

G25

VSS_G25

G27

VSS_G27

G29

VSS_G29

G31

VSS_G31

VSS_H2

VSS_H4

VSS_H6

VSS_H8

H24

VSS_H24

H26

VSS_H26

H28

VSS_H28

H30

VSS_H30

VSS_J1

VSS_J3

VSS_J5

VSS_J7

VSS_J9

J23

VSS_J23

J25

VSS_J25

J27

VSS_J27

J29

VSS_J29

J31

VSS_J31

VSS_K2

VSS_K4

VSS_K6

VSS_K8

K24

VSS_K24

K26

VSS_K26

K28

VSS_K28

K30

VSS_K30

VSS_L1

VSS_L3

VSS_L5

VSS_L7

VSS_L9

L23

VSS_L23

L25

VSS_L25

L27

VSS_L27

L29

VSS_L29

L31

VSS_L31

VSS_M2

VSS_M4

VSS_M6

VSS_M8

M24

VSS_M24

M26

VSS_M26

M28

VSS_M28

M30

VSS_M30

VSS_N2

VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8 VSS_N24 VSS_N26 VSS_N28 VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9 VSS_P23 VSS_P25 VSS_P27 VSS_P29 VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8 VSS_R24 VSS_R26 VSS_R28 VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9 VSS_T23 VSS_T25 VSS_T27 VSS_T29 VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8 VSS_U24 VSS_U26 VSS_U28 VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9 VSS_V23 VSS_V25 VSS_V27 VSS_V29 VSS_V31

VSS_W2

VSS_W4 VSS_W24 VSS_W26 VSS_W28 VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7 VSS_Y13 VSS_Y19 VSS_Y25 VSS_Y31 VSS_AA2 VSS_AA9

VSS_AA15 VSS_AA17 VSS_AA23 VSS_AA30

VSS_AB1 VSS_AB5

VSS_AB11 VSS_AB21 VSS_AB27 VSS_AB31

VSS_AC2 VSS_AC7

VSS_AC13 VSS_AC19 VSS_AC25

VSS_AD3 VSS_AD9

VSS_AD15 VSS_AD17 VSS_AD23 VSS_AD31

VSS_AE2

VSS_AE11 VSS_AE21 VSS_AE27

11 12 11 12

5,46

15 15

12 12 12 12

11 11 11 11 11 11 11 11 11

45 45

5,11,12

12,15 12,15 12,15 12,15 12,15 12,15

12,15

15 12,15 12,15

+CPU_VTT

H1_ODTEN H1_SLEW_CTRL H1_BOOTSEL H1_OPTIMIZED

H1_CPU_PRES_N H1_BSEL0 H1_BSEL1

H1_COMP0 H1_COMP1 H1_COMP2 H1_COMP3

H1_TESTHI0 H1_TESTHI1 H1_TESTHI2 H1_TESTHI3 H1_TESTHI4 H1_TESTHI5 H1_TESTHI6 H1_TESTHI7 H1_TESTHI8

H1_GTLREF01

H1_GTLREF23

H1_THRM_AN H1_THRM_CA NC_H1_PKG_ID

H1_PROCHOT_N H_FORCEPR_N H1_THERMTRIP_N

H_BPM0_N H_BPM1_N H_BPM2_N H_BPM3_N H_BPM4_N H_BPM5_N

ITP_TCK ITP_TDI_H1 ITP_TDO_H1 ITP_TMS ITP_TRST_N

SUB=SUB*_4M319

Place @ CPU1

R1526

1 2

R1528

R1530

1 2

R1601

100-1%

R1597

49.9-1%

R60

301-1%

AC30

G7 C1

A3 AA3 AB3

AD16

E16

AC28

D25

Y6 AA7 AD5 AE5 A26 Y29

W23

W9 F23

F9 AA28

Y27 Y28 AE4

B25 A15 F26

E24 C24 E25 A25 F24

R1531

R1527

1 2

R1529

R1600

1 2

100-1%

R1596

1 2

49.9-1%

H_VTT_PWRGOOD

PROC_1

ODTEN SLEW_CTRL BOOT_SELECT OPTIMIZED/COMPAT

SKTOCC BSEL0 BSEL1

COMP0 COMP1 COMP2 COMP3

TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8

GTLREF0 GTLREF1 GTLREF2 GTLREF3 NC_AA28

THERMDA THERMDC SMB_PRT

PROCHOT FORCEPR THRMTRIP

BPM0 BPM1 BPM2 BPM3 BPM4 BPM5

TCK TDI TDO TMS TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

H_BPM0_N

H_BPM1_N

H_BPM2_N

H_BPM3_N

H_BPM4_N

H_BPM5_N

H1_COMP2

H1_COMP3

H1_COMP0

H1_COMP1

12,15

5,12

VID0 VID1 VID2 VID3 VID4 VID5

VCCPLL

VCCIOPLL

VCCA VSSA

VCCSENSE VSSSENSE

PWRGOOD

RSVD_A16

RSVD_W3 RSVD_Y3

RSVD_AC1 RSVD_AE15 RSVD_AE16 RSVD_AE28 RSVD_AE29

NC_AA29 NC_AB28 NC_AB29 NC_AC29 NC_AD28 NC_AD29

VTTEN

VIDPWRGD

VTT_A4 VTT_B4

VTT_B12

VTT_C5 VTT_C10 VTT_E12 VTT_F10 VTT_Y10

VTT_AA12 VTT_AC10 VTT_AD12

H1_SLEW_CTRL

H1_OPTIMIZED

F3 E3 D3 C3 B3 A1

AD1 AD4

AB4 AA5

B27 D26

AB7

A16 W3 Y3 AC1 AE15 AE16 AE28 AE29

AA29 AB28 AB29 AC29 AD28 AD29

E1 B1

A4 B4 B12 C5 C10 E12 F10 Y10 AA12 AC10 AD12

H1_VID0 H1_VID1 H1_VID2 H1_VID3 H1_VID4 H1_VID5

V_1P5_H1_VCCPLL

V_VTT_H1_VCCA V_VTT_H1_VSSA

H1_VCCSENSE H1_VSSSENSE

H_PWRGOOD

H_TEST_BUS NC_H1_W3 NC_H1_Y3 NC_H1_AC1 NC_H1_AE15 NC_H1_AE16 NC_H1_AE28 NC_H1_AE29

NC_H1_AA28 NC_H1_AA29 NC_H1_AB28 NC_H1_AB29 NC_H1_AC29 NC_H1_AD28 NC_H1_AD29

H1_VTT_EN H_VTT_PWRGOOD

+CPU_VTT

R1523

R1585

0-5%

R1524

R1525

5151

7 7 7 7 7 7

11 11

X00_GT_052203

X00_TJ_061803

X00_GT_052203

11,12,33

11,12

5 5,12

11 12 11 12

5,46

15 15

12 12 12 12

11 11 11 11 11 11 11 11 11

45 45

5,11,12

12,15 12,15 12,15 12,15 12,15 12,15

12,15

15 12,15 12,15

+CPU_VTT

H2_ODTEN H2_SLEW_CTRL H2_BOOTSEL H2_OPTIMIZED

H2_CPU_PRES_N H2_BSEL0 H2_BSEL1

H2_COMP0 H2_COMP1 H2_COMP2 H2_COMP3

H2_TESTHI0 H2_TESTHI1 H2_TESTHI2 H2_TESTHI3 H2_TESTHI4 H2_TESTHI5 H2_TESTHI6 H2_TESTHI7 H2_TESTHI8

H2_GTLREF01

H2_GTLREF23

H2_THRM_AN H2_THRM_CA NC_H2_PKG_ID

H2_PROCHOT_N H_FORCEPR_N H2_THERMTRIP_N

H_BPM0_N H_BPM1_N H_BPM2_N H_BPM3_N H_BPM4_N H_BPM5_N

ITP_TCK ITP_TDI_H2 ITP_TDO_H2 ITP_TMS ITP_TRST_N

SUB=SUB*_4M319

Place @ CPU2

R1603

R1602

1 2

100-1%

R1599

1 2

49.9-1%

100-1%

R1598

49.9-1%

AC30

AA3 AB3

AD16

E16

AC28

D25

AA7 AD5 AE5 A26 Y29

W23

F23

Y27 Y28 AE4

B25 A15 F26

E24 C24 E25 A25 F24

PROC_2

ODTEN SLEW_CTRL

BOOT_SELECT

OPTIMIZED/COMPAT

SKTOCC BSEL0 BSEL1

COMP0 COMP1 COMP2 COMP3

TESTHI0

TESTHI1

TESTHI2

TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8

GTLREF0

GTLREF1 GTLREF2 GTLREF3 NC_AA28

THERMDA THERMDC SMB_PRT

PROCHOT FORCEPR THRMTRIP

BPM0

BPM1

BPM2

BPM3

BPM4

BPM5

TCK TDI TDO TMS TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

H2_COMP2

H2_COMP3

H2_COMP0

H2_COMP1

VID0 VID1 VID2 VID3 VID4 VID5

VCCPLL

VCCIOPLL

VCCA VSSA

VCCSENSE VSSSENSE

PWRGOOD

RSVD_A16

RSVD_W3 RSVD_Y3

RSVD_AC1 RSVD_AE15 RSVD_AE16 RSVD_AE28 RSVD_AE29

NC_AA29 NC_AB28 NC_AB29 NC_AC29 NC_AD28 NC_AD29

VTTEN

VIDPWRGD

VTT_A4 VTT_B4

VTT_B12

VTT_C5 VTT_C10 VTT_E12 VTT_F10 VTT_Y10

VTT_AA12 VTT_AC10 VTT_AD12

F3 E3 D3 C3 B3 A1

AD1 AD4

AB4 AA5

B27 D26

AB7

A16 W3 Y3 AC1 AE15 AE16 AE28 AE29

AA28F9 AA29 AB28 AB29 AC29 AD28 AD29

E1 B1

A4 B4 B12 C5 C10 E12 F10 Y10 AA12 AC10 AD12

H2_SLEW_CTRL

H2_OPTIMIZED

H2_VID0 H2_VID1 H2_VID2 H2_VID3 H2_VID4 H2_VID5

V_1P5_H2_VCCPLL

V_VTT_H2_VCCA V_VTT_H2_VSSA

H2_VCCSENSE H2_VSSSENSE

H_PWRGOOD

H_TEST_BUS NC_H2_W3 NC_H2_Y3 NC_H2_AC1 NC_H2_AE15 NC_H2_AE16 NC_H2_AE28 NC_H2_AE29

NC_H2_AA28 NC_H2_AA29 NC_H2_AB28 NC_H2_AB29 NC_H2_AC29 NC_H2_AD28 NC_H2_AD29

H2_VTT_EN H_VTT_PWRGOOD

+CPU_VTT

R1540

1 2

R1586

1 2

0-5%

R1539

1 2

R1538

1 2

8 8 8 8 8 8

11 11

X00_GT_052203

X00_TJ_061803

X00_GT_052203

11,12,33

11,12

5 5,12

51 51

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

PROCESSOR 1 & 2

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

ECAD: place resistor near processor

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

12 OF 60

subsys done

A B

B D

+CPU_VID1

ROOM=PROC_1

7-14-2004_10:52

x00_tj_041003

+CPU_VID1

SUB=SUB*_4M319

PROC_1

VCC_A2

VCC_A8

A14

VCC_A14

A18

VCC_A18

A24

VCC_A24

A28

VCC_A28

A30

VCC_A30

VCC_B6

B20

VCC_B20

B26

VCC_B26

B29

VCC_B29

B31

VCC_B31

VCC_C2

VCC_C4

C16

VCC_C16

C22

VCC_C22

C28

VCC_C28

C30

VCC_C30

VCC_D1

VCC_D8

D14

VCC_D14

D18

VCC_D18

D24

VCC_D24

D29

VCC_D29

D31

VCC_D31

VCC_E2

VCC_E6

E20

VCC_E20

E26

VCC_E26

E28

VCC_E28

E30

VCC_E30

VCC_F1

VCC_F4

F16

VCC_F16

F22

VCC_F22

F29

VCC_F29

F31

VCC_F31

VCC_G2

VCC_G4

VCC_G6

VCC_G8

G24

VCC_G24

G26

VCC_G26

G28

VCC_G28

G30

VCC_G30

VCC_H1

VCC_H3

VCC_H5

VCC_H7

VCC_H9

H23

VCC_H23

H25

VCC_H25

H27

VCC_H27

H29

VCC_H29

H31

VCC_H31

VCC_J2

VCC_J4

VCC_J6

VCC_J8

J24

VCC_J24

J26

VCC_J26

J28

VCC_J28

J30

VCC_J30

VCC_K1

VCC_K3

VCC_K5

VCC_K7

VCC_K9

K23

VCC_K23

K25

VCC_K25

K27

VCC_K27

K29

VCC_K29

K31

VCC_K31

VCC_L2

VCC_L4

VCC_L6

VCC_L8

L24

VCC_L24

L26

VCC_L26

L28

VCC_L28

L30

VCC_L30

VCC_M1

VCC_M3

VCC_M5

VCC_M7

VCC_M9

M23

VCC_M23

M25

VCC_M25

M27

VCC_M27

M29

VCC_M29

M31

VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 3 OF 4

VCC_N1 VCC_N3 VCC_N5 VCC_N7

VCC_N9 VCC_N23 VCC_N25 VCC_N27 VCC_N29 VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8 VCC_P24 VCC_P26 VCC_P28 VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9 VCC_R23 VCC_R25 VCC_R27 VCC_R29 VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8 VCC_T24 VCC_T26 VCC_T28 VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9 VCC_U23 VCC_U25 VCC_U27 VCC_U29 VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8 VCC_V24 VCC_V26 VCC_V28 VCC_V30

VCC_W1 VCC_W25 VCC_W27 VCC_W29 VCC_W31

VCC_Y2 VCC_Y16 VCC_Y22 VCC_Y30 VCC_AA1 VCC_AA4 VCC_AA6

VCC_AA20 VCC_AA26 VCC_AA31

VCC_AB2 VCC_AB8

VCC_AB14 VCC_AB18 VCC_AB24 VCC_AB30

VCC_AC3 VCC_AC4

VCC_AC16 VCC_AC22 VCC_AC31

VCC_AD2 VCC_AD6

VCC_AD20 VCC_AD26 VCC_AD30

VCC_AE3 VCC_AE8

VCC_AE14 VCC_AE18 VCC_AE24

+CPU_VID1

N1 N3 N5 N7 N9 N23 N25 N27 N29 N31 P2 P4 P6 P8 P24 P26 P28 P30 R1 R3 R5 R7 R9 R23 R25 R27 R29 R31 T2 T4 T6 T8 T24 T26 T28 T30 U1 U3 U5 U7 U9 U23 U25 U27 U29 U31 V2 V4 V6 V8 V24 V26 V28 V30 W1 W25 W27 W29 W31 Y2 Y16 Y22 Y30 AA1 AA4 AA6 AA20 AA26 AA31 AB2 AB8 AB14 AB18 AB24 AB30 AC3 AC4 AC16 AC22 AC31 AD2 AD6 AD20 AD26 AD30 AE3 AE8 AE14 AE18 AE24

+CPU_VID2 +CPU_VID2

PROC_2

SUB=SUB*_4M319

VCC_A2

VCC_A8

A14

VCC_A14

A18

VCC_A18

A24

VCC_A24

A28

VCC_A28

A30

VCC_A30

VCC_B6

B20

VCC_B20

B26

VCC_B26

B29

VCC_B29

B31

VCC_B31

VCC_C2

VCC_C4

C16

VCC_C16

C22

VCC_C22

C28

VCC_C28

C30

VCC_C30

VCC_D1

VCC_D8

D14

VCC_D14

D18

VCC_D18

D24

VCC_D24

D29

VCC_D29

D31

VCC_D31

VCC_E2

VCC_E6

E20

VCC_E20

E26

VCC_E26

E28

VCC_E28

E30

VCC_E30

VCC_F1

VCC_F4

F16

VCC_F16

F22

VCC_F22

F29

VCC_F29

F31

VCC_F31

VCC_G2

VCC_G4

VCC_G6

VCC_G8

G24

VCC_G24

G26

VCC_G26

G28

VCC_G28

G30

VCC_G30

VCC_H1

VCC_H3

VCC_H5

VCC_H7

VCC_H9

H23

VCC_H23

H25

VCC_H25

H27

VCC_H27

H29

VCC_H29

H31

VCC_H31

VCC_J2

VCC_J4

VCC_J6

VCC_J8

J24

VCC_J24

J26

VCC_J26

J28

VCC_J28

J30

VCC_J30

VCC_K1

VCC_K3

VCC_K5

VCC_K7

VCC_K9

K23

VCC_K23

K25

VCC_K25

K27

VCC_K27

K29

VCC_K29

K31

VCC_K31

VCC_L2

VCC_L4

VCC_L6

VCC_L8

L24

VCC_L24

L26

VCC_L26

L28

VCC_L28

L30

VCC_L30

VCC_M1

VCC_M3

VCC_M5

VCC_M7

VCC_M9

M23

VCC_M23

M25

VCC_M25

M27

VCC_M27

M29

VCC_M29

M31

VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 3 OF 4

VCC_N1 VCC_N3 VCC_N5 VCC_N7

VCC_N9 VCC_N23 VCC_N25 VCC_N27 VCC_N29 VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8 VCC_P24 VCC_P26 VCC_P28 VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9 VCC_R23 VCC_R25 VCC_R27 VCC_R29 VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8 VCC_T24 VCC_T26 VCC_T28 VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9 VCC_U23 VCC_U25 VCC_U27 VCC_U29 VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8 VCC_V24 VCC_V26 VCC_V28 VCC_V30

VCC_W1 VCC_W25 VCC_W27 VCC_W29 VCC_W31

VCC_Y2 VCC_Y16 VCC_Y22 VCC_Y30 VCC_AA1 VCC_AA4 VCC_AA6

VCC_AA20 VCC_AA26 VCC_AA31

VCC_AB2 VCC_AB8

VCC_AB14 VCC_AB18 VCC_AB24 VCC_AB30

VCC_AC3 VCC_AC4

VCC_AC16 VCC_AC22 VCC_AC31

VCC_AD2 VCC_AD6

VCC_AD20 VCC_AD26 VCC_AD30

VCC_AE3 VCC_AE8

VCC_AE14 VCC_AE18 VCC_AE24

X00_GT_052803

C536

+CPU_VID2

C294

ECAD: Place 7 caps on each side of the each CPU

+CPU_VID1

+CPU_VID2

+CPU_VTT

SUB*_K1098

560uF

10uF 6.3V

C537

4V-20%

SUB*_K1098

560uF

4V-20%

SUB*_D2341

C1526

C1546

1 2

C1539

SUB*_D2341

C1510

C1540

C1545

C547

SUB*_K1098

560uF

C538

4V-20%

SUB*_K1098

560uF

4V-20%

C539

SUB*_K1098

560uF

4V-20%

C540

SUB*_K1098

560uF

4V-20%

ROOM=PROC_2

SUB*_K1098

560uF

10uF 6.3V

ECAD: Place on back side of planar

10uF 6.3V

C548

4V-20%

SUB*_D2341

C1520

ECAD: Place these 12 caps in CPU socket cavity

C1547

1 2

ECAD: Place on back side of planar

C1538

SUB*_D2341

C1509

ECAD: Place these 12 caps in CPU socket cavity

C1534

ECAD: Place on back side of planar

C1516

ECAD: Place on back side of planar

SUB*_K1098

560uF

SUB*_D2341

10uF 6.3V

1 2

10uF 6.3V

C542

4V-20%

C1525

C1548

C1528

SUB*_D2341

C1508

C1535

C1517

SUB*_K1098

560uF

4V-20%

SUB*_D2341

10uF 6.3V

1 2

10uF 6.3V

SUB*_D2341

10uF 6.3V

C543

C1521

C1549

C1529

C1507

C1541

C1518

SUB*_K1098

560uF

SUB*_D2341

10uF 6.3V

SUB*_D2341

10uF 6.3V

1 2

C545

4V-20%

C1522

C1519

C1506

C1530

C1536

C1515

SUB*_K1098

560uF

SUB*_K1098

C549

10uF 6.3V

560uF

SUB*_D2341

10uF 6.3V

SUB*_D2341

10uF 6.3V

1 2

C546

4V-20%

C1527

C1544

C1502

C1531

C1537

C1511

SUB*_K1098

560uF

4V-20%

SUB*_K1098

C544

SUB*_D2341

10uF 6.3V

SUB*_D2341

10uF 6.3V

560uF

4V-20%

C1523

C1550

C1505

C1532

C1556

C1514

1 2

C550

C541

10uF 6.3V

SUB*_K1098

4V-20%

C1524

C1551

C1542

C1533

C1557

C1512

C551

C552

10uF 6.3V

560uF

SUB*_K1098

560uF

SUB*_D2341

1 2

SUB*_K1098

560uF

4V-20%

SUB*_K1098

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C732

10uF 6.3V

X00_GT_052203

C1552

X00_GT_052203

C1504

SUB*_D2341

C737

C1558

C1513

1 2

C290

SUB*_K1098

C553

SUB*_D2341

10uF 6.3V

SUB*_D2341

10uF 6.3V

SUB*_K1098

560uF

4V-20%

C297

560uF

4V-20%

10uF 6.3V

C733

10uF 6.3V

C1553

C1503

C738

C1559

1 2

10uF 6.3V

C1543

SUB*_K1098

C292

10uF 6.3V

560uF

SUB*_K1098

C296

560uF

4V-20%

SUB*_D2341

C734

C1554

C500

SUB*_D2341

C739

C1560

C511

C291

4V-20%

SUB*_K1098

560uF

SUB*_D2341

10uF 6.3V

SUB*_D2341

10uF 6.3V

C1561

10uF 6.3V

SUB*_K1098

560uF

4V-20%

C295

4V-20%

C735

10uF 6.3V

C1555

10uF 6.3V

C499

C736

10uF 6.3V

C507

SUB*_K1098

C289

10uF 6.3V

560uF

SUB*_K1098

560uF

4V-20%

C1656

C497

C1657

C508

C293

4V-20%

C298

10uF 6.3V

SUB*_K1098

560uF

4V-20%

SUB*_K1098

560uF

4V-20%

C498

C509

10uF 6.3V

C496

10uF 6.3V

1 2

C506

10uF 6.3V

C492

10uF 6.3V

1 2

C502

10uF 6.3V

C495

10uF 6.3V

1 2

C505

10uF 6.3V

C501

10uF 6.3V

1 2

C503

10uF 6.3V

C494

10uF 6.3V

1 2

C504

4.0V-20% 330uF

+CPU_VID2

4.0V-20% 330uF

10uF 6.3V

C493

10uF 6.3V

1 2

C510

1 2

C413

4.0V-20% 330uF

C414

4.0V-20% 330uF

1 2

C415

4.0V-20%

C428

330uF

1 2

C516

4.0V-20% 330uF

C517

4 4

C1496

1 2

C1495

22uF 6.3V

C1494

1 2

22uF 6.3V

C1493

22uF 6.3V

C286

1 2

C1450

22uF 6.3V

1 2

C1449

1uF 6.3V

1 2

C1391

1uF 6.3V

C1374

0.1uF 16V

C1785

0.1uF 16V

X00_GT_062003

COMPUTER CORPORATION

SUB*_C5127

x03b_tj_011903

TITLE

AUSTIN,TEXAS

PROCESSOR 1 & 2

SCHEM,PLN,SV,PE2800/2850/1850

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

subsys done

A B

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

13 OF 60

B D

7-14-2004_10:52

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

D1660

7/14/2004

REV.

A00-00

SHEET

14 OF 60

A B

+CPU_VTT

C76

1 2

C304

1 2

0.1uF 16V

1uF

10V-10%

x00_GT_010704

R1913

1 2

100-5%

R568

x00_tj_051203

R550

1 2

40.2-0.5%

R219

R220

1 2

40.2-0.5%

R221

ITP PORT

R222

1 2

40.2-0.5%

a00_tj_052604

ITP_CONN

ROOM=ITP

x00_tj_051203

R218

R367

40.2-0.5%

1 2

1.5K-5%

1 2

+3.3V_AUX

75-1%

R1756

1 2

B D

ITP_TDI_H1

FOR JTDO:

+CPU_VTT

Install 1-2 for TWO processor system Install 2-3 for UNI processor system

x00_tj_091603

150-5%

R6001

150-5%

(UNI-PROCESSOR IS WITH PROC_1 INSTALLED ONLY!)

7-14-2004_10:52

ROOMS COMPLETE

11,17

H_RST_N

x02_tj_081803

R80

1 2

0-5%

H_BPM0_N

H_BPM1_N

H_BPM2_N

H_BPM3_N

H_BPM4_N

H_BPM5_N

H_RST_ITP_N

CK_167M_ITP_P

CK_167M_ITP_N

(FBO)

(BPM5DR#)

x00_tj_060403

1 3 4 5 6 7 8

9 11 12 13 14 15 16 17 18 19

21 22 23 25

2MM SMT

KEY 26

24 26

R125

ITP_PWR

680-5%

R160

1 2

27.4-1%

NC_ITP_DBA_N ITP_DBR_N

ITP_TDI_H1

ITP_TMS

ITP_TRST_N

ITP_TCK

NC_ITP_FBI

ITP_TDO_H2

NC_ITP_26_KEY

12 12 12 12

12,15

PROC_1 PROC_2

ITP_TDO_H1

ITP_TDI_H2

TDITDI

JTDO

a00_tj_052604

ITP_JPR

1 2 3

+CPU_VTT

R126

x00_tj_060403

1 2

150-5%

ITP_TDI_H2 ITP_TDO_H1 ITP_TDO_H2

12 12 12,15

TDO

ITP_TD0_H2

TDO

ITP ROUTING DRAWING

H1_THERMTRIP_N

+CPU_VTT

R277

R554

2.7K-5%

x02_tj_092203

+3.3V_AUX

Q28

3904

R374

1K-1%

H1_THERMTRIP_3V

ROOM=PROC_1

5,46

H1_PROCHOT_N

+CPU_VTT

R308

1 2

R556

2.7K-5%

+3.3V

+CPU_VTT

R376

1K-1%

H1_PROCHOT_3V

Q30

3904

H1_IERR_N

R266

R419

2.7K-5%

Q68

3904

+3.3V

R415

1K-1%

H1_IERR_3V

11,17

5,46

H_MCERR_N

NP*

R423

1 2

2.7K-5%

NP*

3904

Q71

NP*

+3.3V

R417

1 2

1K-1%

NC_H_MCERR_3V

x03b_sd

H1_BSEL0

R586

1 2

511-1%

R603

2.7K-5%

ROOM = PROC_1

+CPU_VTT +3.3V+CPU_VTT +3.3V

R595

Q61

3904 3904

1K-1%

H1_BSEL0_3V_N

H1_BSEL1

R585

1 2

511-1%

R602

2.7K-5%

R594

Q53

1K-1%

H1_BSEL1_3V_N

ECAD: the components within each circuit need to stay clumped

H2_THERMTRIP_N

+CPU_VTT

R292

1 2

R555

1 2

2.7K-5%

x02_tj_092203

+3.3V_AUX

R375

1 2

Q29

3904

1K-1%

H2_THERMTRIP_3V

ROOM=PROC_2

5,46

H2_PROCHOT_N

+CPU_VTT

R1510

1 2

R557

2.7K-5%

Q31

3904

+3.3V

R377

1 2

1K-1%

H2_PROCHOT_3V

+CPU_VTT

+3.3V

ROOM=PROC_2

1 2

R420

2.7K-5%

R416

Q69

3904

1K-1%

H2_IERR_3V

5,46

R588

1 2

511-1%

H2_IERR_N

R312

ROOM = PROC_2

R597

1K-1%

H2_BSEL0_3V_N

+CPU_VTT +3.3V+CPU_VTT +3.3V

R587

1 2

511-1%

R596

1K-1%

H2_BSEL1_3V_N

H2_BSEL0

R605

2.7K-5%

Q102

R604

H2_BSEL1

2.7K-5%

Q64

39043904

INVERTING LEVEL TRANSLATION

4 4

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

ITP & GTL LEVEL TRANSLATION

subsys done

A B

DWG NO.

DATE

SCHEM,PLN,SV,PE2800/2850/1850

REV.

D1660

SHEET

7/14/2004

15 OF 60

A00-00

B D

+1.8V

ROOM = DDR_TERM

21 21

C360

.1uF

10V-10%

C359

RN28

2 3

71.5

8 7 6 5

DDR2B_A0

DDR2B_A0 DDR2B_A10 DDR2B_A10

16,21 16,21 16,21 16,21

RN29

2 3

71.5

8 7 6 5

DDR2B_A1

DDR2B_A2

16,21 16,21 16,21 16,21

RN30

2 3

71.5

8 7 6 5

DDR2B_A5

DDR2B_A6

16,21 16,21 16,21 16,21

RN31

2 3

71.5

8 7 6 5

DDR2B_A7

DDR2B_A8

16,21 16,21 16,21 16,21

RN32

2 3

71.5

8 7 6 5

DDR2B_A4

DDR2B_A3

16,21 16,21 16,21 16,21

RN33

2 3

71.5

8 7 6 5

DDR2B_A11 DDR2B_A11

DDR2B_A9

16,21 16,21 16,21 16,21

RN36

2 3

71.5

8 7 6 5

DDR2B_BA2 DDR2B_BA2 DDR2B_A12 DDR2B_A12

16,21 16,21 16,21 16,21

RN34

2 3

71.5

8 7 6 5

DDR2B_BA1 DDR2B_BA1 DDR2B_BA0 DDR2B_BA0

16,21 16,21 16,21 16,21

RN35

2 3

71.5

8 7 6 5

DDR2B_CS0_N DDR2B_CS0_N

DDR2B_CAS_N DDR2B_CAS_N

16,21 16,21

RN39

2 3

71.5

8 7 6 5

DDR2B_RAS_N DDR2B_RAS_N

DDR2B_A13 DDR2B_A13

16,21 16,21 16,21 16,21

DDR2B_CS3_N DDR2B_CS3_N DDR2B_CS2_N DDR2B_CS2_N

x00_tj_061903

DDR2B_CS7_N DDR2B_CS7_N

DDR2B_WE_N DDR2B_WE_N

16,21 16,21 16,21 16,21

16,21 16,21

x00_tj_051203

RN37

2 3

71.5

8 7 6 5

RN38

2 3

71.5

8 7 6 5

RN43

2 3

71.5

8 7 6 5

DDR2B_CS1_N DDR2B_CS1_N DDR2B_CS6_N DDR2B_CS6_N

16,21 16,21 16,21 16,21

x00_tj_051203

RN42

2 3

71.5

8 7 6 5

DDR2B_CS5_N DDR2B_CS5_N DDR2B_CS4_N DDR2B_CS4_N

16,21 16,21 16,21 16,21

RN41

2 3

71.5

8 7 6 5

DDR2_CKE4 DDR2_CKE4 DDR2_CKE2 DDR2_CKE2

16,20 16,20 16,20 16,20

DDR2_CKE6 DDR2_CKE6 DDR2_CKE0 DDR2_CKE0

16,20 16,20 16,20 16,20

RN40

2 3

71.5

8 7 6 5

R380

1 2

100-1%

R382

1 2

100-1%

R385

1 2

100-1%

R387

1 2

100-1%

R389

R381

100-1%

R383

100-1%

R386

100-1%

R388

100-1%

1 2

NP*

R390

100-1%

R392

100-1%

R394

100-1%

R396

100-1%

NP*

100-1%

R391

1 2

100-1%

R393

1 2

100-1%

R395

1 2

100-1%

4 4

CK_200M_DIMMB3_P

CK_200M_DIMMB3_N

CK_200M_DIMMB1_P

CK_200M_DIMMB1_N

CK_200M_DIMMB2_P

CK_200M_DIMMB2_N

CK_200M_DIMMB0_P

CK_200M_DIMMB0_N

16,21

1 2 3 4

RN59

71.5 1%

RN58

71.5 1%

RN57

71.5 1%

RN56

71.5 1%

RN55

71.5 1%

RN54

71.5 1%

RN53

71.5 1%

RN52

71.5 1%

RN51

71.5 1%

RN44

71.5 1%

RN45

71.5 1%

RN46

71.5 1%

RN47

71.5 1%

RN50

71.5 1%

RN49

71.5 1%

RN48

71.5 1%

R397

100-1%

R399

100-1%

R401

100-1%

R403

100-1%

R405

100-1%

R409

100-1%

R411

100-1%

R413

100-1%

8 7 6 5

1 2

NP*

1 2

NP*

1 2

R398

100-1%

R400

100-1%

R402

100-1%

R404

100-1%

R408

100-1%

R410

100-1%

R412

100-1%

R414

100-1%

NP*

DDR2A_A10 DDR2A_A10

DDR2A_A0 DDR2A_A0

DDR2A_A2 DDR2A_A2 DDR2A_A1 DDR2A_A1

DDR2A_A6 DDR2A_A6 DDR2A_A5 DDR2A_A5

DDR2A_A8 DDR2A_A8 DDR2A_A7 DDR2A_A7

DDR2A_A3 DDR2A_A3 DDR2A_A4 DDR2A_A4

DDR2A_A9

DDR2A_A9 DDR2A_A11 DDR2A_A11

DDR2A_A12 DDR2A_A12 DDR2A_BA2 DDR2A_BA2

DDR2A_BA0 DDR2A_BA0 DDR2A_BA1 DDR2A_BA1

DDR2A_CAS_N DDR2A_CAS_N DDR2A_CS0_N DDR2A_CS0_N

DDR2A_WE_N

DDR2A_WE_N DDR2A_RAS_N DDR2A_RAS_N

DDR2A_CS3_N DDR2A_CS3_N DDR2A_CS2_N DDR2A_CS2_N

DDR2A_CS7_N DDR2A_CS7_N

DDR2A_A13 DDR2A_A13

DDR2A_CS6_N DDR2A_CS6_N

DDR2A_CS1_N DDR2A_CS1_N

DDR2A_CS5_N DDR2A_CS5_N DDR2A_CS4_N DDR2A_CS4_N

DDR2_CKE1 DDR2_CKE1 DDR2_CKE7 DDR2_CKE7

DDR2_CKE5 DDR2_CKE5 DDR2_CKE3 DDR2_CKE3

CK_200M_DIMMA3_P

CK_200M_DIMMA3_N

CK_200M_DIMMA1_P

CK_200M_DIMMA1_N

CK_200M_DIMMA2_P

CK_200M_DIMMA2_N

CK_200M_DIMMA0_P

CK_200M_DIMMA0_N

16,20 16,20 16,20 16,20

16,20 16,20

16,20 16,20 16,20 16,20

16,21 16,21 16,21 16,21

16,20

.1uF

10V-10%

C364

.1uF

10V-10%

C357

.1uF

10V-10%

C355

.1uF

10V-10%

C353

.1uF

10V-10%

C418

.1uF

10V-10%

C313

.1uF

10V-10%

C351

.1uF

10V-10%

C341

.1uF

10V-10%

C339

.1uF

10V-10%

C322

.1uF

10V-10%

C325

.1uF

10V-10%

C316

.1uF

10V-10%

C369

1 2

.1uF

10V-10%

C371

1 2

.1uF

10V-10%

C373

1 2

.1uF

10V-10%

C375

1 2

.1uF

10V-10%

C374

1 2

.1uF

10V-10%

C366

.1uF

10V-10%

CAD Notes:

1) Place one cap near every 2 signals

2) Place 10uF caps at each end of row

C358

.1uF

10V-10%

C361

.1uF

10V-10%

C362

.1uF

10V-10%

C356

.1uF

10V-10%

C354

.1uF

10V-10%

C352

.1uF

10V-10%

C419

.1uF

10V-10%

C312

.1uF

10V-10%

C342

.1uF

10V-10%

C340

.1uF

10V-10%

C321

.1uF

10V-10%

C363

.1uF

10V-10%

C323

.1uF

10V-10%

C315

.1uF

10V-10%

C370

1 2

.1uF

10V-10%

C372

1 2

.1uF

10V-10%

C314

1 2

.1uF

10V-10%

C368

1 2

.1uF

10V-10%

C365

1 2

.1uF

10V-10%

C367

1 2

.1uF

10V-10%

x00_tj_060503

C73

1 2

10uF 6.3V

C79

10uF 6.3V

16,21 16,21 16,21 16,21 16,21 16,21

21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21

16,21 16,21 16,21

16,20 16,21 16,20 16,21

16,21 16,21 16,21 16,21 16,21 16,21 16,21 16,21

16 16

2U/5U Heatsink assembly

DDR2B_DQS0_P DDR2B_DQS0_N DDR2B_DQS1_P DDR2B_DQS1_N DDR2B_DQS2_P DDR2B_DQS2_N DDR2B_DQS3_P DDR2B_DQS3_N DDR2B_DQS4_P DDR2B_DQS4_N DDR2B_DQS5_P DDR2B_DQS5_N DDR2B_DQS6_P DDR2B_DQS6_N DDR2B_DQS7_P DDR2B_DQS7_N DDR2B_DQS8_P DDR2B_DQS8_N DDR2B_DQS9_P DDR2B_DQS9_N DDR2B_DQS10_P DDR2B_DQS10_N DDR2B_DQS11_P DDR2B_DQS11_N DDR2B_DQS12_P DDR2B_DQS12_N DDR2B_DQS13_P DDR2B_DQS13_N DDR2B_DQS14_P DDR2B_DQS14_N DDR2B_DQS15_P DDR2B_DQS15_N DDR2B_DQS16_P DDR2B_DQS16_N DDR2B_DQS17_P DDR2B_DQS17_N

DDR2B_A0 DDR2B_A1 DDR2B_A2 DDR2B_A3 DDR2B_A4 DDR2B_A5 DDR2B_A6 DDR2B_A7 DDR2B_A8 DDR2B_A9 DDR2B_A10 DDR2B_A11 DDR2B_A12 DDR2B_A13

DDR2B_BA0 DDR2B_BA1 DDR2B_BA2

DDR2B_WE_N DDR2B_CAS_N

DDR2B_RAS_N

DDR2_CKE4 DDR2_CKE5

DDR2_CKE6 DDR2_CKE7

DDR2B_CS0_N DDR2B_CS1_N DDR2B_CS2_N DDR2B_CS3_N DDR2B_CS4_N DDR2B_CS5_N DDR2B_CS6_N DDR2B_CS7_N

CK_200M_DIMMB1_P CK_200M_DIMMB1_N CK_200M_DIMMB2_P CK_200M_DIMMB2_N CK_200M_DIMMB3_P CK_200M_DIMMB3_N CK_200M_DIMMB0_P CK_200M_DIMMB0_N

DDR2B_MCH_VREF

SUB=SUB*_W6123

1U Heatsink assembly

AM28 AN29 AM22 AN23 AK17 AL17 AK11 AL11

AG2 AH2 AA3 AB4

P1 R2 H3

H1 AK5 AK6

AK29 AL29 AK23 AL23 AN18 AN17 AN12 AN11

AJ1 AH1 AB2 AB1

J2 AM6 AN6

AF7

AE14 AN14 AK14 AD15 AH16 AG17 AD18 AL20 AJ21

AC4

AH22 AH23

AA8 AE7

AM25

AH26 AJ27 AJ28 AH28

AH7 AJ6 AH6 AG6 AG8 AE8 AK9 AL8

AN4

B_DQS0_P B_DQS0_N B_DQS1_P B_DQS1_N B_DQS2_P B_DQS2_N B_DQS3_P B_DQS3_N B_DQS4_P B_DQS4_N B_DQS5_P B_DQS5_N B_DQS6_P B_DQS6_N B_DQS7_P B_DQS7_N B_DQS8_P B_DQS8_N B_DQS9_P B_DQS9_N B_DQS10_P B_DQS10_N B_DQS11_P B_DQS11_N B_DQS12_P B_DQS12_N B_DQS13_P B_DQS13_N B_DQS14_P B_DQS14_N B_DQS15_P B_DQS15_N B_DQS16_P B_DQS16_N B_DQS17_P B_DQS17_N

B_MA0 B_MA1 B_MA2 B_MA3 B_MA4 B_MA5 B_MA6 B_MA7 B_MA8 B_MA9 B_MA10 B_MA11 B_MA12 B_MA13

B_BA0 B_BA1 B_BA2

B_WE B_CAS B_RAS

CKE4 CKE5 CKE6 CKE7

B_CS0 B_CS1 B_CS2 B_CS3 B_CS4 B_CS5 B_CS6 B_CS7

B_CMDCLK0_P B_CMDCLK0_N B_CMDCLK1_P B_CMDCLK1_N B_CMDCLK2_P B_CMDCLK2_N B_CMDCLK3_P B_CMDCLK3_N

B_VREF

INTEL LINDENHURST MCH V0P21

x02_tj_041003 x03_tj_121503 x03b_tj_012004

MCH

B_DQ0 B_DQ1 B_DQ2 B_DQ3 B_DQ4 B_DQ5 B_DQ6 B_DQ7

B_DQ8

B_DQ9 B_DQ10 B_DQ11 B_DQ12 B_DQ13 B_DQ14 B_DQ15

B_DQ16 B_DQ17 B_DQ18 B_DQ19 B_DQ20 B_DQ21 B_DQ22 B_DQ23

B_DQ24 B_DQ25 B_DQ26 B_DQ27 B_DQ28 B_DQ29 B_DQ30 B_DQ31

B_DQ32 B_DQ33 B_DQ34 B_DQ35 B_DQ36 B_DQ37 B_DQ38 B_DQ39

B_DQ40 B_DQ41 B_DQ42 B_DQ43 B_DQ44 B_DQ45 B_DQ46 B_DQ47

B_DQ48 B_DQ49 B_DQ50 B_DQ51 B_DQ52 B_DQ53 B_DQ54 B_DQ55

B_DQ56 B_DQ57 B_DQ58 B_DQ59 B_DQ60 B_DQ61 B_DQ62 B_DQ63

B_CB0

B_CB1

B_CB2

B_CB3

B_CB4

B_CB5

B_CB6

B_CB7

HETERO 3 OF 7

ADD=ADD02_W1549_MCHHTSNK1

ADD1=ADD13_X1306_MCHHTSNK2

AM30 AN30 AN27 AM27 AK30 AM31 AL28 AK27

AM24 AN24 AN21 AM21 AL25 AK24 AL22 AK21

AK18 AM18 AN15 AM15 AL19 AM19 AM16 AL16

AK12 AM12 AN9 AM9 AL13 AM13 AM10 AL10

AJ3 AJ4 AF1 AF4 AK3 AK2 AG3 AF3

AC3 AC1 Y3 Y4 AD2 AD3 AA2 Y1

T4 T1 N1 N2 U3 U1 P3 P4

K2 K1 F2 E1 L1 K4 G1 G2

AM7 AL7 AM4 AL4 AN8 AK8 AN5 AL5

x00_tj_041003

DDR2B_SD0_0 DDR2B_SD0_1 DDR2B_SD0_2 DDR2B_SD0_3 DDR2B_SD0_4 DDR2B_SD0_5 DDR2B_SD0_6 DDR2B_SD0_7

DDR2B_SD1_0 DDR2B_SD1_1 DDR2B_SD1_2 DDR2B_SD1_3 DDR2B_SD1_4 DDR2B_SD1_5 DDR2B_SD1_6 DDR2B_SD1_7

DDR2B_SD2_0 DDR2B_SD2_1 DDR2B_SD2_2 DDR2B_SD2_3 DDR2B_SD2_4 DDR2B_SD2_5 DDR2B_SD2_6 DDR2B_SD2_7

DDR2B_SD3_0 DDR2B_SD3_1 DDR2B_SD3_2 DDR2B_SD3_3 DDR2B_SD3_4 DDR2B_SD3_5 DDR2B_SD3_6 DDR2B_SD3_7

DDR2B_SD4_0 DDR2B_SD4_1 DDR2B_SD4_2 DDR2B_SD4_3 DDR2B_SD4_4 DDR2B_SD4_5 DDR2B_SD4_6 DDR2B_SD4_7

DDR2B_SD5_0 DDR2B_SD5_1 DDR2B_SD5_2 DDR2B_SD5_3 DDR2B_SD5_4 DDR2B_SD5_5 DDR2B_SD5_6 DDR2B_SD5_7

DDR2B_SD6_0 DDR2B_SD6_1 DDR2B_SD6_2 DDR2B_SD6_3 DDR2B_SD6_4 DDR2B_SD6_5 DDR2B_SD6_6 DDR2B_SD6_7

DDR2B_SD7_0 DDR2B_SD7_1 DDR2B_SD7_2 DDR2B_SD7_3 DDR2B_SD7_4 DDR2B_SD7_5 DDR2B_SD7_6 DDR2B_SD7_7

DDR2B_CB0 DDR2B_CB1 DDR2B_CB2 DDR2B_CB3 DDR2B_CB4 DDR2B_CB5 DDR2B_CB6 DDR2B_CB7

ROOM = MCH

21 21 21 21 21 21 21 21

16,20 16,20 16,20 16,20 16,20 16,20

16 16

20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20

16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20

16,20 16,20 16,20

16,20 16,21 16,20 16,21

16,20 16,20 16,20 16,20 16,20 16,20 16,20 16,20

DDR2A_DQS0_P DDR2A_DQS0_N DDR2A_DQS1_P DDR2A_DQS1_N DDR2A_DQS2_P DDR2A_DQS2_N DDR2A_DQS3_P DDR2A_DQS3_N DDR2A_DQS4_P DDR2A_DQS4_N DDR2A_DQS5_P DDR2A_DQS5_N DDR2A_DQS6_P DDR2A_DQS6_N DDR2A_DQS7_P DDR2A_DQS7_N DDR2A_DQS8_P DDR2A_DQS8_N DDR2A_DQS9_P DDR2A_DQS9_N DDR2A_DQS10_P DDR2A_DQS10_N DDR2A_DQS11_P DDR2A_DQS11_N DDR2A_DQS12_P DDR2A_DQS12_N DDR2A_DQS13_P DDR2A_DQS13_N DDR2A_DQS14_P DDR2A_DQS14_N DDR2A_DQS15_P DDR2A_DQS15_N DDR2A_DQS16_P DDR2A_DQS16_N DDR2A_DQS17_P DDR2A_DQS17_N

DDR2A_A0 DDR2A_A1 DDR2A_A2 DDR2A_A3 DDR2A_A4 DDR2A_A5 DDR2A_A6 DDR2A_A7 DDR2A_A8 DDR2A_A9 DDR2A_A10 DDR2A_A11 DDR2A_A12 DDR2A_A13

DDR2A_BA0 DDR2A_BA1 DDR2A_BA2

DDR2A_WE_N DDR2A_CAS_N DDR2A_RAS_N

DDR2_CKE0 DDR2_CKE1 DDR2_CKE2 DDR2_CKE3

DDR2A_CS0_N DDR2A_CS1_N DDR2A_CS2_N DDR2A_CS3_N DDR2A_CS4_N DDR2A_CS5_N DDR2A_CS6_N DDR2A_CS7_N

CK_200M_DIMMA1_P CK_200M_DIMMA1_N CK_200M_DIMMA2_P CK_200M_DIMMA2_N CK_200M_DIMMA3_P CK_200M_DIMMA3_N CK_200M_DIMMA0_P CK_200M_DIMMA0_N

DDR2A_MCH_VREF

ROOM=MCH

AJ30 AJ31 AJ24 AJ25 AH19 AH20 AG14 AG15

AC6 AD6

W7 V8 N7 P7 G4

H4 AF9 AG9

AL32 AL31 AF25 AF24 AE20 AE19 AH14 AJ13

AD8 AC7

Y6 P10 N10

H6 AH8 AJ7

AH5

AD14 AL14 AK15 AJ16 AH17 AF18 AN20 AK20 AJ22

AE4

AF22 AG23

AB5 AF6

AE25

Y10

W8 AA6

AE26 AN26 AL26 AK26

T8 T10

AF13 AF12 AH11 AJ12 AH13 AG12 AC10

AD9 AM3

A_DQS0_P A_DQS0_N A_DQS1_P A_DQS1_N A_DQS2_P A_DQS2_N A_DQS3_P A_DQS3_N A_DQS4_P A_DQS4_N A_DQS5_P A_DQS5_N A_DQS6_P A_DQS6_N A_DQS7_P A_DQS7_N A_DQS8_P A_DQS8_N A_DQS9_P A_DQS9_N A_DQS10_P A_DQS10_N A_DQS11_P A_DQS11_N A_DQS12_P A_DQS12_N A_DQS13_P A_DQS13_N A_DQS14_P A_DQS14_N A_DQS15_P A_DQS15_N A_DQS16_P A_DQS16_N A_DQS17_P A_DQS17_N

A_MA0 A_MA1 A_MA2 A_MA3 A_MA4 A_MA5 A_MA6 A_MA7 A_MA8 A_MA9 A_MA10 A_MA11 A_MA12 A_MA13

A_BA0 A_BA1 A_BA2

A_WE A_CAS A_RAS

CKE0 CKE1 CKE2 CKE3

A_CS0 A_CS1 A_CS2 A_CS3 A_CS4 A_CS5 A_CS6 A_CS7

A_CMDCLK0_P A_CMDCLK0_N A_CMDCLK1_P A_CMDCLK1_N A_CMDCLK2_P A_CMDCLK2_N A_CMDCLK3_P A_CMDCLK3_N

A_VREF

INTEL LINDENHURST MCH V0P21

MCH

HETERO 4 OF 7

A_DQ0 A_DQ1 A_DQ2 A_DQ3 A_DQ4 A_DQ5 A_DQ6 A_DQ7

A_DQ8

A_DQ9 A_DQ10 A_DQ11 A_DQ12 A_DQ13 A_DQ14 A_DQ15

A_DQ16 A_DQ17 A_DQ18 A_DQ19 A_DQ20 A_DQ21 A_DQ22 A_DQ23

A_DQ24 A_DQ25 A_DQ26 A_DQ27 A_DQ28 A_DQ29 A_DQ30 A_DQ31

A_DQ32 A_DQ33 A_DQ34 A_DQ35 A_DQ36 A_DQ37 A_DQ38 A_DQ39

A_DQ40 A_DQ41 A_DQ42 A_DQ43 A_DQ44 A_DQ45 A_DQ46 A_DQ47

A_DQ48 A_DQ49 A_DQ50 A_DQ51 A_DQ52 A_DQ53 A_DQ54 A_DQ55

A_DQ56 A_DQ57 A_DQ58 A_DQ59 A_DQ60 A_DQ61 A_DQ62 A_DQ63

A_CB0

A_CB1

A_CB2

A_CB3

A_CB4

A_CB5

A_CB6

A_CB7

AK32 AH31 AH29 AF28 AJ33 AK33 AG30 AG29

AG27 AG26 AD24 AD23 AE28 AF27 AH25 AG24

AF21 AG21 AF19 AG18 AE22 AD21 AJ18 AG20

AF16 AF15 AE13 AD12 AE17 AJ15 AE16 AD17

AH4 AG5 AB8 AB7 AB10 AA9 AE5 AD5

U9 AA5 V6 U7 W10 U10 W5 V5

R6 R5 L7 L6 P9 T5 N8 M9

K5 J5 K8 K10 L9 L10 K7 H7

AJ9 AG11 AE11 AD11 AJ10 AH10 AF10 AE10

DDR2A_SD0_0 DDR2A_SD0_1 DDR2A_SD0_2 DDR2A_SD0_3 DDR2A_SD0_4 DDR2A_SD0_5 DDR2A_SD0_6 DDR2A_SD0_7

DDR2A_SD1_0 DDR2A_SD1_1 DDR2A_SD1_2 DDR2A_SD1_3 DDR2A_SD1_4 DDR2A_SD1_5 DDR2A_SD1_6 DDR2A_SD1_7

DDR2A_SD2_0 DDR2A_SD2_1 DDR2A_SD2_2 DDR2A_SD2_3 DDR2A_SD2_4 DDR2A_SD2_5 DDR2A_SD2_6 DDR2A_SD2_7

DDR2A_SD3_0 DDR2A_SD3_1 DDR2A_SD3_2 DDR2A_SD3_3 DDR2A_SD3_4 DDR2A_SD3_5 DDR2A_SD3_6 DDR2A_SD3_7

DDR2A_SD4_0 DDR2A_SD4_1 DDR2A_SD4_2 DDR2A_SD4_3 DDR2A_SD4_4 DDR2A_SD4_5 DDR2A_SD4_6 DDR2A_SD4_7

DDR2A_SD5_0 DDR2A_SD5_1 DDR2A_SD5_2 DDR2A_SD5_3 DDR2A_SD5_4 DDR2A_SD5_5 DDR2A_SD5_6 DDR2A_SD5_7

DDR2A_SD6_0 DDR2A_SD6_1 DDR2A_SD6_2 DDR2A_SD6_3 DDR2A_SD6_4 DDR2A_SD6_5 DDR2A_SD6_6 DDR2A_SD6_7

DDR2A_SD7_0 DDR2A_SD7_1 DDR2A_SD7_2 DDR2A_SD7_3 DDR2A_SD7_4 DDR2A_SD7_5 DDR2A_SD7_6 DDR2A_SD7_7

DDR2A_CB0 DDR2A_CB1 DDR2A_CB2 DDR2A_CB3 DDR2A_CB4 DDR2A_CB5 DDR2A_CB6 DDR2A_CB7

20 20 20 20 20 20 20 20

subsys done

These can be left floating

But BIOS must turn them off

A B

MCH & DDR TERM

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

D1660

DATE

SHEET

REV.

A00-00

16 OF 607/14/2004

B D

LINDENHURST MCH MCH REFDES = MCH

MCH_HDACVREF

CK_167M_MCH_N

CK_167M_MCH_P

H_ADS_N

H_A3_N

H_A4_N

H_A5_N

H_A6_N

H_A7_N

H_A8_N

H_A9_N

H_A10_N

H_A11_N

H_A12_N

H_A13_N

H_A14_N

H_A15_N

H_A16_N

H_A17_N

H_A18_N

H_A19_N

H_A20_N

H_A21_N

H_A22_N

H_A23_N

H_A24_N

H_A25_N

H_A26_N

H_A27_N

H_A28_N

H_A29_N

H_A30_N

H_A31_N

H_A32_N

H_A33_N

H_A34_N

H_A35_N

H_ADSTB0_N

H_ADSTB1_N

H_AP0_N

H_AP1_N

H_BPRI_N

H_BINIT_N

H_BNR_N

H_DRDY_N

H_DBSY_N

H_DEFER_N

H_HIT_N

H_HITM_N

H_LOCK_N

H_RS0_N

H_RS1_N

H_RS2_N

H_RSP_N

H_REQ0_N

H_REQ1_N

H_REQ2_N

H_REQ3_N

H_REQ4_N

H_TRDY_N

H_BREQ0_N

H_BREQ1_N

11,15

17 17 17

H_MCERR_N

MCH_HCRES0 MCH_HODTCRES MCH_HSLWCRES

ROOM=MCH

J11 K11 B27 K22 J20 G23 G22 H21 K19 H19 G19 E22 E21 F18 E19 F21 F20 D26 C26 A26 D22 B22 A25 B25 D25 C24 A22 B21 D23 A23 B24 A20 D19 C20 C21 D20

G20 C23

G25 H25

A28

G26 B31

B30 H27 B28 E30 D28 C30

F29 D31 G28 J26

K20 J21 J23 H22 K23

A30

F24 D29

H24

C27 E27 F26

E13 D13 F23

BCLKN BCLKP ADS A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35

ADSTB0 ADSTB1

AP0 AP1

BPRI

BINIT BNR

DRDY DBSY DEFER HIT HITM LOCK

RS0 RS1 RS2 RSP

HREQ0 HREQ1 HREQ2 HREQ3 HREQ4

TRDY

BREQ0 BREQ1

MCERR

HCRES0 H0DTCRES HSLWCRES

HDVREF1 HDVREF0 HACVREF

INTEL LINDENHURST MCH V0P21

HETERO 1 OF 7

MCH

D0 D1 D2 D3 D4 D5 D6 D7 D8

DP0 DP1 DP2 DP3

DBINV0 DBINV1 DBINV2 DBINV3

DSTBN0 DSTBP0 DSTBN1 DSTBP1 DSTBN2 DSTBP2 DSTBN3 DSTBP3

C18 B19 C14 A17 A19 B16 C17 B18 D17 A16 B13 A14 A13 D14 C12 B12 E18 J18 H18 F17 G17 K17 E16 J17 J14 F14 F15 G16 K16 H16 G14 K14 E12 C11 H13 F11 G13 D11 E9 F12 G10 D8 H10 F8 J12 G11 K13 H12 B10 A10 A11 C9 B9 C8 B6 B7 E7 B4 A4 B3 D5 C6 D7 C5

C29 E28 E25 F27

D16 E15 F9 A5

B15 C15 H15 J15 D10 E10 A8 A7

H_DP0_N H_DP1_N H_DP2_N H_DP3_N

H_DBI0_N H_DBI1_N H_DBI2_N H_DBI3_N

H_DSTBN0_N H_DSTBP0_N H_DSTBN1_N H_DSTBP1_N H_DSTBN2_N H_DSTBP2_N H_DSTBN3_N H_DSTBP3_N

H_D0_N H_D1_N H_D2_N H_D3_N H_D4_N H_D5_N H_D6_N H_D7_N H_D8_N H_D9_N

11 11 11 11

11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11

11 11 11 11

11 11 11 11 11 11 11 11

ROOM = MCH

+CPU_VTT

ITP_TMS_MCH

ITP_TDI_MCH

ITP_TDO_MCH

ITP_TRST_MCH_N

ITP_TCK1_MCH

31 31

29 29

31 31

+1.5V

R1313

1 2

43.2-1%

PROPAGATION_DELAY=L:S::750

+CPU_VTT

1K-5%

RN7672RN76

1K-5%

1 8

680-5%

RN76

R180

x00_tj_052003

1K-5%

RN76

3 6

EXP_A_UP_0P EXP_A_UP_0N

EXP_A_UP_1P EXP_A_UP_1N

EXP_A_UP_2P EXP_A_UP_2N

EXP_A_UP_3P EXP_A_UP_3N

EXP_A_UP_4P EXP_A_UP_4N

EXP_A_UP_5P EXP_A_UP_5N

EXP_A_UP_6P EXP_A_UP_6N

EXP_A_UP_7P EXP_A_UP_7N

EXP_B_UP_0P EXP_B_UP_0N

EXP_B_UP_1P EXP_B_UP_1N

EXP_B_UP_2P EXP_B_UP_2N

EXP_B_UP_3P EXP_B_UP_3N

EXP_B_UP_4P EXP_B_UP_4N

EXP_B_UP_5P EXP_B_UP_5N

EXP_B_UP_6P EXP_B_UP_6N

EXP_B_UP_7P EXP_B_UP_7N

EXP_C_UP_0P EXP_C_UP_0N

EXP_C_UP_1P EXP_C_UP_1N

EXP_C_UP_2P EXP_C_UP_2N

EXP_C_UP_3P EXP_C_UP_3N

EXP_C_UP_4P EXP_C_UP_4N

EXP_C_UP_5P EXP_C_UP_5N

EXP_C_UP_6P EXP_C_UP_6N

EXP_C_UP_7P EXP_C_UP_7N

4 4

11,15

33 33

5,33

17 17

1K-5%

CK_100M_MCH_P CK_100M_MCH_N

NC_MCH_TESTIN_N PCI_RST_MCH_N

H_RST_N

MCH_PME_N

MCH_GPE_N

HLA_STBS HLA_STBF

HLA_MCH_SWING CK_66M_MCH

HIRCOMP_MCH

HLA_MCH_VREF

SYSTEM_PWRGOOD_CHIPSET

ICH_SEG0_MCH_SCL ICH_SEG0_MCH_SDA

ITP_TMS_MCH

ITP_TDI_MCH

ITP_TDO_MCH

ITP_TCK1_MCH

ITP_TRST_MCH_N

DDRCRES1

DDRCRES2

NC_MCH_AF30 NC_MCH_AE23 NC_MCH_AD20 NC_MCH_AJ19 NC_MCH_R10 NC_MCH_R9 NC_MCH_R8 NC_MCH_M8

+3.3V

AG33 AF33

AE32 AD32

AC30 AD30

AC31 AB31 AD29

AE29

AC25 AC24

AB26 AB25

AA30 AA29

AF30 AE23 AD20 AJ19

ROOM=MCH

MCH

R33 P33

N28 N29

L31 L30

J33 J32

R26 R27

N25 N26

M27 M26

K29 K28

Y25 Y24

Y28 Y27

Y30 Y31

V33 V32

T32 T31

R30 R29

V27 V26

V24 U24

T23 U33 R24

EXP_A_RXP_0 EXP_A_RXN_0

EXP_A_RXP_1 EXP_A_RXN_1

EXP_A_RXP_2 EXP_A_RXN_2

EXP_A_RXP_3 EXP_A_RXN_3

EXP_A_RXP_4 EXP_A_RXN_4

EXP_A_RXP_5 EXP_A_RXN_5

EXP_A_RXP_6 EXP_A_RXN_6

EXP_A_RXP_7 EXP_A_RXN_7

EXP_B_RXP_0 EXP_B_RXN_0

EXP_B_RXP_1 EXP_B_RXN_1

EXP_B_RXP_2 EXP_B_RXN_2

EXP_B_RXP_3 EXP_B_RXN_3

EXP_B_RXP_4 EXP_B_RXN_4

EXP_B_RXP_5 EXP_B_RXN_5

EXP_B_RXP_6 EXP_B_RXN_6

EXP_B_RXP_7 EXP_B_RXN_7

EXP_C_RXP_0 EXP_C_RXN_0

EXP_C_RXP_1 EXP_C_RXN_1

EXP_C_RXP_2 EXP_C_RXN_2

EXP_C_RXP_3 EXP_C_RXN_3

EXP_C_RXP_4 EXP_C_RXN_4

EXP_C_RXP_5 EXP_C_RXN_5

EXP_C_RXP_6 EXP_C_RXN_6

EXP_C_RXP_7 EXP_C_RXN_7

EXP_A_TXP_0 EXP_A_TXN_0

EXP_A_TXP_1 EXP_A_TXN_1

EXP_A_TXP_2 EXP_A_TXN_2

EXP_A_TXP_3 EXP_A_TXN_3

EXP_A_TXP_4 EXP_A_TXN_4

EXP_A_TXP_5 EXP_A_TXN_5

EXP_A_TXP_6 EXP_A_TXN_6

EXP_A_TXP_7 EXP_A_TXN_7

EXP_B_TXP_0 EXP_B_TXN_0

EXP_B_TXP_1 EXP_B_TXN_1

EXP_B_TXP_2 EXP_B_TXN_2

EXP_B_TXP_3 EXP_B_TXN_3

EXP_B_TXP_4 EXP_B_TXN_4

EXP_B_TXP_5 EXP_B_TXN_5

EXP_B_TXP_6 EXP_B_TXN_6

EXP_B_TXP_7 EXP_B_TXN_7

EXP_C_TXP_0 EXP_C_TXN_0

EXP_C_TXP_1 EXP_C_TXN_1

EXP_C_TXP_2 EXP_C_TXN_2

EXP_C_TXP_3 EXP_C_TXN_3

EXP_C_TXP_4 EXP_C_TXN_4

EXP_C_TXP_5 EXP_C_TXN_5

EXP_C_TXP_6 EXP_C_TXN_6

EXP_C_TXP_7 EXP_C_TXN_7

EXP_CLK_P EXP_COMP0 EXP_CLK_N

EXP_COMP1

EXPHPINTR_N

VCCBGEXP

L12

J24

M24

L25

TESTIN RESET_IN

CPURST

PME

GPE

VSSBGEXP

V3REF

E31 D32

H31 L24 K25 F32

HI_STBS HI_STBF

HISWING HICLK HIRCOMP HIVREF

PWRGOOD

DDRSLWCRES

DDRCRES0

DDRIMPCRES

PLLSEL[1] PLLSEL[0]

HI11 HI10

HI9

C3 D4

F3 G5 G6 D2 J9

SMBCLK SMBDATA

TMS TDI TDO TCK TRST

3.3V

HI8 HI7 HI6 HI5 HI4 HI3 HI2 HI1

AE2 AE1

R10

DDR_RES1 DDR_RES2 RESERVED_AF30 RESERVED_AE23 RESERVED_AD20 RESERVED_AJ19 RESERVED_R10

RESERVED_R9

RESERVED_R8

RESERVED_M8

HI0

DEBUG7 DEBUG6 DEBUG5 DEBUG4 DEBUG3 DEBUG2 DEBUG1 DEBUG0

TDIOCATHODE

TDIOANODE

RESERVED_AA24

RESERVED_R32 RESERVED_L33

INTEL LINDENHURST MCH V0P21

HETERO 2 OR 7

P30 P31

N31 N32

M33 M32

K32 K31

P24 P25

P27 P28

M30 M29

L28 L27

AG32 AH32

AF31 AE31

AC33 AD33

AB32 AA32

AD27 AD26

AC27 AC28

AB29 AB28

AA27 AA26

W26 W25

W28 W29

Y33 AA33

W32 W31

U31 U30

V30 V29

T29 T28

T26 T25

U25 E6 U27 U28

H33 AK1 AC9 AL2 A29 C31

G32 J29 E33 F30 J27 K26 H28 G29 G31 C32 H30 J30

D1 L11 D3 B2 H9 G8 G7 J8

F33 D33 AA24 R32 L33

MCH_VCCBGEXP

(MCH_VSSBGEXP)

DDRSLWCRES

DDRIMPCRES MCH_PLLSTRAP_1 MCH_PLLSTRAP_0

HLA_11 HLA_10

HLA_9 HLA_8 HLA_7 HLA_6 HLA_5 HLA_4 HLA_3 HLA_2 HLA_1 HLA_0

NC_ITP_MCH_DEBUG7 NC_ITP_MCH_DEBUG6 NC_ITP_MCH_DEBUG5 NC_ITP_MCH_DEBUG4 NC_ITP_MCH_DEBUG3 NC_ITP_MCH_DEBUG2 NC_ITP_MCH_DEBUG1 NC_ITP_MCH_DEBUG0

NC_MCH_TD_CATHODE

NC_MCH_TD_ANODE NC_MCH_RES_AA24

NC_MCH_RES_R32 NC_MCH_RES_L33

EXP_A_DN_0P_C EXP_A_DN_0N_C

EXP_A_DN_1P_C EXP_A_DN_1N_C

EXP_A_DN_2P_C EXP_A_DN_2N_C

EXP_A_DN_3P_C EXP_A_DN_3N_C

EXP_A_DN_4P_C EXP_A_DN_4N_C

EXP_A_DN_5P_C EXP_A_DN_5N_C

EXP_A_DN_6P_C EXP_A_DN_6N_C

EXP_A_DN_7P_C EXP_A_DN_7N_C

EXP_B_DN_0P_C EXP_B_DN_0N_C

EXP_B_DN_1P_C EXP_B_DN_1N_C

EXP_B_DN_2P_C EXP_B_DN_2N_C

EXP_B_DN_3P_C EXP_B_DN_3N_C

EXP_B_DN_4P_C EXP_B_DN_4N_C

EXP_B_DN_5P_C EXP_B_DN_5N_C

EXP_B_DN_6P_C EXP_B_DN_6N_C

EXP_B_DN_7P_C EXP_B_DN_7N_C

EXP_C_DN_0P_C EXP_C_DN_0N_C

EXP_C_DN_1P_C EXP_C_DN_1N_C

EXP_C_DN_2P_C EXP_C_DN_2N_C

EXP_C_DN_3P_C EXP_C_DN_3N_C

EXP_C_DN_4P_C EXP_C_DN_4N_C

EXP_C_DN_5P_C EXP_C_DN_5N_C

EXP_C_DN_6P_C EXP_C_DN_6N_C

EXP_C_DN_7P_C EXP_C_DN_7N_C

MCH_EXP_COMP

DDRCRES0

33 33 33 33 33 33 33 33 33 33 33 33

+1.5V

18 18 18

R1605

220

x02_tj_091903

1 2

17 17

1K-5%

R1606

+1.5V+3.3V

R1082

220

+1.5V

R1001

1 2

1K-5%

R1247

+3.3V

24.9-1%

4.7K

R1604

1 2

C1738

MCH_EXPHPINTR_N

.1uF

10V-10%

+3.3V

2 1

TLV431A

220

D33

R12

1K-1%1K-1%

x00_tj_051203

100K-1%

EXP_A_DN_0P_C

EXP_A_DN_0N_C

EXP_A_DN_1P_C

EXP_A_DN_1N_C

EXP_A_DN_2P_C

EXP_A_DN_2N_C

EXP_A_DN_3P_C

EXP_A_DN_3N_C

EXP_A_DN_4P_C

EXP_A_DN_4N_C

EXP_A_DN_5P_C

EXP_A_DN_5N_C

EXP_A_DN_6P_C

EXP_A_DN_6N_C

EXP_A_DN_7P_C

EXP_A_DN_7N_C

EXP_B_DN_0P_C

EXP_B_DN_0N_C

EXP_B_DN_1P_C

EXP_B_DN_1N_C

EXP_B_DN_2P_C

EXP_B_DN_2N_C

EXP_B_DN_3P_C

EXP_B_DN_3N_C

EXP_B_DN_4P_C

EXP_B_DN_4N_C

EXP_B_DN_5P_C

EXP_B_DN_5N_C

EXP_B_DN_6P_C

EXP_B_DN_6N_C

EXP_B_DN_7P_C

EXP_B_DN_7N_C

EXP_C_DN_0P_C

EXP_C_DN_0N_C

EXP_C_DN_1P_C

EXP_C_DN_1N_C

EXP_C_DN_2P_C

EXP_C_DN_2N_C

EXP_C_DN_3P_C

EXP_C_DN_3N_C

EXP_C_DN_4P_C

EXP_C_DN_4N_C

EXP_C_DN_5P_C

EXP_C_DN_5N_C

EXP_C_DN_6P_C

EXP_C_DN_6N_C

EXP_C_DN_7P_C

EXP_C_DN_7N_C

10uF 6.3V

C1661

1 2

R1833

1 2

1-1%

x00_tt_052903

C1119

.1uF

10V-10%

C1121

.1uF

10V-10%

C1126

.1uF

10V-10%

C1124

.1uF

10V-10%

C1134

.1uF

10V-10%

C1132

.1uF

10V-10%

C1130

.1uF

10V-10%

C1128

.1uF

10V-10%

C1150

.1uF

10V-10%

C1148

.1uF

10V-10%

C1146

.1uF

10V-10%

C1144

.1uF

10V-10%

C1142

.1uF

10V-10%

C1140

.1uF

10V-10%

C1138

.1uF

10V-10%

C1136

.1uF

10V-10%

C1151

.1uF

10V-10%

C1153

.1uF

10V-10%

C1155

.1uF

10V-10%

C1157

.1uF

10V-10%

C1159

.1uF

10V-10%

C1161

.1uF

10V-10%

C1163

.1uF

10V-10%

C1165

.1uF

10V-10%

NET_PHYSICAL_TYPE=PWR PROPAGATION_DELAY=L:S::1200

L131

1 2

4.7uH 80mA

X00_TJ_060403

10uF 6.3V

MCH_VCCBGEXP

0.1uF 16V 1 2

C823

C195

C1120

.1uF

10V-10%

C1122

.1uF

10V-10%

C1125

.1uF

10V-10%

C1123

.1uF

10V-10%

C1133

.1uF

10V-10%

C1131

.1uF

10V-10%

C1129

.1uF

10V-10%

C1127

.1uF

10V-10%

C1149

.1uF

10V-10%

C1147

.1uF

10V-10%

C1145

.1uF

10V-10%

C1143

.1uF

10V-10%

C1141

.1uF

10V-10%

C1139

.1uF

10V-10%

C1137

.1uF

10V-10%

C1135

.1uF

10V-10%

C1152

.1uF

10V-10%

C1154

.1uF

10V-10%

C1156

.1uF

10V-10%

C1158

.1uF

10V-10%

C1160

.1uF

10V-10%

C1162

.1uF

10V-10%

C1164

.1uF

10V-10%

C1166

.1uF

10V-10%

EXP_A_DN_0P

EXP_A_DN_0N

EXP_A_DN_1P

EXP_A_DN_1N

EXP_A_DN_2P

EXP_A_DN_2N

EXP_A_DN_3P

EXP_A_DN_3N

EXP_A_DN_4P

EXP_A_DN_4N

EXP_A_DN_5P

EXP_A_DN_5N

EXP_A_DN_6P

EXP_A_DN_6N

EXP_A_DN_7P

EXP_A_DN_7N

EXP_B_DN_0P

EXP_B_DN_0N

EXP_B_DN_1P

EXP_B_DN_1N

EXP_B_DN_2P

EXP_B_DN_2N

EXP_B_DN_3P

EXP_B_DN_3N

EXP_B_DN_4P

EXP_B_DN_4N

EXP_B_DN_5P

EXP_B_DN_5N

EXP_B_DN_6P

EXP_B_DN_6N

EXP_B_DN_7P

EXP_B_DN_7N

EXP_C_DN_0P

EXP_C_DN_0N

EXP_C_DN_1P

EXP_C_DN_1N

EXP_C_DN_2P

EXP_C_DN_2N

EXP_C_DN_3P

EXP_C_DN_3N

EXP_C_DN_4P

EXP_C_DN_4N

EXP_C_DN_5P

EXP_C_DN_5N

EXP_C_DN_6P

EXP_C_DN_6N

EXP_C_DN_7P

EXP_C_DN_7N

4 4

R181

2.5V Generation

TITLE

DWG NO.

DATE

COMPUTER CORPORATION

AUSTIN,TEXAS

SCHEM,PLN,SV,PE2800/2850/1850

REV.

D1660

SHEET

A00-00

MCH_HCRES0

MCH_HODTCRES

MCH_HSLWCRES

R982

49.9-1%

48.7-1% SUB*_X5575

x04_sdx04_sd

R1057

1 2

549-1%

442-1%

SUB*_0K260

MCH_HDACVREF

MRGN_MHDAC

1 3 4

TSM 2X2 SMT HDR

R983

49.9-1%

1 2

R1406

775mV

750-1%

R1547

NP01

C1198

220pF

50V-10%

C1191

1uF

10V-10%

R378

1 2

x04_sd

90.9-1%

27,31,35

ICH_SEG0_SDA

ICH_SEG0_SCL

NP*

R1425

1 2

220

R1424

220

x04_tj_031604

ICH_SEG0_MCH_SDA

ICH_SEG0_MCH_SCL

1 2

R1407

8.2K-5%

NP*

NET_PHYSICAL_TYPE=PWR PROPAGATION_DELAY=L:S::1200

8.2K-5%

NP*

MCH & PCI EXPRESS CAPS

1 2

7/14/2004 17 OF 60

subsys done

A B

B D

+CPU_VTT

PROPAGATION_DELAY=L:S::700 NET_PHYSICAL_TYPE=50MIL

MCH_VCCA_VCORE

L113

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

MCH_VCCA_VCORE_L

PROPAGATION_DELAY=L:S::200 NET_PHYSICAL_TYPE=50MIL

R1173

1 2

1-1%

+1.5V

LINDENHURST MCH

ROOM = MCH

+1.8V

+1.5V

MCH

MCH REFDES = MCH

VDDR_F1

VDDR_H5

MCH

A21 A24

4 4

A27

B11 B14 B17 B20 B23 B26 B29

C10 C13 C16 C19 C22 C25 C28 B32

D12 D15 D18 D21 D24

E24 E26 E29 E32

F10 F13 F16 F19 F22 F25 F28 F31

G12 G15 G18 G21 G24 G27 G30

H11 H14 H17 H20 H32

J10 J22 J25 J28 J31

K12 K15 K18 K21 K24

L14 L16 L18 L20 L22 L26 L29 L32

M10 M11 M13 M15 M17 M19 M21 M23 M25 M31

N12 N14 N16 N18 N20 N22 N24 N27 N30

P11 P13 P15

GND-A21 GND-A24 GND-A27

GND-B5

GND-B8 GND-B11 GND-B14 GND-B17 GND-B20 GND-B23 GND-B26 GND-B29

GND-C1

GND-C4

GND-C7 GND-C10 GND-C13 GND-C16 GND-C19 GND-C22 GND-C25 GND-C28 GND-B32

GND-D6

GND-D9 GND-D12 GND-D15 GND-D18 GND-D21 GND-D24

GND-E2

GND-E5 GND-E24 GND-E26 GND-E29 GND-E32

GND-F4

GND-F7 GND-F10 GND-F13 GND-F16 GND-F19 GND-F22 GND-F25 GND-F28 GND-F31

GND-G3

GND-G9 GND-G12 GND-G15 GND-G18 GND-G21 GND-G24 GND-G27 GND-G30

GND-H2

GND-H8 GND-H11 GND-H14 GND-H17 GND-H20 GND-H32

GND-J1

GND-J4

GND-J7 GND-J10 GND-J22 GND-J25 GND-J28 GND-J31

GND-K6 GND-K12 GND-K15 GND-K18 GND-K21 GND-K24

GND-L2

GND-L5

GND-L8 GND-L14 GND-L16 GND-L18 GND-L20 GND-L22 GND-L26 GND-L29 GND-L32

GND-M4 GND-M10 GND-M11 GND-M13 GND-M15 GND-M17 GND-M19 GND-M21 GND-M23 GND-M25 GND-M31

GND-N3

GND-N6

GND-N9 GND-N12 GND-N14 GND-N16 GND-N18 GND-N20 GND-N22 GND-N24 GND-N27 GND-N30

GND-P2

GND-P8 GND-P11 GND-P13 GND-P15

ROOM=MCH

INTEL LINDENHURST MCH V0P21

HETERO 7 OF 7

GND-P17 GND-P19 GND-P23 GND-P26 GND-P32

GND-R1 GND-R4

GND-R7 GND-R12 GND-R14 GND-R16 GND-R18 GND-R20 GND-R22 GND-R25 GND-R28 GND-R31

GND-T6 GND-T11 GND-T13 GND-T15 GND-T17 GND-T19 GND-T21 GND-T30

GND-U2

GND-U5

GND-U8 GND-U12 GND-U14 GND-U16 GND-U18 GND-U20 GND-U22 GND-U26 GND-U32

GND-V4 GND-V10 GND-V11 GND-V13 GND-V15 GND-V17 GND-V19 GND-V21 GND-V25 GND-V28 GND-V31

GND-W3

GND-W6

GND-W9 GND-W12 GND-W14 GND-W16 GND-W18 GND-W20 GND-W22 GND-W24 GND-W30

GND-Y2

GND-Y8 GND-Y11 GND-Y13 GND-Y15 GND-Y17 GND-Y19 GND-Y21 GND-Y23 GND-Y26 GND-Y32 GND-AA1 GND-AA4 GND-AA7

GND-AA10 GND-AA12 GND-AA14 GND-AA16 GND-AA18 GND-AA20 GND-AA22 GND-AA25 GND-AA28 GND-AA31

GND-AB6

GND-AB11

GND-AB13 GND-AB15 GND-AB17 GND-AB19 GND-AB21 GND-AB23 GND-AB30

GND-AC2 GND-AC5 GND-AC8

GND-AC12 GND-AC14 GND-AC16 GND-AC18 GND-AC20 GND-AC22 GND-AC26 GND-AC32

GND-AD4

GND-AD10 GND-AD13 GND-AD16 GND-AD19 GND-AD22 GND-AD25 GND-AD28 GND-AD31

GND-AE3 GND-AE6 GND-AE9

VSSA_CORE

VSSA_HI

VSSA_EXP

P17 P19 P23 P26 P32 R1 R4 R7 R12 R14 R16 R18 R20 R22 R25 R28 R31 T6 T11 T13 T15 T17 T19 T21 T30 U2 U5 U8 U12 U14 U16 U18 U20 U22 U26 U32 V4 V10 V11 V13 V15 V17 V19 V21 V25 V28 V31 W3 W6 W9 W12 W14 W16 W18 W20 W22 W24 W30 Y2 Y8 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y26 Y32 AA1 AA4 AA7 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AA28 AA31 AB6 AB11

AB13 AB15 AB17 AB19 AB21 AB23 AB30 AC2 AC5 AC8 AC12 AC14 AC16 AC18 AC20 AC22 AC26 AC32 AD4 AD10 AD13 AD16 AD19 AD22 AD25 AD28 AD31 AE3 AE6 AE9

F5 P21 V23

MCH_VSSA_SB MCH_VSSA_HI MCH_VSSA_EXP

18 18 18

AE15 AE21 AE27

AF2 AF8

AF11

AF14 AF17 AF20 AF23 AF26 AF29 AF32

AG1 AG4

AG7 AG13 AG19 AG25 AG31

AH9 AH12 AH15 AH18 AH21 AH24 AH27 AH30

AJ2

AJ5 AJ11

ROOM=MCH

MCH

GND-AE15 GND-AE21 GND-AE27 GND-AF2 GND-AF8 GND-AF11

GND-AF14 GND-AF17 GND-AF20 GND-AF23 GND-AF26 GND-AF29 GND-AF32 GND-AG1 GND-AG4 GND-AG7 GND-AG13 GND-AG19 GND-AG25 GND-AG31 GND-AH9 GND-AH12 GND-AH15 GND-AH18 GND-AH21 GND-AH24 GND-AH27 GND-AH30 GND-AJ2 GND-AJ5 GND-AJ11

INTEL LINDENHURST MCH V0P21

HETERO 6 OF 7

GND-AJ17 GND-AJ23 GND-AJ29 GND-AJ32

GND-AK4

GND-AK7 GND-AK10 GND-AK13 GND-AK16 GND-AK19 GND-AK22 GND-AK25 GND-AK28 GND-AK31

GND-AL3

GND-AL9 GND-AL15

GND-AL21 GND-AL27 GND-AL33

GND-AM2

GND-AM5

GND-AM8 GND-AM11 GND-AM14 GND-AM17 GND-AM20 GND-AM23 GND-AM26 GND-AM29 GND-AM32

GND-AN7 GND-AN13 GND-AN19 GND-AN25 GND-AN31

AJ17 AJ23 AJ29 AJ32 AK4 AK7 AK10 AK13 AK16 AK19 AK22 AK25 AK28 AK31 AL3 AL9 AL15

AL21 AL27 AL33 AM2 AM5 AM8 AM11 AM14 AM17 AM20 AM23 AM26 AM29 AM32 AN7 AN13 AN19 AN25 AN31

+1.5V

N11

P12 R11

T12 U11

V12 W11

Y12

AA11

AB3

AB9 AB12 AB14 AB16 AB18 AB20 AB22 AC11 AC13 AC15 AC17 AC19 AC21 AC23

AD1

AD7 AE12 AE18 AE24

AF5 AG10 AG16 AG22 AG28

AH3

AJ8 AJ14 AJ20 AJ26

AL1

AL6 AL12 AL18 AL24 AL30

AN3 AN10 AN16 AN22 AN28

K30

K33

M28

N33

P29

R23

T22

T24

T27

T33

U29

V22

W23

W27

W33

Y22

Y29 AA23 AB24 AB27 AB33 AC29 AE30 AE33 AH33

VDDR_K3

VDDR_M1

VDDR_M7 VDDR_N11

VDDR_P5 VDDR_P12 VDDR_R11

VDDR_T3

VDDR_T9 VDDR_T12 VDDR_U11

VDDR_V1

VDDR_V7 VDDR_V12 VDDR_W11

VDDR_Y5 VDDR_Y12 VDDR_AA11 VDDR_AB3 VDDR_AB9 VDDR_AB12 VDDR_AB14 VDDR_AB16 VDDR_AB18 VDDR_AB20 VDDR_AB22 VDDR_AC11 VDDR_AC13 VDDR_AC15 VDDR_AC17 VDDR_AC19 VDDR_AC21 VDDR_AC23 VDDR_AD1 VDDR_AD7 VDDR_AE12 VDDR_AE18 VDDR_AE24 VDDR_AF5 VDDR_AG10 VDDR_AG16 VDDR_AG22 VDDR_AG28 VDDR_AH3 VDDR_AJ8 VDDR_AJ14 VDDR_AJ20 VDDR_AJ26 VDDR_AL1 VDDR_AL6 VDDR_AL12 VDDR_AL18 VDDR_AL24 VDDR_AL30 VDDR_AN3 VDDR_AN10 VDDR_AN16 VDDR_AN22 VDDR_AN28

VEXP_K30 VEXP_K33 VEXP_M28 VEXP_N33 VEXP_P29 VEXP_R23 VEXP_T22 VEXP_T24 VEXP_T27 VEXP_T33 VEXP_U29 VEXP_V22 VEXP_W23 VEXP_W27 VEXP_W33 VEXP_Y22 VEXP_Y29 VEXP_AA23 VEXP_AB24 VEXP_AB27 VEXP_AB33 VEXP_AC29 VEXP_AE30 VEXP_AE33 VEXP_AH33

INTEL LINDENHURST MCH V0P21

HETERO 5 OF 7

ROOM=MCH

VCORE_C33 VCORE_G33 VCORE_H29

VCORE_K9 VCORE_K27 VCORE_L23 VCORE_M12 VCORE_M22 VCORE_N13 VCORE_N15 VCORE_N17 VCORE_N19 VCORE_N21 VCORE_N23 VCORE_P14 VCORE_P16 VCORE_P18 VCORE_P22 VCORE_R13 VCORE_R15 VCORE_R17 VCORE_R19 VCORE_R21 VCORE_T14 VCORE_T16 VCORE_T18 VCORE_T20

VCORE-U13 VCORE-U15 VCORE_U17 VCORE_U19 VCORE_U21 VCORE_V14 VCORE_V16 VCORE_V18 VCORE_V20 VCORE_W13 VCORE_W15 VCORE_W17 VCORE_W19 VCORE_W21 VCORE_Y14 VCORE_Y16 VCORE_Y18 VCORE_Y20

VCORE_AA13 VCORE_AA15 VCORE_AA17 VCORE_AA19 VCORE_AA21

VTT_A3 VTT_A6

VTT_A9 VTT_A12 VTT_A15 VTT_A18 VTT_A31 VTT_D27 VTT_D30

VTT_E8 VTT_E11 VTT_E14 VTT_E17 VTT_E20 VTT_E23 VTT_H23 VTT_H26 VTT_J13 VTT_J16 VTT_J19 VTT_L13 VTT_L15 VTT_L17 VTT_L19 VTT_L21 VTT_M14 VTT_M16 VTT_M18 VTT_M20

VCCA_CORE

VCCA_DDR VCCA_EXP

VCCA_HI

C33 G33 H29 K9 K27 L23 M12 M22 N13 N15 N17 N19 N21 N23 P14 P16 P18 P22 R13 R15 R17 R19 R21 T14 T16 T18 T20

U13 U15 U17 U19 U21 V14 V16 V18 V20 W13 W15 W17 W19 W21 Y14 Y16 Y18 Y20 AA13 AA15 AA17 AA19 AA21

A3 A6 A9 A12 A15 A18 A31 D27 D30 E8 E11 E14 E17 E20 E23 H23 H26 J13 J16 J19 L13 L15 L17 L19 L21 M14 M16 M18 M20

F6 E4 U23 P20

+1.5V

+CPU_VTT

MCH_VCCA_VCORE MCH_VCCA_DDR MCH_VCCA_EXP MCH_VCCA_HI

18 18 18 18

To be placed near hub link on MCH

C636

1 2

MCH POWER

C1169

0.1uF 16V

C401

.01uF 50V

C117021C1171

1 2

0.1uF 16V

C142

1 2

0.1uF 16V

MRGN_MHVS

3 4

TSM 2X2 SMT HDR

0.1uF 16V

C637

1 2

+1.5V

R234

1 2

@MCH

R551

.01uF 50V

2.7K-5%

NP*

NP01R582

R276

43.2-1%49.9-1%

1 2

R537

1 2

MCH HLA VREF & VSWING

NET_PHYSICAL_TYPE=PWR

24.3-1% 78.7-1%

MRGN_MHVR

1 3 4

HLA_MCH_SWING

HLA_MCH_VREF

TSM 2X2 SMT HDR

(804mv)

(353mv)

NP*

2.7K-5%

1 2

R553

NP01

PROPAGATION_DELAY=L:S::600 NET_PHYSICAL_TYPE=50MIL

PROPAGATION_DELAY=L:S::1200 NET_PHYSICAL_TYPE=50MIL

PROPAGATION_DELAY=L:S::1400 NET_PHYSICAL_TYPE=50MIL

PROPAGATION_DELAY=L:S::1500 NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_SB

MCH_VCCA_DDR

MCH_VSSA_SB

MCH_VCCA_EXP

MCH_VSSA_EXP

MCH_VCCA_HI

MCH_VSSA_HI

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1300

PROPAGATION_DELAY=L:S::1000

1 2

C1589

C1236

1 2

C1238

C1240

10uF 6.3V

x00_tj_042903

1 2

C1242

C1226

1 2

10uF 6.3V

C1225

10uF 6.3V

C1227

10uF 6.3V

C1228

1 2

10uF 6.3V

DDRCRES2

DDRCRES1

0.1uF 16V0.1uF 16V

L112

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

L111

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

0.1uF 16V

L110

1 2

4.7uH 80mA

X00_TJ_060403

X03b_TJ_011904

0.1uF 16V

DDRIMPCRES

DDRCRES0

DDRSLWCRES

23.4mA

MCH_VCCA_DDR_L

PROPAGATION_DELAY=L:S::200 NET_PHYSICAL_TYPE=50MIL

23.4mA

MCH_VCCA_EXP_L

PROPAGATION_DELAY=L:S::200 NET_PHYSICAL_TYPE=50MIL

21.3mA

MCH_VCCA_HI_L

PROPAGATION_DELAY=L:S::200 NET_PHYSICAL_TYPE=50MIL

24.7mA

PN 7H671

ESR = 300mohm

Max current = 80mA Inductance = 4.7uH

R1031

1 2

287-1%

R1004

1 2

1.05K-1%

SUB=SUB*_C6435

976-1%

x04_tj_032904

+1.8V

R1573

40.2-0.5%

C1173

1 2

R1574

1 2

40.2-0.5%

C1172

0.1uF 16V 0.1uF 16V

MCH Power & Ground

COMPUTER CORPORATION

AUSTIN,TEXAS

TITLE

SCHEM,PLN,SV,PE2800/2850/1850

DWG NO.

DATE

D1660

7/14/2004

SHEET

x00_tj_051203 x00_tj_052903 x02_tj_100703

R1174

1-1%

x00_tj_052903

R1175

1 2

.499-1%

R1176

1 2

1-1%

x00_tj_052903

REV.

A00-00

18 OF 60

+1.5V

subsys done

A B

+ 42 hidden pages

MSI MS-9154 Schematic 00

Specifications and Main Features

Frequently Asked Questions

User Manual