MSI MS-9142 9T576A02

EVERGLADES MOTHERBOARD

1

1U DDR DIMM (PC2100)

2

1U DDR DIMM (PC2100)

PCI-X 133 SLOT

3

4

1U DDR DIMM (PC2100)

Registered ECC SDRAMRegistered ECC SDRAM

1U DDR DIMM (PC2100)

BLOCK DIAGRAM

ABC

64 bits data

DATA QUAD PUMPED

(4266 MB/S)

64

Registered ECC SDRAM

SEPARATE INBOUND & OUTBOUND

Registered ECC SDRAM

MEMORY BUS

128 bits data

DATA DOUBLE PUMPED

64

133MHz

(4266 MB/S)

IMB BUS
16 bits

DATA DOUBLE PUMPED

64 BIT PCI-X BUS

400 MHz

(1600 MB/S

EACH WAY)

PCI-X 133

(1067 MB/S)

DATA

PCI-X 133 SLOT

MAIN

PRESTONIA

PROCESSOR 1

64

DATA

P6 Bus

133MHz

RCC

PRESTONIA

PROCESSOR 2

32Mb (4MB)

HARD DRIVES

ATA-100

IDE

(BIOS)

FLASH

X BUS

GCLE

CMIC

16

SEPARATE INBOUND & OUTBOUND

16
DATA

SEPARATE INBOUND & OUTBOUND

AB

DATA DOUBLE PUMPED

THIN IMB BUS

EACH IS 4 bits

200MHz

DOUBLE PUMPED

(200 MB/S EACH WAY)

DATA

IMB BUS
16 bits
400 MHz

(1600 MB/S

EACH WAY)

16

16
DATA

LPC BUS

NATIONAL

PC87414

RCC

CIOB-E

PCI Bridge

RJ-45

Connector

GB ETHERNET

RJ-45

Connector

GB ETHERNET

64 BIT PCI-X BUS

PCI-X 133

(1067 MB/S)

RCC

CIOB-X2

PCI Bridge

FLOPPY

ON BACKPLANE

64 BIT PCI-X BUS

PCI-X 133

(1067 MB/S)

PS/2

KB & MOUSE

ON BACKPLANE

LSI

53C1030

Dual

Channel

Ultra 320

SCSI

SCSI
Term

EXTERNAL BACKPLANE

Connector

Ultra320 SCSI

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

SCSI
Term

USB 1

USB 2

Connector

Connector

RCC

CSB5

South

Bridge

Super

I/O Chip

Connectors

SERIAL A

Connector

Dell Controlled Print

VGA

USB 3

Connector

ON CTRL PANEL

ATI

RAGE XL

Video

USB4

32 BIT PCI BUS

33 MHz

(133 MB/S)

PRIMARY IDE

SECONDARY IDE

ON BACKPLANE

SERIAL PORT B

OPTIONAL

INTEL

i80321

"Verde"

ROMB

Processor

ROMB CARD

OPTIONAL

THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER
CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN
ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE
REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL
COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION
OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE
INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS
NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH
THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF
DELL COMPUTER CORPORATION.

Header

CD-ROM

ON BACKPLANE

USB4

LPC BUS

RAID Memory

128MB DDR200

16Mb (2MB)

FLASH

(RAID)

PROPRIETARY NOTE

TABLE OF CONTENTS

ESM4

Agilent

SP2

Processor

ESM4
FPGA

OPTIONAL

32

DATA

8 MB

SDRAM

(2Mx32)

OPTIONAL

ESM4
CARD

SDRAM

FLASH

QLOGIC
ZIRCON

ESM3

BMC

Processor

D

REVISIONS

REV

X00-00

X01-00

X02-00

X03-00

X04-00 IPMB TEST BUILD 04 FEB 2003

A00-00 140859

A01-00 141268

A01-00

FIRST PROTOTYPES

PRODUCT TEST BUILD

CLEAN UP DFM ISSUES (NOT BUILT)

SYSTEM TEST

A01 PRODUCTION RELEASE SHANE CHIASSON14 FEB 2003

DESCRIPTIONECO DATE

15 MAR 2002

18 OCT 2002

18 OCT 2002

18 DEC 2002

12 FEB 2003

25 FEB 2003141594 A02 PRODUCTION RELEASE

TABLE OF CONTENTS

DESCRIPTION

TABLE OF CONTENTS and BLOCK DIAGRAM

...

1

...

CLOCK DIAGRAM

2

...

3

...

CLOCKS

4

...

MEMORY & PCI CLOCKS

5

...

PROCESSORS

6

...

PROCESSORS

7

...

PROCESSORS

8

...

VRMS

9

...

ITP & LEVEL TRANSLATION

10

...

CMIC-LE (MEMORY INTERFACE)

11

...

CMIC-LE

12

...

CMIC-LE DECOUPLING & SUPPORT

13

...

DDR DIMMS

14

...

15

DDR DIMMS

16...

DDR TERMINATION

...

SPARE GATES

17

...

18

CSB5

...

19

IRQ SERIALIZATION & X-BUS ADDRESS LATCHES

...

20

USB, REAR CYCLOPS

...

SYSTEM BIOS FLASH, CSB5 I2C MUX

21

...

22

SIO

...

23

PS/2 AND SERIAL

...

24

ATI VIDEO

25...

VIDEO MEMORY & CONNECTOR

26

CIOB-X2

...

27

CIOB-X2 POWER

...

28...

CIOB-E -- PCI-X AND PHYSICAL LAYER INTERFACE

29

CIOB-E -- IMB BUS AND STRAPPING

...

30

CIOB-E -- POWER

...

31

...

SECONDARY PCI-X BUS SERIES TERMINATORS

32

...

PHYSICAL LAYER NIC CONNECTORS

33

PCI-X BUS -- PULL-UPS AND CONNECTORS

...
...

34

-12V INVERTER

35

...

ESM3 -- ZIRCON BMP and SUPPORT CPLD

36

ESM3 -- SRAM and FLASH

...

37

...

ESM3 -- I2C

38...

ESM3 -- FANS

39

...

ESM3 -- ESM4 and INTRUSION DETECTION

40

ESM3 -- VOLTAGE MONITORING

...

41

...

DC/DC CONVERTERS: 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.25V

42

...

BACKPLANE CONNECTOR
LSI SCSI CONTROLLER--PCI-X/SCSI DIFFERENTIAL PAIRS

...

43

LSI SCSI CONTROLLER--POWER/MISC

44...
...

45

SCSI TERMINATION AND EXTERNAL SCSI CONNECTOR

46

...

FRONT PANEL CONNECTOR & IMPEDANCE TEST COUPONS
POWERGOOD CPLD

47

...

48...

POWER SUPPLY CONNECTOR

49

...

ESM4 NIC CONNECTOR

50...

RESET BLOCK DIAGRAM

51

ROMB (CONNECTOR, BATTERY, CHARGER, SUPPORT CIRCUITRY)

...

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO
ECO

02/14/03

02/14/03

02/14/03

02/14/03

TITLE

DWG NO.

DATE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

9T576

2/26/2003

EVERGLADES 1 2-26-2003_11:40

DCBA

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

I2C

SRAM

128KB

FLASH

32Mb

DRAWN

DESIGNED

CHECKED

APPROVED

APPROVED

APPROVED

APPROVED

RELEASED

PAGE

XILINX

XC9572XL

ESM3

Support

CPLD

ESM3

EVERGLADES TEAM

SHANE CHIASSON

WILL SMITH

STUART HAYES

APPROVED

SHANE CHIASSONA00 PRODUCTION RELEASE

SHANE CHIASSON

REV.

1 OF 51

1

2

3

4

A02-00

B D

CA

80MHz

OSC

CLOCK DISTRIBUTION DIAGRAM

100MHz

1

14.3MHz
XTAL

XTALOUTXTALIN

133MHz
133MHz

133M

CDC950

2

CLOCK

GENERATOR

133MHz

133MHz

33MHz

PRESTONIA
PROCESSOR

HOST

PRESTONIA
PROCESSOR

HOST

ITP

(DEBUG)

HOST

1-to-9

ZERO

DELAY

Buffer

IN

FB

CMIC-LE

NORTH BRIDGE

MCLK

IMB_CLK_A_R
IMB_CLK_A_T

BCLK

IMB_CLK_B_R
IMB_CLK_B_T

IMB_CLK_T

133MHz

133MHz

200MHz
200MHz

200MHz
200MHz

DIMM

DIMM

DIMM

DIMM

200MHz
200MHz

200MHz
200MHz

CIOB-X2

PCLK0

PFBCLK

FSCLK_T
FSCLK_R

33M

SFBCLK SCLK0

CIOB-E

PCLK0

PFBCLK

PCLK0
PCLK0

FSCLK_T
FSCLK_R

33M

33/66/133MHz
33/66/133MHz

25 MHz

XTAL

100MHz

100MHz

33/66/133MHz

33/66/133MHz

64 BIT PCI-X SLOT

CLKOUT

80MHz

64 BIT PCI-X SLOT

LSI

1030

SCSICLK

PCICLK

ROMB SOCKET

PCICLK_IN

1

2

CSB5

33M

REF

48M

33MHz

14.3MHz

14.3MHz

48MHz

48MHz

1-to-10

BUFFER

3

10MHz

OSC

CLKOUT

33MHz

33MHz

33MHz

33MHz

33MHz

33MHz

33MHz

33MHz

33MHz

33MHz

PIRQ

SHIFTER

CLK

PIRQ

SHIFTER

CLK

ESM4

CONNECTOR

PCICLK

ESM3
CPLD

LPCCLK

ESM3

PROCESSOR

LPCCLK

CLKIN

14.3MHz

48MHz

ATI

VIDEO

PCICLK

XTALIN XTALOUT

LPCCLK

CLKIN

MEM_CLK CLK

SUPER I/O

87414

PROG

VIDEO

MEMORY

14.3MHz

48MHz

SOUTH BRIDGE

PCICLK

REFCLK

USBCLK

3

4

AB

14.3MHz

14.3MHz

48MHz
48MHz

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

AUSTIN,TEXAS

DC

SHEET

REV.

2 OF 51

2-26-2003_11:402EVERGLADES

A02-00

4

B D

CA

1

2

3

$8.35 for 100W SIP

+3.3V_AUX

GREY BOX 1

+12V

+3.3V_FP

PWRGOOD

AC_OKPS_ON

GREY BOX 2

+12V

+3.3V_FP

PWRGOOD

AC_OKPS_ON

PAGE 48

+12V

+12V

+12V

+12V

+12V

+2.5V

+12V

+12V

+5V

8-9A

IN

PWRGOOD

ENABLE

+1.8V

1.7A

IN

+1.8V

PWRGOODENABLE

+3.3V

11A

IN

+3.3V

PWRGOODENABLE

+2.5V

18A

IN

+2.5V

PWRGOODENABLE

+1.5V

2.7A

IN

+1.5V

DDR_TERM

5-6A

IN

+1.25V

PWRGOODENABLE

+3.3V_AUX

+5V

40W SIP=8A MAX
...OR 1x40W + 1x15W

PAGE 41

+5V

15W SIP

PAGE 41

40W SIP=10A MAX
...OR 1x40W + SMALL LINEAR?

PAGE 41

100W SIP=25A MAX

PAGE 41

LINEAR FROM 2.5V

PAGE 41

15W SIP

PAGE 41

+5V_AUX

5V_AUX

100mA

IN

+2.5V

PAGE 37

-12V

IN

100mA

PAGE 34

+2.5V

+3.3V_AUX

+3.3V

PWRGOOD

V_CORE V_CORE

PWRGOOD

INCOMPLETE!

+3.3V_NIC

+2.5V_AUX

0.5A

IN

+3.3V_NIC or +2.5V_NIC ???

+1.2V_AUX

1.9A

IN

PROC 1

VID

THERMTRIP

PROC 2

VID

THERMTRIP

POWERGOOD

CPLD

THERMTRIP1

VID2

THERMTRIP2

+2.5V

PAGE 30

+5V

PAGE 30

VRM_ENVID1

+2.5V_NIC

LINEAR

+1.2V_NIC

LINEAR

CORE VRM 1

V_CORE

VIDV_CORE

ENABLEPWRGOOD

PAGE 9

CORE VRM 2

VID

PWRGOOD

ENABLE

PAGE 9

PIRQ CONNECTIONS

PIRQ0

PIRQ1

PIRQ2

PIRQ3

PIRQ4

DEVICE
CIOB-E
LSI 1030 SCSI
VERDE ROMB

PCI-X SLOT 1
PCI-X SLOT 2
ESM4
ESM3

PCI DEVICE NUMBERS

DEVICE BUS AD LINE DEVICE

CMIC
CIOB-E
CIOB-X2

ATI VIDEO
CSB5 -- MAIN
CSB5 -- IDE

CSB5 -- LPC BUS
CSB5 -- XIOAPIC (UNUSED)
ESM4

PCI-X SLOT 1

LSI 1030 SCSI

PCI-X SLOT 2

GIGABIT NIC A
GIGABIT NIC B

B

A

A
A

USES GPIOE16 ON THE SUPER I/O CHIP -- MUST BE SOFTWARE CONFIGURED TO GENERATE IRQ

PIRQ5

B
B

ABCD

0

AD16
0
0

AD30

0

AD31 0xF 0

0

AD31 0xF

0

AD31 0xF

0
0 AD31 0xF 3

AD31

0

AD24

0

AD22

1

2VERDE ROMB

AD19

AD21

2

AD20

3

4

TO USE ITP CONNECTOR,

POPULATE THE FOLLOWING COMPONENTS:

R106/R107 ON PAGE 4 WITH 22 OHM (133MHz CLOCK TO ITP)
J15 and P11 WITH APPROPRIATE CONNECTORS

PIRQ6

PIRQ7

ABCD

PIRQ8

PIRQ9

0xE

0xF

PIRQ10

PIRQ11

PIRQ12

FUNCTION

0

8

6

3
5

4

1
14

PIRQ13

PIRQ14

0

1
2CSB5 -- USB

4-6

0
1

PIRQ15

1

DCBA

2

3

4

VOLTAGE CONVERTER BLOCK DIAGRAM

AB

-12V

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

AUSTIN,TEXAS

DC

SHEET

REV.

3 OF 51

2-26-2003_11:403EVERGLADES

A02-00

4

B D

CA

ROOM=MAINCLK

R199

R185

21

1

CK_SYN_XIN1

50V-5%

21

CB191

0.1uF 16V

0.1uF 16V

CK_SYN_XIN2

R176

475-1%

12

21

CB17021CB189

0.1uF 16V

4

4
4

0.1uF 16V

4,7,12,22

V_3P3_SYN1

V_3P3_SYN2

X3

21

14.31818MHz

R179

12

1M-5%

NP*

21

12

CB168

.01UF

50V-20%

C242

.01UF

10pF

NP*

50V-20%

12

CB171

10pF

12

C235

50V-5%

NP*

+3.3V

21

2

C248

+3.3V

21

C230

4.7uF

6.3V-10%

4.7uF

6.3V-10%

C247

12

C231

12

L41

21

600mA

CB193

.01UF

50V-20%

L39

12

600mA

.01UF

CB172

50V-20%

21

21

4.7uF
CB190

6.3V-10%

4.7uF
CB178

6.3V-10%

12

CB169

0.1uF 16V0.1uF 16V

21

12

0.1uF 16V

12

CB167

12

CB192

.01UF

50V-20%

.01UF

50V-20%

12

CB179

22-5%

47

4
4

4

R184

12

22-5%

R_CK_33M_PCI

GPI_SYN_SEL100

R_CK_14M_CSB

SYN_IREF_26

R_CK_48M_USB
R_CK_48M_SIO

SYN_MULTSEL0
SYN_MULTSEL1

GPI_SPREAD_EN

SYNTH_EN

R183

12

22-5%

21

22-5%

22 7

XIN HCLK0

23

XOUT

1

CLK33

48

SEL100/133

19

REF

26

IREF

3

3V48/SELA

4

3V48B/SELB

30

MULTISEL0

29

MULTISEL1

20

SPREAD

44

PWRDWN

2

VDD0

6

VDD1

12

VDD2

18

VDD3

24

VDD4

25

VDD5

31

VDD6

37

VDD7

43

VDD8

46

VDD9

U24

CDC950/9248

TSSOP48

HCLKB0

HCLK1

HCLKB1

HCLK2

HCLKB2

HCLK3

HCLKB3

HCLK4

HCLKB4

HCLK5

HCLKB5

HCLK6

HCLKB6

HCLK7

HCLKB7

SUB*_4C853

4C853 RCC_SYN (TSSOP48) IS:

TI CDC950DGG
ICS ICS9248AG-150
PHILIPS PCK2022RDGG
PERICOM PI6C210A

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

8

10
11

13
14

16
17

42
41

39
38

36
35

33
32

5
9
15
21
27
28
34
40
45
47

CK_14M_TO_BUFFER

CK_48M_SIO

CK_48M_USB

CK_33M_PBUF2

4

22

18

5

R_CK_100M_CPU0_P

R_CK_100M_CPU0_N

R_CK_100M_CPU1_P

R_CK_100M_CPU1_N

NC_CK_100M_MEM_P

NC_CK_100M_MEM_N

NC_CK_100M_SYN_16

NC_CK_100M_SYN17

R_CK_100M_ITP_P

R_CK_100M_ITP_N

NC_CK_100M_SP2_P

NC_CK_100M_SP2_N

R_CK_100M_CMIC_P

R_CK_100M_CMIC_N

NC_CK_100M_SYN33_P

NC_CK_100M_SYN32_N

R195

22-5%

R197

12

22-5%

R171

NP0

22-5%

R173

12

22-5%

R194

12

22-5%

21

R196

22-5%

R170

12

NP0

22-5%

21

R172

12

22-5%

21

21

R208

R210

49.9-1%

21

R209

49.9-1%

21

49.9-1%

R211

21

49.9-1%

21

R152

R154

49.9-1%

21

R153

49.9-1%

21

49.9-1%

R155

21

49.9-1%

CK_100M_CPU0_P

CK_100M_CPU0_N

CK_100M_CPU1_P

CK_100M_CPU1_N

CK_100M_ITP_P

CK_100M_ITP_N

CK_100M_CMIC_P

CK_100M_CMIC_N

1

6

6

6

6

10

10

12

12

2

+3.3V

3

+3.3V

R214

21

NP

10K-5%

10K-5%

10K-5%

12

10K-5%

SPREAD LOW = SPREAD ENABLED

4

SPREAD HIGH = SPREAD DISABLED
SEL100 LOW = 100MHZ

SEL100 HIGH = 133MHZ
MULTSEL0 & MULTSEL1 SELECTION

0 0 60ohm, 0.71V
0 1 50ohm, 0.71V

SELA & SELB SELECTION

0 0 H=NORMAL MODE

R192

R175

R169

R193

12

10K-5%

21

NP

R174

12

10K-5%

21

R198

10K-5%

NP

NP

21

NP

R212

12

R207

1K-5%

21

1K-5%

21

R205

R156

1K-5%

12

220

21

R157

NP

220

R213

12

220

21

R151

NP

220

R_CK_14M_CSB

R_CK_48M_SIO

R_CK_48M_USB

SYN_MULTSEL0

SYN_MULTSEL1

GPI_SPREAD_EN

GPI_SYN_SEL100

4

4

4

4

4

4

4,7,12,22

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

CK_14M_TO_BUFFER

4

+3.3V

21

CB509

0.1uF 16V

14 U65

2
3

74VHC02

+3.3V

14 U65

5
6

74VHC02

+3.3V

14 U65

8
9

74VHC02

+3.3V

14 U65

11
12

74VHC02

220

R470

12

CK_14M_XLSYN_R

1

SUB*_907XP
SUB TO LCX FOR EDGE RATE

CK_14M_CSB_R

4

SUB*_907XP
SUB TO LCX FOR EDGE RATE

CK_14M_RNDM_R

10

SUB*_907XP
SUB TO LCX FOR EDGE RATE

NC_14MBUF_X2

13

SUB*_907XP
SUB TO LCX FOR EDGE RATE

X01 -- BUFFERED 14MHz CLOCK TO IMPROVE EDGE RATES

AB

R472

33-5%

R471

33-5%

R494

33-5%

21

CK_14M_XLSYN

21

CK_14M_CSB

21

CK_14M_RNDM

NP*

24

18

47

3

4

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

DATE

9T576

2/26/2003

EVERGLADES 4 2-26-2003_11:40

DC

AUSTIN,TEXAS

REV.

SHEET

4 OF 51

A02-00

B D

CK_133M_MCLK_P

11

CK_133M_MCLK_N

11

1

CK_MEM_FB_133M_N

+2.5V

C345

12

12

CB271

0.1uF 16V

L46

600mA

L45

600mA

0.1uF 16V

21

21

6.3V-10%

4.7uF

CB272

1

2

12

C328

12

CB284

CB283

3300pF

50V-10%

CB282

.01UF

50V-20%

12

0.1uF 16V

12

.01UF

50V-20%

12

CB281

12

CB273

0.1uF 16V

0.1uF 16V

CK_MEM_FB_133M_P

+2.5V

C335

12

12

CB285

.01UF

50V-20%

0.1uF 16V

12

CB274

14,15,21
14,15,21

0.1uF 16V

2

OVERLAP THESE THREE PINS
IF POSSIBLE

CA

R294

12

100-1%

ROOM=DDRCLK

R276

12

100-1%

ASDATA_2P5V
ASCLK_2P5V

R295

12

0-5%

C332

12

0.1uF 16V

13

CLKIN_P

14

CLKIN_N

35

FBIN_N

36

FBIN_P

37

SDA

12

SCK

16

AVCC

17

AGND

4

VDDQ0

11

VDDQ1

15

I2CVDD

21

VDDQ3

28

VDDQ4

34

VDDQ5

38

VDDQ6

45

VDDQ7

1

GND0

7

GND1

8

GND2

18

GND3

24

GND4

25

GND5

31

GND6

41

GND7

42

GND8

48

GND9

2.5V PLL CLOCK DRIVER

FBIN_N AND FBIN_P ARE SWAPPED ON DIFFERENT VENDORS
BUT FBOUT_P AND FBOUT_N ARE ALSO SWAPPED

NOTE

SO IT IS NOT A PROBLEM

0-5%

12

RB134

NP*

FBOUT_LOOP1_N

12

RB141
RB139

12

NP*

FBOUT_LOOP2_N

0-5%

U33

CLK0_P
CLK0_N

CLK1_P
CLK1_N

CLK2_P
CLK2_N

CLK3_P
CLK3_N

CLK4_P
CLK4_N

CLK5_P
CLK5_N

CLK6_P
CLK6_N

CLK7_P
CLK7_N

CLK8_P
CLK8_N

CLK9_P
CLK9_N

FBOUT_P
FBOUT_N

0-5%0-5%

12

RB137
RB133

12

NP*

0-5%

3
2

5
6

10
9

20
19

22
23

46
47

44
43

39
40

29
30

27
26

32
33

59PRT IS:

TI CDCV850DGG
ICS ICS93701BG
PHILIPS PCK2057DGG

CK_SP5_133M_P
CK_SP5_133M_N

CK_SP1_133M_P
CK_SP1_133M_N
CK_SP2_133M_P
CK_SP2_133M_N
CK_SP3_133M_P
CK_SP3_133M_N

CK_DBG_133M_P
CK_DBG_133M_N

CK_SP4_133M_P
CK_SP4_133M_N

CK_133M_DDR3_P
CK_133M_DDR3_N

CK_133M_DDR2_P
CK_133M_DDR2_N

CK_133M_DDR1_P
CK_133M_DDR1_N

CK_133M_DDR0_P
CK_133M_DDR0_N

CK_MEM_FB_OUT_133M_P
CK_MEM_FB_OUT_133M_N

OVERLAP THESE THREE PINS
IF POSSIBLE

1

5
5

5
5

5
5

5
5

5
5

15
15

15
15

14
14

14
14

HEADER FOR LOGIC ANALYZER CLOCK

J4

1

NP*

100-1%

J3

1

NP*

5

5

5

CK_SP1_133M_P

CK_SP1_133M_N

CK_SP2_133M_P

R292

100-1%

12

R297

12

2

R293

100-1%

CK_SP2_133M_N

5

CK_SP3_133M_P

5

CK_SP3_133M_N

5

CK_SP4_133M_P

5

12

R296

100-1%100-1%

12

OVERLAP THESE THREE PINS

33 MHz PCI CLOCK GENERATION

3

+3.3V

12

0.1uF 16V
C426

21

L50

600mA

21

CB427

4.7uF

21

CB413

6.3V-10%

V_3P3_PBUF2

C418

12

0.1uF 16V

.01UF

50V-20%

C397

12

.01UF

50V-20%

12

C405

C398

12

0.1uF 16V

CK_33M_PBUF2

4

.01UF

50V-20%

12

CB415

.01UF

50V-20%

RB267

10K-5%

21

10K-5%

4

2204T CKBUF_M (SSOP28) IS:

ROOM=PCICLK

10K-5%

VDD0
VDD1
VDD2
VDD3
VDD4
VDD5

SDATA

SCLOCK

BUF_IN

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5

W40S11_02

SUB*_2204T

U37

R371

1

5
10
19
24
28

14

21

15

9

4

8
12
17
21
25

R345

21

VDDIIC

SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9

VSSIIC

PBUF2_OE

13

20

OE

2
3
6
7
22
23
26
27
11
18

16

R_CK_33M_LPC

R_CK_33M_CIOB

R_CK_33M_VIDEO

R_CK_33M_SIO

R_CK_33M_PIRQ0

R_CK_33M_RISER

R_CK_33M_ESM4

R_CK_33M_CPLD1

R_CK_33M_CSB5

R_CK_33M_PIRQ1

RB242

21

22-5%

RB246

21

22-5%

R344

21

22-5%

R336

12

22-5%

R347

21

22-5%

R343

22-5%

RB245

22-5%

RB244

22-5%

RB241

22-5%

RB265

22-5%

21

21

21

21

21

IF POSSIBLE

CK_33M_LPC

CK_33M_CIOB

CK_33M_VIDEO

CK_33M_SIO

CK_33M_PIRQ0

CK_33M_CIOBE

CK_33M_ESM4

CLK_PCI32_ZIRCON

CK_33M_CSB5

CK_33M_PIRQ1

0-5%

NP*

12

0-5% 0-5%

RB142
RB140

12

NP*

0-5% 0-5%

19

27

24

22

19

28

39

35

18

19

RB136

FBOUT_LOOP1_P

12

FBOUT_LOOP2_P

12

RB138
RB135

12

NP*

MEMORY CLOCK GENERATION

CYPRESS W40S11-02
PERICOM PI6C182AH
ICS ICS9279AF-03

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

AB

OVERLAP THESE THREE PINS
IF POSSIBLE

R275

CK_SP4_133M_N

5

CK_SP5_133M_P

5

CK_SP5_133M_N

5

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

DATE

9T576

2/26/2003

EVERGLADES 5 2-26-2003_11:40

DC

12

R300

100-1%

12

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

5 OF 51

A02-00

3

4

B D

CA

1

H_A3

6,11

H_A4

6,11

H_A5

6,11

H_A6

6,11

H_A7

6,11

H_A8

6,11

H_A9

6,11

H_A10

6,11

H_A11

6,11

H_A12

6,11

H_A13

6,11

H_A14

6,11

H_A15

6,11

H_A16

6,11

H_A17

6,11

H_A18

6,11

H_A19

6,11

H_A20

6,11

H_A21

6,11

H_A22

6,11

H_A23

6,11

H_A24

6,11

H_A25

6,11

H_A26

6,11

H_A27

6,11

H_A28

6,11

H_A29

6,11

H_A30

6,11

H_A31

6,11

H_A32

6,11

H_A33

2

3

6,11
6,11
6,11

6,11
6,11

6,11
6,11
6,11

6,11

6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11
6,11

6,10
6,10
6,10
6,10

6,10,12

6,10

6,10
6,11

6,10
6,10
6,10
6,10

H_A34
H_A35

H_AP0
H_AP1

H_BNR
H_BPRI
H_BREQ0
H_BREQ1

6

H_BREQ23_PU

6

H_BREQ23_PU

6

H_LOCK

H_ADSTB0
H_ADSTB1
H_ADS
H_REQ0
H_REQ1
H_REQ2
H_REQ3
H_REQ4

H_RS0
H_RS1
H_RS2
H_RSP
H_TRDY

CK_100M_CPU0_P

4

CK_100M_CPU0_N

4

H_INTR
H_NMI
H_SLP
H_STPCLK
H_RST
H_INIT

H0_IERR

10

H_MCERR
H_BINIT

H_A20M
H_SMI
H_FERR
H_IGNNE

A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13

A9

B8
E13
D12
C11

B7

A6

A7

C9

C8

E10

D9

F20
D23
D20
F12
E11
D10
A17

F17
F14
D19
B19
B21
C21
C20
B22

E21
D22
F21

C6
E19

Y4

W5
B24
G23
AE6

D4

Y8

D6

E5

D7
F11

F27
C27
E27
C26

PRESTONIA/NOCONA 604 PROCESSOR

4

PROC_0

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

AP0
AP1

BNR
BPRI
BR0
BR1
BR2
BR3
LOCK

ADSTB0
ADSTB1
ADS
REQ0
REQ1
REQ2
REQ3
REQ4

RS0
RS1
RS2
RSP
TRDY

BCLK0
BCLK1
LINT0
LINT1
SLP
STPCLK
RESET
INIT

IERR
MCERR
BINIT

A20M
SMI
FERR
IGNNE

REV. 1.5-EMTS, ZIF SKT

HETERO 1 OF 5

ADD1=ADD*_Y0363_SCREW
ADD2=ADD*_Y0363_SCREW
ADD3=ADD*_Y0363_SCREW
ADD4=ADD*_Y0363_SCREW
ADD5=ADD*_Y0363_SCREW
ADD6=ADD*_Y0363_SCREW
ADD7=ADD*_Y0363_SCREW
ADD8=ADD*_Y0363_SCREW

DSTBN0
DSTBN1
DSTBN2
DSTBN3
DSTBP0
DSTBP1
DSTBP2
DSTBP3

HITM

DEFER

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

HIT

H_A3

6,11

H_A4

6,11

H_A5

6,11

H_A6

6,11

Y26

D0

AA27

D1

Y24

D2

AA25

D3

AD27

D4

Y23

D5

AA24

D6

AB26

D7

AB25

D8

AB23

D9

AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
AD10
AD8
AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
AD7
AE7
AC6
AC5
AA8
Y9
AB6

AC18
AE19
AC15
AE17

Y21
Y18
Y15
Y12
Y20
Y17
Y14
Y11

A23
E22
C23

AC27
AD22
AE12
AB9
F18
E18

H_DSTBN0
H_DSTBN1
H_DSTBN2
H_DSTBN3
H_DSTBP0
H_DSTBP1
H_DSTBP2
H_DSTBP3

H_HITM
H_HIT
H_DEFER

H_DBI0
H_DBI1
H_DBI2
H_DBI3

H_DBSY
H_DRDY

H_D0
H_D1
H_D2
H_D3
H_D4
H_D5
H_D6
H_D7
H_D8

H_D9
H_D10
H_D11
H_D12
H_D13
H_D14
H_D15
H_D16
H_D17
H_D18
H_D19
H_D20
H_D21
H_D22
H_D23
H_D24
H_D25
H_D26
H_D27
H_D28
H_D29
H_D30
H_D31
H_D32
H_D33
H_D34
H_D35
H_D36
H_D37
H_D38
H_D39
H_D40
H_D41
H_D42
H_D43
H_D44
H_D45
H_D46
H_D47
H_D48
H_D49
H_D50
H_D51
H_D52
H_D53
H_D54
H_D55
H_D56
H_D57
H_D58
H_D59
H_D60
H_D61
H_D62
H_D63

H_DP0
H_DP1
H_DP2
H_DP3

6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11

6,12
6,12
6,12
6,12
6,12
6,12
6,12
6,12

6,11
6,11
6,11

6,11
6,11

Swizzled.

ADD1=ADD*_89JJP_SCREW2
ADD2=ADD*_89JJP_SCREW2
ADD3=ADD*_89JJP_SCREW2
ADD4=ADD*_89JJP_SCREW2
ADD5=ADD*_89JJP_SCREW2
ADD6=ADD*_89JJP_SCREW2
ADD7=ADD*_89JJP_SCREW2
ADD8=ADD*_89JJP_SCREW2

6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11

6,11
6,11

6,11
6,11

6,11

6,11

6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11
6,11

6,10
6,10
6,10
6,10

6,10,12

6,10

6,10
6,11

6,10
6,10
6,10
6,10

H_A7
H_A8
H_A9
H_A10
H_A11
H_A12
H_A13
H_A14
H_A15
H_A16
H_A17
H_A18
H_A19
H_A20
H_A21
H_A22
H_A23
H_A24
H_A25
H_A26
H_A27
H_A28
H_A29
H_A30
H_A31
H_A32
H_A33
H_A34
H_A35

H_AP0
H_AP1

H_BNR
H_BPRI
H_BREQ1

6

H_BREQ0
H_BREQ23_PU

6

H_BREQ23_PU

6

H_LOCK

H_ADSTB0
H_ADSTB1
H_ADS
H_REQ0
H_REQ1
H_REQ2
H_REQ3
H_REQ4

H_RS0
H_RS1
H_RS2
H_RSP
H_TRDY

CK_100M_CPU1_P

4

CK_100M_CPU1_N

4

H_INTR
H_NMI
H_SLP
H_STPCLK
H_RST
H_INIT

H1_IERR

10

H_MCERR
H_BINIT

H_A20M
H_SMI
H_FERR
H_IGNNE

A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13

A9

B8
E13
D12
C11

B7

A6

A7

C9

C8

E10

D9

F20
D23
D20
F12
E11
D10
A17

F17
F14
D19
B19
B21
C21
C20
B22

E21
D22
F21

C6
E19

Y4

W5
B24
G23
AE6

D4

Y8

D6

E5

D7
F11

F27
C27
E27
C26

PRESTONIA/NOCONA 604 PROCESSOR

SOURCE SYNC GROUP 1 - BUS_NAME=GTL1
SOURCE SYNC GROUP 2 - BUS_NAME=GTL2
SOURCE SYNC GROUP 3 - BUS_NAME=GTL3
SOURCE SYNC GROUP 4 - BUS_NAME=GTL4
SOURCE SYNC GROUP 5 - BUS_NAME=GTL5
SOURCE SYNC GROUP 6 - BUS_NAME=GTL6
GTL "WIRE-OR" SIGNALS - BUS_NAME=GTL_WIREOR
GTL COMMON CLOCK INPUT SIGNALS - BUS_NAME=GTL_INPUT
GTL COMMON CLOCK I/O SIGNALS - BUS_NAME=GTL_IO

PROC_1

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

AP0
AP1

BNR
BPRI
BR0
BR1
BR2
BR3
LOCK

ADSTB0
ADSTB1
ADS
REQ0
REQ1
REQ2
REQ3
REQ4

RS0
RS1
RS2
RSP
TRDY

BCLK0
BCLK1
LINT0
LINT1
SLP
STPCLK
RESET
INIT

IERR
MCERR
BINIT

A20M
SMI
FERR
IGNNE

REV. 1.5-EMTS, ZIF SKT

HETERO 1 OF 5

DSTBN0
DSTBN1
DSTBN2
DSTBN3
DSTBP0
DSTBP1
DSTBP2
DSTBP3

HITM

DEFER

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

HIT

Y26

D0

AA27

D1

Y24

D2

AA25

D3

AD27

D4

Y23

D5

AA24

D6

AB26

D7

AB25

D8

AB23

D9

AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
AD10
AD8
AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
AD7
AE7
AC6
AC5
AA8
Y9
AB6

AC18
AE19
AC15
AE17

Y21
Y18
Y15
Y12
Y20
Y17
Y14
Y11

A23
E22
C23

AC27
AD22
AE12
AB9
F18
E18

H_DSTBN0
H_DSTBN1
H_DSTBN2
H_DSTBN3
H_DSTBP0
H_DSTBP1
H_DSTBP2
H_DSTBP3

H_HITM
H_HIT
H_DEFER

H_DBI0
H_DBI1
H_DBI2
H_DBI3

H_DBSY
H_DRDY

H_D0
H_D1
H_D2
H_D3
H_D4
H_D5
H_D6
H_D7
H_D8

H_D9
H_D10
H_D11
H_D12
H_D13
H_D14
H_D15
H_D16
H_D17
H_D18
H_D19
H_D20
H_D21
H_D22
H_D23
H_D24
H_D25
H_D26
H_D27
H_D28
H_D29
H_D30
H_D31
H_D32
H_D33
H_D34
H_D35
H_D36
H_D37
H_D38
H_D39
H_D40
H_D41
H_D42
H_D43
H_D44
H_D45
H_D46
H_D47
H_D48
H_D49
H_D50
H_D51
H_D52
H_D53
H_D54
H_D55
H_D56
H_D57
H_D58
H_D59
H_D60
H_D61
H_D62
H_D63

H_DP0
H_DP1
H_DP2
H_DP3

6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11
6,11

6,11
6,11
6,11
6,11

6,12
6,12
6,12
6,12
6,12
6,12
6,12
6,12

6,11
6,11
6,11

6,11
6,11

ROOM=PROC_0

ROOM=LEVEL_TRANSLATION

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_1

ROOM=PROC_0

ROOM=PROC_0

ROOM=PROC_0

NACONA GUIDELINES RECOMMEND 47pF HERE
INSTEAD OF 27pF LIKE BOXSTER

AB

ASYNC LINES DRIVEN BY PROCESSORS

THERMTRIP--TERMINATE AT RECEIVER ONLY

FERR--TERMINATE BOTH ENDS OF LINE

VCORE

RB167

56.2-1%

RB185

56.2-1%

12

12

IERR--TERMINATED AT RECEIVER ONLY

H_FERR

Put RB424 close to PROC_0

6,10

Put RB411 close to LEVEL TRANSLATION

ASYNC LINES DRIVEN BY CHIPSET

RB168

12

301-1%

RB183

12

301-1%

RB189

12

301-1%

RB173

12

301-1%

RB233

12

301-1%

RB156

12

301-1%

RB170

12

301-1%

RB191

12

301-1%

RB219

12

301-1%

RB164

12

49.9-1%
RB192

12

49.9-1%
RB153

12

49.9-1%
RB155

12

49.9-1%

H_A20M

H_IGNNE

H_SMI

SUB*_143MM

SUB TO 130 OHM

H_STPCLK

H_SLP

H_INIT

H_INTR

H_NMI

H_PWRGOOD

BREQ SIGNALS (NO ON-DIE TERMINATION)

H_BREQ1

H_BREQ0

H_BREQ23_PU

PLACEMENT NOT CRITICAL

6,10

6,10

6,10

6,10

6,10

6,10

6,10

6,10

7,47

BREQ1--TERMINATE AT EITHER END (DOESN'T GO TO CHIPSET)

6

BREQ0--TERMINATE AT END FARTHER FROM CHIPSET

6,11

BREQ23--LOCATION ISN'T CRITICAL

6

WIRED-OR SIGNALS AC TERM AT MIDDLE PROCESSOR

ROOM=PROC_1

CB294

47pF
50V-5%
CB293

47pF
50V-5%
CB292

47pF
50V-5%
CB297

47pF
50V-5%
CB289

47pF
50V-5%

21

21

21

21

21

RB145

12

40.2-1%

RB144

12

40.2-1%

RB143

12

40.2-1%

RB162

12

40.2-1%

RB146

12

40.2-1%

H_BINIT

H_BNR

H_HIT

H_HITM

H_MCERR

6,11

6,11

6,11

6,11

6,10

TERMINATION

PROCESSORS 1 & 2

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

DATE

9T576

2/26/2003

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

6 OF 51

2-26-2003_11:406EVERGLADES

1

2

3

4

A02-00

1

VCORE

21

R322

49.9-1%

R321

FOR NOCONA

SUB*_97604

12

VCORE

21

R314

R315

12

FOR NOCONA

SUB*_97604

100-1%100-1%

49.9-1%

SUB TO 84.5 OHM

SUB TO 84.5 OHM

12

CB371

12

CB321

1uF

10V-10%

1uF

CB322

10V-10%

H0_GTLREF01

CB363

21

0.1uF 16V

H0_GTLREF23

21

0.1uF 16V

21

CB359

CB320

0.1uF 16V

21

0.1uF 16V

21

CB370

21

CB323

7

0.1uF 16V

7

0.1uF 16V

NC_PROC0HS_3

NC_PROC0HS_4

CHANGED FOR NOCONA SUPPORT:

PIN A4 CONNECTED TO PIN C5
ADDED 50OHM PULL-UP TO PIN A15
CHANGED PIN C1 FROM GND TO 50OHM PULL-DOWN
CHANGED PIN G7 FROM GND TO NO CONNECT
CHANGED PIN AC30 FROM GND TO PU/PD OPTION
CHANGED CAPS ON WIRED-OR AC TERM FROM 27pF TO 47pF

--S HAYES 4/30/02

+3.3V_AUX

PROC0_HS

1

P1

2

P2

3

P3

45

MP1 MP2

SW PUSHBUTTON

SPDT

NP*

R319

12

8.2K-5%

GPI_PROC0_HS_PRES

NC_PROC0HS_5

PLACE THIS RESISTOR NEAR PROC_0

22,35,47

7,10

ITP_TDI_H0

B D

+3.3V

8.2K-5%

12

PERHAPS 3.3V WOULD BE BETTER HERE?

VCORE

RB193

150-1%

12

7

CPU_SMBALERT

7,22,35,47
7,22,35,47

RB215

H1_CPU_PRES
H0_CPU_PRES

+3.3V_AUX

RB166

RB174

12

12

8.2K-5%

8.2K-5%

ROOM=PROC_0 ROOM=PROC_1

CA

+3.3V_AUX

PROC1_HS

1

P1

NC_PROC1HS_3

NC_PROC1HS_4 NC_PROC1HS_5

3

P3

45

MP1 MP2

SW PUSHBUTTON

SPDT

NP*

R320

12

8.2K-5%

2

P2

GPI_PROC1_HS_PRES

22,35,47

VCORE

21

R324

R323

12

SUB*_97604

SUB TO 84.5 OHM

FOR NOCONA

VCORE

21

R316

R317

12

SUB*_97604

SUB TO 84.5 OHM

FOR NOCONA

49.9-1%100-1%

49.9-1%

100-1%

12

CB367

12

CB315

1uF

10V-10%

1uF

10V-10%

CB366

21

CB316

21

H1_GTLREF01

21

CB351

0.1uF 16V

0.1uF 16V

H1_GTLREF23

21

CB318

0.1uF 16V

21

CB355

21

CB317

0.1uF 16V

7

0.1uF 16V

7

0.1uF 16V

1

VCORE

21

1K-1%

RB172

On DIE term
enabled

2

SUB COMP TO 43.2 PER SERVERWORKS

X01 -- CHANGING BACK TO 49.9 TO IMPROVE MARGIN -swh10/18

Tsensor = 30h/31h

PI-ROM = A0h/A1h

3

VCORE

RB225

12

0-5%

SUB TO 0 OHM

RB224

12

0-5%

LB7

21

4.7uH 30mA

SUB*_7H671

LB4

4.7uH 30mA

SUB*_7H671

H0_CPU_TYPE

18

21

220

RB158

NP

RB218

12

49.9-1%

1K-1%

1K-1%

RB217

RB210

12

12

+80%-20%

22uF 10V

SUB*_3X016

CB408

12

12

CB401

SUB*_3X016

+80%-20%

22uF 10V

12

8.2K-5%

22uF 10V

CB402

12

12

CB407

22uF 10V

+80%-20%

SUB*_3X016

12

SUB 22uF CAPS ON BOTTOM
OF BOARD UNDER PROCESSORS
TO LOW-PROFILE VERSION

+3.3V_AUX

RB220

7,22,35,47

21

RB154

49.9-1%

CB386

21

0.1uF 16V
21

SUB*_3X016

+80%-20%

0.1uF 16V

CB385

4 4

10

6,7,47

10

7,21,37,46
7,21,37,46

7

7,10
7,10

7,10
7,10

7,10
7,10

10
7,10
7,10

4,7,12,22

H0_ODTEN
H0_PROCHOT
H_PWRGOOD
H0_CPU_PRES
H0_THERMTRIP

H0_COMP0
H0_COMP1

CPU_SMBALERT

7

ENV_SEG0_SCL
ENV_SEG0_SDA

H0_SM_EP_A012

H0_SM_TS_A01

GPO_SMB_WP

H_BPM02
H_BPM13

H_BPM4
H_BPM5

ITP_TCK
ITP_TDI_H0
ITP_TDO_H0
ITP_TMS
ITP_TRST

9,47
9,47
9,47
9,47
9,47

V_VID_H0_VCCA
NC_H0_VCCSENSE
H0_VSSA
NC_H0_VSSSENSE
V_VID_H0_VPLL

H0_GTLREF01

7

H0_GTLREF23

7

H0_TESTHI0

7

H0_TESTHI1

7

H0_TESTHI2

7

H0_TESTHI3

7

H0_TESTHI4

7

H0_TESTHI5

7

H0_TESTHI6

7

H0_THERM_D+

37

H0_THERM_D-

37

GPI_SYN_SEL100
NC_H0_RSVD77

+3.3V

H0_VID0
H0_VID1
H0_VID2
H0_VID3
H0_VID4

B5

ODTEN

B25

PROCHOT

AB7

PWRGOOD

A3

SKTOCC

F26

THRMTRIP

AD16

COMP0

E16

COMP1

AE29

SM_VCC_AE29

AE28

SM_VCC_AE28

AD28

SM_ALERT

AC28

SM_CLK

AC29

SM_DAT

AA29

SM_EP_A0

AB29

SM_EP_A1

AB28

SM_EP_A2

AA28

SM_TS1_A0

Y29

SM_TS1_A1

AD29

SM_WP

F6

BPM0

F8

BPM1

E7

BPM2

F5

BPM3

E8

BPM4

E4

BPM5

E24

TCK

C24

TDI

E25

TDO

A25

TMS

F24

TRST

F3

VID0

E3

VID1

D3

VID2

C3

VID3

B3

VID4

AB4

VCCA

B27

VCCSENSE

AA5

VSSA

D26

VSSSENSE

AD4

VCCIOPLL

W23

GTLREF0

W9

GTLREF1

F23

GTLREF2

F9

GTLREF3

W6

TESTHI0

W7

TESTHI1

W8

TESTHI2

Y6

TESTHI3

AA7

TESTHI4

AD5

TESTHI5

AE5

TESTHI6

Y27

THRM_ANODE

Y28

THRM_CATH

AE4

SMB_PRT

AA3

BSEL0

AB3

BSEL1

PRESTONIA/NOCONA 604 PROCESSOR

PROC_0

RSVD_A1

VCCVID/RSVD_A4

FORCEPR/RSVD_A15

RSVD_A16
RSVD_A26

VCCVIDLB/RSVD_C5

REV. 1.5-EMTS, ZIF SKT

HETERO 2 OF 5

RSVD_B1

RSVD_D25

RSVD_W3

RSVD_Y3
RSVD_AC1
RSVD_AD1

RSVD_AE15
RSVD_AE16

A1
A4
A15
A16
A26
B1
C5
D25
W3
Y3
AC1
AD1
AE15
AE16

VCORE

NC_H0_RSVD1
H0_VCCVIDLOOP
H0_FORCEPR
NC_H0_RSVD4
NC_H0_RSVD5
NC_H0_RSVD8

NC_H0_RSVD17
NC_H0_RSVD89
NC_H0_RSVD66
NC_H0_RSVD80
NC_H0_RSVD83
NC_H0_RSVD87
NC_H0_RSVD88

RB200

12

SUB*_6610C

1K-1%
RB197

12

SUB*_6610C

1K-1%
RB194

12

SUB*_6610C

1K-1%
RB205

12

SUB*_6610C

1K-1%
RB206

12

SUB*_6610C

1K-1%
RB231

12

SUB*_6610C

1K-1%
RB232

12

SUB*_6610C

1K-1%

H0_TESTHI0

H0_TESTHI1

H0_TESTHI2

H0_TESTHI3

H0_TESTHI4

H0_TESTHI5

H0_TESTHI6

7

7

7

7

7

7

7

VCORE

21

RB147

49.9-1%

X01 -- CHANGING BACK TO 49.9 TO IMPROVE MARGIN -swh10/18

SUB COMP TO 43.2 PER SERVERWORKS

Tsensor = 32h/33h

PI-ROM = A2h/A3h

VCORE

RB222

12

0-5%

RB223

12

0-5%

LB5

21

4.7uH 30mA

SUB*_7H671

LB6

4.7uH 30mA

SUB*_7H671

H1_CPU_TYPE

18

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

VCORE

21

NP

RB165

On DIE term disabled

RB175

1K-1% 1K-1%

12

RB208

12

RB207

12

SUB*_3X016

CB405

12

SUB*_3X016

+80%-20%

22uF 10V

8.2K-5%

21

RB221

+80%-20%

22uF 10V

CB393

12

12

CB406

22uF 10V

+3.3V

100-1% 1K-1%

+80%-20%

22uF 10V

SUB*_3X016

12

CB394

12

SUB 22uF CAPS ON BOTTOM
OF BOARD UNDER PROCESSORS
TO LOW-PROFILE VERSION

+3.3V_AUX

RB230

12

7,22,35,47

R318

12

49.9-1%

CB381

21

0.1uF 16V
21

SUB*_3X016

+80%-20%

6,7,47

7,21,37,46

49.9-1%
7,21,37,46

0.1uF 16V

CB382

4,7,12,22

H1_ODTEN
H1_PROCHOT

10

H_PWRGOOD
H1_CPU_PRES
H1_THERMTRIP

10

H1_COMP0
H1_COMP1

CPU_SMBALERT

7

ENV_SEG0_SCL
ENV_SEG0_SDA

H1_SM_PR_A1
H1_SM_PR_A2
H1_SM_TS_A0

NC_H1_SM_TS_A1

7

H_BPM02

7,10

H_BPM13

7,10

H_BPM4

7,10

H_BPM5

7,10

ITP_TCK

7,10

ITP_TDI_H1

10

ITP_TDO_H1

10

ITP_TMS

7,10

ITP_TRST

7,10

9,47
9,47
9,47
9,47
9,47

V_VID_H1_VCCA
NC_H1_VCCSENSE
H1_VSSA
NC_H1_VSSSENSE
V_VID_H1_VPLL

H1_GTLREF01

7

H1_GTLREF23

7

H1_TESTHI0

7

H1_TESTHI1

7

H1_TESTHI2

7

H1_TESTHI3

7

H1_TESTHI4

7

H1_TESTHI5

7

H1_TESTHI6

7

H1_THERM_D+

37

H1_THERM_D-

37

GPI_SYN_SEL100
NC_H1_RSVD77

+3.3V

H1_SM_EP_A0

GPO_SMB_WP

H1_VID0
H1_VID1
H1_VID2
H1_VID3
H1_VID4

B5

ODTEN

B25

PROCHOT

AB7

PWRGOOD

A3

SKTOCC

F26

THRMTRIP

AD16

COMP0

E16

COMP1

AE29

SM_VCC_AE29

AE28

SM_VCC_AE28

AD28

SM_ALERT

AC28

SM_CLK

AC29

SM_DAT

AA29

SM_EP_A0

AB29

SM_EP_A1

AB28

SM_EP_A2

AA28

SM_TS1_A0

Y29

SM_TS1_A1

AD29

SM_WP

F6

BPM0

F8

BPM1

E7

BPM2

F5

BPM3

E8

BPM4

E4

BPM5

E24

TCK

C24

TDI

E25

TDO

A25

TMS

F24

TRST

F3

VID0

E3

VID1

D3

VID2

C3

VID3

B3

VID4

AB4

VCCA

B27

VCCSENSE

AA5

VSSA

D26

VSSSENSE

AD4

VCCIOPLL

W23

GTLREF0

W9

GTLREF1

F23

GTLREF2

F9

GTLREF3

W6

TESTHI0

W7

TESTHI1

W8

TESTHI2

Y6

TESTHI3

AA7

TESTHI4

AD5

TESTHI5

AE5

TESTHI6

Y27

THRM_ANODE

Y28

THRM_CATH

AE4

SMB_PRT

AA3

BSEL0

AB3

BSEL1

PRESTONIA/NOCONA 604 PROCESSOR

PROC_1

VCCVID/RSVD_A4

FORCEPR/RSVD_A15

VCCVIDLB/RSVD_C5

REV. 1.5-EMTS, ZIF SKT

HETERO 2 OF 5

RSVD_A1

RSVD_A16
RSVD_A26

RSVD_B1

RSVD_D25

RSVD_W3

RSVD_Y3
RSVD_AC1
RSVD_AD1

RSVD_AE15
RSVD_AE16

A1
A4
A15
A16
A26
B1
C5
D25
W3
Y3
AC1
AD1
AE15
AE16

VCORE

NC_H1_RSVD1
H1_VCCVIDLOOP
H1_FORCEPR
NC_H1_RSVD4
NC_H1_RSVD5
NC_H1_RSVD8

NC_H1_RSVD17
NC_H1_RSVD89
NC_H1_RSVD66
NC_H1_RSVD80
NC_H1_RSVD83
NC_H1_RSVD87
NC_H1_RSVD88

RB198

12

H1_TESTHI0

SUB*_6610C

1K-1%
RB196

12

H1_TESTHI1

SUB*_6610C

1K-1%
RB195

12

H1_TESTHI2

SUB*_6610C

1K-1%
RB203

12

H1_TESTHI3

SUB*_6610C

1K-1%
RB209

12

H1_TESTHI4

SUB*_6610C

1K-1%
RB216

12

H1_TESTHI5

SUB*_6610C

1K-1%
RB213

12

H1_TESTHI6

SUB*_6610C

1K-1%

VCORE

21

RB163

49.9-1%

7

7

7

7

7

7

7

PROCESSORS 1 & 2

CPU-- Misc. & RSVD

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

DC

AUSTIN,TEXAS

REV.

SHEET

7 OF 51

2-26-2003_11:407EVERGLADES

A02-00

2

3

B D

0

_

L6
L8
L24
L26
L28
L30
M1
M3
M5
M7
M9
M23
M25
M27
M29
M31
N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y10
Y16
Y22
Y30

Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AC30
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

VCOREVCORE

PROC_1

VSS_A5
VSS_A11
VSS_A21
VSS_A27
VSS_A29
VSS_A31
VSS_B2
VSS_B9
VSS_B15
VSS_B17
VSS_B23
VSS_B28
VSS_B30
VSS/TESTLOW
VSS_C7
VSS_C13
VSS_C19
VSS_C25
VSS_C29
VSS_C31
VSS_D2
VSS_D5
VSS_D11
VSS_D21
VSS_D27
VSS_D28
VSS_D30
VSS_E1
VSS_E9
VSS_E15
VSS_E17
VSS_E23
VSS_E29
VSS_E31
VSS_F2
VSS_F7
VSS_F13
VSS_F19
VSS_F25
VSS_F28
VSS_F30
VSS_G1
VSS_G3
VSS_G5
VSS/BOOTSEL
VSS_G9
VSS_G25
VSS_G27
VSS_G29
VSS_G31
VSS_H2
VSS_H4
VSS_H6
VSS_H8
VSS_H24
VSS_H26
VSS_H28
VSS_H30
VSS_J1
VSS_J3
VSS_J5
VSS_J7
VSS_J9
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_K2
VSS_K4
VSS_K6
VSS_K8
VSS_K24
VSS_K26
VSS_K28
VSS_K30
VSS_L1
VSS_L3
VSS_L5

REV. 1.5-EMTS, ZIF SKT

HETERO 4 OF 5

VSS_L7

VSS_L9
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31

VSS_M2

VSS_M4

VSS_M6

VSS_M8
VSS_M24
VSS_M26
VSS_M28
VSS_M30

VSS_N2

VSS_N4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13

L7
L9
L23
L25
L27
L29
L31
M2
M4
M6
M8
M24
M26
M28
M30
N2
N4
N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13

VCORE

+80%-20%

+80%-20%

SUB*_3X016

SUB*_3X016

22uF 10V

22uF 10V

CB291

12

VCORE

+80%-20%

22uF 10V

CB365

12

SUB 22uF CAPS ON BOTTOM
OF BOARD UNDER PROCESSORS
TO LOW-PROFILE VERSION 3X016

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

12

C373

+80%-20%

22uF 10V

CB348

12

SUB*_3X016

+80%-20%

22uF 10V

SUB*_3X016

+80%-20%

22uF 10V

SUB*_3X016

VCORE

RB226

H1_SLEWCTL

RB227

A5
A11
A21
A27
A29
A31

B2

B9
B15
B17
B23
B28
B30

C1

H1_C1

21

RB176

NC_H1_BS

21

12

C7
C13
C19
C25
C29

49.9-1%
C31

D2

D5
D11
D21
D27
D28
D30

E1

E9
E15
E17
E23
E29
E31

F2

F7
F13
F19
F25
F28
F30

G1

G3

G5

G7

G9
G25
G27
G29
G31

H2

H4

H6

H8
H24
H26
H28
H30

J1

J3

J5

J7

J9
J23
J25
J27
J29
J31

K2

K4

K6

K8
K24
K26
K28
K30

L1

L3

L5

PRESTONIA/NOCONA 604 PROCESSOR

49.9-1%0-5%
NP*

VCOREVCORE

PROC_0

A2

VCC_A2

A8

VCC_A8

A14

VCC_A14

A18

VCC_A18

A24

VCC_A24

A28

VCC_A28

A30

VCC_A30

1

2

3

B4

VCC_B4

B6

VCC_B6

B12

VCC_B12

B20

VCC_B20

B26

VCC_B26

B29

VCC_B29

B31

VCC_B31

C2

VCC_C2

C4

VCC_C4

C10

VCC_C10

C16

VCC_C16

C22

VCC_C22

C28

VCC_C28

C30

VCC_C30

D1

VCC_D1

D8

VCC_D8

D14

VCC_D14

D18

VCC_D18

D24

VCC_D24

D29

VCC_D29

D31

VCC_D31

E2

VCC_E2

E6

VCC_E6

E12

VCC_E12

E20

VCC_E20

E26

VCC_E26

E28

VCC_E28

E30

VCC_E30

F1

VCC_F1

F4

VCC_F4

F10

VCC_F10

F16

VCC_F16

F22

VCC_F22

F29

VCC_F29

F31

VCC_F31

G2

VCC_G2

G4

VCC_G4

G6

VCC_G6

G8

VCC_G8

G24

VCC_G24

G26

VCC_G26

G28

VCC_G28

G30

VCC_G30

H1

VCC_H1

H3

VCC_H3

H5

VCC_H5

H7

VCC_H7

H9

VCC_H9

H23

VCC_H23

H25

VCC_H25

H27

VCC_H27

H29

VCC_H29

H31

VCC_H31

J2

VCC_J2

J4

VCC_J4

J6

VCC_J6

J8

VCC_J8

J24

VCC_J24

J26

VCC_J26

J28

VCC_J28

J30

VCC_J30

K1

VCC_K1

K3

VCC_K3

K5

VCC_K5

K7

VCC_K7

K9

VCC_K9

K23

VCC_K23

K25

VCC_K25

K27

VCC_K27

K29

VCC_K29

K31

VCC_K31

L2

VCC_L2

L4

VCC_L4

PRESTONIA/NOCONA 604 PROCESSOR

REV. 1.5-EMTS, ZIF SKT

VCORE

HETERO 3 OF 5

PROC_0

AA1

VCC_AA1

AA4

VCC_AA4

AA6

VCC_AA6

AA12

VCC_AA12

AA20

VCC_AA20

AA26

VCC_AA26

AA31

VCC_AA31

AB2

VCC_AB2

AB8

VCC_AB8

AB14

VCC_AB14

AB18

VCC_AB18

AB24

VCC_AB24

AB30

VCC_AB30

SCHEM,PLNR,PE1750,2XCPU

AC3

VCC_AC3

AC4

VCC_AC4

AC10

VCC_AC10

AC16

VCC_AC16

AC22

VCC_AC22

AC31

VCC_AC31

AD2

VCC_AD2

AD6

VCC_AD6

4 4

AD12

VCC_AD12

AD20

VCC_AD20

AD26

VCC_AD26

AD30

VCC_AD30

AE3

VCC_AE3

AE8

VCC_AE8

AE14

VCC_AE14

AE18

VCC_AE18

AE24

VCC_AE24

PRESTONIA/NOCONA 604 PROCESSOR

REV. 1.5-EMTS, ZIF SKT

ROOM=PROC_0

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC13
VSS_AC19
VSS_AC25

SLEWCTRL/VSS

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE11
VSS_AE21
VSS_AE27

HETERO 5 OF 5

VCC_L6

VCC_L8
VCC_L24
VCC_L26
VCC_L28
VCC_L30

VCC_M1

VCC_M3

VCC_M5

VCC_M7

VCC_M9
VCC_M23
VCC_M25
VCC_M27
VCC_M29
VCC_M31

VCC_N1

VCC_N3

VCC_N5

VCC_N7

VCC_N9
VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8
VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9
VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8
VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9
VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8
VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W1
VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y2
VCC_Y10
VCC_Y16
VCC_Y22
VCC_Y30

VSS_Y19
VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AB1
VSS_AB5

VSS_AC2
VSS_AC7

VSS_AD3
VSS_AD9

VSS_AE2

L6
L8
L24
L26
L28
L30
M1
M3
M5
M7
M9
M23
M25
M27
M29
M31
N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y10
Y16
Y22
Y30

Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AC30
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

A5
A11
A21
A27
A29
A31

B2

B9
B15
B17
B23
B28
B30

H0_C1

C1

21

RB184

NC_H0_BS

H0_SLEWCTL

C7
C13
C19
C25
C29

49.9-1%
C31

D2

D5
D11
D21
D27
D28
D30

E1

E9
E15
E17
E23
E29
E31

F2

F7
F13
F19
F25
F28
F30

G1

G3

G5

G7

G9
G25
G27
G29
G31

H2

H4

H6

H8
H24
H26
H28
H30

J1

J3

J5

J7

J9
J23
J25
J27
J29
J31

K2

K4

K6

K8
K24
K26
K28
K30

L1

L3

L5

PRESTONIA/NOCONA 604 PROCESSOR

VCORE

21

RB229

49.9-1%0-5%
NP*

RB228

12

PROC_0

VSS_A5
VSS_A11
VSS_A21
VSS_A27
VSS_A29
VSS_A31
VSS_B2
VSS_B9
VSS_B15
VSS_B17
VSS_B23
VSS_B28
VSS_B30
VSS/TESTLOW
VSS_C7
VSS_C13
VSS_C19
VSS_C25
VSS_C29
VSS_C31
VSS_D2
VSS_D5
VSS_D11
VSS_D21
VSS_D27
VSS_D28
VSS_D30
VSS_E1
VSS_E9
VSS_E15
VSS_E17
VSS_E23
VSS_E29
VSS_E31
VSS_F2
VSS_F7
VSS_F13
VSS_F19
VSS_F25
VSS_F28
VSS_F30
VSS_G1
VSS_G3
VSS_G5
VSS/BOOTSEL
VSS_G9
VSS_G25
VSS_G27
VSS_G29
VSS_G31
VSS_H2
VSS_H4
VSS_H6
VSS_H8
VSS_H24
VSS_H26
VSS_H28
VSS_H30
VSS_J1
VSS_J3
VSS_J5
VSS_J7
VSS_J9
VSS_J23
VSS_J25
VSS_J27
VSS_J29
VSS_J31
VSS_K2
VSS_K4
VSS_K6
VSS_K8
VSS_K24
VSS_K26
VSS_K28
VSS_K30
VSS_L1
VSS_L3
VSS_L5

REV. 1.5-EMTS, ZIF SKT

HETERO 4 OF 5

VSS_L7

VSS_L9
VSS_L23
VSS_L25
VSS_L27
VSS_L29
VSS_L31

VSS_M2

VSS_M4

VSS_M6

VSS_M8
VSS_M24
VSS_M26
VSS_M28
VSS_M30

VSS_N2

VSS_N4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13

L7
L9
L23
L25
L27
L29
L31
M2
M4
M6
M8
M24
M26
M28
M30
N2
N4
N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13

A B

A2

A8
A14
A18
A24
A28
A30

B4

B6
B12
B20
B26
B29
B31

C2

C4
C10
C16
C22
C28
C30

D1

D8
D14
D18
D24
D29
D31

E2

E6
E12
E20
E26
E28
E30

F1

F4
F10
F16
F22
F29
F31

G2

G4

G6

G8
G24
G26
G28
G30

H1

H3

H5

H7

H9
H23
H25
H27
H29
H31

J2

J4

J6

J8
J24
J26
J28
J30

K1

K3

K5

K7

K9
K23
K25
K27
K29
K31

L2

L4

PRESTONIA/NOCONA 604 PROCESSOR

VCORE

AA1
AA4
AA6

AA12
AA20
AA26
AA31

AB2
AB8

AB14
AB18
AB24
AB30

AC3
AC4

AC10
AC16
AC22
AC31

AD2
AD6

AD12
AD20
AD26
AD30

AE3
AE8

AE14
AE18
AE24

PRESTONIA/NOCONA 604 PROCESSOR

PROC_1

VCC_A2
VCC_A8
VCC_A14
VCC_A18
VCC_A24
VCC_A28
VCC_A30
VCC_B4
VCC_B6
VCC_B12
VCC_B20
VCC_B26
VCC_B29
VCC_B31
VCC_C2
VCC_C4
VCC_C10
VCC_C16
VCC_C22
VCC_C28
VCC_C30
VCC_D1
VCC_D8
VCC_D14
VCC_D18
VCC_D24
VCC_D29
VCC_D31
VCC_E2
VCC_E6
VCC_E12
VCC_E20
VCC_E26
VCC_E28
VCC_E30
VCC_F1
VCC_F4
VCC_F10
VCC_F16
VCC_F22
VCC_F29
VCC_F31
VCC_G2
VCC_G4
VCC_G6
VCC_G8
VCC_G24
VCC_G26
VCC_G28
VCC_G30
VCC_H1
VCC_H3
VCC_H5
VCC_H7
VCC_H9
VCC_H23
VCC_H25
VCC_H27
VCC_H29
VCC_H31
VCC_J2
VCC_J4
VCC_J6
VCC_J8
VCC_J24
VCC_J26
VCC_J28
VCC_J30
VCC_K1
VCC_K3
VCC_K5
VCC_K7
VCC_K9
VCC_K23
VCC_K25
VCC_K27
VCC_K29
VCC_K31
VCC_L2
VCC_L4

REV. 1.5-EMTS, ZIF SKT

HETERO 3 OF 5

VCC_L6

VCC_L8
VCC_L24
VCC_L26
VCC_L28
VCC_L30

VCC_M1

VCC_M3

VCC_M5

VCC_M7

VCC_M9
VCC_M23
VCC_M25
VCC_M27
VCC_M29
VCC_M31

VCC_N1

VCC_N3

VCC_N5

VCC_N7

VCC_N9
VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8
VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9
VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8
VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9
VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8
VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W1
VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y2
VCC_Y10
VCC_Y16
VCC_Y22
VCC_Y30

PROC_1

VSS_Y19

VCC_AA1
VCC_AA4
VCC_AA6
VCC_AA12
VCC_AA20
VCC_AA26
VCC_AA31
VCC_AB2
VCC_AB8
VCC_AB14
VCC_AB18
VCC_AB24
VCC_AB30
VCC_AC3
VCC_AC4
VCC_AC10
VCC_AC16
VCC_AC22
VCC_AC31
VCC_AD2
VCC_AD6
VCC_AD12
VCC_AD20
VCC_AD26
VCC_AD30
VCC_AE3
VCC_AE8
VCC_AE14
VCC_AE18
VCC_AE24

REV. 1.5-EMTS, ZIF SKT

ROOM=PROC_1

VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB1
VSS_AB5

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC2
VSS_AC7

VSS_AC13
VSS_AC19
VSS_AC25

SLEWCTRL/VSS

VSS_AD3
VSS_AD9

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE2

VSS_AE11
VSS_AE21
VSS_AE27

HETERO 5 OF 5

CA

VCORE

2.5V-20%-2STACK

12

680uF

+

VCORE

2.5V-20%-2STACK

12

680uF

+

+80%-20%

22uF 10V

CB311

12

12

C374

+80%-20%

22uF 10V

CB339

12

12

2.5V-20%-2STACK

680uF

+

C357

2.5V-20%-2STACK

680uF

+

C380

+80%-20%

22uF 10V

CB306

12

SUB*_3X016

+80%-20%

22uF 10V

12

C375

21

21

C307

+80%-20%

22uF 10V

SUB*_3X016

+80%-20%

22uF 10V

C376

SUB*_3X016

VCORE

12

CB304

2.5V-20%-2STACK

680uF

+

C390

21

2.5V-20%-2STACK

680uF

+

C393

21

VCORE

10V-10%

VCORE

10V-10%

VCORE

12

12

CB332

0.1uF 16V

0.1uF 16V

+80%-20%

22uF 10V

CB379

CB336

12

12

SUB*_3X016

+80%-20%

22uF 10V

CB380

12

12

SUB*_3X016

12

CB310

CB305

0.1uF 16V

0.1uF 16V

2.5V-20%-2STACK

680uF

C377

2.5V-20%-2STACK

680uF

C359

10V-10%

CB400

12

1uF

1uF

10V-10%

CB387

12

1uF

1uF

12

CB314

CB331

0.1uF 16V

+80%-20%

22uF 10V

12

SUB*_3X016

+80%-20%

22uF 10V

CB340

SUB*_3X016

12

CB377

0.1uF 16V

VCORE

0.1uF 16V

2.5V-20%-2STACK

680uF

+

+

CB334

12

12

C370

12

0.1uF 16V

+

C356

21

2.5V-20%-2STACK

680uF

+

C364

21

10V-10%

10V-10%

CB360

CB398

12

12

1uF

1uF

10V-10%

10V-10%

12

12

C387

C386

1uF

1uF

ROOM=PROC_0

ROOM=PROC_1

+80%-20%

CB309

12

22uF 10V

CB383

12

12

CB347

0.1uF 16V

22uF 10V

SUB*_3X016

+80%-20%

22uF 10V

SUB*_3X016

CB372

12

0.1uF 16V

0.1uF 16V

CB308

12

+80%-20%

22uF 10V

CB345

SUB*_3X016

+80%-20%

CB307

12

SUB*_3X016

12

CB378

0.1uF 16V

0.1uF 16V

21

CB29512CB298

2.5V-20%-2STACK

C354

21

2.5V-20%-2STACK

C355

21

10V-10%

12

C367

1uF

10V-10%

CB353

12

1uF

+80%-20%

22uF 10V

CB399

12

SUB*_3X016

+80%-20%

22uF 10V

CB344

12

SUB*_3X016

12

0.1uF 16V

0.1uF 16V
21

CB301

680uF

+

680uF

+

10V-10%

12

1uF

10V-10%

12

1uF

CB397

12

SUB*_3X016

+80%-20%

CB373

12

SUB*_3X016

12

C369

0.1uF 16V

0.1uF 16V

CB325

12

2.5V-20%-2STACK

C363

21

2.5V-20%-2STACK

C365

21

10V-10%

CB396

12

1uF

10V-10%

CB390

12

1uF

VCORE

12

CB346

VCORE

12

CB343

+80%-20%

22uF 10V

CB342

12

22uF 10V

CB389

12

12

CB312

680uF

+

21

680uF

+

21

10V-10%

CB303

12

C383

1uF

10V-10%

CB327

CB392

12

1uF

12

CB333

0.1uF 16V

0.1uF 16V

603 pkg

12

CB338

0.1uF 16V

0.1uF 16V

+80%-20%

22uF 10V

CB324

12

SUB*_3X016

+80%-20%

22uF 10V

CB356

12

SUB*_3X016

12

CB337

0.1uF 16V

0.1uF 16V

2.5V-20%-2STACK

680uF

+

C391

2.5V-20%-2STACK

680uF

+

C392

10V-10%

10V-10%

12

C382

1uF

1uF

10V-10%

10V-10%

CB375

12

1uF

1uF

12

CB341

CB335

0.1uF 16V

12

C385

CB329

0.1uF 16V

+80%-20%

22uF 10V

CB395

12

SUB*_3X016

+80%-20%

22uF 10V

CB391

12

SUB*_3X016

12

CB349

CB299

0.1uF 16V

ROOMS COMPLETE

2.5V-20%-2STACK

680uF

+

C362

21

2.5V-20%-2STACK

C379

21

CB361

12

680uF

C378

21

+

C358

21

ROOM=PROC_0

CB352

12

ROOM=PROC_1

12

0.1uF 16V

12

0.1uF 16V

+80%-20%

22uF 10V

SUB*_3X016

+80%-20%

22uF 10V

12

SUB*_3X016

12

0.1uF 16V

TITLE

DWG NO.

DATE

12

12

C366

12

CB326

+80%-20%

CB404

12

SUB*_3X016

+80%-20%

22uF 10V

CB388

SUB*_3X016

12

C371

CB362

0.1uF 16V

12

CB350

0.1uF 16V

22uF 10V

CB369

12

CB302

12

SUB*_3X016

12

CB313

0.1uF 16V

C368

0.1uF 16V

CB328

0.1uF 16V

+80%-20%

22uF 10V

SUB*_3X016

+80%-20%

22uF 10V

0.1uF 16V

EVERGLADES MB

9T576

2/26/2003

DC

ROOM=PROC_0

ROOM=PROC_1

12

12

C384

0.1uF 16V

12

12

CB354

0.1uF 16V

CB357

12

CB300

12

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

C381

12

12

CB358

0.1uF 16V

0.1uF 16V

12

CB330

0.1uF 16V

12

C388

0.1uF 16V

0.1uF 16V

0.1uF 16V

ROOM=PROC_

ROOM=PROC

REV.

A02-00

8 OF 51

2-26-2003_11:408EVERGLADES

1

2

3

B D

T

CA

ROOMS COMPLETE

+12V

L49

VRM1_+12V

9

1

9,47

9

+

C336

21

270uF

16V-20%

VRM1_+12V

9

NC_VRM1_5
VRM_VID3
NC_VRM1_9
VRM1_GND_SENSE

VCORE

2

NC_VRM1_51
VCORE_EN_1

47

VRM_VID0

9,47

VRM_VID4

9,47

VRM1_VCORE_SENSE

9

VRM1_GND_SENSE

3

9

12

+

C353

12

VIN+_1 VIN+_2

34

VIN+_3 VIN+_4

5

RSVD_1

78

VID3 VID1

9

RSVD_2

11

VO-SEN-

13 14

VO-_1 VO+_1

15 16

VO-_2 VO+_2

17 18

VO-_3 VO+_3

19 20

VO-_4 VO+_4

21 22

VO-_5 VO+_5

23 24

VO-_6 VO+_6

25 26

VO-_7 VO+_7

27 28

VO-_8 VO+_8

29

VO-_9

31

VO-_10

33

VO+_10

35

VO+_11 VO-_13

37

VO+_12

39

VO+_13

41

VO+_14

43

VO+_15

45

VO+_16

47

VO+_17

49

VO+_18

51

RSVD_4

53

OUTEN

55

VID0

57

VID4

59 60

VIN-_1 VIN-_2

61 62

VIN-_3 VIN-_4

MH1 MH2

MH1 MH2

VRM, 12V, 9.1, 1U

SUB*_2U299

VCORE

R299

12

0-5%
R309

21

0-5%

12

1uH 4.4A

12

270uF

16V-20%

1uH 4.4A

VRM1

KEY 6

PWRGD

RSVD_3

VO+_9
VO-_11
VO-_12

VO-_14
VO-_15
VO-_16
VO-_17
VO-_18
VO-_19
VO+_20

VO-SEN+

ISHARE

VID2

VRM-PRES

MS2MS1

9,35,47

L48

+3.3V

VCORE

R312

12

10
12

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

MS2MS1

0X621 IS ARTESYN
2U299 IS CELESTICA

VCORE

VCORE_PWRGOOD_1

X01:
CHANGING TO WEAKER PULL-UP (AT RAMESH'S REQUEST),
AND USING HYSTERESIS BUFFER TO KEEP EDGE AT CPLD FAST

--STUART 10/7/2002

+3.3V_AUX+3.3V_AUX

U30

3144

1K-5%

SUB*_69958

SUB TO 8.2K

R235

12

22-5%

VRM_VID1
VCORE_PWRGOOD_1_ATVRM
NC_VRM1_12

21

C361

1000pF

50V-10%

NP*

VRM1_VCORE_SENSE
VRM1_ISHARE
VRM_VID2
NC_VRM1_58 VRM_VID2

9

Q20

2N7002

VRM1_ISHARE

R311

12

D

3

1

G

S

2

9
9
9,47

220

R227

21

0-5%

21

C272

NP*

9,47

PLACE NEAR VRM PIN 52!

R313

12

0-5%

VRM1_OK

GREEN

VRM2_ISHARE

+3.3V

13

1000pF

50V-10%

1142

VHC14VHC14

U30

9

VCORE_PWRGOOD_1

9,35,47

9,35,47

9

NC_VRM2_5
VRM_VID3

9,47

NC_VRM2_9
VRM2_GND_SENSE

9

NC_VRM2_51
VCORE_EN_2

47

VRM_VID0

9,47

VRM_VID4

9,47

VCORE_PWRGOOD_2

VRM2_+12V

VCORE

Q18

2N7002

G

1

VRM2_+12V

9

12

VIN+_1 VIN+_2

34

VIN+_3 VIN+_4

5

RSVD_1

78

VID3 VID1

9

RSVD_2

11

VO-SEN-

13 14

VO-_1 VO+_1

15 16

VO-_2 VO+_2

17 18

VO-_3 VO+_3

19 20

VO-_4 VO+_4

21 22

VO-_5 VO+_5

23 24

VO-_6 VO+_6

25 26

VO-_7 VO+_7

27 28

VO-_8 VO+_8

29

VO-_9

31

VO-_10

33

VO+_10

35

VO+_11 VO-_13

37

VO+_12

39

VO+_13

41

VO+_14

43

VO+_15

45

VO+_16

47

VO+_17

49

VO+_18

51

RSVD_4

53

OUTEN

55

VID0

57

VID4

59 60

VIN-_1 VIN-_2

61 62

VIN-_3 VIN-_4

MH1 MH2

MH1 MH2

VRM, 12V, 9.1, 1U

SUB*_2U299

R281

12

220

D

3

S

2

VRM2_OK

GREEN

VRM2

VRM-PRES

KEY 6

PWRGD

RSVD_3

VO+_9
VO-_11
VO-_12

VO-_14
VO-_15
VO-_16
VO-_17
VO-_18
VO-_19
VO+_20

VO-SEN+

ISHARE

VID2

MS2MS1

+3.3V

13

12

C317

VCORE

10
12

30
32
34
36
38
40
42
44
46
48
50
52
54
56
58

MS2MS1

0X621 IS ARTESYN
2U299 IS CELESTICA

+

270uF

VCORE

+

C316

21

16V-20%

+3.3V

270uF

R301

1K-5%

SUB*_69958

SUB TO 8.2K

12

R236

12

22-5%

VRM_VID1
VCORE_PWRGOOD_2_ATVRM
NC_VRM2_12

VRM2_VCORE_SENSE
VRM2_ISHARE

NC_VRM2_58

VRM2_VCORE_SENSE

9

VRM2_GND_SENSE

9

16V-20%

21

C360

9148

1000pF

50V-10%

NP*

1uH 4.4A

1uH 4.4A

9
9
9,47

ROOM=VRM_P0

VRM1

VRM2

+12V

L43

21

L44

21

+3.3V_AUX+3.3V_AUX

1000pF

50V-10%

5146

U30

U30

R231

VHC14 VHC14

9,47

0-5%

21

21

C279

NP*

PLACE NEAR VRM PIN 52!

VCORE

R310

12

0-5%
R307

21

0-5%

ROOM=VRM_P1

VCORE_PWRGOOD_2

9,35,47

1

2

3

HS_HOLD_1

GND1

+3.3V

8.2K-5%

8.2K-5%

81

RNB59

8.2K-5%

8.2K-5%

63

RNB59

RNB5945RNB59

27

8.2K-5%
RB181

12

8.2K-5%
R57

12

8.2K-5%

8.2K-5%

54

RN336RN3

8.2K-5%

8.2K-5%

72

RN318RN3

4

+3.3V+3.3V

RN1136RN11

RN11

72

8.2K-5%

54

8.2K-5%

8.2K-5%

18

RN11

8.2K-5%

12

8.2K-5%

RB15

VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3
VRM_VID4

H0_VID3
H0_VID2
H0_VID1
H0_VID0
H0_VID4

H1_VID0
H1_VID1
H1_VID2
H1_VID3
H1_VID4

9,47
9,47
9,47
9,47
9,47

7,47
7,47
7,47
7,47
7,47

7,47
7,47
7,47
7,47
7,47

GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16

HEATSINK CLIP
DELL PN 52JXN

16 GND VIAS

HS_HOLD_3

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16

HEATSINK CLIP
DELL PN 52JXN

16 GND VIAS

HS_HOLD_2

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16

HEATSINK CLIP
DELL PN 52JXN

16 GND VIAS

HS_HOLD_4

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16

HEATSINK CLIP
DELL PN 52JXN

16 GND VIAS

ADD1=ADD*_0W836_BRCKT

ADD2=ADD*_4W001_BUMPER

PLASTIC HEATSINK HOLDERS

ROOM=PWRGOOD_CPLD

VID SIGNAL PULL-UPS

AB

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

575EM is VRM 9.0 keyed with no latches
7G715 is VRM 9.1 keyed with latches
5F852 is VRM 9.1 keyed with latches
00JDV is VRM 9.0 keyed with latches

DELL USES VRM9.0 KEYING FOR VRMS EVEN IN VRM9.1 APPLICA

Core VRMs

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

DC

AUSTIN,TEXAS

REV.

SHEET

9 OF 51

2-26-2003_11:409EVERGLADES

A02-00

4

B D

CA

ROOMS COMPLETE

VCORE

21

C337

12

1

7,10
7,10

7,10
7,10
6,12

1uF

C338

12

10V-10%

0.1uF 16V

H_BPM02
H_BPM13

H_BPM4
H_BPM5
H_RST

CK_100M_ITP_P

4

CK_100M_ITP_N

4

R266

R267

12

49.9-1%

40.2-1%

R265

12

40.2-1%

SUB*_6610C

SUB*_6610C

ITP PORT

R268

R269

12

12

40.2-1%

40.2-1%

1

SUB*_6610C

SUB*_6610C

(BPM5DR#)

(FBO)

34
56
78

9
11 12
13 14
15 16
17 18
19
21 22
23
25

2MM SMT

P2

K

KEY 26

+3.3V

R286

ROOM=ITP

R290

40.2-1%

12

2

10

ITP_FBI

20

ITP_PWR
24
26

21

21

560

R289

R288

12

1.5K-1%

C346

12

27-5%

0.1uF 16V

R285

75-1%

12

21

R287

220

NP

R291

1.5K-5%

12

NC_ITP_DBA
ITP_DBR

ITP_TDI_H0
ITP_TMS
ITP_TRST
ITP_TCK

ITP_TDO_H1
NC_ITP_26_KEY

47

7
7
7
7

7,10

VCORE

FOR JTDO:

PROC_0 PROC_1

TDI

Install 1-2 for TWO processor system
Install 2-3 for UNI processor system

(UNI-PROCESSOR IS WITH PROC_0 INSTALLED ONLY!)

ITP_TDO_H0

ITP_TDI_H1

JTDO

1

2

TDI

ITP_TDI_H0

1

3

RB160

150-1%

12

1

ITP_TDI_H1
ITP_TDO_H0

+3.3V

21

RB186

3

2

2

J2

3

VCORE

56.2-1%

H0_IERR

6

1K-1%

CSB_FERR_3V

ITP_TDO_H1

12

RB150

RB149

2.7K-5%

VCORE

12

56.2-1%
RB171

VCORE

CHANGED TRST# PULLDOWN TO 560 OHMS

2

3

4

FROM 150 OHMS, PER ITP700 DESIGN GUIDE VER 1.20

--S HAYES 4/30/2002

SUBBED BPM TERM TO 50 OHMS

--S HAYES 6/26/02

+3.3V

H0_THERMTRIP

7

H1_THERMTRIP

7

H_MCERR

6

VCORE

56.2-1%

12

VCORE

56.2-1%

12

VCORE

21

R305

RB190

RB188

2.7K-5%

RB180

RB179

12

2.7K-5%

150-1%

R306

12

2.7K-5%

3904

21

QB8

QB5

3904

1

1

3904

+3.3V

Q19

1

21

RB187

RB177

12

1K-1%

H0_THERMTRIP_3V

3

2

1K-1%

H1_THERMTRIP_3V

3

2

+3.3V

R357

12

2.7K-5%

GPE_MCERR

3

2

47

47

18

7,10
7,10

7,10
7,10

H1_PROCHOT

7

H_BPM02
H_BPM13

H_BPM4
H_BPM5

H0_PROCHOT

7

54

RNBB1

VCORE

21

RB161

12

2.7K-5%

RNBB1

18

39 OHM-5%

SUB*_389YV

VCORE

RB169

12

2.7K-5%

56.2-1%

3904

RB148

72

RNBB1

RNBB1

36

39 OHM-5%

SUB*_389YV

THESE SHOULD BE PLACED AT FAR END
OF THESE LINES (AWAY FROM ITP CONNECTOR)

39 OHM-5%

SUB*_389YV

39 OHM-5%

SUB*_389YV

ROOM=PROC_1

+3.3V

21

1K-1%

QB3

3904

1

21

+3.3V

1K-1%

RB159

12

H1_PROCHOT_3V

3

2

RB151

H0_PROCHOT_3V

3

2

H_FERR

6

35

35

RB178

2.7K-5%

56.2-1%

RB152

QB1

1

3904

21

H1_IERR

6

QB7

1

V1

+3.3V

QB2

3904

1

21

RB157

12

2.7K-5%

3904

RB182

12

2.7K-5%

7
7
7,10

R430

12

2.7K-5%

3

+3.3V

2

R436

QB4

3904

1

+3.3V

RB333

12

QB6

3

1

2

GPE_IERR1

12

2.7K-5%

GPE_IERR0

3

2

1K-1%

CSB_FERR_3V

18,35

TDO

TDO

2

ITP ROUTING DRAWING

ITP_TD0_H1

+3.3V

SUB*_22327

SUB TO 1K

RB284

4.7K

21

CSB_SMI_OUT

18

CSB_STPCLK_3V

18

CSB_SLP_3V

18

18,35

2.2K-5%

A20M_3V

18

INTR_3V

18

IGNNE_3V

18

NMI_3V

18

18

11,18,22

P_INIT

+3.3V

2.2K-5%

12

12

RB290

RB304

1K-5%

RB293

21

NP*

2.2K-5%

12

RB28921RB297

+2.5V

12

1K-5%

R435

NP*

56

7407

RB305

12

0-5%

R429

12

0-5%

2.2K-5%

7407

7407

7407

12

7407

RB322

1K-5%

12

98

7407

U51

U51

U51

U51

U51

U51

SIGNAL LEVEL TRANSLATION -- PROCESSOR INPUTS

ROOM=LEVEL_TRANSLATION

H_SMI

H_STPCLK

H_SLP

1011

H_A20M

1213

H_INTR

43

H_IGNNE

H_NMI

PROCESSOR SIDE PULL-UPS
ARE ON PAGE 6

H_INIT

6

6

6

6

6

6

6

6

3

4

ROOM=LEVEL_TRANSLATION

SIGNAL LEVEL TRANSLATION -- PROCESSOR OUTPUTS

AB

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

AUSTIN,TEXAS

DC

SHEET

10 OF 51

REV.

A02-00

2-26-2003_11:4110EVERGLADES

ROOM=CMIC (FOR THE CMIC CHIP ITSELF)

B D

CA

U_CMIC

A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7

A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7

A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7

A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7

A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7

A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7

A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7

A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7

A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7

A_DQS0_0
A_DQS0_1

A_DQS1_0
A_DQS1_1

A_DQS2_0
A_DQS2_1

A_DQS3_0
A_DQS3_1

A_DQS4_0
A_DQS4_1

A_DQS5_0
A_DQS5_1

A_DQS6_0
A_DQS6_1

A_DQS7_0
A_DQS7_1

A_DQS8_0
A_DQS8_1

ACKE
BCKE

REMC

B_SD0_0
B_SD0_1
B_SD0_2
B_SD0_3
B_SD0_4
B_SD0_5
B_SD0_6
B_SD0_7

B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7

B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7

B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7

B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7

B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7

B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7

B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7

B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7

B_DQS0_0
B_DQS0_1

B_DQS1_0
B_DQS1_1

B_DQS2_0
B_DQS2_1

B_DQS3_0
B_DQS3_1

B_DQS4_0
B_DQS4_1

B_DQS5_0
B_DQS5_1

B_DQS6_0
B_DQS6_1

B_DQS7_0
B_DQS7_1

B_DQS8_0
B_DQS8_1

HETERO 3 OF 6

SYMBOL PROBLEM:

PIN P1 IS B_DQS5_0
PIN P3 IS B_DQS5_1
PIN R10 IS B_DQS6_0
PIN U2 IS B_DQS6_1

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

RAS
CAS

WE

Y20
AA21
AA19
V17
V18
Y19
AB20
Y18

AF22
AE21
Y17
V16
AE22
AE20
AC18
AE18

AF16
AF15
AC15
AB14
AG16
AG15
AD14
Y15

AA13
AD13
AC12
AG9
V13
AE12
AF10
AG7

AB4
AB2
AA1
T8
AA3
AA2
Y1
AA5

P8
R3
P5
J8
P10
N2
N5
N6

W3
V1
T2
T1
T6
U4
R7
R8

M1
J1
M5
L10
K1
L2
M6
M8

AD9
AD8
AG4
AD7
V12
Y12
AE7
AG3

AA20
AB21

AF20
AE19

AE15
AD15

AG11
AG10

AA4
Y5

R10

U2

P1
P3

L4
M7

AC9
AF6

AC1
W8
AB1

R_B_SD0_0
R_B_SD0_1
R_B_SD0_2
R_B_SD0_3
R_B_SD0_4
R_B_SD0_5
R_B_SD0_6
R_B_SD0_7

R_B_SD1_0
R_B_SD1_1
R_B_SD1_2
R_B_SD1_3
R_B_SD1_4
R_B_SD1_5
R_B_SD1_6
R_B_SD1_7

R_B_SD2_0
R_B_SD2_1
R_B_SD2_2
R_B_SD2_3
R_B_SD2_4
R_B_SD2_5
R_B_SD2_6
R_B_SD2_7

R_B_SD3_0
R_B_SD3_1
R_B_SD3_2
R_B_SD3_3
R_B_SD3_4
R_B_SD3_5
R_B_SD3_6
R_B_SD3_7

R_B_SD4_0
R_B_SD4_1
R_B_SD4_2
R_B_SD4_3
R_B_SD4_4
R_B_SD4_5
R_B_SD4_6
R_B_SD4_7

R_B_SD5_0
R_B_SD5_1
R_B_SD5_2
R_B_SD5_3
R_B_SD5_4
R_B_SD5_5
R_B_SD5_6
R_B_SD5_7

R_B_SD6_0
R_B_SD6_1
R_B_SD6_2
R_B_SD6_3
R_B_SD6_4
R_B_SD6_5
R_B_SD6_6
R_B_SD6_7

R_B_SD7_0
R_B_SD7_1
R_B_SD7_2
R_B_SD7_3
R_B_SD7_4
R_B_SD7_5
R_B_SD7_6
R_B_SD7_7

R_B_SD8_0
R_B_SD8_1
R_B_SD8_2
R_B_SD8_3
R_B_SD8_4
R_B_SD8_5
R_B_SD8_6
R_B_SD8_7

R_B_DQS0_0
R_B_DQS0_1

R_B_DQS1_0
R_B_DQS1_1

R_B_DQS2_0
R_B_DQS2_1

R_B_DQS3_0
R_B_DQS3_1

R_B_DQS4_0
R_B_DQS4_1

R_B_DQS6_0
R_B_DQS6_1

R_B_DQS5_0
R_B_DQS5_1

R_B_DQS7_0
R_B_DQS7_1

R_B_DQS8_0
R_B_DQS8_1

MRAS

MCAS

MWE

12 OHM-5%12 OHM-5%

36RNB4

12 OHM-5%

45RNB1

12 OHM-5%

27RNB4

12 OHM-5%

45RNB7

12 OHM-5%

45RNB11

12 OHM-5%

27RNB7

12 OHM-5%

27RNB9

12 OHM-5%

18RNB11

12 OHM-5%

18RNB14

12 OHM-5%

27RNB11

12 OHM-5%

36RNB16

12 OHM-5%

45RNB18

12 OHM-5%

18RNB20

12 OHM-5%

36RNB18

12 OHM-5%

27RNB20

12 OHM-5%

45RNB37

12 OHM-5%

36RNB39

12 OHM-5%

36RNB37

12 OHM-5%

18RNB39

12 OHM-5%

27RNB42

12 OHM-5%

45RNB46

12 OHM-5%

18RNB42

12 OHM-5%

27RNB46

12 OHM-5%

45RNB48

12 OHM-5%

18RNB50

12 OHM-5%

27RNB48

12 OHM-5%

36RNB50

12 OHM-5%

18RNB52

12 OHM-5%

36RNB55

12 OHM-5%

27RNB52

12 OHM-5%

18RNB54

12 OHM-5%

45RNB24

12 OHM-5%

45RNB28

12 OHM-5%

27RNB22

12 OHM-5%

36RNB28

12 OHM-5%

18RNB1

12 OHM-5%

18RNB7

12 OHM-5%

36RNB14

12 OHM-5%

45RNB20

12 OHM-5%

45RNB39

12 OHM-5%

27RNB50

12 OHM-5%

18RNB44

12 OHM-5%

45RNB55

12 OHM-5%

27RNB24

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

RB89

12 OHM 5%

RB92

12 OHM 5%

36

RNB29

45

RNB29

45

RNB34

36 RNB34

21

21

27RNB1

12 OHM-5%

45RN9

12 OHM-5%

36RNB1

12 OHM-5%

18RNB4

12 OHM-5%

36RN6338

12 OHM-5%

36RNB11

12 OHM-5%

45RNB9

12 OHM-5%

18RNB9

12 OHM-5%

45RNB14

12 OHM-5%

27RNB16

12 OHM-5%

27RNB14

12 OHM-5%

18RNB16

12 OHM-5%

27RNB18

12 OHM-5%

45RNB22

12 OHM-5%

18RNB18

12 OHM-5%

36RNB22

12 OHM-5%

27RNB37

12 OHM-5%

45RNB42

12 OHM-5%

18RNB37

12 OHM-5%

36RNB42

12 OHM-5%

45RNB44

12 OHM-5%

36RNB46

12 OHM-5%

36RNB44

12 OHM-5%

18RNB46

12 OHM-5%12 OHM-5%

36RNB48

12 OHM-5%

36RNB52

12 OHM-5%

18RNB48

12 OHM-5%

45RNB52

12 OHM-5%

36RNB54

12 OHM-5%

18RNB55

12 OHM-5%

45RNB54

12 OHM-5%

27RNB55

12 OHM-5%

36RNB24

12 OHM-5%

27RNB28

12 OHM-5%

18RNB22

12 OHM-5%

18RNB28

12 OHM-5%

45RNB4

12 OHM-5%

36RNB9

12 OHM-5%

45RNB16

12 OHM-5%

36RNB20

12 OHM-5%

27RNB39

12 OHM-5%

45RNB50

12 OHM-5%

27RNB44

12 OHM-5%

27RNB54

12 OHM-5%

18RNB24

12 OHM-5%

X_MRAS

Y_MRAS

X_MCAS

Y_MCAS

X_MWE

Y_MWE

B_SD0_0
B_SD0_1
B_SD0_2
B_SD0_3

B_SD0_4
B_SD0_5

B_SD0_6
B_SD0_7

B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7

B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7

B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7

B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7

B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7

B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7

B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7

B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7

B_DQS0_0
B_DQS0_1

B_DQS1_0
B_DQS1_1

B_DQS2_0
B_DQS2_1

B_DQS3_0
B_DQS3_1

B_DQS4_0
B_DQS4_1

B_DQS6_0
B_DQS6_1

B_DQS5_0
B_DQS5_1

B_DQS7_0
B_DQS7_1

B_DQS8_0
B_DQS8_1

14,16

15,16

14,16

15,16

14,16

15,16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

A1

GND_1

A27

GND_2

B5

GND_3

B6

GND_4

B10

GND_5

B11

GND_6

B14

GND_7

C17

GND_8

C18

GND_9

C25

GND_10

D5

GND_11

D6

GND_12

D10

GND_13

D11

GND_14

D14

GND_15

D21

GND_16

D23

GND_17

D25

GND_18

E2

GND_19

E17

GND_20

E18

GND_21

E22

GND_22

E24

GND_23

F10

GND_24

F11

GND_25

F14

GND_26

G7

GND_27

G17

GND_28

G18

GND_29

G26

GND_30

J2

GND_31

J4

GND_32

J6

GND_33

J7

GND_34

J9

GND_35

J11

GND_36

J13

GND_37

J15

GND_38

J17

GND_39

J19

GND_40

J21

GND_41

J23

GND_42

J25

GND_43

K2

GND_44

K4

GND_45

K6

GND_46

K16

GND_47

K21

GND_48

K23

GND_49

K25

GND_50

L9

GND_51

L12

GND_52

L14

GND_53

L16

GND_54

L19

GND_55

M11

GND_56

M13

GND_57

M15

GND_58

M18

GND_59

N9

GND_60

N12

GND_61

N14

GND_62

N16

GND_63

N19

GND_64

P2

GND_65

SERVERWORKS "CMIC-LE" - REV 1.01

R_MCS0

11

R_MCS1

11

R_MCS3

11

R_MCS2

11

TITLE

DWG NO.

DATE

U_CMIC

GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130

HETERO 6 OF 6

RNB40

81

39 OHM-5%

RNB40

27

39 OHM-5%

RNB40

63

39 OHM-5%

RNB40

45

39 OHM-5%

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

9T576

2/26/2003

DC

P6
P11
P13
P15
P22
P26
R9
R12
R14
R16
R19
T11
T13
T15
T18
U3
U5
U7
U12
U14
U16
V3
V5
V7
V21
V23
V25
W9
W11
W13
W15
W19
W21
W23
W25
AA10
AA11
AA14
AA17
AB17
AB18
AC2
AC4
AC6
AC10
AC11
AC21
AC23
AC25
AD2
AD4
AD6
AD17
AD18
AD21
AD23
AD25
AE10
AE11
AF7
AF14
AF17
AF18
AG1
AG27

MCS0

14

MCS1

15

MCS3

15

MCS2

14

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

11 OF 51

2-26-2003_11:4111EVERGLADES

A02-00

H_ADS

6

1

H_ADSTB0

6

H_ADSTB1

6

H_AP0

6

H_AP1

6

H_BPRI

6

H_BREQ0

6

H_BINIT

2

6

H_BNR

6

H_DRDY

6

H_DBSY

6

H_DEFER

6

H_HIT

6

H_HITM

6

H_LOCK

6

H_RS0

6

H_RS1

6

H_RS2

6

H_RSP

6

H_REQ0

6

H_REQ1

6

H_REQ2

6

H_REQ3

6

H_REQ4

6

H_TRDY

6

H_DP0

6

H_DP1

6

H_DP2

6

H_DP3

6

H_A3

6

H_A4

6

H_A5

6

H_A6

6

H_A7

6

H_A8

6

H_A9

6

H_A10

6

H_A11

6

H_A12

6

H_A13

6

H_A14

6

H_A15

6

H_A16

6

H_A17

6

H_A18

6

H_A19

6

H_A20

6

H_A21

6

H_A22

6

H_A23

6

H_A24

6

H_A25

6

H_A26

6

H_A27

6

H_A28

6

H_A29

6

H_A30

6

H_A31

6

H_A32

6

H_A33

6

H_A34

6

H_A35

6

K15
A17
A19
B18
A18
B19
A20
G16
C19
E19
H17
H16
D19
F18
H18
G19
F19
A23
B23
A22
A21
F20
B20
A24
A25
D20
B21
E20
B25
B27
A26
C22
D22

D18
C20

E23
C24

F23
F21
H19

K17

D24

E16
G15
F15
C16
H15

C26
B26
E21
E25

F1

G2

H5

E1
C1
D1
G3

B1
G1
F2

F4

I2C FOR CMIC IS C0h

MA0

11

MA1

11

MA2

11

MA3

11

MA4

11

MA5

3

MA8

11

MA9

11

MA2

11

MA14

11

MA4

11

4 4

MA3

11

MA6

11

11
11

11
11
11
11

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

MA6

R_MCS0
R_MCS1
R_MCS2
R_MCS3

27 RNB31

18

RNB31

36

RNB31

45

RNB31

27 RNB25

18

RNB25

36

RNB25

45

RNB25

27 RNB26

18

RNB26

36

RNB26

45

RNB26

27 RNB29

18

RNB29

X_MA8

Y_MA8

X_MA9

Y_MA9

X_MA2

Y_MA2

X_MA14

Y_MA14

X_MA4

Y_MA4

X_MA3

Y_MA3

X_MA6

Y_MA6

AD5
AE5
Y10
AA8

Y9
Y7

AF1

U8

U10

W7
V8

SERVERWORKS "CMIC-LE" REV 1.01

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

ADS

PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA32
PA33
PA34
PA35

AD_STB0
AD_STB1

AP0
AP1

BPRI
BREQ0
BINIT
BNR

DRDY
DBSY
DEFER
HIT
HITM
LOCK

RS0
RS1
RS2

RSP

HREQ0
HREQ1
HREQ2
HREQ3
HREQ4

P_TRDY

DP0
DP1
DP2
DP3

MA0
MA1
MA2
MA3
MA4
MA5
MA6

R_CS_0
CS_1
CS_2
CS_3

HETERO 1 OF 6

11

11

11

11

11

11

11

U_CMIC

HOST

BUS

REMC

MA7

MA10

MA12

MA5

MA0

MA1

MA13

PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD32
PD33
PD34
PD35
PD36
PD37
PD38
PD39
PD40
PD41
PD42
PD43
PD44
PD45
PD46
PD47
PD48
PD49
PD50
PD51
PD52
PD53
PD54
PD55
PD56
PD57
PD58
PD59
PD60
PD61
PD62
PD63

DINV0
DINV1
DINV2
DINV3

P_INIT

MA10
MA11
MA12
MA13
MA14

CS_4
CS_5
CS_6
CS_7

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

H_D0

C2

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9

MA7
MA8
MA9

27 RNB30

18

36

45

27 RNB33

18

36

45

27 RNB32

18

36

45

18

27

H_D1

E3

H_D2

B3

H_D3

C3

H_D4

F3

H_D5

D4

H_D6

A2

H_D7

D2

H_D8

D3

H_D9

A3

H_D10

H6

H_D11

F6

H_D12

G8

H_D13

F5

H_D14

H8

H_D15

H10

H_D16

F7

H_D17

G9

H_D18

E7

H_D19

E6

H_D20

A4

H_D21

B4

H_D22

D7

H_D23

A5

H_D24

G10

H_D25

K11

H_D26

B7

H_D27

C6

H_D28

F8

H_D29

C7

H_D30

E9

H_D31

K12

H_D32

D8

H_D33

C8

H_D34

D9

H_D35

B9

H_D36

E10

H_D37

A7

H_D38

A10

H_D39

A8

H_D40

B12

H_D41

A11

H_D42

F12

H_D43

A12

H_D44

G13

H_D45

F13

H_D46

K13

H_D47

H12

H_D48

B13

H_D49

D12

H_D50

A13

H_D51

E13

H_D52

C13

H_D53

C14

H_D54

A15

H_D55

B15

H_D56

D15

H_D57

E14

H_D58

E15

H_D59

H14

H_D60

K14

H_D61

C15

H_D62

A16

H_D63

G14

G5
A6
C10
H13

AF23

AE2
AD3
AE3
AF2
Y8
V10
AA7
AB6

AE1
AD1
AA6
Y6

RNB30

RNB30

RNB30

RNB33

RNB33

RNB33

RNB32

RNB32

RNB32

RNB34

RNB34

H_DBI0
H_DBI1
H_DBI2
H_DBI3

P_INIT

MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14

NC_MCS4

NC_MCS5
CK_133M_MCLK_N
CK_133M_MCLK_P

CMIC-LE "P" CLOCK TO PLL's "N" CLOCK

X_MA7

Y_MA7

X_MA10

Y_MA10

X_MA12

Y_MA12

X_MA5

Y_MA5

X_MA0

Y_MA0

X_MA1

Y_MA1

X_MA13

Y_MA13

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

14,16

15,16

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

6
6
6
6

10,18,22

11
11
11
11
11
11
11
11

5
5

RN5

RN18

RN26

RN18

RN20

RN32

RN26

RN36

RN36

RN40

RN57

RN61

RN67

RN87

RN92

RN87

RN98

RN100

RN46

RN53

RN30

RN40

RN61

RN78

R_A_SD0_0
R_A_SD0_1
R_A_SD0_2
R_A_SD0_3
R_A_SD0_4
R_A_SD0_5
R_A_SD0_6
R_A_SD0_7

R_A_SD1_0
R_A_SD1_1
R_A_SD1_2
R_A_SD1_3
R_A_SD1_4
R_A_SD1_5
R_A_SD1_6
R_A_SD1_7

R_A_SD2_0
R_A_SD2_1
R_A_SD2_2
R_A_SD2_3
R_A_SD2_4
R_A_SD2_5
R_A_SD2_6
R_A_SD2_7

R_A_SD3_0
R_A_SD3_1
R_A_SD3_2
R_A_SD3_3
R_A_SD3_4
R_A_SD3_5
R_A_SD3_6
R_A_SD3_7

R_A_SD4_0
R_A_SD4_1
R_A_SD4_2
R_A_SD4_3
R_A_SD4_4
R_A_SD4_5
R_A_SD4_6
R_A_SD4_7

R_A_SD5_0
R_A_SD5_1
R_A_SD5_2
R_A_SD5_3
R_A_SD5_4
R_A_SD5_5
R_A_SD5_6
R_A_SD5_7

R_A_SD6_0
R_A_SD6_1
R_A_SD6_2
R_A_SD6_3
R_A_SD6_4
R_A_SD6_5
R_A_SD6_6
R_A_SD6_7

R_A_SD7_0
R_A_SD7_1
R_A_SD7_2
R_A_SD7_3
R_A_SD7_4
R_A_SD7_5
R_A_SD7_6
R_A_SD7_7

R_A_SD8_0
R_A_SD8_1
R_A_SD8_2
R_A_SD8_3
R_A_SD8_4
R_A_SD8_5
R_A_SD8_6
R_A_SD8_7

R_A_DQS0_0
R_A_DQS0_1

R_A_DQS1_0
R_A_DQS1_1

R_A_DQS2_0
R_A_DQS2_1

R_A_DQS3_0
R_A_DQS3_1

R_A_DQS4_0
R_A_DQS4_1

R_A_DQS5_0
R_A_DQS5_1

R_A_DQS6_0
R_A_DQS6_1

R_A_DQS7_0
R_A_DQS7_1

R_A_DQS8_0
R_A_DQS8_1

AA22
AD22
AC19
AA18
AB23
AB19
AD19

Y16

V15
AG22
AB15
AD16
AG21
AF19
AG17
AB16

AG14

Y14
AF13
AG12
AE14

V14
AG13
AE13

Y13

AF9

AE8
AD10
AA12

AG8

AG6

AG5

T10

Y4

R11

T7
W5
Y3
U6
U1

T3
R2
R4
R5
T5
R1
K8
R6

N3
N1
M2
M4
N8
N4
L1
M3

H1
H2
L6

M10

J5
J3
L8

K10

AF3

AG2
AB10

AA9

AE6

AF5

AC8

AB9

AC20
AD20

AG20
AG19

AB13
AC13

AE9

AF8

Y2
W1

T4
P7

N10

N7

H4
H3

Y11

V11

AB8

AE4

SERVERWORKS "CMIC_LE" - REV 1.01

ROOM=MEM_SERIESTERM (FOR MEMORY BUS SERIES TERMINATION RESISTORS)

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

14-16
14-16

RB88

RB87

21

21

A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7

A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7

A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7

A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7

A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7

A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7

A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7

A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7

A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7

A_DQS0_0
A_DQS0_1

A_DQS1_0
A_DQS1_1

A_DQS2_0
A_DQS2_1

A_DQS3_0
A_DQS3_1

A_DQS4_0
A_DQS4_1

A_DQS5_0
A_DQS5_1

A_DQS6_0
A_DQS6_1

A_DQS7_0
A_DQS7_1

A_DQS8_0
A_DQS8_1

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

12 OHM-5%

X_MA11

Y_MA11

18

36

45

45

27 RN18

27 RN26

18 RN20

45 RN20

18 RN30

36 RN32

36

45

36 RN36

18 RN46

45 RN36

27 RN46

36 RN57

27

45

18 RN67

27

36 RN82

18 RN78

45

27 RN87

27

45 RN87

18 RN98

27 RN100

45

18

36 RN104

27

36 RN53

45

45 RN53

27

27

45

27

36 RN61

36

18

36

45

14,16

15,16

RN9

RN13

RN5

RN13

RN30

RN32

RN67

RN57

RN78

RN82

RN98

RN104

RN100

RN48

RN46

RN9

RN20

RN30

RN40

RN78

RN92

RN100

RN48

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

14-16
14-16
14-16
14-16
14-16
14-16
14-16
14-16

MA11

11

12 OHM 5%

12 OHM 5%

27 RN5 18RN5

18 RN13

12 OHM-5%

36

12 OHM-5%

27 RN13

12 OHM-5%

18

12 OHM-5%

18

12 OHM-5%

36

12 OHM-5%

36

12 OHM-5%

45 RN26

12 OHM-5%

18

12 OHM-5%

36

12 OHM-5%

27 RN32

12 OHM-5%

18

12 OHM-5%

36 RN40

12 OHM-5%

27

12 OHM-5%

45

12 OHM-5%

18

12 OHM-5%

27 RN61

12 OHM-5%

27 RN57

12 OHM-5%

45

12 OHM-5%

36

12 OHM-5%

18 RN82

12 OHM-5%

45 RN67

12 OHM-5%

27 RN82

12 OHM-5%

18

12 OHM-5%

45

12 OHM-5%

36

12 OHM-5%

27 RN92

12 OHM-5%

45 RN98

12 OHM-5%

27 RN104

12 OHM-5%

36

12 OHM-5%

45

12 OHM-5%

18 RN48

12 OHM-5%

18 RN53

12 OHM-5%

36

12 OHM-5%

27

12 OHM-5%

36 RN9

12 OHM-5%

45 RN18

12 OHM-5%

27

12 OHM-5%

18

12 OHM-5%

18

12 OHM-5%

45

12 OHM-5%

36 RN92

12 OHM-5%

18 RN104

12 OHM-5%

36 RN48

12 OHM-5%

X_CKE

14,16

Y_CKE

15,16

A B

1

2

3

B D

CA

201

V

18

YA1

16

YA2

14

YA3

128

YA4A4

9

YB1

7

YB2

5

YB3

317

YB4B4

U18
74VHC125

+2.5V

14

+2.5V

GPE_CMIC_FATAL
CMIC_WARMRST
MEMOFF_CSB
MEMOFFACK
ENV_SEG4_25V_SCL
ENV_SEG4_25V_SDA
GPE_CMIC_ALERT
CMIC_TM_R

U18
74VHC125

645

+2.5V

U18

14

74VHC125

9108

+2.5V

U18

14

74VHC125

12

13

12,18,35
12
12,18
12
12,21
12,21
12,18

R114

12

0-5%

NP*

11

CMIC_TESTMODE

GPE_CIOB2_ALERT
TO CIOB-E

GPE_CIOB1_ALERT
TO CIOBX2

PCIX_SCSI_GNT2
TO CIOBX2

PCIX_SEC_GNT3
TO CIOB-E

12

18,28

18,27

26

28,29

12

IMB_R_W_PTR_DLY

+2.5V +2.5V

21

RB75

PU : normal operation

PD : do not use

ON CMIC 3.0 --

12

2.7K-5%

R125

1K-5%

12

NP

PD : 6 Clocks

PU : 5 Clocks

12

R139

CMIC_RSVD

21

R142

2.7K-5%

1K-5%

NP

IOQ_DEPTH

12

PU : TIMB is 100MHz

PD : TIMB is 200MHz

+2.5V

NP

RB82

12

R131

12

2.7K-5%

1K-5%

+2.5V +2.5V

NP

RB79

12

COMP_IMB

12

PU : IOQ DEPTH IS 1

PD : IOQ DEPTH IS 12 (default)

GPI_SYN_SEL100

4,7,22

2.7K-5%

R128

1K-5%

12

PU : A_IMB IS COMPATIBILITY IMB

PD : 533MHz

RB76

12

Q12

2.7K-5%

R124

1K-5%

12

NP

CMIC_PLL_EN

12

PD : DEFER IS DISABLED

PU : DEFER ENABLED (DEFAULT)PU : 400MHz

CMIC_DEFER_EN

12

3

D

2N7002

1

G

2

S

PD : THIN IMB IS COMPATIBILITY IMB (DEFAULT)

+2.5V

RB74

12

2.7K-5%

NP

R122

1K-5%

12

DETERMINISTIC_IMB

12

PU : APLL DISABLED

PD : APLL IS ENABLED (DEFAULT)

+2.5V

RB83

12

2.7K-5%

R135

1K-5%

12

NP

PU : Non Deterministic IMB (DEFAULT)

IMB_TRAINING

12

NP

PD : Deterministic IMB

+2.5V

RB81

12

2.7K-5%

R133

1K-5%

12

PU : ENABLE IMB Training (DEFAULT)

IMB_CRC_PARITY

12

PD : DISABLE IMB Training

+2.5V

RB77

12

2.7K-5%

R129

1K-5%

12

NP

PD : IMB Parity Checking

PU : IMB CRC Checking (DEFAULT)

CMIC_SRESET

12,47

CMIC_PLL_EN

12

CMIC_DEFER_EN

12

COMP_IMB

12

IOQ_DEPTH

12

DETERMINISTIC_IMB

12

IMB_TRAINING

12

IMB_CRC_PARITY

12

1

IMB_R_W_PTR_DLY

12

CMIC_SRESET

12,47

OEA

19

OEB

2

A1

4

A2

6

A3

11

B1

13

B2

15

B3

74VHC244

SUB*_8H192

U20

+2.5V

14
213

ROOM=CHIPSET_STRAP

E4
E5
E8
E11
E12
F16
F17
G4
G11
G12
G20
J10
J12
J14
J16
J18

G6

DSTBN0

F9

DSTBN1

C9

DSTBN2

D13

DSTBN3

H7

DSTBP0

H11

DSTBP1

A9

DSTBP2

A14

DSTBP3

C27

CPURST

AE24
AE26
AF26

PCIRST

CMIC_WARMRST
CMIC_TESTMODE

MEMOFFACK
MEMOFF_CSB

21

VCORE

H_RST
NC_CMIC_DLYRST
CMIC_WARMRST
CMIC_PCIRST

+2.5V

R181

12

2.2-5%

H_DSTBN0
H_DSTBN1
H_DSTBN2
H_DSTBN3

H_DSTBP0
H_DSTBP1
H_DSTBP2
H_DSTBP3

12
12

12
12,18

6
6
6
6

6
6
6
6

6,10

12
47

+1.5V

E26

VDD_1.5_E26

G23

VDD_1.5_G23

K19

VDD_1.5_K19

K22

VDD_1.5_K22

K24

VDD_1.5_K24

K26

VDD_1.5_K26

L22

VDD_1.5_L22

L24

VDD_1.5_L24

L26

VDD_1.5_L26

M17

VDD_1.5_M17

+2.5V

M19

VDD_1.5_M19

K3

VDD_2.5_K3

K5

VDD_2.5_K5

K7

VDD_2.5_K7

K9

VDD_2.5_K9

L3

VDD_2.5_L3

L5

VDD_2.5_L5

L7

VDD_2.5_L7

L11

VDD_2.5_L11

L13

VDD_2.5_L13

L15

VDD_2.5_L15

M9

VDD_2.5_M9

M12

VDD_2.5_M12

M14

VDD_2.5_M14

M16

VDD_2.5_M16

N11

VDD_2.5_N11

N13

VDD_2.5_N13

N15

VDD_2.5_N15

P4

VDD_2.5_P4

P9

VDD_2.5_P9

P12

VDD_2.5_P12

P14

VDD_2.5_P14

P16

VDD_2.5_P16

R13

VDD_2.5_R13

R15

VDD_2.5_R15

T9

VDD_2.5_T9

T12

VDD_2.5_T12

T14

VDD_2.5_T14

T16

VDD_2.5_T16

U11

VDD_2.5_U11

U13

VDD_2.5_U13

U15

VDD_2.5_U15

V2

VDD_2.5_V2

V4

VDD_2.5_V4

V6

VDD_2.5_V6

V9

VDD_2.5_V9

V22

VDD_2.5_V22

W2

VDD_2.5_W2

SERVERWORKS "CMIC-LE" - REV 1.01

HETERO 5 OF 6

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

DC

U_CMIC

VDD_1.5_P24
VDD_1.5_P19
VDD_1.5_P17
VDD_1.5_T17
VDD_1.5_T19
VDD_1.5_U22
VDD_1.5_U24
VDD_1.5_U26
VDD_1.5_V19
VDD_1.5_V24
VDD_1.5_V26

VDD_2.5_W4

VDD_2.5_W6
VDD_2.5_W10
VDD_2.5_W12
VDD_2.5_W14
VDD_2.5_W16
VDD_2.5_W18
VDD_2.5_Y23
VDD_2.5_Y25

VDD_2.5_AA15
VDD_2.5_AA16

VDD_2.5_AB3
VDD_2.5_AB5
VDD_2.5_AB7

VDD_2.5_AB11
VDD_2.5_AB12
VDD_2.5_AB22
VDD_2.5_AB24
VDD_2.5_AB26

VDD_2.5_AC3
VDD_2.5_AC5
VDD_2.5_AC7

VDD_2.5_AC14
VDD_2.5_AC16
VDD_2.5_AC17
VDD_2.5_AC22
VDD_2.5_AC24
VDD_2.5_AC26
VDD_2.5_AD11
VDD_2.5_AD12
VDD_2.5_AE16
VDD_2.5_AE17

VDD_2.5_AF4

VDD_2.5_AF11
VDD_2.5_AF12
VDD_2.5_AF21
VDD_2.5_AF24

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

+1.5V

P24
P19
P17
T17
T19
U22
U24
U26
V19
V24
V26

W4
W6
W10
W12
W14
W16
W18
Y23
Y25
AA15
AA16
AB3
AB5
AB7
AB11
AB12
AB22
AB24
AB26
AC3
AC5
AC7
AC14
AC16
AC17
AC22
AC24
AC26
AD11
AD12
AE16
AE17
AF4
AF11
AF12
AF21
AF24

REV.

12 OF 51

2-26-2003_11:4112EVERGLADES

+2.5V

A02-00

+2.5V

21

R13221RB80

10K-5%

VCORE

B2

VTT_1.2_B2

B8

VTT_1.2_B8

B16

VTT_1.2_B16

B17

VTT_1.2_B17

B22

VTT_1.2_B22

B24

VTT_1.2_B24

C4

VTT_1.2_C4

C5

VTT_1.2_C5

C11

VTT_1.2_C11

C12

VTT_1.2_C12

C21

VTT_1.2_C21

C23

VTT_1.2_C23

D16

VTT_1.2_D16

D17

VTT_1.2_D17

D26

VTT_1.2_D26

AG18

DCOMP

F22

GTL_COMP_PD

G21

GTL_COMP_PU

H20

GTL_RCOMP

AB27

AVDD
AGND

H9

GTLVREF1

K18

GTLVREF2

AF25

SRESET

AG24

MEMOFF

AG26

MEMOFFACK

AD26

TESTMODE

SERVERWORKS "CMIC-LE" - REV 1.01

R123

10K-5%

12

0.1uF 16V
CB150

12

A_IMB_UP_CLK_N

27

A_IMB_UP_CLK_P

27

B_IMB_UP_CLK_N

29

B_IMB_UP_CLK_P

12,18,35

12,21

28,47

29

A_IMB_UP_CON

27

B_IMB_UP_CON

29

A_IMB_UP_PAR

27

B_IMB_UP_PAR

29

A_IMB_UP_D0

27

A_IMB_UP_D1

27

A_IMB_UP_D2

27

A_IMB_UP_D3

27

A_IMB_UP_D4

27

A_IMB_UP_D5

27

A_IMB_UP_D6

27

A_IMB_UP_D7

27

A_IMB_UP_D8

27

A_IMB_UP_D9

27

A_IMB_UP_D10

27

A_IMB_UP_D11

27

A_IMB_UP_D12

27

A_IMB_UP_D13

27

A_IMB_UP_D14

27

A_IMB_UP_D15

27

B_IMB_UP_D0

29

B_IMB_UP_D1

29

B_IMB_UP_D2

29

B_IMB_UP_D3

29

B_IMB_UP_D4

29

B_IMB_UP_D5

29

B_IMB_UP_D6

29

B_IMB_UP_D7

29

B_IMB_UP_D8

29

B_IMB_UP_D9

29

B_IMB_UP_D10

29

B_IMB_UP_D11

29

B_IMB_UP_D12

29

B_IMB_UP_D13

29

B_IMB_UP_D14

29

B_IMB_UP_D15

29

CSB_IMB_UP_D0

18

CSB_IMB_UP_D1

18

CSB_IMB_UP_D2

18

CSB_IMB_UP_D3

18

CSB_IMB_UP_CLK

18

CSB_IMB_UP_CON

18

CSB_IMB_UP_PAR

18

CMIC_IMB_COMP_PD

12

CMIC_IMB_COMP_PU

12

CMIC_IMB_RCOMP

12

GPE_CMIC_FATAL
ENV_SEG4_25V_SCL

CK_100M_CMIC_P

4

CK_100M_CMIC_N

4

PLLRST_CMIC

12

12

12

2

3

+1.5V

RB102

12

CMIC_IMB_COMP_PU

100-1%

RB97

12

CMIC_IMB_RCOMP

100-1%

R186

CMIC_IMB_COMP_PD

12

4 4

249 Ohm-1%

H24

A_IMBCLK_R_N

H25

A_IMBCLK_R_P

P27

B_IMBCLK_R_N

P25

B_IMBCLK_R_P

F25 M20

A_IMBCON_R A_IMBCON_T

N20 R20

B_IMBCON_R B_IMBCON_T

F26 L23

A_IMBPAR_R A_IMBPAR_T

N21 V27

B_IMBPAR_R B_IMBPAR_T

L20

A_IMBD_R0

L17

A_IMBD_R1

L18

A_IMBD_R2

K20

A_IMBD_R3

J24

A_IMBD_R4

H23

A_IMBD_R5

H22

A_IMBD_R6

J22

A_IMBD_R7

H26

A_IMBD_R8

F27

A_IMBD_R9

G24

A_IMBD_R10

G27

A_IMBD_R11

G25

A_IMBD_R12

E27

A_IMBD_R13

F24

A_IMBD_R14

J20

A_IMBD_R15

R25

B_IMBD_R0

T23

B_IMBD_R1

R26

B_IMBD_R2

R27

B_IMBD_R3

R22

B_IMBD_R4

P23

B_IMBD_R5

R24

B_IMBD_R6

R23

B_IMBD_R7

N25

B_IMBD_R8

N22

B_IMBD_R9

P21

B_IMBD_R10

N23

B_IMBD_R11

N24

B_IMBD_R12

P20

B_IMBD_R13

R18

B_IMBD_R14

R17

B_IMBD_R15

Y26

T_IMBD_R0

W24

T_IMBD_R1

AA26

T_IMBD_R2

W22

T_IMBD_R3

Y27 AA24

T_IMBCLK_R T_IMBCLK_T

AA27 AA23

T_IMBCON_R T_IMBCON_T

W20 AB25

T_IMBPAR_R T_IMBPAR_T

D27

IMB_COMP_PD

H21

IMB_COMP_PU

G22

IMB_RCOMP

AG23 AE23

SCL SDA

AD27

BCLKP

AE27

BCLKN

AE25

DLLRST

SERVERWORKS "CMIC-LE" - REV 1.01

CMIC-LE heatsink (U3001)

A3.0 rev CMIC IS 6U018
A3.1 rev CMIC IS 3X719

U_CMIC

A_IMBCLK_T_N
A_IMBCLK_T_P

IM

B_IMBCLK_T_N
B_IMBCLK_T_P

A_IMBD_TO
A_IMBD_T1
A_IMBD_T2
A_IMBD_T3
A_IMBD_T4
A_IMBD_T5
A_IMBD_T6
A_IMBD_T7
A_IMBD_T8

A_IMBD_T9
A_IMBD_T10
A_IMBD_T11
A_IMBD_T12
A_IMBD_T13
A_IMBD_T14
A_IMBD_T15

B_IMBD_TO

B_IMBD_T1

B_IMBD_T2

B_IMBD_T3

B_IMBD_T4

B_IMBD_T5

B_IMBD_T6

B_IMBD_T7

B_IMBD_T8

B_IMBD_T9
B_IMBD_T10
B_IMBD_T11
B_IMBD_T12
B_IMBD_T13
B_IMBD_T14
B_IMBD_T15

T_IMBD_TO

T_IMBD_T1

T_IMBD_T2

T_IMBD_T3

T_IMBVREFF

RAS

HETERO 2 OF 6

ADD=ADD*_P0199_U_CMIC

SUB*_3X719

ALERTFATAL

IMBVREF1

RSVD
MEMVREF
MEMVREF

M23

A_IMB_DN_CLK_N

L25

A_IMB_DN_CLK_P

W27

B_IMB_DN_CLK_N

W26

B_IMB_DN_CLK_P

A_IMB_DN_CON
B_IMB_DN_CON

A_IMB_DN_PAR
B_IMB_DN_PAR

A_IMB_DN_D0

M26

A_IMB_DN_D1

M25

A_IMB_DN_D2

N27

A_IMB_DN_D3

N18

A_IMB_DN_D4

N17

A_IMB_DN_D5

M24

A_IMB_DN_D6

N26

A_IMB_DN_D7

L27

A_IMB_DN_D8

M27

A_IMB_DN_D9

L21
M22

A_IMB_DN_D10

H27

A_IMB_DN_D11

J27

A_IMB_DN_D12

K27

A_IMB_DN_D13

J26

A_IMB_DN_D14

M21

A_IMB_DN_D15

B_IMB_DN_D0

U21

B_IMB_DN_D1

U23

B_IMB_DN_D2

T20

B_IMB_DN_D3

U18

B_IMB_DN_D4

U17

B_IMB_DN_D5

V20

B_IMB_DN_D6

U20

B_IMB_DN_D7

T22

B_IMB_DN_D8

T21

B_IMB_DN_D9

R21

B_IMB_DN_D10

T25

B_IMB_DN_D11

U27

B_IMB_DN_D12

T24

B_IMB_DN_D13

U25

B_IMB_DN_D14

T27

B_IMB_DN_D15

T26

R_CSB_IMB_DN_D0

Y22

R_CSB_IMB_DN_D1

AA25

R_CSB_IMB_DN_D2

Y21

R_CSB_IMB_DN_D3

Y24

R_CSB_IMB_DN_CLK
R_CSB_IMB_DN_CON
R_CSB_IMB_DN_PAR

CMIC_T_IMBVREF

U19

GPE_CMIC_ALERT

AF27AG25

ENV_SEG4_25V_SDA

CMIC_IMBVREF

P18

CMIC_RSVD

AD24
U9
W17

+2.5V

27
27
28
28

27
29

27
29

27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27

29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29

24 OHM-5%

24 OHM-5%

24 OHM-5%

13

12,18
12,21

13
12

R148

12

GPE_CMIC_ALERT

4.7K
R137

21

GPE_CMIC_FATAL

4.7K

+2.5V

VCORE

RB105

12

100-1%

(SW RECOMMENDS 23.5 WITH 43.2 ON PROC)

X01 -- CHANGING TO 24.3 TO IMPROVE MARGIN ON GTL BUS --SWH 10/18

RN66

45

24 OHM-5%

SUB*_4282E

RN71

36

RN71

27

RN66

27

RN71

24 OHM-5%

RN66

18

24 OHM-5%

SUB*_4282E
SUB*_4282E
SUB*_4282E

54

RN71

18

24 OHM-5%

RN66

36

24 OHM-5%

SUB*_4282E
SUB*_4282E

Sub to 33 Ohm

12,18

12,18,35

(OR 24.5 WITH 49.9 ON PROC)

SP_RN2093_5SP_RN2093_4

CSB_IMB_DN_D0
CSB_IMB_DN_D1
CSB_IMB_DN_D2
CSB_IMB_DN_D3

CSB_IMB_DN_CLK
CSB_IMB_DN_CON
CSB_IMB_DN_PAR

SUB*_4282E
SUB*_4282E

RB104

21

249 Ohm-1%

SUB*_20JDN
SUB TO 332 1%
FOR CMIC 3.1

1X055 -- 24.3 OHMS 0603 1%
6W083 -- 23.7 OHMS 0603 1%

18
18
18
18

18
18
18

R143

249 Ohm-1%

RB103

12

20.5 Ohm-1%

SUB*_1X055 AC27

SUB TO 24.3

21

12
12

13
13

12,47
12,18

12
12

12

12

CMIC_DCOMP

CMIC_GTL_COMP_PD
CMIC_GTL_COMP_PU
CMIC_GTL_RCOMP

CMIC_AVDD
CMIC_AGND

CMIC_GTLVREF1
CMIC_GTLVREF2

CMIC_SRESET
MEMOFF_CSB
MEMOFFACK
CMIC_TESTMODE

CMIC_AVDD

CMIC_AGND

U_CMIC

VTT_1.2_E11
VTT_1.2_F12
VTT_1.2_F16
VTT_1.2_F17

VTT_1.2_G11
VTT_1.2_G12
VTT_1.2_G20
VTT_1.2_J10
VTT_1.2_J12
VTT_1.2_J14
VTT_1.2_J16
VTT_1.2_J18

RESET & TEST

HETERO 4 OF 6

21

RB78

1K-5%

10K-5%

10V-10%

12

1uF

47uH 135MA

C217

22uF 10V

12

C216

VTT_1.2_E4
VTT_1.2_E5
VTT_1.2_E8

VTT_1.2_G4

DLYRESET

WARMRST

L40

R147

12

0-5%

ROOM=CMIC

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

1

2

3

B D

CA

VCORE

RB98

12

49.9-1%

CMIC_GTLVREF2

1

21

RB99

100-1%

12

CB202

1uF

10V-10%

CB201

21

0.1uF 16V

12

21

CB188

50V-20%

.01UF

12

0.1uF 16V

CB187

CB186

12

1000pF

50V-10%

50V-20%

.01UF

12

CB183

12

CB199

VCORE

1000pF

50V-10%

RB96

12

49.9-1%100-1%

RB95

12

CMIC_GTLVREF1

21

1uF

CB181

10V-10%

21

CB182

12

21

CB198

0.1uF 16V

0.1uF 16V

CMIC GTL REFERENCE VOLTAGE

ROOM=CMIC

+1.5V

+2.5V

ROOM=CMIC

21

RB93

100-1%

21

RB94

100-1%

12

CB166

1uF

10V-10%

21

CB164

2

.01UF

CB165

50V-20%

CMIC_IMBVREF

21

0.1uF 16V

12

RB86

100-1%

12

RB85

100-1%

12

21

CB133

1uF

10V-10%

CB129

12

.01UF

CB125

50V-20%

21

0.1uF 16V

21

CB128

21

CB126

0.1uF 16V

CMIC_T_IMBVREF

0.1uF 16V

12

+2.5V

4V-20%

820uF

+

SUB*_700DN

4.0V-20%

SUB*_700DN

C61

21

+2.5V

21

C204

0.1uF 16V

+1.5V

4.0V-20%
330uF

+

21

VCORE

330uF

C340

+

21

21

12

C232

CB136

1000pF

50V-10%

21

21

C202

C218

0.1uF 16V

C277

21

.1uF

CB161

SUB TO 330uF

SUB*_700DN

4V-20%

820uF

+

C207

1000pF

50V-10%

C203

0.1uF 16V

21

.1uF

CB162

10V-10%

C304

21

C269

21

1000pF

21

0.1uF 16V

21

CB160

10V-10%

21

1000pF

50V-10%

12

CB130

50V-10%

21

C237

.1uF

10V-10%

21

.1uF

CB200

C201

1000pF

50V-10%

C205

0.1uF 16V

21

C243

0.1uF 16V

C268

12

10V-10%

12

0.1uF 16V

21

0.1uF 16V

21

C236

1uF

10V-10%

12

C200

CB131

0.1uF 16V

21

.1uF

CB17521CB176

10V-10%

21

CB163

0.1uF 16V

0.1uF 16V

21

1uF

C265

C254

10V-10%

12

CB132

0.1uF 16V

.1uF

CB147

10V-10%

21

C249

0.1uF 16V

21

C264

0.1uF 16V

12

0.1uF 16V

21

0.1uF 16V

21

CB185

C266

12

0.1uF 16V

12

CB134

0.1uF 16V

21

CB153

CB156

0.1uF 16V

0.1uF 16V

21

CB217

0.1uF 16V

12

CB135

21

0.1uF 16V

12

0.1uF 16V

CB158

0.1uF 16V

21

CB149

0.1uF 16V

CB210

12

0.1uF 16V

21

.1uF

21

CB145

12

CB220

21

CB177

10V-10%

CB137

0.1uF 16V

12

C267

0.1uF 16V

.1uF

12

CB174

10V-10%

21

0.1uF 16V

12

CB218

0.1uF 16V

12

CB155

0.1uF 16V

12

CB219

0.1uF 16V

0.1uF 16V

12

C263

0.1uF 16V

12

C351

0.1uF 16V

1

2

0.1uF 16V

CMIC IMB REFERENCE VOLTAGE

+2.5V

21

0.1uF 16V

+2.5V

R52

21

C100

ROOM=DIMM_VREF

100-1%

NP*

12

R77

12

0.1uF 16V

NP*

C96

100-1%

21

1uF

10V-10%

SSTLREF_D1

14,15

21

CB18421CB159

.1uF

10V-10%

.1uF

10V-10%

ROOM=CMIC

21

CB146

.1uF

10V-10%

VCORE

21

CB151

.1uF

10V-10%

21

CB154

.1uF

10V-10%

21

CB157

.1uF

10V-10%

R58

VTT_SSTL_1

16

VTT_SSTL_2

16

X01 -- CHANGED DIMM VREF TO TRACK DDR VTT

12

100-1%

R60

12

100-1%

C86

50V-20%

12

.01UF

10V-10%

C333

CB319

3

DIMM DDR REFERENCE VOLTAGE

21

CB205

.1uF

12

1000pF

50V-10%

21

CB216

.1uF

10V-10%

3

ROOM=CMIC

CMIC DECOUPLING CAPS

4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

13 OF 51

A02-00

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

AB

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

EVERGLADES 13 2-26-2003_11:41

DC

4

C173

.01UF

50V-20%

CA

.01UF

12

50V-20%

C187

12

C292

.01UF

50V-20%

.01UF

12

50V-20%

C198

12

C228

.01UF

50V-20%

.01UF

12

50V-20%

C245

12

C258

.01UF

50V-20%

.01UF

12

50V-20%

C271

12

C276

.01UF

50V-20%

.01UF

12

50V-20%

+2.5V

C286

12

.01UF

50V-20%

B D

+2.5V

21

C147

C137

C131

C305

+80%-20%

C118

12

+80%-20%

22uF 10V

.01UF

50V-20%

.01UF

12

50V-20%

.01UF

12

50V-20%

12

C79

12

22uF 10V

1

C80

12

+80%-20%

22uF 10V

C289

21

22uF 10V

C179

+80%-20%

12

0.1uF 16V

C221

12

C256

.01UF

50V-20%

.01UF

12

50V-20%

C150

12

C296

.01UF

50V-20%

.01UF

12

50V-20%

C191

12

.01UF

50V-20%

C122

12

C239

.01UF

50V-20%

.01UF

12

50V-20%

C273

12

C280

.01UF

50V-20%

.01UF

12

50V-20%

Put one 22 uF cap at each end of DIMM

Put one 22 uF cap at each end of DIMM

DIMM_1A

SUB*_726NT

X ADDR/CTRL

A DATA

DQS0

DM0_DQS9

D10
D11

DQS1

DM1_DQS10

D12
D13
D14
D15
D16
D17
D18
D19

DQS2

DM2_DQS11

D20
D21
D22
D23
D24
D25
D26
D27

DQS3

DM3_DQS12

D28
D29
D30
D31
D32
D33
D34
D35

DQS4

DM4_DQS13

D36
D37
D38
D39
D40
D41
D42
D43

DQS5

DM5_DQS14

D44
D45
D46
D47
D48
D49
D50
D51

DQS6

DM6_DQS15

D52
D53
D54
D55
D56
D57
D58
D59

DQS7

DM7_DQS16

D60
D61
D62

D63
ECC0
ECC1
ECC2
ECC3
DQS8

DM8_DQS17

ECC4
ECC5
ECC6
ECC7

D0
D1
D2
D3

D4
D5
D6
D7
D8
D9

11,14
11,14

CK_133M_DDR0_P
CK_133M_DDR0_N

X_CKE

NC_FETEN_DDR0

SSTLREF_D1

13-15

NC_VDDID_DDR0

ASCLK_2P5V
ASDATA_2P5V

PU_WP_DDR

NC_NC1_DDR0
NC_NC2_DDR0
DDR_RESET
NC_NC4_DDR0
NC_NC5_DDR0
NC_CS3_DDR0

NC_CS2_DDR0
NC_CLK2_N_DDR0
NC_CLK2_P_DDR0
NC_CLK1_N_DDR0
NC_CLK1_P_DDR0
NC_BA2_DDR0
NC_A13_DDR0

+2.5V

+2.5V

1

C87

2

0.1uF 16V

X_MA0
X_MA1
X_MA2
X_MA3
X_MA4
X_MA5
X_MA6
X_MA7
X_MA8
X_MA9
X_MA10
X_MA11
X_MA12

X_MA13
X_MA14

MCS0
MCS2

X_MRAS
X_MCAS
X_MWE

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16

220

11,14,16
11,14,16
11,14,16

5
5

11,14,16

5,14,15,21
5,14,15,21

14,15

14,15,47

2

+2.5V

21

R259

21

220

R250

3

SSTLREF_D1

13-15

4 4

1

CB20

2

0.1uF 16V

130

125

122

141
118
115

157
158
154

137
138

111

167

184

181
182
183

102
101

173
163

113
103

168
148
120
108

136
180
156
112
164
143
128
104

172

48
43
41

37
32

29

27

59
52

65
63

21

1

82

92
91

90

10

9

71
76
75
17
16

85
70
46
38

7

96

77
62
54
30
22
15

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

BA0
BA1

CS
CS1
RAS
CAS
WE

CLK0_P
CLK0_N

CLKE0
CLKE1

FETEN

VREF

VDDSPD
VDDID

SCL
SDA
SA0
SA1
SA2
WP

NC1
NC2
RESET
NC4
NC5
CS3_NU
CS2_NU
CLK2_N_DU
CLK2_P_DU
CLK1_N_DU
CLK1_P_DU
BA2_NU
A13_NU

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16

2
4
6
8
5
97
94
95
98
99
12
13
19
20
14
107
105
106
109
110
23
24
28
31
25
119
114
117
121
123
33
35
39
40
36
129
126
127
131
133
53
55
57
60
56
149
146
147
150
151
61
64
68
69
67
159
153
155
161
162
72
73
79
80
78
169
165
166
170
171
83
84
87
88
86
177
174
175
178
179
44
45
49
51
47
140
134
135
142
144

A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_DQS0_0
A_DQS0_1
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7
A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_DQS1_0
A_DQS1_1
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7
A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_DQS2_0
A_DQS2_1
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7

A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_DQS3_0
A_DQS3_1
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7
A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_DQS4_0
A_DQS4_1
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7
A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_DQS5_0
A_DQS5_1
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7
A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_DQS6_0
A_DQS6_1
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7
A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_DQS7_0

A_DQS7_1
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7
A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_DQS8_0
A_DQS8_1
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

+2.5V

R249

12

ROOM=DIMM_2A

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16

11,14,16
11,14,16
11,14,16

11,14,16

5,14,15,21

R248

5,14,15,21

12

4.7K

220

14,15,47

11,14
11,14

5
5

13-15

14,15

X_MA0
X_MA1
X_MA2
X_MA3
X_MA4
X_MA5
X_MA6
X_MA7
X_MA8
X_MA9
X_MA10
X_MA11
X_MA12

X_MA13
X_MA14

MCS0
MCS2

X_MRAS
X_MCAS
X_MWE

CK_133M_DDR1_P
CK_133M_DDR1_N

X_CKE

NC_FETEN_DDR1

SSTLREF_D1

NC_VDDID_DDR1

ASCLK_2P5V
ASDATA_2P5V

PU_WP_DDR

NC_NC1_DDR1
NC_NC2_DDR1
DDR_RESET
NC_NC4_DDR1
NC_NC5_DDR1
NC_CS3_DDR1

NC_CS2_DDR1
NC_CLK2_N_DDR1
NC_CLK2_P_DDR1
NC_CLK1_N_DDR1
NC_CLK1_P_DDR1
NC_BA2_DDR1
NC_A13_DDR1

+2.5V

+2.5V

48

A0

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS

158

CS1

154

RAS

65

CAS

63

WE

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

182

SA1

183

SA2

90

WP

102

NC1

101

NC2

10

RESET

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

76

CLK2_N_DU

75

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD1

148

VDD2

120

VDD3

108

VDD4

85

VDD5

70

VDD6

46

VDD7

38

VDD8

7

VDD10

136

VDDQ1

180

VDDQ2

156

VDDQ3

112

VDDQ4

164

VDDQ5

143

VDDQ6

128

VDDQ7

104

VDDQ8

96

VDDQ9

172

VDDQ10

77

VDDQ11

62

VDDQ12

54

VDDQ13

30

VDDQ14

22

VDDQ15

15

VDDQ16

CS0/2

ROOM=DIMM_1A

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

DIMM_1B

SUB*_726NT

X ADDR/CTRL

B DATA

CS0/2

DQS0

DM0_DQS9

D10
D11

DQS1

DM1_DQS10

D12
D13
D14
D15
D16
D17
D18
D19

DQS2

DM2_DQS11

D20
D21
D22
D23
D24
D25
D26
D27

DQS3

DM3_DQS12

D28
D29
D30
D31
D32
D33
D34
D35

DQS4

DM4_DQS13

D36
D37
D38
D39
D40
D41
D42
D43

DQS5

DM5_DQS14

D44
D45
D46
D47
D48
D49
D50
D51

DQS6

DM6_DQS15

D52
D53
D54
D55
D56
D57
D58
D59

DQS7

DM7_DQS16

D60
D61
D62

D63
ECC0
ECC1
ECC2
ECC3
DQS8

DM8_DQS17

ECC4
ECC5
ECC6
ECC7

D0
D1
D2
D3

D4
D5
D6
D7
D8
D9

2
4
6
8
5
97
94
95
98
99
12
13
19
20
14
107
105
106
109
110
23
24
28
31
25
119
114
117
121
123
33
35
39
40
36
129
126
127
131
133
53
55
57
60
56
149
146
147
150
151
61
64
68
69
67
159
153
155
161
162
72
73
79
80
78
169
165
166
170
171
83
84
87
88
86
177
174
175
178
179
44
45
49
51
47
140
134
135
142
144

B_SD0_0
B_SD0_1
B_SD0_2
B_SD0_3
B_DQS0_0
B_DQS0_1
B_SD0_4
B_SD0_5
B_SD0_6
B_SD0_7
B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_DQS1_0
B_DQS1_1
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7
B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_DQS2_0
B_DQS2_1
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7

B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_DQS3_0
B_DQS3_1
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7
B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_DQS4_0
B_DQS4_1
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7
B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_DQS5_0
B_DQS5_1
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7
B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_DQS6_0
B_DQS6_1
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7
B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_DQS7_0

B_DQS7_1
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7
B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_DQS8_0
B_DQS8_1
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16

11,15,16
11,15,16

11,15,16
11,15,16

11,15,16

11,15,16
11,15,16

TITLE

DWG NO.

DATE

DC

SSTLREF_D1

13-15

2

1

C97

0.1uF 16V

COMPUTER
CORPORATION
AUSTIN,TEXAS

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

9T576

2/26/2003

SHEET

14 OF 51

REV.

2-26-2003_11:4114EVERGLADES

1

C99

2

0.1uF 16V

A02-00

1

2

3

B D

CA

+2.5V

12

+80%-20%

22uF 10V

C309

21

22uF 10V

C98

C238

12

+80%-20%

C219

.01UF

50V-20%

.01UF

12

50V-20%

C255

12

C126

.01UF

50V-20%

.01UF

12

50V-20%

C171

12

C139

.01UF

50V-20%

.01UF

12

50V-20%

C149

12

C162

.01UF

50V-20%

.01UF

12

12

50V-20%

C208

.01UF

50V-20%

.01UF

12

50V-20%

Put one 22 uF cap at each end of DIMM

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16
11,15,16

11,15

11,15
11,15,16
11,15,16
11,15,16

5
5

11,15,16

+2.5V

R245

12

4.7K

220

R253

12

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

13-15

5,14,15,21
5,14,15,21

14,15

14,15,47

Y_MA0
Y_MA1
Y_MA2
Y_MA3
Y_MA4
Y_MA5
Y_MA6
Y_MA7
Y_MA8
Y_MA9
Y_MA10
Y_MA11
Y_MA12

Y_MA13
Y_MA14

MCS1
MCS3

Y_MRAS
Y_MCAS
Y_MWE

CK_133M_DDR3_P
CK_133M_DDR3_N

Y_CKE

NC_FETEN_DDR3

SSTLREF_D1

NC_VDDID_DDR3

ASCLK_2P5V
ASDATA_2P5V

PU_WP_DDR

NC_NC1_DDR3
NC_NC2_DDR3
DDR_RESET
NC_NC4_DDR3
NC_NC5_DDR3
NC_CS3_DDR3

NC_CS2_DDR3
NC_CLK2_N_DDR3
NC_CLK2_P_DDR3
NC_CLK1_N_DDR3
NC_CLK1_P_DDR3
NC_BA2_DDR3
NC_A13_DDR3

+2.5V

+2.5V

130

125

122

141
118
115

157
158
154

137
138

111

167

184

181
182
183

102
101

173
163

113
103

168
148
120
108

136
180
156
112
164
143
128
104

172

48
43
41

37
32

29

27

59
52

65
63

21

1

82

92
91

90

10

9

71
76
75
17
16

85
70
46
38

7

96

77
62
54
30
22
15

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

BA0
BA1

CS
CS1
RAS
CAS
WE

CLK0_P
CLK0_N

CLKE0
CLKE1

FETEN

VREF

VDDSPD
VDDID

SCL
SDA
SA0
SA1
SA2
WP

NC1
NC2
RESET
NC4
NC5
CS3_NU
CS2_NU
CLK2_N_DU
CLK2_P_DU
CLK1_N_DU
CLK1_P_DU
BA2_NU
A13_NU

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16

DIMM_2B

SUB*_726NT

Y ADDR/CTRL

B DATA

CS1/3

C288

.01UF

12

50V-20%

DM0_DQS9

DM1_DQS10

DM2_DQS11

DM3_DQS12

DM4_DQS13

DM5_DQS14

DM6_DQS15

DM7_DQS16

DM8_DQS17

C178

12

DQS0

D10
D11

DQS1

D12
D13
D14
D15
D16
D17
D18
D19

DQS2

D20
D21
D22
D23
D24
D25
D26
D27

DQS3

D28
D29
D30
D31
D32
D33
D34
D35

DQS4

D36
D37
D38
D39
D40
D41
D42
D43

DQS5

D44
D45
D46
D47
D48
D49
D50
D51

DQS6

D52
D53
D54
D55
D56
D57
D58
D59

DQS7

D60
D61
D62

D63
ECC0
ECC1
ECC2
ECC3
DQS8

ECC4
ECC5
ECC6
ECC7

.01UF

50V-20%

D0
D1
D2
D3

D4
D5
D6
D7
D8
D9

C190

12

2
4
6
8
5
97
94
95
98
99
12
13
19
20
14
107
105
106
109
110
23
24
28
31
25
119
114
117
121
123
33
35
39
40
36
129
126
127
131
133
53
55
57
60
56
149
146
147
150
151
61
64
68
69
67
159
153
155
161
162
72
73
79
80
78
169
165
166
170
171
83
84
87
88
86
177
174
175
178
179
44
45
49
51
47
140
134
135
142
144

C195

.01UF

50V-20%

.01UF

12

B_SD0_0
B_SD0_1
B_SD0_2
B_SD0_3
B_DQS0_0
B_DQS0_1
B_SD0_4
B_SD0_5
B_SD0_6
B_SD0_7
B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_DQS1_0
B_DQS1_1
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7
B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_DQS2_0
B_DQS2_1
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7
B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_DQS3_0
B_DQS3_1
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7
B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_DQS4_0
B_DQS4_1
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7
B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_DQS5_0
B_DQS5_1
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7
B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_DQS6_0
B_DQS6_1
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7
B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_DQS7_0
B_DQS7_1
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7
B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_DQS8_0
B_DQS8_1
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7

50V-20%

SSTLREF_D1

13-15

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

COMPUTER
CORPORATION

TITLE

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

DWG NO.

9T576

DATE

2/26/2003

EVERGLADES 15 2-26-2003_11:41

DC

AUSTIN,TEXAS

SHEET

15 OF 51

REV.

C91

2

1

1

C92

2

0.1uF 16V

0.1uF 16V

A02-00

+2.5V

1

12

C315

21

C78

+80%-20%

22uF 10V

21

C24421C22721C19721C18621C17221C16021C14621C13621C28521C11721C27521C130

+80%-20%

22uF 10V

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

.01UF

50V-20%

Put one 22 uF cap at each end of DIMM

DIMM_2A

DM1_DQS10

DM2_DQS11

DM3_DQS12

DM4_DQS13

DM5_DQS14

DM6_DQS15

DM7_DQS16

DM8_DQS17

SUB*_726NT

11,15
11,15

CK_133M_DDR2_P
CK_133M_DDR2_N

Y_CKE

NC_FETEN_DDR2

SSTLREF_D1

13-15

NC_VDDID_DDR2

ASCLK_2P5V
ASDATA_2P5V

PU_WP_DDR

NC_NC1_DDR2
NC_NC2_DDR2
DDR_RESET
NC_NC4_DDR2
NC_NC5_DDR2
NC_CS3_DDR2

NC_CS2_DDR2
NC_CLK2_N_DDR2
NC_CLK2_P_DDR2
NC_CLK1_N_DDR2
NC_CLK1_P_DDR2
NC_BA2_DDR2
NC_A13_DDR2

+2.5V

+2.5V

Y_MA0
Y_MA1
Y_MA2
Y_MA3
Y_MA4
Y_MA5
Y_MA6
Y_MA7
Y_MA8
Y_MA9
Y_MA10
Y_MA11
Y_MA12

Y_MA13
Y_MA14

MCS1
MCS3

Y_MRAS
Y_MCAS
Y_MWE

11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16
11,15,16

11,15,16

2

+2.5V

220

R246

12

11,15,16

11,15,16
11,15,16
11,15,16

11,15,16

5,14,15,21
5,14,15,21

R247

12

4.7K
14,15

14,15,47

5
5

3

4 4

48

A0

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS

158

CS1

154

RAS

65

CAS

63

WE

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

182

SA1

183

SA2

90

WP

102

NC1

101

NC2

10

RESET

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

76

CLK2_N_DU

75

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD1

148

VDD2

120

VDD3

108

VDD4

85

VDD5

70

VDD6

46

VDD7

38

VDD8

7

VDD10

136

VDDQ1

180

VDDQ2

156

VDDQ3

112

VDDQ4

164

VDDQ5

143

VDDQ6

128

VDDQ7

104

VDDQ8

96

VDDQ9

172

VDDQ10

77

VDDQ11

62

VDDQ12

54

VDDQ13

30

VDDQ14

22

VDDQ15

15

VDDQ16

21

C27021C257

.01UF

50V-20%

DQS0

DM0_DQS9

D10
D11

DQS1

D12
D13
D14
D15
D16
D17
D18
D19

DQS2

D20
D21
D22
D23
D24
D25
D26
D27

DQS3

D28
D29
D30
D31
D32
D33
D34
D35

DQS4

D36
D37
D38
D39
D40
D41
D42
D43

DQS5

D44
D45
D46
D47
D48
D49
D50
D51

DQS6

D52
D53
D54
D55
D56
D57
D58
D59

DQS7

D60
D61
D62

D63
ECC0
ECC1
ECC2
ECC3
DQS8

ECC4
ECC5
ECC6
ECC7

D0
D1
D2
D3

D4
D5
D6
D7
D8
D9

.01UF

50V-20%

2
4
6
8
5
97
94
95
98
99
12
13
19
20
14
107
105
106
109
110
23
24
28
31
25
119
114
117
121
123
33
35
39
40
36
129
126
127
131
133
53
55
57
60
56
149
146
147
150
151
61
64
68
69
67
159
153
155
161
162
72
73
79
80
78
169
165
166
170
171
83
84
87
88
86
177
174
175
178
179
44
45
49
51
47
140
134
135
142
144

.01UF

50V-20%

A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_DQS0_0
A_DQS0_1
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7
A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_DQS1_0
A_DQS1_1
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7
A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_DQS2_0
A_DQS2_1
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7

A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_DQS3_0
A_DQS3_1
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7
A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_DQS4_0
A_DQS4_1
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7
A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_DQS5_0
A_DQS5_1
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7
A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_DQS6_0
A_DQS6_1
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7
A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_DQS7_0

A_DQS7_1
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7
A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_DQS8_0
A_DQS8_1
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7

13-15

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

11,14,16
11,14,16
11,14,16
11,14,16

11,14,16

11,14,16
11,14,16
11,14,16
11,14,16
11,14,16

SSTLREF_D1

C93

2

1

1

C88

2

0.1uF 16V

0.1uF 16V

C77

Y ADDR/CTRL

A DATA

CS1/3

ROOM=DIMM_2B

ROOM=DIMM_1B

A B

1

2

3

CA

+2.5V

B D

+2.5V

ROOM=DDRTERM1

0.1uF 16V

0.1uF 16V

22uF 10V

1

12

C60

21

C65

1
2
3
4
5
6
7
8

UTERM1

VDD_1
VDD_2

VTTFORCE_3
VSS_4
VSS_5

VTTFORCE_6
VDD_7
VSS_8

FAN1655MTF

R47

1.8K-1W-5%

SUB TO 2%

(5% P/N IS OBSOLETE)

NC_16

VRREFOUT

SHDN

VREFIN

VTTSENSE

NC_9

21

SUB_8M268

VDDQ

VSSQ

16
15
14
13
12
11
10
9

R18

12

0.1uF 16V
21

C34

8.2K-5%

0.1uF 16V
22uF 10V

21

C33

4V-20%

12

C47

820uF

+

VTT_SSTL_1

12

C19

13,16

22uF 10V

12

C327

CB269

21

1
2
3
4
5
6
7
8

UTERM2

VDD_1
VDD_2

VTTFORCE_3
VSS_4
VSS_5

VTTFORCE_6
VDD_7
VSS_8

FAN1655MTF

R274

1.8K-1W-5%

SUB TO 2%

(5% P/N IS OBSOLETE)

NC_16

VRREFOUT

VREFIN

VTTSENSE

21

SUB_8M268

VDDQ

VSSQ

SHDN

NC_9

16
15
14
13
12
11
10
9

DDR TERMINATOR +1.25V REGULATORS

X01 -- CHANGED 4 SIGNALS TO OTHER RAIL TO KEEP SOURCE SYNC GROUPS TOGETHER --SWH 10/14

VTT_SSTL_1

13,16

B_SD0_5

1

1

8

RN6

2

7

3

6

4

5

33

1

8

RN10

2

7

3

6

4

5

33

1

8

RN14

2

7

3

6

4

5

33

1

8

RN16

2

7

3

6

4

5

33

1

8

RN21

2

7

3

6

4

5

33

RN24

18

51 OHM-5%

RN24

27

51 OHM-5%

RN24

36

51 OHM-5%

RN24

45

51 OHM-5%

RN27

18

51 OHM-5%

RN27

27

51 OHM-5%

RN27

36

51 OHM-5%

RN27

45

51 OHM-5%

1

8

RN29

2

7

3

6

4

5

33 33

1

8

RN33

2

7

3

6

4

5

33

RN37

18

51 OHM-5%

RN37

27

51 OHM-5%

RN37

36

51 OHM-5%

RN37

45

51 OHM-5%

8

1

RN41

7

2

6

3

5

4

33

1

8

RN42

2

7

3

6

4

5

33

RN49

18

51 OHM-5%

RN49

27

51 OHM-5%

RN49

36

51 OHM-5%

RN49

45

51 OHM-5%

8

1

RN51

7

2

6

3

5

4

33

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

11,14

A_SD0_1
A_SD0_5
A_SD0_0
A_SD0_4

A_SD0_7
A_SD0_6
A_DQS0_0
A_DQS0_1

A_SD1_1
A_SD1_0
A_SD0_3
A_SD0_2

A_DQS1_1
A_DQS1_0
A_SD1_5
A_SD1_4

A_SD1_2
A_SD1_7
A_SD1_6
A_SD1_3

X_MA8

X_MA5

NC_RN6100_6

X_CKE

X_MA11

X_MA9

X_MA7

X_MA12

A_SD2_6
A_SD2_2
A_DQS2_1
A_DQS2_0

A_SD3_4
A_SD3_0
A_SD2_7
A_SD2_3

X_MA3

X_MA2

X_MA4

X_MA6

A_SD8_0
A_SD3_3
A_SD3_6
A_SD3_2

A_SD8_5
A_SD8_1
A_SD8_4
A_SD3_7

X_MA10

X_MA14

X_MA0

X_MA1

A_SD8_7
A_DQS8_0
A_SD8_6
A_DQS8_1

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15

2

11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

3

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

4 4

11,14,15
11,14,15
11,14,15
11,14,15

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

RNB2

33

RNB3

33

RNB5

33

RNB6

33

RNB8

33

RNB10

33

RNB12

33

RNB13

RNB15

33

RNB17

33

RNB19

33

RNB21

33

RNB23

33

RNB27

33

2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

B_SD0_1
B_SD0_4
B_SD0_0

B_SD0_6
B_SD0_2
B_DQS0_1
B_DQS0_0

B_SD1_1
B_SD1_0
B_SD0_3
B_SD0_7

B_DQS1_1
B_SD1_5
B_DQS1_0
B_SD1_4

B_SD1_3
B_SD1_2
B_SD1_7
B_SD1_6

A_SD2_4
B_SD2_1
B_SD2_0
B_SD2_4

A_SD2_1
A_SD2_5
A_SD2_0
B_DQS2_0

B_SD2_6
B_SD2_2
B_DQS2_1
B_SD2_5

B_SD3_4
B_SD3_0
B_SD2_7
B_SD2_3

B_SD3_5
A_SD3_1
A_SD3_5
B_SD3_1

B_DQS3_1
B_DQS3_0
A_DQS3_0
A_DQS3_1

B_SD3_7
B_SD3_3
B_SD3_2
B_SD3_6

B_SD8_1
B_SD8_0
B_SD8_5
B_SD8_4

B_SD8_6
B_SD8_2
B_DQS8_1
B_DQS8_0

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

C194

21

C123

21

12

C148

CB60

21

12

CB119

12

CB53

12

C182

12

C101

12

C166

+80%-20%

.22uF 16V

C115

21

+80%-20%

.22uF 16V

12

C138

+80%-20%

.22uF 16V

CB49

21

+80%-20%

.22uF 16V

12

CB120

+80%-20%

.22uF 16V

12

CB37

+80%-20%

.22uF 16V

12

C188

+80%-20%

.22uF 16V

21

C192

+80%-20%

22uF 10V

C163

21

+80%-20%

.22uF 16V

12

C127

+80%-20%

.22uF 16V

C154

21

+80%-20%

.22uF 16V

12

CB75

+80%-20%

.22uF 16V

CB10912CB102

21

+80%-20%

.22uF 16V

CB80

21

+80%-20%

.22uF 16V

12

C180

+80%-20%

.22uF 16V

+80%-20%

22uF 10V

12

CB124

+80%-20%

.22uF 16V

C132

21

+80%-20%

.22uF 16V

12

C158

+80%-20%

.22uF 16V

CB121

21

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

12

CB24

+80%-20%

.22uF 16V

12

CB91

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

B_SD4_4
B_SD4_0
A_SD8_2
A_SD8_3

A_SD4_1
A_SD4_4
B_SD4_1
A_SD4_0

A_DQS4_1
A_SD4_2
A_DQS4_0
A_SD4_5

B_SD5_5
A_SD4_7
B_SD5_0
A_SD4_6

A_SD5_0
A_SD5_4
A_SD4_3
NC_RN6342.5

A_DQS5_1
A_DQS5_0
A_SD5_1
A_SD5_5

A_SD5_7
A_SD5_3
A_SD5_6
A_SD5_2

A_SD6_5
A_SD6_1
A_SD6_4
A_SD6_0

A_SD6_7
A_SD6_6
A_DQS6_0
A_DQS6_1

A_SD7_0
A_SD7_4
A_SD6_3
A_SD6_2

A_DQS7_1
A_DQS7_0
A_SD7_1
A_SD7_5

A_SD7_3
A_SD7_2
A_SD7_7
A_SD7_6

A B

13,16

VTT_SSTL_2

1

8

RN54

2

7

3

6

4

5

33

1

8

RN55

2

7

3

6

4

5

33

1

8

RN62

2

7

3

6

4

5

33

1

8

RN68

2

7

3

6

4

5

33

1

8

RN73

2

7

3

6

4

5

33

1

8

RN76

2

7

3

6

4

5

33

8

1

RN83

7

2

6

3

5

4

33

1

8

RN88

2

7

3

6

4

5

33

1

8

RN93

2

7

3

6

4

5

33

1

8

RN95

2

7

3

6

4

5

33

1

8

RN101

2

7

3

6

4

5

33

1

8

RN105

2

7

3

6

4

5

33

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

8

RNB35

7
6
5

33

8

RNB36

7
6
5

33

8

RNB38

7
6
5

33

RNB41

51 OHM-5%

RNB41

51 OHM-5%

RNB41

51 OHM-5%

RNB41

51 OHM-5%

8

RNB43

7
6
5

33

8

RNB45

7
6
5

33

8

RNB47

7
6
5

33

8

RNB49

7
6
5

33

8

RNB51

7
6
5

33

8

RNB53

7
6
5

33

8

RNB56

7
6
5

33

1
2
3
4

1
2
3
4

1
2
3
4

18

27

36

45

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

R264

12

8.2K-5%

0.1uF 16V
21

C319

NC_RN6273_1
NC_RN6273_2
B_SD8_7
B_SD8_3

B_DQS4_1
B_SD4_2
B_DQS4_0
B_SD4_5

B_SD5_4
B_SD4_3
B_SD4_7
B_SD4_6

X_MCAS

X_MWE

X_MRAS

X_MA13

B_DQS5_0
B_DQS5_1
B_SD5_1
NC_RN6289.4

B_SD5_7
B_SD5_3
B_SD5_6
B_SD5_2

B_SD6_5
B_SD6_1
B_SD6_4
B_SD6_0

B_DQS6_0
B_SD6_7
B_SD6_6
B_DQS6_1

B_SD7_5
B_SD7_4
B_SD6_3
B_SD6_2

B_SD7_6
B_DQS7_1
B_SD7_1
B_SD7_0

B_SD7_3
B_SD7_2
B_SD7_7
B_DQS7_0

ROOM=DDRTERM2

0.1uF 16V
22uF 10V

21

C321

11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14

11,14

11,14

11,14

11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

11,14,15
11,14,15
11,14,15
11,14,15

12

C322

4V-20%

820uF

+

VTT_SSTL_2

12

C344

21

49.9-1%

21

49.9-1%

21

49.9-1%

21

49.9-1%

21

49.9-1%

21

49.9-1%

21

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

49.9-1%

12

49.9-1%

13,16

R109

R105

R103

R130

R149

R140

R138

R110

R126

R127

R113

R177

R146

R150

R178

R200

R187

R180

R101

21

C293

C222

Y_MA9

Y_MA11

Y_MA12

Y_MA4

Y_MA1

Y_MA2

Y_MA3

Y_MA7

21

Y_MA6

21

Y_MA5

21

Y_MA8

21

Y_MA14

21

Y_MA10

21

Y_MA0

21

Y_MA13

21

Y_MCAS

21

Y_MWE

21

Y_MRAS

21

Y_CKE

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

11,15

C278

CB227

C165

C185

CB152

C246

C199

TITLE

DWG NO.

DATE

EVERGLADES 16 2-26-2003_11:41

DC

12

CB244

+80%-20%

22uF 10V

+80%-20%

22uF 10V

12

CB173

+80%-20%

.22uF 16V

C274

21

+80%-20%

.22uF 16V

12

CB231

+80%-20%

.22uF 16V

CB180

21

+80%-20%

.22uF 16V

12

C153

+80%-20%

.22uF 16V

C250

21

+80%-20%

.22uF 16V

12

C240

+80%-20%

.22uF 16V

CB215

21

+80%-20%

.22uF 16V

EVERGLADES MB

SCHEM,PLNR,PE1750,2XCPU

9T576

2/26/2003

12

+80%-20%

.22uF 16V

21

+80%-20%

.22uF 16V

12

+80%-20%

.22uF 16V

21

+80%-20%

.22uF 16V

12

+80%-20%

.22uF 16V

12

+80%-20%

.22uF 16V

12

+80%-20%

.22uF 16V

21

+80%-20%

.22uF 16V

C262

C284

CB127

C220

C196

CB24512CB204

C25112C259

C209

12

+80%-20%

.22uF 16V

12

CB236

21

+80%-20%

+80%-20%

.22uF 16V

.22uF 16V

CB148

21

21

+80%-20%

+80%-20%

.22uF 16V

.22uF 16V

12

C233

21

+80%-20%

+80%-20%

.22uF 16V

.22uF 16V

12

CB209

21

+80%-20%

+80%-20%

.22uF 16V

.22uF 16V

21

21

12

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

C234

21

+80%-20%

.22uF 16V

16 OF 51

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

+80%-20%

.22uF 16V

REV.

A02-00

1

2

3