MSI MS-9128 Schematic 0920
1
Cover Sheet
Block Diagram
Revision History 1 - 3
Intel mPGA478B CPU - Signals
1
2
3 - 5
6
VISE (MS-6715)
Intel (R) Springdale (GMCH) + ICH5 Chipset
Version 0AED
09/12/2002 Initial
Intel Northwood & Prescott mPGA478B Processor
Intel mPGA478B CPU - Power
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP & LDT Signals
Intel ICH5 - PCI & IDE & AC97 Signals
Intel ICH5 - Other Signals
Clock - Cypress CY28405 & FWH & Manual
LPC I/O - LPC47B387
AC97 Audio - AD1981B
7
8
9
10
11
12
13
14
15
CPU:
Intel Northwood/Prescott - 3.0G & Above
System Chipset:
Intel Springdale - GMCH (North Bridge)
Intel ICH5 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
AC'97 Codec -- AD1981B
LPC Super I/O -- LPC47B387
A A
Broadcom BCM5702
DDR System Memory 1 & 2
DDR System Memory 3 & 4
16
17
18
LAN -- CSR Interface
CLOCK -- Cypress CY28405
H/W Monitoring -- ADM1027
AGP 4X/8X Slot & PCI Riser Card
PCI Slots 1 & 2 & 3
ATA33/66/100 IDE & Video Connectors
USB & LAN Connectors
H/W Monitor & FAN
ATX & Front Panel
AGP & MEMORY & USB Regulator Controller
VCC_DAC & VTT Regulator & VR Thermal
VRM 10 - Intersil HIP 6556B + HIP 6602B
PULL UP/ DOWN RESISTORS
GPIO
19
20
21
22
23
24
25
26
27
28
29
Main Memory:
DDR2700 * 4 (Max 4GB)
Expansion Slots:
PCI2.3 SLOT * 3
AGP4X/8X SLOT * 1
Intersil PWM:
Controller: HIP6556B
Driver: HIP6602B * 2
Regulators
System : FAN5236
1
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
COVER SHEET
VISE (MS-6715)
of
131Friday, September 20, 2002
0AED
1
VRM 10
Intersil 6556
Intel mPAG478B Processor
Block Diagram
4-Phase PWM
FSB
64bit DDR
133/166MHz@2.1/2.7GB/s
4 DDR
DIMM
Modules
AGP 1.5V
Connector
Analog
133/166MHz@4.2/4.5GB/s
4X/8X w/Fast Write
66MHz@2.1GB/s
Springdale
Video
Out
HCT
ICH5
Link
PCI CNTRL
PCI ADDR/DATA
33MHz@133MB/s
PCI Slot 1
PCI Slot 2
PCI Slot 3
66MHz@266MB/s
UltraDMA
IDE Primary
IDE Secondary
A A
USB Port 0
33/66/100/133
44.44MHz(W)/50MHz(R)@88.9/100MB/s
USB Port 1
USB Port 2
USB Port 3
USB Port 4
USB
240MHz@60MB/s
LPC Bus
33MHz@16.5MB/s
LPC SIO
USB Port 5
SMSC
LPC47B387
USB Port 6
USB Port 7
AD1981B
AC'97 Codec
GIGA LAN
BCM5702
AC'97 Link
12.288MHz@1.536MB/s
PCI
33MHz@133MB/s
Flash
Keyboard
Mouse
1
Floopy Parallel Serial
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
BLOCK DIAGRAM
VISE (MS-6715)
231Friday, September 20, 2002
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0AED
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Revision Initial ver: 0AE0 on 07/31/2002
Schematic Initial on July 31.
Revision change list from ver: 0AE0 to ver: 0AE1 on 08/01/2002
Sheet 1: Modify some txts.
Sheet 2: Modify some txts.
Sheet 16: Move Lan connector to page 26.
D D
Sheet 25: Modify some block for customer request, detail list on below:
(1) Modify 5v USB power supplier.
(2) Modify 5V main power circuit.
(3) Modify GMCH VTT voltage supplier.
(4) Add GMCH VTT reference voltage circuit.
Sheet 26: Modify some block for customer request, detail list on below:
(1) Modify 3V standby power supplier.
(2) Change VTT_DDR to LP2995.
(3) Add lan magnetic circuit.
(4) Modify Lan connector.
(5) Add 1.5V standby voltage.
Revision change list from ver: 0AE1 to ver: 0AE2 on 08/09/2002
Sheet 8: Change VTT_FSB to capacitors termination on pin A15 and A21.
Sheet 9: Change VCC_DDR to capacitors termination on pin
C C
E35,E35,AA35,AR21 and AR15.
Sheet 27: Change some bulk caps from 2200uF to 560uF.
Revision change list from ver: 0AE2 to ver: 0AE3 on 08/13/2002
Sheet 12: Modify some block for customer request, detail list on below:
(1) Delete GP14 and GP15 on pin U21 and pin T20 on ICH5.
(2) Add CHASIS_ID2 on pin V3 on ICH5.
(3) Delete USB6+, USB6-, USB7+, and USB7-.
(4) Change FRONT_USB_DET# from pin C13 to pin D13 on ICH5.
Sheet 13: Modify some block for customer request, detail list on below:
(1) Modify clock generator library.
(2) Change PCI clock label.
(3) Add strapping resistors.
Sheet 17: Delete some caps on VCC_DDR.
Sheet 18: Delete some caps on VCC_DDR.
B B
Sheet 19: Delete some AGP termination resistors.
Sheet 20: Change PCI clock label.
Sheet 22: Modify some block for customer request, detail list on below:
(1) Delete 2 ports USB, and one USB power.
(2) Removed LAN connector to here.
Sheet 24: Modify some block for customer request, detail list on below:
(1) Change from GP14 to NC on pin 10 of F_P1.
(2) Change from NC to CHASIS_ID2 on pin 15 of F_P1.
(3) Change from GP15 to CHASIS_ID0 on pin 17 of F_P1.
(4) Change from GND to CHASIS_ID1 on pin 18 of F_P1.
(5) Pull VCC3_SB to pin C13 on ICH5.
Sheet 27: Modify some block for customer request, detail list on below:
(1) Change R473 from 1Kohm to NC.
A A
(2) Change R475 from 0 ohm to NC.
(3) Change some bulk caps from 2200uF to 560uF.
Sheet 28: Delete R89,R90,R91, and R92.
5
4
3
Revision change list from ver: 0AE3 to ver: 0AE4 on 8/14/2002
Sheet 13: Modify clock generator library.
Sheet 14: Modify some block for customer request, detail list on below:
(1) Change SERIAL PORT 2 connector to 10 pin center-keyed shrouded header.
(2) Add TI GD75232.
(3) Change label PS_ON to PS_ON#.
Sheet 15: Modify some block for customer request, detail list on below:
(1) Delete Q7,Q8,Q10,Q11,Q12,Q34.
(2) Modify this page same as reference schematic.
Sheet 17: Exchange pin 103 and pin 167 on DIMM1 and DIMM2.
Sheet 18: Exchange pin 103 and pin 167 on DIMM3 and DIMM4.
Sheet 21: Modify some block for customer request, detail list on below:
(1) Add 33 ohm series resistors on Data 15:0 on Primary IDE.
(2) Add 33 ohm series resistors on Data 15:0 on Secondary IDE.
(3) Delete U12, NC7WZ08.
Sheet 24: Modify some block for customer request, detail list on below:
(1) Delete Q31, R376, R377,and R378.
(2) Change label PS_ON to PS_ON#.
(3) Delete U12, NC7WZ08.
Sheet 25: Change Q25 from 2N3904 to 2N7002.
Revision change list from ver: 0AE4 to ver: 0AE5 on 08/16/2002
Sheet 6: Modify some block for customer request, detail list on below:
(1) All TESTHI pull up resistors change from 51ohm to 62ohm.
(2) Delete OPTIMZ label.
Sheet 7: Modify some block for customer request, detail list on below:
(1) Delete EC1 and EC2.
(2) Change L1 and L2 from 4.7uH to 10uH.
Sheet 8: Modify some block for customer request, detail list on below:
(1) Separate from VCCA_FSB and add 0.1uF cap to GND on pin A31.
(2) Change C225 from 0.22uF to 0.47uF.
Sheet 10: Modify some block for customer request, detail list on below:
(1) Add 2pins header to pin T20.
(2) Change pin D14 and C14 to OC#2 signal.
(3) Change label OC#2 to OC#3.
(4) Change label OC#3 to OC#7.
(5) Add label CI_VREF and CI_SWING to pin AF4 and AF2.
(6) Delete R65 on pin AG10.
Sheet 11: Modify some block for customer request, detail list on below:
(1) Add 0.1uF cap to pin F19.
(2) Add 0.1uF cap to pin Y5, AA4 and AB4.
(3) Add 0.1uF cap to pin F7 and F8.
Sheet 12: Modify some block for customer request, detail list on below:
(1) Change R102 from 0ohm to 10Kohm.
Sheet 13: Modify some block for customer request, detail list on below:
(1) Change R154 and R152 from 300ohm to 330ohm.
(1) Change R151 from 2Kohm to 2.2Kohm.
Sheet 15: Modify some block for customer request, detail list on below:
(1) Add 47ohm resistor to AC_SDIN0.
(2) Change R199 from 10ohm to 47ohm and add 47pF cap.
(3) Change R219 and R209 from 4.7Kohm to 100ohm.
(4) Change R202, R203, R207, R208 from 6.8Kohm to 4.7Kohm.
(5) Add divide 1Kohm pull down resistor to OUT_R and OUT_L signals.
(6) Delete C71.
4
3
2
1
Revision change list from ver: 0AE4 to ver: 0AE5 on 08/16/2002
Sheet 17: Modify some block for customer request, detail list on below:
(1) Add two 75 ohm divide resistors in DDR_VREF.
(2) Change 110ohm to 56ohm on Rterm array resistors.
(3) Add two divide 75ohm resistors pin 1.
Sheet 18: Modify some block for customer request, detail list on below:
(1) Add two 75 ohm divide resistors in DDR_VREF.
(2) Change 110ohm to 56ohm on Rterm array resistors.
(3) Add two divide 75ohm resistors pin 1.
Sheet 20: Modify some block for customer request, detail list on below:
(1) Add 2pins header for support Prochot latch.
Sheet 21: Modify some block for customer request, detail list on below:
(1) Change R299 and R295 from 4.7Kohm to 8.2Kohm.
Sheet 22: Modify some block for customer request, detail list on below:
(1) Add one usb power circuit to seperate port 0,1 and 2,3.
(2) Change R315 and R313 from 21Kohm to 470Kohm.
(3) Change R320 and R319 from 51Kohm to 560Kohm.
(4) Change C134 from 470pF to 1000pF.
Sheet 24: Modify some block for customer request, detail list on below:
(1) Change R380 from 330ohm to 68ohm.
Sheet 27: Modify some block for customer request, detail list on below:
(1) Change CT41-CT44 from 2200uF to 560uF.
Sheet 28: Modify some block for customer request, detail list on below:
(1) Change label OC#3 to OC#7.
(2) Add some divide resistors to CI_VREF and CI_SWING signals.
(3) Change R1 from 100ohm to 200ohm and add a 200ohm resistor pull to VTT voltage.
(4) Delete R14. and ITP_VCC direct connect to Vccp.
(5) Change BPM# from 51ohm to 62ohm.
(6) Change R30 from 220ohm to 200ohm.
(7) Add two 0ohm resistors to support ITP or USB_ITP port.
(6) Change R17 from 27ohm to 47ohm.
Revision change list from ver: 0AE5 to ver: 0AE6 on 08/19/2002
Sheet 25: Modify some block for customer request, detail list on below:
(1) Add 300 ohm resistor from BOOT to VCC_VID and change R423 to 10Kohms.
(2) Change R411 and R415 to 3V_SW_CTRL# signal.
Sheet 27: Modify some block for customer request, detail list on below:
(1) Add Northwood FB network and Prescott FB network to VRM controlled by BOOT.
(2) Change 110ohm to 56ohm on Rterm array resistors.
(3) Change R460,R464,R467,and R470 from 2.83Kohm to 3.3Kohm.
Sheet 28: Add teo 10Kohm pull down resistors to RSMRST# and ICH_GD signals.
Revision change list from ver: 0AE6 to ver: 0AE7 on 08/20/2002
Sheet 13: Modify some block for customer request, detail list on below:
(1) Change R495 from ICHPCLK to LANPCLK signal.
(2) Change R496 from FWHPCLK to PCICLK0 signal.
(3) Change R497 from LANPCLK to PCICLK1 signal.
Sheet 16: Delete CB89,CB90,CB88,CB114, CB117, and CB118.
Sheet 17: Change all component from 0603 to 0402.
Sheet 18: Change all component from 0603 to 0402.
MSI
Title
Size Document Number Rev
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
REVISION HISTORY - 1
VISE (MS-6715)
1
331Friday, September 20, 2002
0AED
of
5
Revision change list from ver: 0AE7 to ver: 0AE8 on 08/21/2002
Sheet 7: Change some caps of north side to not install.
Sheet 12: Modify some block for customer request, detail list on below:
(1) Add LPC_DRQ#1 label on pin R2 on ICH5.
(2) Change pin Y12 from INTRUDER# to HOOD_SENSE#.
Sheet 13: Modify some block for customer request, detail list on below:
D D
(1) Remove R143 and R142. Connect FWH RST# signal directly to PCIRST#.
(2) Delete R154,Q5,Q3, and R151.
(3) Change R152 from 330 ohm to 8.2K ohm.
(4) Add one resistor to SEC_PCLK signal and share with SIO_PCLK.
(5) Delete INIT# BLOCK.
Sheet 14: Modify some block for customer request, detail list on below:
(1) Change pin 44 to BRD_V1.
(2) Change pin 45 to MB_ADPT_DET#.
(3) Change pin 47 to SEC_TPM_PRES.
(4) Change pin 49 to MB_ADPT_DET#.
(5) Change pin 54 to FDD_2M.
(6) Add pin 104 to 5V_IN.
Sheet 18: Change all component from 0603 to 0402.
Sheet 20: Modify some block for customer request, detail list on below:
C C
(1) Change TAP resistors from 4.7Kohm to 2.2Kohm.
(2) Add a 2.2Kohm pull down resistor to PCIRST#1.
Sheet 24: Add Security header.
Sheet 25: Change VCC5 & VCC3 Discharge Residual Voltage same as reference schematic.
Revision change list from ver: 0AE8 to ver: 0AE9 on 08/23/2002
Sheet 16: Support BCM4401.
Sheet 20: Modify some block for customer request, detail list on below:
(1) Delete CT17.
(2) Change CT16 from intall to not install.
Sheet 23: Delete CB284 and R324.
Sheet 27: Change R456,R466,R479, and R489 from 1 ohm/1206 to 4.7ohm/0805.
Revision change list from ver: 0AE9 to ver: 0AEA on 08/26/2002
Sheet 11: Change Label from VCC3_SB to 3VSB.
Sheet 13: Modify some block for customer request, detail list on below:
B B
(1) Change Label from PCIRST# to PCIRST_ICH5#.
(2) Change all pull high resistors of clock generator from VCC3V to VCC3.
Sheet 14: Modify some block for customer request, detail list on below:
(1) Change Label from VCC3_SB to 3VSB.
(2) Change pin 45 to GP25 and add a 4.7Kohm resistor to VCC3 on GP25.
(3) Add a label SYSMAG_INT on pin 61.
(4) Change pin 44 to MB_ADPT_DET#.
(5) Change pin 49 to SEC_TPM_PRES.
Sheet 15: Modify some block for customer request, detail list on below:
(1) Delete R514, R515, C81, C86, C88, C89.
(2) Change R211 & R216 to 0 ohm.
(3) Change C82 & C84 to 4.7uF.
(4) Change R209 & R219 to 4.7K.
A A
(5) Add 0.22uF and 4.12K in series to pin1 of Front Audio Header.
(6) Add label bias circuit to pin 3 of Front Audio Header.
(7) Add X_330 ohm from OUT_L to junction of C218 & R504.
Sheet 16: Change Label from VCC3_SB to 3VSB.
Sheet 21: Change Label from VCC3_SB to 3VSB.
Sheet 22: Change Label from VCC3_SB to 3VSB.
5
4
Revision change list from ver: 0AE9 to ver: 0AEA on 08/26/2002
Sheet 23: Modify some block for customer request, detail list on below:
(1) Change H/W monitoring circuit.
(2) Change Fan circuit.
Sheet 24: Change Label from VCC3_SB to 3VSB.
Sheet 25: Change Label from VCC3_SB to 3VSB.
Sheet 26: Change Label from VCC3_SB to 3VSB.
Sheet 27: Change Label from VCC3_SB to 3VSB.
Sheet 28: Change Label from VCC3_SB to 3VSB.
Revision change list from ver: 0AEA to ver: 0AEB on 09/03/2002
Sheet 6: Change CPU Symbol - pin F6=GTLREF3, pin F20=GTLREF2, pin
AA6=GTLREF1, pin AA21=GTLREF0.
Sheet 9: Modify some block for customer request, detail list on below:
(1) Disconnect U28 pin E34 (GMCH) directly to VREF.
(2) Add a 2.2uF cap to this pin E34.
Sheet 13: Modify some block for customer request, detail list on below:
(1) Change R135 & R139 from 1K to 10K.
(2) Add pullup resistor from BSEL0 to VCC3.
(3) Add pullup resistor from BSEL1 to VCC3.
Sheet 21: Change FB16, FB18 & FB20 to be the same as FB17, FB19 & FB21.
Sheet 25: Modify some block for customer request, detail list on below:
(1) Change Q40 & Q41 to Depletion Mode JFETs.
(2) Connect R400 to -12V.
(3) Change R399 to a 39 ohm RNET and connect in parallel to VCC5.
(4) Change R405 to a 39 ohm RNET and connect in parallel to VCC3.
(5) Move R417 from Drain of Q51 to Source.
(6) Change R417 from 150 to 866 ohms.
(7) Change R425 from 150 to 634ohms.
(8) Change R426 from 150 to 499 ohms.
Sheet 28: Change R46 & R50 to 150 ohms 1%.
Revision change list from ver: 0AEB to ver: 0AEC on 09/09/2002
Sheet 7: Delete 0.1uF caps on CPU side.
Sheet 8: Change R41 from 24.9ohm to 20ohm.
Sheet 9: Modify some block for customer request, detail list on below:
(1) Disconnect U2 pin AR31 (GMCH).
(2) Disconnect U2 pin AL35 (GMCH) and add single cap to it.
Sheet 17: Delete decoupling caps between VCC_DDR and VTT_DDR.
3
2
1
Revision change list from ver: 0AEC to ver: 0AED on 09/12/2002
Sheet 14: Modify some block for customer request, detail list on below:
(3) Swap net BRD_V1 and FAN_CLAMP.
(2) Delete R551, and change net 5V_IN to COMM_B_DET#.
Sheet 15: Modify some block for customer request, detail list on below:
(1) Change R196 to 3.3Kohm.
(2) Add a 270pF cap to GND and AGND, not install.
(3) Add a 1uF caps to MONO_L and MONO_L_R.
(4) Add a 1uF caps to MONO_R and MONO_R_R.
(5) Change R501 and R555 to 130ohm.
(6) Change C218 from 4700pF to 0.01uF.
Sheet 17: Change net DDR_VREF to DDR_VREF1.
Sheet 18: Change net DDR_VREF to DDR_VREF2, and add two resistors.
Sheet 23: Modify some block for customer request, detail list on below:
(1) Modify H/W monitoring and FAN controller.
(2) Change U13 pin 22 from VCC_DDR to No Connect.
Sheet 24: Add PROCHOT# LED.
Sheet 25: Modify some block for customer request, detail list on below:
(1) Delete R394 and R401.
(2) Change C166 to 0.01uF.
(3) Change Q38 pin 5 and pin 6 to VCC5_STR.
(4) Change Q39 pin 5 and pin 6 to VCC3.
(5) Change Q38 pin 3 to PHASE_2V5.
(6) Change Q39 pin 3 to PHASE_1V5.
(7) Change DZ5 to VCC5.
(8) Change U15 pin 15 and 16 to VCC5_STR.
Sheet 26: Modify some block for customer request, detail list on below:
(1) Add VR THERMAL BLOCK.
(2) Add ICH5 VCCSUS1_5A, B, and C voltage regulatot to support this version fail
chipset.
Sheet 28: Modify some block for customer request, detail list on below:
(1) Delete R35, IERR#.
(2) Change net GPI12 to PS_DETECT.
(3) Change net GPI7 to PROC_HOT#.
(4) Add Thermtrip Translation Block.
(5) Change RN3 pin 2 to No Connect.
(6) Delete C36, C37, and R100.
(7) Delete net RTC_XI.
Sheet 18: Delete decoupling caps between VCC_DDR and VTT_DDR.
Sheet 21: Change all arrary resistors from 0603 to 0402 on all IDE.
Sheet 22: Add secondary transformer to support 10M and 100M NIC.
Revision change list from ver: 0AEC to ver: 0AED on 09/12/2002
Sheet 6: Modify some block for customer request, detail list on below:
(1) Disconnect CPU1 pin AC3, IERR# signal.
(2) Add a pull down resistor to CPU1 pin AE26, OPTIMIZ signal, and not install.
Sheet 7: Change R36 from 1Kohm to 2.43Kohm.
Sheet 11: Add RN91 to support VCCSUS1_5A,B,C voltage for ICH5.
Sheet 12: Modify some block for customer request, detail list on below:
(1) Change net GPI12 to PS_DETECT.
(2) Add net FAN_CMD to pin U20.
(3) Change net GPI7 to PROC_HOT#.
(4) Change R102 to 390Kohm, not install ,and a resistor to GND.
(5) Delete net RTC_XI.
Sheet 14: Modify some block for customer request, detail list on below:
(1) Change net TRMTRIP# to SIO_TRMTRIP#.
(2) Delete R551, and change net 5V_IN to COMM_B_DET#.
4
3
2
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
REVISION HISTORY - 2
VISE (MS-6715)
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B B
A A
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
REVISION HISTORY - 3
VISE (MS-6715)
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CPU SIGNAL BLOCK
HA#[3..31]8
D D
HA#10
HA#14
A15#
D30#
J24
A14#
D29#
HA#13
HA#12
A13#
D28#
L22
M21
A12#
D27#
HA#11
A11#
D26#
H24
G26
A10#
D25#
HA#9
A9#
D24#
L21
HA#8
A8#
D23#
D26
HA#7
A7#
D22#
F26
HA#6
A6#
D21#
E25
HA#5
A5#
D20#
F24
HA#4
A4#
D19#
F23
HA#3
A3#
D18#
G23
D17#
E24
AE25A5A4
DBR#
D16#
D15#
H22
D25
VCC_SENSE
D14#
D13#
J21
D23
C26
AD26
AC26
ITP_CLK1
ITP_CLK0
VSS_SENSE
D12#
D11#
D10#
D9#
H21
G22
B25
C24
VID5
AD2
AD3
VID5#
VIDPWRGD
D8#
D7#
D6#
C23
B24
VID4
AE1
VID4#
D5#
D22
VID3
AE2
VID3#
D4#
C21
VID2
AE3
VID2#
D3#
A25
VID1
AE4
A23
HA#17
HA#20
HA#22
A30#
D45#
HA#29
HA#28
A29#
D44#
T26
R24
A28#
D43#
HA#26
HA#27
A27#
D42#
R25
P24
A26#
D41#
HA#24
HA#25
A25#
D40#
R21
N25
A24#
D39#
HA#23
A23#
D38#
N26
M26
HA#30
HA#31
CPU1A
HDBI#[0..3]8
FERR#12
STPCLK#12
HDBI#0
HDBI#1
HDBI#2
HDBI#3
HINIT#12
HDBSY#8
HDRDY#8
HTRDY#8
HADS#8
HDEFER#8
ITP_TRST#29
THERMDP#24
THERMDN#24
TRMTRIP#24,29
SKTOCC#14
PROCHOT#8,24,25
HLOCK#8
HBNR#8
HIT#8
HITM#8
HBPRI#8
ITP_TDI29
ITP_TDO29
ITP_TMS29
ITP_TCK29
IGNNE#12
SMI#12
A20M#12
SLP#12
BOOT26,28
R627 X_0
BSEL08,13
BSEL18,13
OPTIMIZ
C C
B B
CPU_GD12,29
CPURST#8,29
HD#[0..63]8
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
A32#
A31#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
V22
U21
V25
U23
U24
U26
T23
T22
T25
A22#
D37#
HA#21
A21#
D36#
N23
M24
HA#19
A20#
D35#
P21
A19#
D34#
HA#18
A18#
D33#
N22
M23
A17#
D32#
HA#16
HA#15
A16#
D31#
H25
K23
ITP_DBR# 29
VCC_SENSE 28
VSS_SENSE 28
VID_GD 7
VID[0..5] 24,28
VID0
AE5
VID1#
VID0#
GTLREF0
GTLREF1
GTLREF2
GTLREF3
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D2#
D1#
D0#
NORTHWOOD/PRESCOTT
B22
B21
{Priority}
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
GTLREF
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI2
TESTHI1
TESTHI0
HRS#2
HRS#1
HRS#0
COMP1
COMP0
GTLREF 8,29
C2 220p_X7R
{VOLTAGE}
BPM#5 29
BPM#4 29
BPM#3 29
BPM#2 29
BPM#1 29
BPM#0 29
R3 62
R4 62
R5 62
R6 62
R7 62
R9 62
R624 62
R10 62
CPU_CLK# 13
CPU_CLK 13
HBR#0 8,29
R13 61.9RST
R15 61.9RST
HADSTB#1 8
HADSTB#0 8
HDSTBP#3 8
HDSTBP#2 8
HDSTBP#1 8
HDSTBP#0 8
HDSTBN#3 8
HDSTBN#2 8
HDSTBN#1 8
HDSTBN#0 8
NMI 12
INTR 12
HREQ#[0..4] 8
VCCP
HRS#[0..2] 8
HD#49
HD#48
HD#46
HD#47
HD#44
HD#45
6
HD#43
HD#42
HD#41
HD#38
HD#39
HD#37
HD#36
HD#34
HD#35
HD#32
HD#33
HD#53
HD#50
HD#51
A A
8
7
HD#52
HD#40
HD#30
HD#31
HD#29
HD#28
HD#26
HD#27
HD#24
HD#25
5
HD#22
HD#23
HD#21
HD#20
HD#18
HD#19
HD#16
HD#17
HD#15
HD#14
HD#13
HD#12
HD#10
HD#11
HD#9
HD#8
HD#7
HD#6
4
HD#5
HD#4
HD#3
HD#2
HD#1
HD#0
MSI
Title
Size Document Number Rev
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Intel mPGA478B - Signals
VISE (MS-6715)
2
631Friday, September 20, 2002
1
0AED
of
8
7
6
5
4
3
2
1
U1
AF7
D14
VID_GD6,13
VCC
VSS
AF9
D16
VIDGD rising time is 150ns.VID to VIDGD deassertion time is 1ms for max.
B11
VCC
VSS
D18
1
3
2
B13
B15
B17
B19B7B9
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
D20
D21D3D24D6D8E1E11
VIN
GNDENPOK
SN105125-150mA-N
{Priority}
VCC
VCC
VSS
VSS
VCC3
AE6
VCC
VSS
C15
VCC
VSS
AE8
AF11
VCC
VSS
C17C2C19
CB336 0.1u_Y5V
AF13
AF15
AF17
AF19
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
C22
C25C5C7C9D12
VCC
VSS
AF2
VCC
VSS
AF21
VCC
VSS
AF5
VCC
VSS
CPU VOLTAGE BLOCK
VID Voltage is from 1.14V to 1.32V.
It is derived from 3.3V.
D D
VCCP
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
VCC
VSS
AE9
VCC
VSS
AF1
VCC
VSS
VCC
VSS
AF10
VCC
VSS
AF12
VCC
VSS
AF14
AC14
AF16
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
AE13
VSS
AE15
VSS
AE17
VSS
AE19
VSS
AE22
VCC
VSS
AE24
AE7
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
C C
B B
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
VSS
AD12
VSS
AD14
VSS
AD16
VSS
AD18
VSS
AD21
VSS
AD23
AD4
VSS
AD8
VSS
VSS
AE11
It should be able to source 150mA.
It drives the power logic of BSEL[1:0] and VID[5:0]. It must rout to the enable pin of PWM and CK-409.
VID to VIDGD delay time is from 1ms to 10ms. VIDGD to Vccp delay time is from 1ms to 10ms.
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B23
B20
B26B4B8
C11
C13
C10
VCC
VSS
C12
VCC
VSS
VOUT
C14
VCC
VSS
E13
C16
E15
C18
VCC
VSS
E17
5
4
C20C8D11
VCC
VCC
VSS
VSS
E19
E23
VCC
VSS
D13
D15
VCC
VCC
VSS
VSS
E7E9F10
E4
E26
R36
2.43KST
D17
VCC
VCC
VSS
VSS
D19D7D9
VCC
VCC
VSS
VSS
F12
E10
VCC
VCC
VSS
VSS
F14
F16
VCC_VID
C4
1u-0805_Y5V
E12
E14
E16
E18
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
F18F2F22
F25F5F8
E20E8F11
VCC
VCC
VSS
VSS
F13
VCC
VSS
G21G6G24
Near processorNear regulator
F15
F17
VCC
VCC
VCC
VSS
VSS
VSS
G3H1H23
C5
0.1u_Y5V
F19
F9
VCC
VCC
VSS
VSS
H26H4J2
AF4
VCC-VID
VSS
VSS
1.2V 150mA
VCC_VID
AE23
AD20
AF3
VCCA
VCC-IOPLL
VCC-VIDPRG
VSS
VSS
VSS
VSS
VSS
J22
J25J5K21
NORTHWOOD/PRESCOTT
{Priority}
CPU_IOPLL
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
EC3
22u-1206_Y5V
{VOLTAGE}
VSSA
It must close bulk caps.
It support DC current if 100mA.
L1 4.7uH-1206
L2 4.7uH-1206
EC4
10u-1206_Y5V
{VOLTAGE}
DC voltage drop should
be less than 70mV.
VCCP
CPU DECOUPLING CAPACITORS
VCCP
EC5
22u-1206_Y5V
EC13
22u-1206_Y5V
EC21
22u-1206_Y5V
EC28
22u-1206_Y5V
EC35
A A
22u-1206_Y5V
EC42
22u-1206_Y5V
Place these caps within socket cavity Place these caps within south side of processor
8
VCCP VCCP VCCP VCCP VCCP VCCPVCCP
EC6
22u-1206_Y5V
EC14
22u-1206_Y5V
EC22
22u-1206_Y5V
EC29
22u-1206_Y5V
EC36
22u-1206_Y5V
EC43
22u-1206_Y5V
7
EC37
22u-1206_Y5V
EC15
22u-1206_Y5V
EC23
22u-1206_Y5V
EC30
X_22u-1206_X5R-N
EC7
X_22u-1206_X5R-N
EC44
X_22u-1206_X5R-N
Place these caps within north side of processor
6
EC8
22u-1206_Y5V
EC32
22u-1206_Y5V
EC39
22u-1206_Y5V
EC31
22u-1206_Y5V
EC17
22u-1206_Y5V
EC45
22u-1206_Y5V
5
EC9
X_22u-1206_X5R-N
EC38
X_22u-1206_X5R-N
EC25
X_22u-1206_X5R-N
EC16
X_22u-1206_X5R-N
EC24
X_22u-1206_X5R-N
EC46
X_22u-1206_X5R-N
EC10
22u-1206_Y5V
EC18
22u-1206_Y5V
EC26
22u-1206_Y5V
EC33
22u-1206_Y5V
EC40
22u-1206_Y5V
4
EC11
22u-1206_Y5V
EC19
22u-1206_Y5V
EC27
22u-1206_Y5V
EC34
22u-1206_Y5V
EC41
22u-1206_Y5V
3
820u/2.5V properly in further
+
EC12
150u-2.5V
{Priority}
+
EC20
150u-2.5V
MSI
{Priority}
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Intel mPGA478B - Power
VISE (MS-6715)
2
731Friday, September 20, 2002
of
1
Solder side
Title
Size Document Number Rev
Date: Sheet
0AED
8
VCCA_FSB29
VCCA_DPLL29
HA#3
HA#[3..31]6
D D
C C
HADSTB#06
HADSTB#16
HBR#06,29
HBPRI#6
HBNR#6
HLOCK#6
HADS#6
HREQ#[0..4]6
HIT#6
HITM#6
HDEFER#6
HTRDY#6
HDBSY#6
HDRDY#6
HRS#[0..2]6
B B
MCH_CLK13
MCH_CLK#13
PWRGDA14
CPURST#6,29
PCIRST_ICH5#11
PROCHOT#6,27,29
R37 2.49KST
BSEL0
BSEL1
R38 2KST
R39 2KST
R40 2.49KST
R41 20RST
HSWING29
GTLREF6,29
220p_X7R
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
ICH_SYNC#
SEL0
SEL1
HRCOMP
C6
AE14
D26
D30
E29
B32
K23
C30
C31
B31
E30
B33
F25
D34
C32
F28
C34
G27
F29
E28
H27
K24
E32
F31
G30
G26
B30
D28
B24
B26
B28
E25
F27
B29
C29
K21
E23
D24
E27
G24
G22
C27
B27
AK4
AJ8
E24
C25
F23
VCCA_FSB
C224 0.1u_Y5V
VCCA_DPLL
U2A
HA3#
HA4#
L23
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
J25
HA11#
HA12#
HA13#
HA14#
J24
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
J27
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
J26
HA30#
HA31#
HAD_STB0#
HAD_STB1#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
J23
HREQ1#
L22
HREQ2#
HREQ3#
J21
HREQ4#
HIT#
HITM#
L21
DEFER#
HTRDY#
DBSY#
DRDY#
RS0#
RS1#
RS2#
B7
HCLKP
C7
HCLKN
PWROK
E8
CPURST#
RSTIN#
ICH_SYNC#
L20
PROCHOT#
L13
BSEL0
L12
BSEL1
HDRCOMP
HDSWING
HDVREF
7
B3
VCCA_DPLL
A31
B4
J6J7J8J9K6K7K8K9L6L7L9
VCC
VCCA_FSB
VCCA_FSB
VSS
VSS
VSS
VSS
VSS
C12
C14
C16
C18
C10
C8
VCC
VSS
C20
VCC
VSS
C22
VCC
VSS
C24
VCC
VSS
C26
VCC
VCC
VCC
VSS
VSS
VSS
C28D1D11
6
VCC_AGP VTT
N11N9P10
P11
R11
T16
T17
T18
VCC
VSS
D35
VCC
VSS
T19
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
F3F5F8
E3
F1
E1
N10
M10
M11M8M9
L10
L11
VCC
VCC
D19
VCC
VSS
D21
VCC
VSS
D23
VCC
VSS
D25
VCC
VSS
D27
VSS
D29
VCC
VSS
D31
VSS
D33
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
D13
D15
D17
D9
VCC
VSS
5
U16
U17
U20
V16
V18
V20
W16
W19
W20
Y16
Y17
Y18
Y19
VCC
VSS
Y20
A3
A33
A35B2B25
VCC
VCC
VSS
VSS
F26
G28
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G31
G35
H12
H14
H5
H8
H9
T20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
F10
VCC
VSS
VSS
VSS
VSS
VSS
VSS
F18
F20
F22
F24
F14
F16
F12
VSS
VSS
H16H2H20
H18
B34C1C23
VSS
VSS
H22
VSS
H24
VSS
4
C35
H26
VSS
E26
H30
VSS
M31
H33
VSS
R25
J10
NC
VSS
AF13
VSS
J12
AF23
VSS
J14
AJ12
VSS
J16
AN1
J18
VSS
AP2
J20
VSS
AR3
J22
VSS
AR33
VSS
J28
AR35
VSS
J32
A7A9A11
VSS
J35
K11
VSS
VSS
3
D5D6D7E6E7
F7
VTT
VSS
VTT
VSS
L31
VTT
VSS
M3M6M26
L35
VTT
VSS
A4A5A6B5B6C5C6
VTT
VTT
VSS
VSS
M27
A13
A16
A20
A23
A25
A27
A29
A32
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K12
K14
K16
K18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K33
K20
K22
K25
K27
K29
L24
L25
L26
VTT
VSS
VTT
VSS
M28
VTT
VSS
M30
VTT
VSS
M33N1N4
2
A15
VTT
VTT
VTT
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
VSS
VSS
Intel Springdale-N
{Priority}
VTT_FSB1
VTT_FSB2
A21
HD0#
HD1#
HD2#
HD3#
VTT_FSB
VTT_FSB
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8
C17
L17
L14
C15
B19
C19
L19
K19
G9
F9
D12
E12
C225 0.47u_Y5V
C226 0.47u_Y5V
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HDBI#0
HDBI#1
HDBI#2
HDBI#3
1
{VOLTAGE}
HD#[0..63] 6
HDBI#[0..3] 6
HDSTBP#0 6
HDSTBN#0 6
HDSTBP#1 6
HDSTBN#1 6
HDSTBP#2 6
HDSTBN#2 6
HDSTBP#3 6
HDSTBN#3 6
A A
PWRGDA14
8
PWRGDA
ICH_SYNC#
VCC3
53
1
4
2
U28
X_NC7WZ08
7
ICH_GD 12
6
PWRGDA ICH_GD
R526 0
5
4
3
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Intel Springdale - CPU Signals
VISE (MS-6715)
2
831Friday, September 20, 2002
1
0AED
of
8
MCS_A#017
MCS_A#117
D D
MCS_A#217
MCS_A#317
MRAS_A#17
MCAS_A#17
MWE_A#17
MA_A[0..12]17
MAB_A[1..5]17
C C
MBA_A017
MBA_A117
MDQM_A[0..7]17
MDQS_A[0..7]17
MCLK_A017
MCLK_A#017
MCLK_A117
B B
MCLK_A#117
MCLK_A217
MCLK_A#217
MCLK_A317
MCLK_A#317
MCLK_A417
MCLK_A#417
MCLK_A517
MCLK_A#517
0.01u_X7RC12
0.01u_X7RC15
0.01u_X7RC16
0.01u_X7RC18
C256 2.2u_Y5V
{VOLTAGE}
C227 0.47u_Y5V
C228 0.22u_Y5V
C229 0.1u_Y5V
8
C230 0.22u_Y5V
C231 0.1u_Y5V
A A
MDQ_A[0..63]17 MCKE_A[0..3] 17
AA34
Y31
Y32
W34
AC33
Y34
AB34
MA_A0
AJ34
MA_A1
AL33
MA_A2
AK29
MA_A3
AN31
MA_A4
AL30
MA_A5
AL26
MA_A6
AL28
MA_A7
AN25
MA_A8
AP26
MA_A9
AP24
MA_A10
AJ33
MA_A11
AN23
MA_A12
AN21
MAB_A1
AL34
MAB_A2
AM34
MAB_A3
AP32
MAB_A4
AP31
MAB_A5
AM26
AE33
AH34
MDQM_A0
AP12
MDQM_A1
AP16
MDQM_A2
AM24
MDQM_A3
AP30
MDQM_A4
AF31
MDQM_A5
W33
MDQM_A6
M34
MDQM_A7
H32
MDQS_A0
AN11
MDQS_A1
AP15
MDQS_A2
AP23
MDQS_A3
AM30
MDQS_A4
AF34
MDQS_A5
V34
MDQS_A6
M32
MDQS_A7
H31
AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32
XRCOMP
AK9
XCOMPH
AN9
XCOMPL
AL9
SMVREF
E34
XRCOMP29
XCOMPH29
XCOMPL29
VREF29
VCC_DDR_C229
VCC_DDR_C329
U2B
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SRAS_A#
SCAS_A#
SWE_A#
SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12
SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5
SBA_A0
SBA_A1
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SMDCLK_A0
SMDCLK_A0#
SMDCLK_A1
SMDCLK_A1#
SMDCLK_A2
SMDCLK_A2#
SMDCLK_A3
SMDCLK_A3#
SMDCLK_A4
SMDCLK_A4#
SMDCLK_A5
SMDCLK_A5#
SMXRCOMP
SMXCOMPVOH
SMXCOMPVOL
SMVREF_A
VCC_DDR_C1
VCC_DDR_C2
VCC_DDR_C3
VCC_DDR_C4
VCC_DDR_C5
7
MDQ_A3
MDQ_A4
MDQ_A2
AM12
AN13
AM10
SDQ_A1
SDQ_A2
SDQ_A3
VCC_DDR
VCC_DDR
VCC_DDR
AA35
R35
AR21
MDQ_A7
MDQ_A5
MDQ_A6
AL10
AL12
AP13
SDQ_A4
SDQ_A5
SDQ_A6
VCC_DDR
VCC_DDR
VCC_DDR
AL7
AR15
AL6
MDQ_A9
MDQ_A8
AP14
AM14
SDQ_A7
SDQ_A8
SDQ_A9
VCC_DDR
VCC_DDR
VCC_DDR
AM1
AM2
MDQ_A0
MDQ_A1
AP10
AP11
SDQ_A0
E35
VCC_DDR
MDQ_B[0..63]18
7
MDQ_A12
MDQ_A10
MDQ_A11
AL18
AP19
AL14
SDQ_A10
SDQ_A11
SDQ_A12
VCC_DDR
VCC_DDR
VCC_DDR
AN8
AP3
AP4
MDQ_A13
MDQ_A14
MDQ_A15
AN15
AP18
AM18
SDQ_A13
SDQ_A14
SDQ_A15
VCC_DDR
VCC_DDR
VCC_DDR
AP5
AP6
AP7
6
MDQ_A16
MDQ_A17
MDQ_A18
AP22
AM22
AL24
SDQ_A16
SDQ_A17
VCC_DDR
VCC_DDR
AR4
AR5
AR7
6
MDQ_A19
MDQ_A21
MDQ_A20
AN27
AP21
AL22
SDQ_A18
SDQ_A19
SDQ_A20
VCC_DDR
VCC_DDR
AR31
AJ10
MDQ_B0
MDQ_A23
MDQ_A22
AP25
AP27
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_B0
SDQ_B1
SDQ_B2
AE15
AL11
MDQ_B2
MDQ_B1
MDQ_A25
MDQ_A24
MDQ_A26
AP28
AP29
AP33
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_B3
SDQ_B4
SDQ_B5
AE16
AL8
AF12
MDQ_B3
MDQ_B5
MDQ_B4
MDQ_A28
MDQ_A29
MDQ_A27
AM33
AM28
AN29
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_B6
SDQ_B7
SDQ_B8
AK11
AG12
AE17
MDQ_B6
MDQ_B8
MDQ_B7
MDQ_A32
MDQ_A30
MDQ_A31
AM31
AN34
AH32
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_B9
SDQ_B10
SDQ_B11
AL13
AK17
AL17
MDQ_B11
MDQ_B10
MDQ_B9
5
MDQ_A35
MDQ_A34
MDQ_A33
AG34
AF32
AD32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_B12
SDQ_B13
SDQ_B14
AK13
AJ14
AJ16
MDQ_B12
MDQ_B14
MDQ_B13
5
MDQ_A38
MDQ_A36
MDQ_A37
AH31
AG33
AE34
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_B15
SDQ_B16
SDQ_B17
AJ18
AE19
AE20
MDQ_B15
MDQ_B17
MDQ_B16
MDQ_A41
MDQ_A40
MDQ_A39
AD34
AC34
AB31
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_B18
SDQ_B19
SDQ_B20
AG23
AK23
AL19
MDQ_B18
MDQ_B20
MDQ_B19
MDQ_A42
MDQ_A44
MDQ_A43
V32
V31
AD31
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_B21
SDQ_B22
SDQ_B23
AK21
AJ24
AE22
MDQ_B22
MDQ_B23
MDQ_B21
MDQ_A45
MDQ_A47
MDQ_A46
AB32
U34
U33
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_B24
SDQ_B25
SDQ_B26
AK25
AH26
AG27
MDQ_B24
MDQ_B26
MDQ_B25
MDQ_A50
MDQ_A48
MDQ_A49
T34
T32
K34
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_B27
SDQ_B28
SDQ_B29
AF27
AJ26
AJ27
MDQ_B27
MDQ_B28
MDQ_B29
MDQ_A51
MDQ_A53
MDQ_A52
K32
T31
P34
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_B30
SDQ_B31
SDQ_B32
AD25
AF28
AE30
MDQ_B30
MDQ_B32
MDQ_B31
4
MDQ_A55
MDQ_A56
MDQ_A54
L34
L33
J33
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_B33
SDQ_B34
SDQ_B35
AC27
AC30
Y29
MDQ_B35
MDQ_B33
MDQ_B34
4
MDQ_A59
MDQ_A57
MDQ_A58
H34
E33
F33
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_B36
SDQ_B37
SDQ_B38
AE31
AB29
AA26
MDQ_B37
MDQ_B36
MDQ_B38
MDQ_A61
MDQ_A60
MDQ_A62
K31
J34
G34
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_B39
SDQ_B40
SDQ_B41
AA27
AA30
W30
MDQ_B40
MDQ_B41
MDQ_B39
MCKE_A0
MDQ_A63
F34
AL20
SDQ_A63
SCKE_A0
SDQ_B42
SDQ_B43
SDQ_B44
U27
T25
AA31
MDQ_B43
MDQ_B44
MDQ_B42
MCKE_A2
MCKE_A1
MCKE_A3
AN19
AM20
AP20
SCKE_A1
SCKE_A2
SCKE_A3
SDQ_B45
SDQ_B46
SDQ_B47
V29
U25
R27
MDQ_B47
MDQ_B46
MDQ_B45
AB25
AC25
VCCA_DDR
VCCA_DDR
SDQ_B48
SDQ_B49
SDQ_B50
P29
R30
K28
MDQ_B49
MDQ_B48
MDQ_B50
3
VCCA_DDR
C20 0.1u_Y5V
VCCADDR
AC26
AN4
AM3
AL35
VCC_DDR
VCCA_DDR
VCCA_DDR
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
L30
R31
R26
P25
L32
MDQ_B53
MDQ_B55
MDQ_B51
MDQ_B52
MDQ_B54
3
AN5
AM5
AM6
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B55
SDQ_B56
SDQ_B57
K30
H29
F32
MDQ_B58
MDQ_B56
MDQ_B57
2
VCCA_DDR 29
VCC_DDR
Its current is 5.1A.
AM7
AM8
AN2
AN6
AN7
P3P6P8
N35
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B58
SDQ_B59
SDQ_B60
G33
N25
M25
MDQ_B61
MDQ_B60
MDQ_B59
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B61
SDQ_B62
SDQ_B63
J29
G32
MDQ_B62
MDQ_B63
N32
VSS
VSS
SCKE_B0
SCKE_B1
AK19
AF19
AG19
MCKE_B2
MCKE_B0
MCKE_B1
VSS
VSS
VSS
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMYRCOMP
SMYCOMPVOH
SMYCOMPVOL
SMVREF_B
SCKE_B2
SCKE_B3
Intel Springdale-N
AE18
{Priority}
MCKE_B3
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12
SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5
SBA_B0
SBA_B1
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
U26
T29
V25
W25
W26
W31
W27
AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20
AE27
AD26
AL29
AL27
AE23
Y25
AA25
AG11
AG15
AE21
AJ28
AC31
U31
M29
J31
AF15
AG13
AG21
AH27
AD29
U30
L27
J30
AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30
AA33
R34
R33
AP9
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MAB_B1
MAB_B2
MAB_B3
MAB_B4
MAB_B5
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
YRCOMP
YCOMPH
YCOMPL
VREF
MCKE_B[0..3] 18
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Intel Springdale - Memory Signals
VISE (MS-6715)
2
1
MCS_B#0 18
MCS_B#1 18
MCS_B#2 18
MCS_B#3 18
MRAS_B# 18
MCAS_B# 18
MWE_B# 18
MA_B[0..12] 18
MAB_B[1..5] 18
MBA_B0 18
MBA_B1 18
MDQM_B[0..7] 18
MDQS_B[0..7] 18
MCLK_B0 18
MCLK_B#0 18
MCLK_B1 18
MCLK_B#1 18
MCLK_B2 18
MCLK_B#2 18
MCLK_B3 18
MCLK_B#3 18
MCLK_B4 18
MCLK_B#4 18
MCLK_B5 18
MCLK_B#5 18
0.01u_X7RC11
0.01u_X7RC13
0.01u_X7RC14
0.01u_X7RC17
YRCOMP 29
YCOMPH 29
YCOMPL 29
931Friday, September 20, 2002
1
0AED
of
8
7
6
5
4
3
2
1
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
AN20
AN22
AN24
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
AN26
AN28
VCCA_AGP_C
VCC_AGP
VCC_AGP
VSS
VSS
AN30
AN32
VCC_AGP_C
P26
P27
P28
P30
P33R1R4
R32T1T3
VSS
VSS
VSS
VSS
AE35
AF3
VSS
VSS
AF6
VSS
VSS
AF9
VSS
VSS
VSS
VSS
AF11
T6T8T9
VSS
VSS
AF16
AF14
VSS
VSS
AD33
VSS
AD28
AE1
VSS
AE4
VSS
VSS
AE10
P9
VSS
VSS
AE11
VSS
VSS
AE12
VSS
VSS
AE13
VSS
VSS
AE25
VSS
VSS
AE26
AE32
GAD[0..31]19
D D
C C
GC_BE#[0..3]19
AD_STB019
AD_STB#019
AD_STB119
AD_STB#119
GREQ#19
GGNT#19
ST[0..2]19
RBF#19
WBF#19
GFRAME#19
GIRDY#19
GTRDY#19
GDEVSEL#19
B B
GSTOP#19
GPAR19
MCH_6613
SBA[0..7]19
SB_STB19
SB_STB#19
PIPE#19
VCC_AGP
DBI_LO19
R66 43.2RST
0.01u_X7RC28
GSWING19
AGP_REF19
0.01u_X7RC29
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3
ST0
ST1
ST2
RBF#
WBF#
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
GRCOMP
GSWING
U2C
AE6
GAD0/DVOB_HSYNC
AC11
GAD1/DVOB_VSYNC
AD5
GAD2/DVOB_D1
AE5
GAD3/DVOB_D0
AA10
GAD4/DVOB_D3
AC9
GAD5/DVOB_D2
AB11
GAD6/DVOB_D5
AB7
GAD7/DVOB_D4
AA9
GAD8/DVOB_D6
AA6
GAD9/DVOB_D9
AA5
GAD10/DVOB_D8
W10
GAD11/DVOB_D11
AA11
GAD12/DVOB_D10
W6
GAD13/DVOBC_CLKINT
W9
GAD14/DVOB_FLDSTL
V7
GAD15/MDDC_DATA
AA2
GAD16/DVOC_VSYNC
Y4
GAD17/DVOC_HSYNC
Y2
GAD18/DVOC_BLANK#
W2
GAD19/DVOC_D0
Y5
GAD20/DVOC_D1
V2
GAD21/DVOC_D2
W3
GAD22/DVOC_D3
U3
GAD23/DVOC_D4
T2
GAD24/DVOC_D7
T4
GAD25/DVOC_D6
T5
GAD26/DVOC_D9
R2
GAD27/DVOC_D8
P2
GAD28/DVOC_D11
P5
GAD29/DVOC_D10
P4
GAD30/DVOBC_INTR#
M2
GAD31/DVOC_FLDSTL
Y7
GCBE0/DVOB_D7
W5
GCBE1/DVOB_BLANK#
AA3
GCBE2
U2
GCBE3/DVOC_D5
AC6
GADSTBF0/DVOB_CLK
AC5
GADSTBS0/DVOB_CLK#
V4
GADSTBF1/DVOC_CLK
V5
GADSTBS1/DVOC_CLK#
N6
GREQ
M7
GGNT
N3
GST0
N5
GST1
N2
GST2
R10
GRBF
R9
GWBF
U6
GFRAME/MDVI_DATA
V11
GIRDY/MI2CCLK
AB5
GTRDY/MDVI_CLK
AB4
GDEVSEL/MI2CDATA
W11
GSTOP/MDDC_CLK
AB2
GPAR/ADD_DETECT
H4
GCLKIN
R6
GSBA0#/ADD_ID0
P7
GSBA1#/ADD_ID1
R3
GSBA2#/ADD_ID2
R5
GSBA3#/ADD_ID3
U9
GSBA4#/ADD_ID4
U10
GSBA5#/ADD_ID5
U5
GSBA6#/ADD_ID6
T7
GSBA7#/ADD_ID7
U11
GSBSTBF
T11
GSBSTBS
M4
DBI_HI
M5
DBI_LO
AC2
GRCOMP/DVOBC_RCOMP
AC3
GVSWING
AD2
GVREF
AD30
A A
VSS
VSS
VSS
VSS
AF18
T10
VSS
VSS
AF20
T26
VSS
VSS
AF22
T27
VSS
VSS
AF24
T28
VSS
VSS
AF25
T30
VSS
VSS
AF30
T33
VSS
VSS
AF33
T35
AG4
VSS
VSS
U4
VSS
VSS
AG8
U18
U19
U32V3V8V9V10
VSS
VSS
VSS
VSS
VSS
VSS
AG14
AG16
AG18
AG20
VSS
VSS
V6
VSS
VSS
AG22
VSS
VSS
AG24
VSS
VSS
AG26
VSS
VSS
AG28
V17
VSS
VSS
AG32
V19
VSS
VSS
AG35
V26
AH3
V27
VSS
VSS
AH6
V28
V30W4W17
VSS
VSS
VSS
VSS
AH12
AH10
VSS
VSS
V33
VSS
VSS
AH14
VSS
VSS
AH16
VSS
VSS
AH18
W18
VSS
VSS
AH20
Y3
W32Y6Y8Y9Y26
Y10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ1
AJ4
AH22
AH24
AH30
AH33
Y28
Y30
Y33
Y35
Y27
AA1
AA4
AA32
AB10
AB26
AC1
AC4
AC32
VSS
VSS
AB30
VSS
VSS
AM9
AB33
VSS
VSS
AM11
VSS
VSS
AM13
VSS
VSS
AM15
VSS
VSS
AM17
AC35
VSS
VSS
AM19
AD3
VSS
VSS
AM21
AD6
VSS
VSS
AM23
AD8
AM25
AB27
VSS
VSS
AB8
VSS
VSS
AK22
AB9
VSS
VSS
AK24
VSS
VSS
AK26
VSS
VSS
AK28
AB28
VSS
VSS
AL1
AL32
AB3
AB6
VSS
VSS
VSS
VSS
VSS
AK8
VSS
VSS
VSS
VSS
AK10
VSS
AK12
VSS
AK14
VSS
AK16
VSS
VSS
AK18
AK20
VSS
VSS
VSS
VSS
VSS
VSS
AK3
AJ9
AJ32
AJ35
C23 0.1u_Y5VC215 0.1u_Y5V
L1L5Y1J1J2J3K2K3K4K5J4J5L4L2L3
AD9
AD10
VSS
VSS
VSS
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM27
AM29
AM35
AN10
AN12
AN14
AN16
AN18
VCC_AGP
VCC_AGP
VSS
VSS
AR9
AR11
AR13
VCCA_AGP
AG1
Y11
VCC_AGP
VCCA_AGP
VCCA_AGP
HI_STRF
HI_STRS
HI_RCOMP
HI_SWING
HI_VREF
CISTRF
CISTRS
CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
DDCA_CLK
DDCA_DATA
VSYNC
HSYNC
GREEN
GREEN#
REFSET
VCC_DAC
VCC_DAC
VCCA_DAC
VSSA_DAC
EXTTS#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VSS
VSS
VSS
VSS
AR23
AR16
AR20
AF5
HI0
AG3
HI1
AK2
HI2
AG5
HI3
AK5
HI4
AL3
HI5
AL2
HI6
AL4
HI7
AJ2
HI8
AH2
HI9
AJ3
HI10
AH5
AH4
AD4
AE3
AE2
AK7
CI0
AH7
CI1
AD11
CI2
AF7
CI3
AD7
CI4
AC10
CI5
AF8
CI6
AG7
CI7
AE9
CI8
AH9
CI9
AG6
CI10
AJ6
AJ5
AG2
AF2
AF4
G4
F2
H3
E2
G3
H7
BLUE
G6
BLUE#
H6
G5
F4
RED
E4
RED#
D2
G1
G2
C2
D3
AP8
AG9
AG10
AN35
AP34
AR1
AR25
VSS
AR27
VSS
AR29
VSS
AR32
VSS
Intel Springdale-N
{Priority}
C24
0.1u_Y5V
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7GAD8
HL8
HL9
HL10
HL_COMP
CI_RCOMP
C232 0.1u_Y5V
C233 0.1u_Y5V
GSET
CB24
0.1u_Y5V
VCCA_DAC
C27
0.1u_Y5V
VCC_DAC
VCC_AGP
HL_STRF 12
HL_STRS 12
R62 52.3RST-N
HL_SWING 29
HL_VREF 29
R63 52.3RST-N
CI_SWING 29
CI_VREF 29
DOT_48 13
3VDDCCL
3VDDCDA
CRT_VSYNC
CRT_HSYNC
CRT_B
CRT_G
CRT_R
R64 137RST
CB25
0.01u_X7R
CB26
0.01u_X7R
L6 100nH-300mA
1.7V@250mA
0.01u_X7RC25
0.01u_X7RC26
VCC3
HL[0..10] 12
VCC_AGP
VCC_AGP
+
CT27
470u-16V
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
H/W Project Leader : Andy Chen
H/W Project Engineer : Prudence Wang
Intel Springdale - AGP & HLink & LAN Signals
VISE (MS-6715)
2
10 31Friday, September 20, 2002
of
1
0AED
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