MSI MS-9102 Schematic 0B
1
MS-9102
Dual Intel Foster Proces s or
ServerWorks GCLE + CIOB-X2 + CIOB-G + CSB5 Ch i pset
National Semiconduct o r PC87417 LPC IO Ch ip
Cover Sheet 1
Block Diagram
Clock & Reset Map
2
3
4,5,6,7Foster CPU #1 & #2
CPU GTLREF & SMBus Address 8
ITP Connector
A A
Ratio & Level Shift Circuit
CPU Level Shift Circuit
CMIC-LE
9
10
11
12,13,14,15,16
DDR Module 1/2/3/4 17,18
Memory Termination #1 & #2
Clock Synthesizer
PCI 33 Clock Buf f e r
DDR Clock Buffer
CIOB-X2
19,20
21
22
23
24,25,26
27,28,29CIOB-G
CIOB-X2 Clock Buffe r
Thin IMB Termination
Stitching Capacitors
PCI 64 Slot 1/2 (66MHz / 6 4 B i t )
SCSI AIC7899W/7902
30
31
32
33
34,35,36,37,38
39PCI-X Slot 1/ 2
AGP Pro Slot
40
CSB5
PCI 32 Slot 1/2 (33MHz / 3 2 B i t )
LAN 82559ER(82550)
Interrupt Mapping Ckt
41,42
43
44,45
46
47USB Connector
ATA-HDD Connector
XAD Bus/Flash ROM
NS PC87417 SIO & IO C onn ec to r
Hardware M o ni t o r
Power OK Circ ui t
Front Panel
Extra FAN Control
IPMI Slot
I2C Switching & MT H
Reset Buffer Circuit
Power Requlator - 3VSB/USBPWR
VRM 9.0 for CPU1 & C P U 2
VCC25 & AVTT
VDD_AGP & VAGP_CARD
VDD_IMB
48
49
50,51,52,53
54
55
56
57
51
51
52
52
53
54
55
55
Manual Par t 56
Note 68 - 73
1
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Micro Star Restricted Secret
Cover Sheet
Last Revision Date:
Tuesday, November 13, 2001
Sheet
162
of
Rev
0B
MS-9102 Block D ia g r a m
Full ATX - 12"*13"*8 Layers (10 MTHole)
VRM1
BLOCK DIAGRAM
Scoket 603 CPU1
CTRL
ADDR
DATA
ADDR
CTRL
1
Scoket 630 CPU2 VRM2
DATA
CTRL
ADDR
GTL BUS
DATA
FSB Suport 100/133MHz Foster/Gullatin CPU Support
VRM1/VRM2 Support VRM 9.0
6 DDR
DIMM
Modules
Support Register ECC DDR
DIMM Only (Up to 12GB)
66MHz/64Bit or 33MHz/32Bit Support
P64 PCI CONN 2
P64 PCI CONN 1
PCI 66MHz/64Bit Bus
ServerWorks
CIOB-X2
A-IMB Bus
SM BUS
ServerWorks
CMIC-LE
Dual Channel
AIC 7899W/7902
EMRL
Ultra160/320 SCSI
Ultra 160/320
Ultra 160/320
PCI-X Bus
PCI-X CONN 1
PCI-X Bus (Up to 133MHz)
PCI-X CONN 2
Thin IMB Bus
B-IMB Bus
ServerWorks
CIOB-G
CTRL
ADDR
DATA
AGP Pro Slot
A A
IDE Primary
IDE Secondary
USB Port 1/2
USB Port 3/4
W83782D HWM
LPC
Ultra DMA66
USB 1.1
SM BUS
ServerWorks
CSB5 2.0
LPC
LPC
LPC
XAD Bus
FLASH ROM
PCI-X Bus
PCI 32 CONN
Intel 82550/559
PCI LAN Chip
IPMI
Slot
Floopy
NS
PC87417
Keyboard
Mouse
Serial 1
Serial 2
1
Parallel
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung- He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Micro Star Restricted Secret
Block Diagram
Last Revision Date:
Tuesday, November 13, 2001
Sheet
262
of
Rev
0B
1
RESET SCHEME
WTX
POWER
SUPPLY
CONN.
RESET SWITCH
ITP_RESET#
PS_PWRGD
AND
INVERTER
RESET GEN
140mS PERIOD
RESET Vth =
4.5V
PS_PWRGD#
POWERGOOD
CPU_VRM_PWRGD
PS_PWRGD#
PLLRST
PCIRST#
CMIC CIOB'S
SRESET#
AND
RSB5
PLLRST
PCIRST#
PLLRST
PCIRST#
PCIRST#
P1/P2_PCIRST#
S1/S2_PCIRST#
PROC_RESET#
RESETDLY#
CPU_PWRGD
RESET FOR RSB
PCI BUS
RESETS FOR PCI
BUSES
CPU RESET
Config RESET - 4
BCLK delay w.r.t.
PROC_RESET#
POWER
t0
PSU PWR GOOD
PLL RST
t0+100mS
POWERGOOD
VRM POWERGOOD
PROCESSOR POWERGOOD
PROCESSOR RESET
PCI RESET
CONFIG RESET
t0+100mS
t0+50mS
t0+120mS
t0+120mS
t0+120mS+1mS
t0+120mS+1mS
t0+120mS+1mS+4 clocks
CLOCKING SCHEME
- CPU 0
- CPU1
- CMIC
- DIMM PLL
A A
14.318 MHz
X-TAL
CLK SYNTH.
BCLK
BCLK#
33MHz
48MHz
48MHz
14MHz
- ITP Connector
- PROBE Header
6 Pairs of 100MHz
Differential
CLOCKs
From CLK
SYNTH.
33MHz Low Skew
Buffer
n
BCLK
BCLK#
DIMM PLL
FBOUT#
FBOUT
33MHz CLOCK TO RSB and
DEVICES behind it.
8 Pairs of 100MHz
Differential CLOCKs
for 8 DIMMs
33MHz
CIOB
P1_CLKO
S1_CLKO
P1_FBCLK
PCI-X PLLs
S1_FBCLK
TO PCI
CONNs.
TO PCI
CONNs.
48MHz USB CLK to RSB
48MHz CLK to SIO
14 MHz CLK to RSB
33MHz
CIOB-G
FBCLK
66MHz
1
AGP CONN.
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung- He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Micro Star Restricted Secret
Clock & Reset Map
Last Revision Date:
Tuesday, November 13, 2001
Sheet
362
of
Rev
0A
A
B
C
D
E
P1_SM_ADDR[0..2]<8> CPU_SDA <6,51>
VCC_P
VCC3
VCC3
P1_SM_TS_ADDR[0..1]<8>
R752
1K
R745
X_R
R535
X_R
C395
1000p-0805
P1_VCCIOPLL<11>
FSB_VCC_SENSE<6>
FSB_GND_SENSE<6>
Enable
P1_ODTEN
Disable
OnDie
Termination
P1_SM_WP
PD#[0..63]<6,12>
4 4
3 3
2 2
1 1
P1_SM_ADDR[0..2]
P1_SM_TS_ADDR[0..1]
PD#[0..63]
P1_VCCA<11>
P1_VSSA<11>
P1_ODTEN
TP6
1
AP#0<6,12>
AP#1<6,12>
HCLK1<22>
HCLK1_N<22>
PA#[3..35]<6,12>
BREQ#0<6,12>
BREQ#1<6>
BREQ#2<6>
BREQ#3<6>
BNR#<6,11,12>
BPRI#<6,12>
PD#0
PD#1
PD#2
PD#3
PD#4
PD#5
PD#6
PD#7
PD#8
PD#9
PD#10
PD#11
PD#12
PD#13
PD#14
PD#15
PD#16
PD#17
PD#18
PD#19
PD#20
PD#21
PD#22
PD#23
PD#24
PD#25
PD#26
PD#27
PD#28
PD#29
PD#30
PD#31
PD#32
PD#33
PD#34
PD#35
PD#36
PD#37
PD#38
PD#39
PD#40
PD#41
PD#42
PD#43
PD#44
PD#45
PD#46
PD#47
PD#48
PD#49
PD#50
PD#51
PD#52
PD#53
PD#54
PD#55
PD#56
PD#57
PD#58
PD#59
PD#60
PD#61
PD#62
PD#63
AP#0
AP#1
HCLK1
HCLK1_N
PA#[3..35]
CPU1A
AA27
AA25
AD27
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AD10
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
PGA-S603
A3B5D26
Y26
D0#
D1#
Y24
D2#
D3#
D4#
Y23
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
AE9
D44#
D45#
AD8
D46#
AC9
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
AC8
D56#
AD7
D57#
AE7
D58#
AC6
D59#
AC5
D60#
AA8
D61#
Y9
D62#
AB6
D63#
E10
AP0#
D9
AP1#
Y4
BCLK0
W5
BCLK1
VCC3
R748 43
P1_SM_WP
P1_SM_ADDR0
P1_SM_ADDR1
P1_SM_ADDR2
P1_SM_TS_ADDR0
P1_SM_TS_ADDR1
AA5
B27
AD4
AB4
AD29
AE29
AE28
Y29
AA28
VSSA
VCCA
ODTEN
SKTOCC#
VSSSENSE
SM_VCC
SMB_WP
SM_VCC1
VCCIOPLL
SM_TS_A1
VCCSENSE
P1_COMP1
AB28
AB29
AA29
AC29
AC28
AD28
E16
SM_CLK
SM_DAT
SM_TS_A0
SM_EP_A2
SM_EP_A1
SM_EP_A0
SM_ALERT
FOSTER
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
PA#3
PA#4
PA#5
PA#6
PA#7
PA#8
PA#9
PA#10
PA#11
PA#12
A20#
B13
A12
C15
C14
D16
D15
F15
A10
B10
PA#13
PA#14
PA#15
PA#16
PA#17
PA#18
PA#19
PA#20
PA#21
COMP1
A21#
R537 43
P1_COMP0
AD16
B11
PA#22
COMP0
A22#
A23#
C12
PA#23
W6W7W8Y6AA7
TESTHI0
A24#
A25#
E14
D13A9B8
PA#24
PA#25
PA#26
CPU_SCL <6,51>
CPU_SMBALERT# <6>
VCC_P
R538 180
R539 180
AD5
AE5
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
A26#
A27#
A28#
A29#
A30#
A31#
E13
D12
C11B7A6A7C9C8D20
PA#27
PA#28
PA#29
PA#30
PA#31
DP#1
DP#0
DP#2
DP#3
E25
C24
AE17
AC15
AE19
AC18
TDO
DP3#
DP2#
DP1#
DP0#
A32#
A33#
A34#
A35#
BR0#
BR1#
BR2#
BR3#
BNR#
F12
E11
D10
F20
D23
BREQ#0
BREQ#1
BREQ#2
BREQ#3
PA#32
PA#33
PA#34
PA#35
E19
F24
E24
TDI
TCK
TRST#
TRDY#
THERMTRIP#
BPRI#
BINIT#
DBSY#
DRDY#
F11
F18
E18
BINIT#
DBSY#
DRDY#
R747 39.2
R749 39.2
R750 39.2
R751 39.2
PLACE AT PROC 1
HREQ#[0..4]
DSTBP#[0..3]
DSTBN#[0..3]
BPM#[2..5]
VRM_VID[0..4]
DINV#[0..3]
DP#[0..3]
A25
TMS
DBI3#
DBI2#
DBI1#
DBI0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
SLP#
STPCLK#
SMI#
PWRGD
PR0CH0T#
INIT#
LINIT1
LINIT0
FERR#
IGNNE#
A20M#
RESET#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
LOCK#
MCERR#
RSP#
RS2#
RS1#
RS0#
IERR#
DEFER#
HITM#
ADS#
ADSTB0#
ADSTB1#
HREQ#[0..4] <6,12>
DSTBP#[0..3] <6,12>
DSTBN#[0..3] <6,12>
BPM#[2..5] <6,9,11>
VRM_VID[0..4] <6,48,53>
DINV#[0..3] <6,12>
DP#[0..3] <6,12>
P1_TDO <6,9>
P1_TDI <9>
P1_TCK <9>
P_TRDY# <6,12>
ITP_TRST# <6,9>
TMS <6,9>
DINV#3
AB9
DINV#2
AE12
DINV#1
AD22
DINV#0
AC27
VRM_VID0
F3
VID0
E3
VID1
VRM_VID2
D3
VID2
VRM_VID3
C3
VID3
VRM_VID4
B3
VID4
F9
F23
W9
W23
DSTBP#3
Y11
DSTBP#2
Y14
DSTBP#1
Y17
DSTBP#0
Y20
DSTBN#3
Y12
DSTBN#2
Y15
DSTBN#1
Y18
DSTBN#0
Y21
BPM#2
F6
BPM#3
F8
BPM#2
E7
BPM#3
F5
BPM#4
E8
BPM#5
E4
AE6
D4
C27
F26
AB7
B25
D6
G23
B24
E27
C26
F27
Y8
HREQ#0
B19
HREQ#1
B21
HREQ#2
C21
HREQ#3
C20
HREQ#4
B22
A17
D7
C6
F21
D22
E21
P1_IERR#
E5
DEFER#
C23
HITM#
A23
HIT#
E22
HIT#
ADS#
D19
ADSTB#0
F17
ADSTB#1
F14
VCC_P
Check Which CPU is
close to ITP
P1_GTLREF1 <8>
P1_GTLREF0 <8>
SLP# <6,11>
CPU_STPCLK# <6,11>
SMI# <6,11>
P1_THERMTRIP# <10>
CPU1_PWRGD <49>
P1_PROCHOT# <10>
INIT# <6,11>
LINT1 <6,10,11>
LINT0 <6,10,11>
FERR# <6,10,11>
IGNNE# <6,10,11>
A20M# <6,10,11>
PROC_RESET# <6,9,11,13>
LOCK# <6,11,12>
MCERR# <6,11>
RSP# <6,12>
RS#2 <6,12>
RS#1 <6,12>
RS#0 <6,12>
P1_IERR# <10>
DEFER# <6,12>
HITM# <6,11,12>
HIT# <6,11,12>
ADS# <6,12>
ADSTB#0 <6,12>
ADSTB#1 <6,12>
DRDY# <6,12>
DBSY# <6,12>
BINIT# <6,11,12>
PLACE NEAR CENTER OF VCC_FSB PLANES
FSB_VCC_SENSE<6>
FSB_GND_SENSE<6>
ALL SENSE LINES MEET AT CENTRES OF PLANES
Route FSB_VCC/GND_SENSE,
VRM_ISHARE signals in 25/50
Mils trace width
VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3
VRM_VID4
FSB_VCC_SENSEVRM_VID1
FSB_GND_SENSE
RN105 1K
R746 1K
Philips/Vishay Iz=5mA
R732 0
TP8
1
TP7
1
R731 0
VCC3
12
34
56
78
VCC_P
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
Foster CPU #1
E
Last Revision Date:
Tuesday, November 13, 2001
Sheet
Rev
0B
of
462
1 1
2 2
3 3
4 4
A
A
VCC_P
W27
W25
R23
R25
R27
PGA-S603
VCC
VCC
VCC
VCC
GND42
EMI_GND10
GND43
EMI_GND11
GND44
EMI_GND12
GND45
EMI_GND13
GND46
EMI_GND14
GND47
EMI_GND15
GND48
EMI_GND16
VCC
VCC
VCC
VCC
V8
V24
V26
B
V28
P24
P26
P28
R3R5R7
R9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U23
U25
U27
U29V2V4
V6
N23
N25
N27
N29
P2P4P6
P8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T24
T26
T28U3U5U7U9
M23
M25
M27
M29
N3N5N7
N9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L24
L26
L28
M3M5M7
M9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
K23
K25
K27
K29
L2L4L6
L8
VCC
VCC
VCC
VCC
VCC
VCC
J26
J28
K3K5K7
K9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H25
H27
H29
J24
J2J4J6
J8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FOSTER_PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA4
AA6
AA12
AA20
AA26
AB2
AB8
AB14
AB18
AB24
AC3
AC4
AC10
AC16
AC22
AD2
AD6
AD12
AD20
AD26
AE3
AE8
AE14
AE18
AE24
R29T2T4T6T8
VSS
VSS
VSS
VSS
H26
H28J3J5
W29Y2Y10
Y16
Y22
G24
G26
G28
H23
H3H5H7
H9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G25
G27
G29H2H4H6H8
H24
F10
F16
F22
F29
G2G4G6
G8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F13
F19
F25
F28G3G5G7G9
D29
E12
E20
E26
E28
E2
E6
F4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D28E9E15
E17
E23
E29F2F7
C10
C16
C22
C28D8D14
D18
D24
VCC
VCC
VCC
VSS
VSS
VSS
D21
D27
B29
C2
C4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B28C7C13
C19
C25
C29D2D5
D11
A14
A18
A24
A28B6B12
B20
B26
VCC
VCC
VSS
VSS
B17
B23
A2
A8
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND33
EMI_GND1
GND34
EMI_GND2
GND35
EMI_GND3
GND36
EMI_GND4
GND37
EMI_GND5
GND38
EMI_GND6
GND39
EMI_GND7
GND40
EMI_GND8
GND41
EMI_GND9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A5
A11
A21
A27
A29B2B9
B15
B
VCC_P
AC13
AC19
AC25 AD3
AC7
PGA-S603
VSS
VSS
VSS
VSS VSS
GND1
MTG_GND1
GND2
MTG_GND2
GND3
MTG_GND3
GND4
MTG_GND4
GND5
MTG_GND5
GND6
MTG_GND6
GND7
MTG_GND7
GND8
MTG_GND8
GND9
MTG_GND9
GND10
MTG_GND10
GND11
MTG_GND11
GND12
MTG_GND12
GND13
MTG_GND13
GND14
MTG_GND14
GND15
MTG_GND15
GND16
MTG_GND16
GND17
MTG_GND17
C
GND18
GND19
GND20
MTG_GND18
MTG_GND19
MTG_GND20
VSS
VSS
AD9
AD15
VSS
AD17
AA15
AA17
AA23
AB11
AB21
AB27
AC2
VSS
VSS
AD23
AA9
AB5
AA2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD80
RSVD83
RSVD86
RSVD87
RSVD88
VSS
VSS
VSS
AC1
AD1
AE4
AE15
AE16
AE11
AE21
AE27
AE2
Y25
VSS
VSS
RSVD73
RSVD77
AB3
Y13
Y19
VSS
RSVD69
Y28
AA3
Y5
Y7
VSS
VSS
RSVD67
RSVD68
Y3
Y27
W28
VSS
VSS
RSVD17
RSVD63
W3
W24
W26
VSS
RSVD13
C5
D25
W4
VSS
RSVD8
B1
W2
VSS
VSS
RSVD4
RSVD5
A26
V29
VSS
RSVD3
A16
V25
V27
VSS
A15
V23
V9
VSS
VSS
VSS
VSS
GAL_VSS31
GAL_VSS32
GAL_VSS33
GAL_VSS34
AB31
AC30
AD31
U28
V3V5V7
VSS
VSS
VSS
GAL_VSS28
GAL_VSS29
GAL_VSS30
Y31
AA30
AB1
U24
U26
U8
VSS
VSS
GAL_VSS26
GAL_VSS27
V31
W30
Y1
U2U4U6
VSS
VSS
VSS
VSS
GAL_VSS22
GAL_VSS23
GAL_VSS24
GAL_VSS25
T31U1U30
T23
T25
T27
T29
T9
VSS
VSS
VSS
VSS
VSS
VSS
FOSTER_PWR
GAL_VSS16
GAL_VSS17
GAL_VSS18
GAL_VSS19
GAL_VSS20
GAL_VSS21
N30
P31R1R30
R28
T3T5T7
VSS
VSS
GAL_VSS14
GAL_VSS15
L31M1M30
R24
R26
R8
VSS
VSS
VSS
VSS
GAL_VSS10
GAL_VSS11
GAL_VSS12
GAL_VSS13
J31K1K30
R2R4R6
VSS
VSS
GAL_VSS8
GAL_VSS9
G31H1H30
P25
P27
P29
VSS
VSS
VSS
GAL_VSS5
GAL_VSS6
GAL_VSS7
D30
E31F1F30
P23
P9
VSS
VSS
VSS
GAL_VSS2
GAL_VSS3
GAL_VSS4
B30
C1
C31
N28
P3P5P7
VSS
VSS
VSS
GAL_VDD35
GAL_VSS1
A31
AD30
N24
N26
N8
VSS
VSS
VSS
VSS
GAL_VDD31
GAL_VDD32
GAL_VDD33
GAL_VDD34
AA31
AB30
AC31
N2N4N6
VSS
VSS
VSS
GAL_VDD28
GAL_VDD29
GAL_VDD30
W31
Y30
AA1
M24
M26
M28
VSS
VSS
VSS
GAL_VDD25
GAL_VDD26
GAL_VDD27
U31V1V30
W1
M8
VSS
VSS
VSS
GAL_VDD22
GAL_VDD23
GAL_VDD24
R31T1T30
L27
L29
M2M4M6
VSS
VSS
VSS
GAL_VDD19
GAL_VDD20
GAL_VDD21
N31P1P30
L23
L25
L9
VSS
VSS
VSS
GAL_VDD16
GAL_VDD17
GAL_VDD18
M31
N1
K28
L3L5L7
VSS
VSS
VSS
VSS
GAL_VDD12
GAL_VDD13
GAL_VDD14
GAL_VDD15
K31L1L30
K24
K26
K8
VSS
VSS
VSS
GAL_VDD10
GAL_VDD11
GAL_VDD9
H31J1J30
VSS
VSS
GAL_VDD7
GAL_VDD8
F31G1G30
J27
J29
K2K4K6
VSS
VSS
VSS
MTG_GND21
MTG_GND22
MTG_GND23
MTG_GND24
MTG_GND25
MTH_GND26
MTG_GND27
MTG_GND28
MTG_GND29
MTG_GND30
MTG_GND31
MTG_GND32
GAL_VDD4
GAL_VDD5
GAL_VDD6
D1
D31E1E30
J23
J25
J9
VSS
VSS
RSVD1
RSVD2
GAL_VDD2
GAL_VDD3
B4
B31
C30
J7
VSS
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
A1
A4
GAL_VDD1
A30
CPU1C
C
VCC_P
D
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
562
of
0B
Title
Micro Star Restricted Secret
Foster CPU #1 PWR
Rev
DON'T STUFF
R620
X_R
PLACE AROUND P1 SOCKET
C457
1u
C459
1u
C462
1u
C483
1u
C492
C458
0.1u
C493
0.1u
C468
0.1u
1u
C494
1u
C463
1u
VCC_P
C484
C471
0.1u
1u
VCC_P
C527
C517
C487
C479
C456
C452
C438
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
VCC_P
C550
C584
C583
C582
C470
C581
C580
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
VCC_P
C439
C453
C460
C477
C488
C518
C526
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
VCC_P
C396
C397
C469
C398
C399
C400
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
CPU1 CORE DECOUPLING
VCC_P
D
E
A
B
C
D
E
4 4
3 3
2 2
1 1
VCC_P
VCC3
VCC3
P2_SM_ADDR[0..2]<8>
P2_SM_TS_ADDR[0..1]<8>
FSB_VCC_SENSE<4>
FSB_GND_SENSE<4>
R532
X_R
DON'T STUFF
P2_ODTEN
R530
1K
OnDie
Termination
R742
X_R
DON'T STUFF
P2_SM_WP
1000p-0805
C576
P2_VCCIOPLL<11>
Enable
Disable
PD#[0..63]<4,12>
P2_VCCA<11>
P2_VSSA<11>
HCLK2_N<22>
AP#0<4,12>
AP#1<4,12>
HCLK2<22>
P2_SM_ADDR[0..2]
P2_SM_TS_ADDR[0..1]
PD#[0..63]
P2_ODTEN
TP18
1
CPU2A
PD#0
Y26
PD#1
AA27
PD#2
Y24
PD#3
AA25
PD#4
AD27
PD#5
Y23
PD#6
AA24
PD#7
AB26
PD#8
AB25
PD#9
AB23
PD#10
AA22
PD#11
AA21
PD#12
AB20
PD#13
AB22
PD#14
AB19
PD#15
AA19
PD#16
AE26
PD#17
AC26
PD#18
AD25
PD#19
AE25
PD#20
AC24
PD#21
AD24
PD#22
AE23
PD#23
AC23
PD#24
AA18
PD#25
AC20
PD#26
AC21
PD#27
AE22
PD#28
AE20
PD#29
AD21
PD#30
AD19
PD#31
AB17
PD#32
AB16
PD#33
AA16
PD#34
AC17
PD#35
AE13
PD#36
AD18
PD#37
AB15
PD#38
AD13
PD#39
AD14
PD#40
AD11
PD#41
AC12
PD#42
AE10
PD#43
AC11
PD#44
AE9
PD#45
AD10
PD#46
AD8
PD#47
AC9
PD#48
AA13
PD#49
AA14
PD#50
AC14
PD#51
AB12
PD#52
AB13
PD#53
AA11
PD#54
AA10
PD#55
AB10
PD#56
AC8
PD#57
AD7
PD#58
AE7
PD#59
AC6
PD#60
AC5
PD#61
AA8
PD#62
Y9
PD#63
AB6
AP#0
E10
AP#1
D9
HCLK2
Y4
HCLK2_N
W5
PGA-S603
PA#[3..35]
PA#[3..35]<4,12>
BREQ#1<4>
BREQ#0<4,12>
BREQ#2<4>
BREQ#3<4>
BNR#<4,11,12>
BPRI#<4,12>
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
AP0#
AP1#
BCLK0
BCLK1
A3B5D26
ODTEN
SKTOCC#
CPU_SDA <4,51>
CPU_SCL <4,51>
CPU_SMBALERT# <4>
VCC_P
VCC3
R740 43
R533 43
P2_SM_ADDR0
P2_SM_TS_ADDR1
P2_SM_TS_ADDR0
P2_SM_ADDR1
P2_SM_ADDR2
P2_SM_WP
AA5
B27
AD4
AB4
AD29
AE29
AE28
Y29
VSSA
VCCA
SM_VCC
SMB_WP
SM_VCC1
VCCIOPLL
VSSSENSE
SM_TS_A1
VCCSENSE
P2_COMP1
AA28
AB28
AB29
AA29
AC29
AC28
AD28
SM_CLK
SM_DAT
SM_TS_A0
SM_EP_A2
SM_EP_A1
SM_EP_A0
SM_ALERT
R739 180
R738 180
P2_COMP0
E16
AD16
W6W7W8Y6AA7
COMP1
COMP0
TESTHI0
TESTHI1
TESTHI2
DP#3
AE17
AD5
AE5
TESTHI3
TESTHI4
TESTHI5
TESTHI6
HREQ#[0..4]
DSTBP#[0..3]
DSTBN#[0..3]
BPM#[2..5]
VRM_VID[0..4]
DINV#[0..3]
DP#[0..3]
DP#1
DP#0
DP#2
E25
C24
E24
AC15
AE19
AC18
TDI
TCK
TDO
DP3#
DP2#
DP1#
DP0#
FOSTER
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
BR0#
BR1#
BR2#
BR3#
BNR#
BPRI#
A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13A9B8
E13
D12
C11B7A6A7C9C8D20
PA#3
PA#4
PA#5
PA#6
PA#7
PA#8
PA#9
PA#10
PA#11
PA#12
PA#13
PA#14
PA#15
PA#16
PA#17
PA#18
PA#19
PA#20
PA#21
PA#22
PA#23
PA#32
PA#33
PA#34
PA#24
PA#25
PA#26
PA#27
PA#35
PA#28
PA#29
PA#30
PA#31
BINIT#
F12
E11
D10
F20
D23
F11
BINIT#
BNR#
BPRI#
BREQ#3
BREQ#0
BREQ#2
BREQ#1
E19
F24
A25
TMS
TRST#
TRDY#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
STPCLK#
THERMTRIP#
PWRGD
PR0CH0T#
RESET#
MCERR#
DEFER#
ADSTB0#
ADSTB1#
DBSY#
DRDY#
F18
E18
DRDY#
DBSY#
DBI3#
DBI2#
DBI1#
DBI0#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
SLP#
INIT#
LINIT1
LINIT0
FERR#
IGNNE#
A20M#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
LOCK#
RSP#
RS2#
RS1#
RS0#
IERR#
HITM#
ADS#
VID0
VID1
VID2
VID3
VID4
SMI#
HIT#
HREQ#[0..4] <4,12>
DSTBP#[0..3] <4,12>
DSTBN#[0..3] <4,12>
BPM#[2..5] <4,9,11>
VRM_VID[0..4] <4,48,53>
DINV#[0..3] <4,12>
DP#[0..3] <4,12>
P2_TDO <9>
P1_TDO <4,9>
P2_TCK <9>
P_TRDY# <4,12>
ITP_TRST# <4,9>
TMS <4,9>
AB9
AE12
AD22
AC27
F3
E3
D3
C3
B3
F9
F23
W9
W23
Y11
Y14
Y17
Y20
Y12
Y15
Y18
Y21
F6
F8
E7
F5
E8
E4
AE6
D4
C27
F26
AB7
B25
D6
G23
B24
E27
C26
F27
Y8
B19
B21
C21
C20
B22
A17
D7
C6
F21
D22
E21
E5
C23
A23
E22
D19
F17
F14
Place these close to CPU2
R531 40.2
R649 40.2
Check Which CPU is
close to ITP
DINV#3
DINV#2
DINV#1
DINV#0
VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3
VRM_VID4
DSTBP#3
DSTBP#2
DSTBP#1
DSTBP#0
DSTBN#3
DSTBN#2
DSTBN#1
DSTBN#0
BPM#2
BPM#3
BPM#2
BPM#3
BPM#4
BPM#5
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
P2_IERR#
DEFER#
HITM#
HIT#
ADS#
ADSTB#0
ADSTB#1
P2_GTLREF1 <8>
P2_GTLREF0 <8>
SLP# <4,11>
CPU_STPCLK# <4,11>
SMI# <4,11>
P2_THERMTRIP# <10>
CPU2_PWRGD <49>
P2_PROCHOT# <10>
INIT# <4,11>
LINT1 <4,10,11>
LINT0 <4,10,11>
FERR# <4,10,11>
IGNNE# <4,10,11>
A20M# <4,10,11>
PROC_RESET# <4,9,11,13>
LOCK# <4,11,12>
MCERR# <4,11>
RSP# <4,12>
RS#2 <4,12>
RS#1 <4,12>
RS#0 <4,12>
P2_IERR# <10>
DEFER# <4,12>
HITM# <4,11,12>
HIT# <4,11,12>
ADS# <4,12>
ADSTB#0 <4,12>
ADSTB#1 <4,12>
VCC_P
DRDY# <4,12>
DBSY# <4,12>
BINIT# <4,11,12>
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
Foster CPU #2
E
Last Revision Date:
Tuesday, November 13, 2001
Sheet
Rev
0B
of
662
1 1
2 2
3 3
4 4
A
PGA-S603
GND42
GND43
GND44
GND45
GND46
GND47
GND48
W27
W25
R27
VCC
VCC
VCC
VCC
EMI_GND10
EMI_GND11
EMI_GND12
EMI_GND13
EMI_GND14
EMI_GND15
EMI_GND16
VCC
VCC
VCC
VCC
V24
V26
V28
VCC_P
G24
G26
M23
M25
M27
R23
R25
R9
VCC
VCC
VCC
VCC
VCC
N29
P24
P26
P28
R3R5R7
P2P4P6
P8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N3N5N7
N9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L24
L26
L28
M3M5M7
M9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
K23
K25
K27
K29
K3K5K7
K9
L2L4L6
L8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M29
N23
N25
N27
H29
J24
J26
J28
J2J4J6
J8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
G28
H23
H25
H27
H3H5H7
H9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F16
F22
F29
G2G4G6
G8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D29
E12
E20
E26
E28
F10
E2
E6
F4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C10
C16
C22
C28D8D14
D18
D24
VCC
VCC
VCC
VCC
VCC
B20
B26
B29
C2
C4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FOSTER_PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V8
U27
U29V2V4
V6
T24
T26
T28U3U5U7U9
U23
U25
AD20
AD26
AE3
AE8
AE14
AE18
AE24
R29T2T4T6T8
AD12
AC3
AC4
AC10
AC16
AC22
AD2
AD6
AB24
AB18
AB14
AA12
AA20
AA26
AB2
AB8
VSS
VSS
W29Y2Y10
Y16
Y22
AA4
AA6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H24
H26
H28J3J5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F25
F28G3G5G7G9
G25
G27
G29H2H4H6H8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E17
E23
E29F2F7
F13
F19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C29D2D5
D11
D21
D27
D28E9E15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B15
B17
B23
B28C7C13
C19
C25
A28B6B12
VCC
VCC
EMI_GND1
EMI_GND2
EMI_GND3
EMI_GND4
EMI_GND5
EMI_GND6
EMI_GND7
EMI_GND8
EMI_GND9
VSS
VSS
CPU2B
A14
A18
A24
A2
A8
VCC
VCC
VCC
VCC
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
VSS
VSS
VSS
VSS
A5
A11
A21
A27
A29B2B9
A
VCC_P
B
PGA-S603
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
AC19
AC25 AD3
VSS
VSS
VSS VSS
MTG_GND1
MTG_GND2
MTG_GND3
MTG_GND4
MTG_GND5
MTG_GND6
MTG_GND7
MTG_GND8
MTG_GND9
MTG_GND10
MTG_GND11
MTG_GND12
MTG_GND13
MTG_GND14
MTG_GND15
MTG_GND16
MTG_GND17
MTG_GND18
MTG_GND19
MTG_GND20
VSS
VSS
AD9
AC13
AD15
AA15
AA17
AA23
AB11
AB21
AB27
AC7
AC2
AA9
AB5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W24
W26
W28
AA2
Y13
Y19
Y25
Y7
VSS
VSS
VSS
VSS
VSS
V25
V27
V29
W2
W4
Y5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U24
U26
U28
V23
V3V5V7
V9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T25
T27
T29
U2U4U6
U8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R24
R26
R28
T23
T3T5T7
T9
VSS
VSS
VSS
VSS
VSS
VSS
P27
P29
R2R4R6
R8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N26
N28
P23
P25
P3P5P7
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M24
M26
M28
N24
N2N4N6
N8
VSS
VSS
VSS
VSS
VSS
VSS
L27
L29
M2M4M6
M8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K24
K26
K28
L23
L25
L9
VSS
VSS
VSS
VSS
K2K4K6
K8
L3L5L7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FOSTER_PWR
GAL_VDD10
GAL_VDD11
GAL_VDD12
GAL_VDD13
GAL_VDD14
GAL_VDD15
GAL_VDD16
GAL_VDD17
GAL_VDD18
GAL_VDD19
GAL_VDD20
GAL_VDD21
GAL_VDD22
GAL_VDD23
GAL_VDD24
GAL_VDD25
GAL_VDD26
GAL_VDD27
GAL_VDD28
GAL_VDD29
GAL_VDD30
GAL_VDD31
GAL_VDD32
GAL_VDD33
GAL_VDD34
GAL_VSS5
GAL_VSS6
D30
E31F1F30
GAL_VSS2
GAL_VSS3
GAL_VSS4
B30
C1
C31
GAL_VDD35
GAL_VSS1
A31
AD30
AC31
AB30
AA31
GAL_VDD7
GAL_VDD8
GAL_VDD9
F31G1G30
H31J1J30
K31L1L30
M31
N1
N31P1P30
R31T1T30
U31V1V30
W1
W31
Y30
AA1
RSVD88
VSS
VSS
VSS
VSS
VSS
VSS
Y28
AA3
AC1
AD1
AB3
AE4
AE15
AE16
AE11
AE21
AE27
AD17
AD23
AE2
RSVD3
RSVD4
RSVD5
RSVD8
A15
A16
A26
B1
C5
D25
W3
Y3
Y27
AD31
AC30
AB31
V31
W30
Y1
Y31
AA30
AB1
L31M1M30
N30
P31R1R30
T31U1U30
GAL_VSS34
RSVD13
RSVD17
RSVD63
RSVD67
RSVD68
RSVD69
RSVD73
RSVD80
RSVD83
RSVD77
RSVD86
RSVD87
GAL_VSS7
GAL_VSS8
GAL_VSS9
G31H1H30
J31K1K30
GAL_VSS10
GAL_VSS11
GAL_VSS12
GAL_VSS13
GAL_VSS14
GAL_VSS15
GAL_VSS16
GAL_VSS17
GAL_VSS18
GAL_VSS19
GAL_VSS20
GAL_VSS21
GAL_VSS22
GAL_VSS23
GAL_VSS24
GAL_VSS25
GAL_VSS26
GAL_VSS27
GAL_VSS28
GAL_VSS29
GAL_VSS30
GAL_VSS31
GAL_VSS32
GAL_VSS33
J27
J29
J25
VSS
VSS
VSS
VSS
MTG_GND21
MTG_GND22
MTG_GND23
MTG_GND24
MTG_GND25
MTG_GND26
MTG_GND27
MTG_GND28
MTG_GND29
MTG_GND30
MTG_GND31
MTG_GND32
RSVD1
RSVD2
GAL_VDD3
GAL_VDD4
GAL_VDD5
GAL_VDD6
C30
D1
D31E1E30
J23
J7
J9
VSS
VSS
GAL_VDD1
GAL_VDD2
A30
B4
B31
CPU2C
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
A1
A4
B
VCC_P
C
DON'T STUFF
R736
X_R
C
D
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
762
of
0B
Title
Micro Star Restricted Secret
Foster CPU #2 PWR
Rev
PLACE AROUND P2 SOCKET
C515
1u
CPU2 CORE
C544
C522
C519
C486
C478
C454
C448
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
VCC_P
4.7u-0805
C389
VCC_P
C390
C391
C392
C499
C393
C394
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
VCC_P
4.7u-0805
C450
C455
C480
C489
C516
C523
C541
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
C513
1u
C503
1u
C481
1u
C514
0.1u
C475
0.1u
C495
0.1u
C497
0.1u
VCC_P
C507
1u
C482
1u
C476
1u
VCC_P
C474
1u
C575
C574
C573
C572
C498
C571
C570
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
4.7u-0805
DECOUPLING
D
VCC_P
E
A
4 4
B
C
D
E
R568
X_R
R718
X_R
DON'T STUFF
VCC3
R576
X_R
R577
R569
1K
1K
VCC3
R708
X_R
R7091KR697
R719
1K
VCC_P
R561
51
C426
0.1u
R604
X_R
DON'T STUFF
P1_SM_ADDR0
P1_SM_ADDR1P1_SM_TS_ADDR0
P1_SM_ADDR2
R605
1K
Addr._0 : 1010 000Z
R696
1K
P2_SM_ADDR0
P2_SM_ADDR1
P2_SM_ADDR2
X_R
DON'T STUFF
P1_GTLREF1
C414
R585
C418
0.1u
1u
100
Z = R/W bit
Addr._1 : 1010 001Z
P1_GTLREF1 <4>P1_GTLREF0 <4>
P1_SM_ADDR[0..2]
P2_SM_ADDR[0..2]
P1_SM_TS_ADDR[0..1]
P2_SM_TS_ADDR[0..1]
P1_SM_ADDR[0..2] <4>
P2_SM_ADDR[0..2] <6>
P1_SM_TS_ADDR[0..1] <4>
P2_SM_TS_ADDR[0..1] <6>
Z = R/W bit
CPU_0 Thermal Sensor SM Bus
Addr._0 : 0011X00Z
: 1001X00Z
: 0101X00Z
3 3
OR
OR
CPU_1 Thermal Sensor SM Bus
Addr._1 : 0011X01Z
: 1001X01Z
: 0101X01Z
2 2
DON'T STUFF
OR
OR
R687
X_R
R688
1K
R615
X_R
R614
1K
VCC3
VCC3
VCC_P
R543
51
C383
0.1u
R588
DON'T STUFF
X_R
P1_SM_TS_ADDR1
R589
1K
R700
1K
P2_SM_TS_ADDR0
P2_SM_TS_ADDR1
R701
X_R
DON'T STUFF
R536
C384
100
0.1u
P1_GTLREF0
C385
1u
VCC_P
R737
51
P2_GTLREF0 P2_GTLREF1
C586
C587
0.1u
1 1
A
B
R741
0.1u
C585
100
1u
PLACE EACH 220pf OF
GTLREF NEAR PROC
PIN
C
VCC_P
R690
51
C551
0.1u
C557
0.1u
R707
100
C562
1u
P2_GTLREF1 <6>P2_GTLREF0 <6>
Micro Star Restricted Secret
Title
CPU GTLREF & SM Bus Slave Address
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
Rev
0B
of
862
1 1
2 2
3 3
4 4
A
CLK_100M_ITP = BCLK (to
processors) + Length of
BPM# trace from ITP
Place this HDR next to the
CPU nearest to ITP conn.
D1x3-BK
JP8_23
JC-D2-GN
B
P2_TDO
Look at Routing guidelines while
Placing components from this
sheet
P1_TDO <4,6>
P2_TDO <6>
RES. TO BE WITHIN
1" OF ITP CONN.
JP8
123
R441
150
R418
330
P1_TDI
P1_TDO
R393
75
RES. TO BE WITHIN
1" OF ITP CONN.
P1_TDI <4>
VCC_P
VCC_P
LAYOUT NOTE:
BPM#[0..5], RST#, FBO, BCKN, BCKP, TCK, AND FBI
ARE CRITICAL ROUTES.
R396 1K
R484 330
processors) + Length of
BPM# trace from ITP
connector to first CPU.
R499 1K
R400 1K
R399 1K
R397 1K
FBO = TCK (to
74LVC244A-SO20
GND
VCC
10
VCC_P
C308
0.1u
17119
2A41G2G
2Y4
VCC_P
TCK
246
1A1
U26
1Y1
18161412975320
R_P1_TCK
R403 22
R945 X_0
R944 X_0
R_P2_TCK
R_FBO
P1_TCK =
P2_TCK
TCK
R943 X_0
R_P1_TCK
Length of
111315
8
1A2
1A3
1A4
2A1
2A2
2A3
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
R_P2_TCK
R_FBO
R398 22
R404 22
C
D
connector to first CPU.
X_R
X_R
R497
680
RES. TO BE WITHIN
1" OF ITP CONN.
R493
150
Within 1" of the last
device on this Net
R505
R506
CLK_100M_ITP1<22>
25
X_CON25A_1
24
24
P2_TDO
ITP Conn. as
possible
THIS NET TO BE DAISY
CHAINED ALONG PROCS.
Place it as close to
CLK_100M_ITP0<22>
PROC_RESET#<4,6,11,13>
BPM#5<4,6,11>
FBO
R494 0
TCK
ITP_TRST# <4,6>
BPM#3<4,6,11>
BPM#4<4,6,11>
11131517192123
10121416182022
P1_TDI
TMS <4,6>
BPM#2<4,6,11>
8
ITP_RESET# <49>
DBA#
13579
135791113151719212325
246
246810121416182022
RES. TO BE WITHIN
1" OF ITP CONN.
R480 40.2
R495 40.2
R541 40.2
R540 40.2
R542 40.2
PLACE NEAR CPU1
J3
RES. TO BE WITHIN
1" OF ITP CONN.
R496
39.2
R498
1K
R517
150
R516
X_R
DON'T STUFF
VCC_P
VCC_P
VCC_P
VCC3
A
B
C
D
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
962
of
0B
Title
Micro Star Restricted Secret
CPU GTLREF & SM Bus Slave Address
Rev
X_22P
C351
X_22P
X_22P
C352
C340
FBO
P1_TCK <4>
P2_TCK <6>
E
A A
B B
C C
D D
5
VCC3
RESETDLY#
G
GTL2005
NMI
13115
4Y
B1B2B3
A1A2A3
12
A20M#_3V
LINT1_3V
131210
235
A20M#
LINT1
RSB_IGNNE#<39>
INTR<39>
RSB_IGNNE#
111014
6
VCCGND
LINT0_3V
IGNNE#_3V
GTLREF_1
9
4 1
B4
GTLREF DIRB-A
A4
6
LINT0
IGNNE#
INTR
RN108
330
123456
78
P6_CGF1
P6_CGF3
P6_CGF2
235
1A1B2A2B3A3B4A4BA/B
1Y2Y3Y
479
P6_CGF4
VCC
168
U45
11
8
GND
GND
GND
VDD
14
7
R711
1K
B1B2B3
B4
SW1
D4P-D-SB
A1A2A3
A4
U39
VCC3
R762
0
P1_PROCHOT#<4>
P2_PROCHOT#<6>
P1_THERMTRIP#<4>
P1_IERR#<4>
P2_IERR#<6>
4
R689 51
R695
330
VCC3
7
GTL2005
VDD
GND
GND
GND
3
C545
1000p-0805
R684 51
R680 51
R679 51
14
6
A4
GTLREFDIRB-A
B4
9
41811
GTLREF_1
GTLREF_1
RSB_P2_PROCHOT# <39>
RSB_P1_IERR# <39>
RSB_P2_IERR# <39>
1000p-0805
235
U38
A1A2A3
B1B2B3
131210
RN104
1K
RSB_P1_PROCHOT# <39>
C549
VCC_P
VCC3
VCC3
12
34
56
78
P2_THERMTRIP#<6>
R683 51
R626 51
C559
0.1u
R694
100
C556
0.1u
RSB_A20M#
R727
330
RSB_A20M# <39>
NMI <38>
VCC_P
VCC_P
R699
51
GTLREF_1
RESETDLY# <12>
C558
1000p-0805
C577
1000p-0805
C566
1000p-0805
74F157-SOIC16
GTLREF_1
VCC3VCC
5
4
3
2
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
Last Revision Date:
Sheet
Tuesday, November 13, 2001
10 62
of
0B
Title
Micro Star Restricted Secret
Ratio & Level Shift Circuit
Rev
FERR#<4,6,11>
LINT0 <4,6,11>
IGNNE# <4,6,11>
A20M# <4,6,11>
LINT1 <4,6,11>
X8 H H H H
X9/X23 H H H L
X20 H H L H
X10 H H L L
X12 H L H H
X13 H L H L
X14 H L L H
X15 H L L L
X16 L H H H
X17 L H H L
X18 L H L H
X19 L H L L
X20 L L H H
X21 L L H L
X22 L L L H
X24 L L L L
NMI A20M# IGNNE# INTR
LINT1
VCC_P
R712
330
VCC_P
R717
330
Q45
NPN-PMBT2369-SOT23
RSB_FERR# <38>
VCC3
R725
330
LINT0
2
1
1 1
2 2
3 3
4 4
A
VCC_P VCC_P
R551 0
1 2
L24 4.7u_1206
10u
10u
EC75
EC74
+
1 2
B
P1_VCCIOPLL <4>
R759 0
1 2
L33 4.7u_1206
10u
C
1 2
C3871uC380
1u
P1_VSSA <4>
10u
EC104
+
+
EC103
+
R524 0
1 2
L23 4.7u_1206
12
P1_VCCA <4>
R758 0
1 2
L32 4.7u_1206
12
Place these Close to CPU1
Place these Close to CPU2
BPM#[2..5]<4,6,9>
CMIC_PINIT#<12,39,46>
(Make small Cu Islands for P1/P2_VCCA, P1/P2_VSSA and P1/P2_VCCIOPLL nets )
9 8
DM7407-SOIC14
INIT#
VCC25
U46D
R730 1K
EXT_SMI#<39,45>
VCC3
5 6
DM7407-SOIC14
SMI#
R733 1K
U46C
MCERR#<4,6>
LOCK#<4,6,12>
HITM#<4,6,12>
BNR#<4,6,12>
HIT#<4,6,12>
BINIT#
PLACE THESE
CLOSE TO
CPU2
R622 150
R599 150
R586 150
R621 150
R609 150
R598 150
VCC_P
SLP#<4,6>
SLP#
A20M#<4,6,10>
BPM#4
BPM#5
BPM#4
BPM#3
BPM#2
LINT0<4,6,10>
LINT1<4,6,10>
IGNNE#<4,6,10>
BINIT#<4,6,12>
FERR#<4,6,10>
INIT#<4,6>
SMI#<4,6>
SMI#
INIT#
CPU_STPCLK#
R642 40.2
R713 40.2
R698 40.2
R702 40.2
R685 40.2
R720 40.2
R715 40.2
R706 40.2
R724 40.2
R704 40.2
R607 X_R
R629 X_R
R691 X_R
R617 40.2
R606 40.2
R623 40.2
R616 40.2
VCC_P
PLACE NEAR CPU1
DON'T STUFF PLACE NEAR CPU2
PROC_RESET#<4,6,9,13>
CPU_STPCLK#<4,6>
A
B
C
D
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
11 62
of
0B
Title
Micro Star Restricted Secret
CPU Level Shift Circuit
Rev
P2_VCCIOPLL <6>
C5951uC594
1u
P2_VSSA <6>
P2_VCCA <6>
C579
VCC3
RSB_STPCLK#<39>
1 2
DM7407-SOIC14
CPU_STPCLK#
VCC
U46A
PLACE THE TERM CAPS NEAR THE TERMINATION
RESISTORS
VCC3
1K
R753
13 12
DM7407-SOIC14
U46F
11 10
DM7407-SOIC14
U46E
RSB_SLP#<39>
3 4
DM7407-SOIC14
SLP#
U46B
1K
R744
0.1u
VCC_P VCC_P
C436
0.1u
C432
0.1u
C427
0.1u
C419
0.1u
C440
0.1u
C382
0.1u
D
E
A
4 4
3 3
DSTBN#[0..3]<4,6>
DSTBP#[0..3]<4,6>
PCIRST_X#<52>
2 2
R306
VCC25
R299
VCC25
R307
VCC25
R308
VCC25
R310
VCC25
VCC_P
R373 100
R346 255
R343 20
*** Difference
with Rev:A1.0
Ckt
DINV#[0..3]<4,6>
R305
C240
22p
4.7K
10K
4.7K
4.7K
4.7K
PA#[3..35]<4,6>
PD#[0..63]<4,6>
DP#[0..3]<4,6>
MEMOFFACK#
WRMRST#
CMIC_FATAL#
MEMOFF#
ALERT#
GTL_COMP_PD
GTL_COMP_PU
GTL_RCOMP
B
PA#[3..35]
PD#[0..63]
DINV#[0..3]
DP#[0..3]
DSTBN#[0..3]
DSTBP#[0..3]
22
C
PA#3
PA#4
PA#5
PA#6
PA#7
PA#8
PA#9
PA#10
PA#11
PA#12
PA#13
PA#14
PA#15
PA#16
PA#17
PA#18
PA#19
PA#20
PA#21
PA#22
PA#23
PA#24
PA#25
PA#26
PA#27
PA#28
PA#29
PA#30
PA#31
PA#32
PA#33
PA#34
PA#35
ADSTB#0
ADSTB#0<4,6>
ADSTB#1
ADSTB#1<4,6>
ADS#
ADS#<4,6>
BNR#
BNR#<4,6,11>
BPRI#
BPRI#<4,6>
DBSY#
DBSY#<4,6>
DRDY#
DRDY#<4,6>
HIT#
HIT#<4,6,11>
HITM#
HITM#<4,6,11>
LOCK#
LOCK#<4,6,11>
P_TRDY#
P_TRDY#<4,6>
DEFER#
DEFER#<4,6>
BREQ#0
BREQ#0<4,6>
PS_PWRGD#<25,27,39,49>
RESETDLY#<10>
CMIC_PINIT#<11,39,46>
HCLK_CMIC<22>
HCLK_CMIC_N<22>
CMIC_FATAL#<16,39>
MEMOFFACK#<16>
RESETDLY#
R_PCIRST_X#
WRMRST#
WRMRST#<16>
RS#0
RS#0<4,6>
RS#1
RS#1<4,6>
RS#2
RS#2<4,6>
RSP#
RSP#<4,6>
HREQ#0
HREQ#0<4,6>
HREQ#1
HREQ#1<4,6>
HREQ#2
HREQ#2<4,6>
HREQ#3
HREQ#3<4,6>
HREQ#4
HREQ#4<4,6>
AP#0
AP#0<4,6>
AP#1
AP#1<4,6>
ALERT#
ALERT#<16,25,27,39>
BINIT#<4,6,11>
CMIC_FATAL#
MEMOFF#
MEMOFF#<16,38>
MEMOFFACK#
GTL_VREF_CMIC
GTL_COMP_PU
GTL_COMP_PD
GTL_RCOMP
VCC25
12
U20A
K15
AG25
AG24
AG26
AE25
AE24
AF26
AE26
AF27
AF23
AD27
AE27
A17
A19
B18
A18
B19
A20
G16
C19
E19
H17
H16
D19
F18
H18
G19
F19
A23
B23
A22
A21
F20
B20
A24
A25
D20
B21
E20
B25
B27
A26
C22
D22
D18
C20
H19
K17
F23
D24
E16
G15
F15
C16
H15
E23
C24
F21
K18
G21
F22
H20
F1
G2
H5
C1
D1
G3
F4
E1
B1
G1
F2
H9
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB0#
ADSTB1#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
LOCK#
TRDY#
DEFER#
BREQ0#
PLLRST
DLYRST
PCIRST#
WRMRST#
RS0#
RS1#
RS2#
RSP#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
AP0#
AP1#
ALERT#
BINIT#
HINIT#
BCLKP
BCLKN
FATAL#
MEMOFF#
MEMOFFACK#
GTL_VREF
GTL_VREF
GTL_COMP_PU
GTL_COMP_PD
GTL_RCOMP
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DP0#
DP1#
DP2#
DP3#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
CMIC-CE
+
EC50
150u
C251
1u
C262
1000p-0805
C274
1000p-0805
PD#0
C2
PD#1
E3
PD#2
B3
PD#3
C3
PD#4
F3
PD#5
D4
PD#6
A2
PD#7
D2
PD#8
D3
PD#9
A3
PD#10
H6
PD#11
F6
PD#12
G8
PD#13
F5
PD#14
H8
PD#15
H10
PD#16
F7
PD#17
G9
PD#18
E7
PD#19
E6
PD#20
A4
PD#21
B4
PD#22
D7
PD#23
A5
PD#24
G10
PD#25
K11
PD#26
B7
PD#27
C6
PD#28
F8
PD#29
C7
PD#30
E9
PD#31
K12
PD#32
D8
PD#33
C8
PD#34
D9
PD#35
B9
PD#36
E10
PD#37
A7
PD#38
A10
PD#39
A8
PD#40
B12
PD#41
A11
PD#42
F12
PD#43
A12
PD#44
G13
PD#45
F13
PD#46
K13
PD#47
H12
PD#48
B13
PD#49
D12
PD#50
A13
PD#51
E13
PD#52
C13
PD#53
C14
PD#54
A15
PD#55
B15
PD#56
D15
PD#57
E14
PD#58
E15
PD#59
H14
PD#60
K14
PD#61
C15
PD#62
A16
PD#63
G14
DINV#0
G5
DINV#1
A6
DINV#2
C10
DINV#3
H13
DP#0
C26
DP#1
B26
DP#2
E21
DP#3
E25
DSTBN#0
G6
DSTBN#1
F9
DSTBN#2
C9
DSTBN#3
D13
DSTBP#0
H7
DSTBP#1
H11
DSTBP#2
A9
DSTBP#3
A14
D
E
VCC_P
R349
GTL_VREF_CMIC
C271
1u
C269
0.1u
51
R347
100
VCC25
C241
0.1u
C242
0.1u
C236
0.1u
C238
0.1u
C237
0.1u
0.1u
C256
VCC25
C259
1u
1 1
Micro Star Restricted Secret
Title
CMIC Foster Interface
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
12 62
Rev
0B
A
B
C
D
E
B_IMB_D_R[0..15]<27>
4 4
3 3
2 2
B_IMB_D_T[0..15]<27>
A_IMB_D_R[0..15]<25>
A_IMB_D_T[0..15]<25>
T_IMB_D_R[0..3]<39>
T_IMB_D_T[0..3]<39>
T_IMB_CLK_T<39>
T_IMB_CON_T<39>
T_IMB_PAR_T<39>
B_IMB_D_R[0..15]
B_IMB_D_T[0..15]
A_IMB_D_R[0..15]
A_IMB_D_T[0..15]
T_IMB_D_R[0..3]
T_IMB_D_T[0..3]
T_IMB_D_T0
T_IMB_D_T1
T_IMB_D_T3
B_IMB_CON_R<27>
B_IMB_CLK_R_P<27>
B_IMB_CLK_R_N<27>
B_IMB_PAR_R<27>
B_IMB_CON_T<27>
B_IMB_CLK_T_P_R<27>
B_IMB_CLK_T_N_R<27>
B_IMB_PAR_T<27>
R322 24
R314 24
R325 24
R335 24
R323 24
R326 24
R311 24
IMB_VREF_CMIC
B_IMB_D_R0
B_IMB_D_R1
B_IMB_D_R2
B_IMB_D_R3
B_IMB_D_R4
B_IMB_D_R5
B_IMB_D_R6
B_IMB_D_R7
B_IMB_D_R8
B_IMB_D_R9
B_IMB_D_R10
B_IMB_D_R11
B_IMB_D_R12
B_IMB_D_R13
B_IMB_D_R14
B_IMB_D_R15
B_IMB_D_T0
B_IMB_D_T1
B_IMB_D_T2
B_IMB_D_T3
B_IMB_D_T4
B_IMB_D_T5
B_IMB_D_T6
B_IMB_D_T7
B_IMB_D_T8
B_IMB_D_T9
B_IMB_D_T10
B_IMB_D_T11
B_IMB_D_T12
B_IMB_D_T13
B_IMB_D_T14
B_IMB_D_T15
R930 0
R932 0
R_TIMB_D_T0
R_TIMB_D_T1
R_TIMB_D_T2T_IMB_D_T2
R_TIMB_D_T3
R_TIMB_CLKT
R_TIMB_CONT
R_TIMB_PART
IMB_VREF_CMIC
CMIC_IMB_COMP_PD
CMIC_IMB_COMP_PU
CMIC_IMB_RCOMP
U20B
R25
BIMBD_R0
T23
B IMBD_R1
R26
BIMBD_R2
R27
BIMBD_R3
R22
BIMBD_R4
P23
BIMBD_R5
R24
BIMBD_R6
R23
BIMBD_R7
N25
BIMBD_R8
N22
BIMBD_R9
P21
BIMBD_R10
N23
BIMBD_R11
N24
BIMBD_R12
P20
BIMBD_R13
R18
BIMBD_R14
R17
BIMBD_R15
N20
BIMBCON_R
P25
BIMBCLK_R_P
P27
BIMBCLK_R_N
N21
BMBPAR_R
U21
BIMBD_T0
U23
BIMBD_T1
T20
BIMBD_T2
U18
BIMBD_T3
U17
BIMBD_T4
V20
BIMBD_T5
U20
BIMBD_T6
T22
BIMBD_T7
T21
BIMBD_T8
R21
BIMBD_T9
T25
BIMBD_T10
U27
BIMBD_T11
T24
BIMBD_T12
U25
BIMBD_T13
T27
BIMBD_T14
T26
BIMBD_T15
R20
BIMBCON_T
W26 L25
BIMBCLK_T_P AIMBCLK_T_P
W27
BIMBCLK_T_N
V27
BIMBDPAR_T
Y22
T_IMBD_T0
AA25
T_IMBD_T1
Y21
T_IMBD_T2
Y24
T_IMBD_T3
P18
IMB_VREF
D27
IMB_COMP_PD
H21
IMB_COMP_PU
G22
IMB_RCOMP
AIMBD_R0
AIMBD_R1
AIMBD_R2
AIMBD_R3
AIMBD_R4
AIMBD_R5
AIMBD_R6
AIMBD_R7
AIMBD_R8
AIMBD_R9
AIMBD_R10
AIMBD_R11
AIMBD_R12
AIMBD_R13
AIMBD_R14
AIMBD_R15
AIMBCON_R
AIMBCLK_R_P
AIMBCLK_R_N
AIMBPAR_R
AIMBD_T0
AIMBD_T1
AIMBD_T2
AIMBD_T3
AIMBD_T4
AIMBD_T5
AIMBD_T6
AIMBD_T7
AIMBD_T8
AIMBD_T9
AIMBD_T10
AIMBD_T11
AIMBD_T12
AIMBD_T13
AIMBD_T14
AIMBD_T15
AIMBCON_T
AIMBCLK_T_N
AIMBPAR_T
T_IMBD_R0
T_IMBD_R1
T_IMBD_R2
T_IMBD_R3
T_IMBCLK_RT_IMBCLK_T
T_IMBCON_RT_IMBCON_T
T_IMBPAR_RT_IMBPAR_T
CPURST#
SRESET#
TESTMODE#
SCLK
SDA
CMIC-CE
L20
L17
L18
K20
J24
H23
H22
J22
H26
F27
G24
G27
G25
E27
F24
J20
F25
H25
H24
F26
M26
M25
N27
N18
N17
M24
N26
L27
M27
L21
M22
H27
J27
K27
J26
M21
M20
M23
L23
Y26
W24
AA26
W22
Y27AA24
AA27AA23
W20AB25
C27
AF25
AD26
AE23
AG23
A_IMB_D_R0
A_IMB_D_R1
A_IMB_D_R2
A_IMB_D_R3
A_IMB_D_R4
A_IMB_D_R5
A_IMB_D_R6
A_IMB_D_R7
A_IMB_D_R8
A_IMB_D_R9
A_IMB_D_R10
A_IMB_D_R11
A_IMB_D_R12
A_IMB_D_R13
A_IMB_D_R14
A_IMB_D_R15
A_IMB_D_T0
A_IMB_D_T1
A_IMB_D_T2
A_IMB_D_T3
A_IMB_D_T4
A_IMB_D_T5
A_IMB_D_T6
A_IMB_D_T7
A_IMB_D_T8
A_IMB_D_T9
A_IMB_D_T10
A_IMB_D_T11
A_IMB_D_T12
A_IMB_D_T13
A_IMB_D_T14
A_IMB_D_T15
R931 0
R933 0
T_IMB_D_R0
T_IMB_D_R1
T_IMB_D_R2
T_IMB_D_R3
R318 1K
A_IMB_CON_R <25>
A_IMB_CLK_R_P <25>
A_IMB_CLK_R_N <25>
A_IMB_PAR_R <25>
A_IMB_CON_T <25>
A_IMB_CLK_T_P_R <25>
A_IMB_CLK_T_N_R <25>
A_IMB_PAR_T <25>
T_IMB_CLK_R <39>
T_IMB_CON_R <39>
T_IMB_PAR_R <39>
PROC_RESET# <4,6,9,11>
POWERGOOD_CMIC <16,49>
VCC25
TESTMODE# <16>
RCC_SDA <16,25,27,48,51>
RCC_SCL <16,25,27,48,51>
C273
0.1u
VDD_IMB
C277
1000p-0805
C
R340
100
R334
100
Micro Star Restricted Secret
Title
CMIC IMB Interface
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
13 62
Rev
0B
VDD_IMB
IMB_VREF_CMIC
C270
1u
IMB_VREF_CMIC
B
CMIC_IMB_COMP_PD
CMIC_IMB_RCOMP
CMIC_IMB_COMP_PU
CMIC_IMB_COMP_PD
CMIC_IMB_COMP_PU
R372 X_255
R350 100
R883 100
R884 255
R358 X_255
*** Difference with
Rev:A1.0 Ckt
1 1
A
A
B
C
D
E
4 4
R_A_SD0_0
AA22
R_A_SD0_1
AD22
R_A_SD0_2
AC19
R_A_SD0_3
AA18
R_A_SD0_4
AB23
R_A_SD0_5
AB19
R_A_SD0_6
AD19
R_A_SD0_7
R_A_SD1_0
R_A_SD1_1
R_A_SD1_2
R_A_SD1_3
R_A_SD1_4
R_A_SD1_5
R_A_SD1_6
R_A_SD1_7
R_A_SD2_0
R_A_SD2_1
R_A_SD2_2
R_A_SD2_3
R_A_SD2_4
R_A_SD2_5
R_A_SD2_6
R_A_SD2_7
R_A_SD3_0
R_A_SD3_1
R_A_SD3_2
R_A_SD3_3
3 3
2 2
1 1
R_A_SD3_4
R_A_SD3_5
R_A_SD3_6
R_A_SD3_7
R_A_SD4_0
R_A_SD4_1
R_A_SD4_2
R_A_SD4_3
R_A_SD4_4
R_A_SD4_5
R_A_SD4_6
R_A_SD4_7
R_A_SD5_0
R_A_SD5_1
R_A_SD5_2
R_A_SD5_3
R_A_SD5_4
R_A_SD5_5
R_A_SD5_6
R_A_SD5_7
R_A_SD6_0
R_A_SD6_1
R_A_SD6_2
R_A_SD6_3
R_A_SD6_4
R_A_SD6_5
R_A_SD6_6
R_A_SD6_7
R_A_SD7_0
R_A_SD7_1
R_A_SD7_2
R_A_SD7_3
R_A_SD7_4
R_A_SD7_5
R_A_SD7_6
R_A_SD7_7
R_A_SD8_0
R_A_SD8_1
R_A_SD8_2
R_A_SD8_3
R_A_SD8_4
R_A_SD8_5
R_A_SD8_6
R_A_SD8_7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
Y16
V15
AG22
AB15
AD16
AG21
AF19
AG17
AB16
AG14
Y14
AF13
AG12
AE14
V14
AG13
AE13
Y13
AF9
AE8
AD10
AA12
AG8
AG6
AG5
T10
Y4
R11
T7
W5
Y3
U6
U1
T3
R2
R4
R5
T5
R1
K8
R6
N3
N1
M2
M4
N8
N4
L1
M3
H1
H2
L6
M10
J5
J3
L8
K10
AF3
AG2
AB10
AA9
AE6
AF5
AC8
AB9
AD5
AE5
Y10
AA8
Y9
Y7
AF1
AE2
AD3
AE3
AF2
Y8
CMIC-CE
U20C
A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7
A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7
A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7
A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7
A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7
A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7
A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7
A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7
A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
R_A_DQS0_0
R_A_DQS0_1
R_A_DQS1_0
R_A_DQS1_1
R_A_DQS2_0
R_A_DQS2_1
R_A_DQS3_0
R_A_DQS3_1
R_A_DQS4_0
R_A_DQS4_1
R_A_DQS5_0
R_A_DQS5_1
R_A_DQS6_0
R_A_DQS6_1
R_A_DQS7_0
R_A_DQS7_1
R_A_DQS8_0
R_A_DQS8_1
AC20
AG20
AB13
AE9Y2T4
AC13
AF8W1P7N7H3
A_DQS2_0
A_DQS3_0
A_DQS4_0
A_DQS2_1
A_DQS3_1
B_DQS2_0
B_DQS3_0
B_DQS1_1
B_DQS2_1
B_DQS3_1
AE15
AG11
AA4P1R10L4AC9
AD15
AG10Y5P3U2M7
R_B_DQS2_0
R_B_DQS2_1
R_B_DQS3_0
R_B_DQS3_1
R_B_DQS4_0
N10H4Y11
V11
B_SD0_0
B_SD0_1
B_SD0_2
A_DQS5_0
A_DQS6_0
A_DQS4_1
A_DQS5_1
B_DQS4_0
B_DQS5_0
B_DQS4_1
B_DQS5_1
R_B_DQS4_1
R_B_DQS5_0
R_B_DQS5_1
R_B_DQS6_0
B_SD0_3
A_DQS7_0
A_DQS8_0
A_DQS6_1
A_DQS7_1
A_DQS8_1
B_SD0_4
B_SD0_5
B_SD0_6
B_SD0_7
B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7
B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7
B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7
B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7
B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7
B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7
B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7
B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7
B_DQS6_0
B_DQS7_0
B_DQS8_0
B_DQS6_1
B_DQS7_1
B_DQS8_1
CS7
AF6
Y6
AA6
R_B_DQS6_1
R_B_DQS7_0
R_B_DQS7_1
R_B_DQS8_0
R_B_DQS8_1
TP3
1
TP2
WE#
RAS#
CAS#
A_CKE
B_CKE
CS6
1
R_B_SD0_0
Y20
R_B_SD0_1
AA21
R_B_SD0_2
AA19
R_B_SD0_3
V17
R_B_SD0_4
V18
R_B_SD0_5
Y19
R_B_SD0_6
AB20
R_B_SD0_7
Y18
R_B_SD1_0
AF22
R_B_SD1_1
AE21
R_B_SD1_2
Y17
R_B_SD1_3
V16
R_B_SD1_4
AE22
R_B_SD1_5
AE20
R_B_SD1_6
AC18
R_B_SD1_7
AE18
R_B_SD2_0
AF16
R_B_SD2_1
AF15
R_B_SD2_2
AC15
R_B_SD2_3
AB14
R_B_SD2_4
AG16
R_B_SD2_5
AG15
R_B_SD2_6
AD14
R_B_SD2_7
Y15
R_B_SD3_0
AA13
R_B_SD3_1
AD13
R_B_SD3_2
AC12
R_B_SD3_3
AG9
R_B_SD3_4
V13
R_B_SD3_5
AE12
R_B_SD3_6
AF10
R_B_SD3_7
AG7
R_B_SD4_0
AB4
R_B_SD4_1
AB2
R_B_SD4_2
AA1
R_B_SD4_3
T8
R_B_SD4_4
AA3
R_B_SD4_5
AA2
R_B_SD4_6
Y1
R_B_SD4_7
AA5
R_B_SD5_0
P8
R_B_SD5_1
R3
R_B_SD5_2
P5
R_B_SD5_3
J8
R_B_SD5_4
P10
R_B_SD5_5
N2
R_B_SD5_6
N5
R_B_SD5_7
N6
R_B_SD6_0
W3
R_B_SD6_1
V1
R_B_SD6_2
T2
R_B_SD6_3
T1
R_B_SD6_4
T6
R_B_SD6_5
U4
R_B_SD6_6
R7
R_B_SD6_7
R8
R_B_SD7_0
M1
R_B_SD7_1
J1
R_B_SD7_2
M5
R_B_SD7_3
L10
R_B_SD7_4
K1
R_B_SD7_5
L2
R_B_SD7_6
M6
R_B_SD7_7
M8
R_B_SD8_0
AD9
R_B_SD8_1
AD8
R_B_SD8_2
AG4
R_B_SD8_3
AD7
R_B_SD8_4
V12
R_B_SD8_5
Y12
R_B_SD8_6
AE7
R_B_SD8_7
AG3
WE#
AB1
RAS#
AC1
CAS#
W8
A_CKE
AB8
B_CKE
AE4
R_CS_0
U8
CS0
R_CS_1
U10
CS1
R_CS_2
W7
CS2
R_CS_3
V8
CS3
R_CS_4
AE1
CS4
R_CS_5
AD1
CS5
R34239.2
CS_0
CS_1
CS_2
CS_3
CS_4
CS_5
CS_0 <17,18>
CS_1 <17,18>
CS_2 <17,18>
CS_3 <17,18>
CS_4 <19>
CS_5 <19>
R34439.2
R33639.2
R33939.2
R91739.2
R91839.2
AD20
AG19
A_DQS0_0
A_DQS1_0
A_DQS0_1
A_DQS1_1
B_DQS0_0
B_DQS1_0
B_DQS0_1
MA12
MA13
MA14
AA20
AF20
AB21
AE19
V10
AA7
AB6
R_B_DQS0_0
R_B_DQS0_1
R_B_DQS1_0
R_B_DQS1_1
R_B_SD0_[0..7]<20>
R_B_SD1_[0..7]<20>
R_B_SD2_[0..7]<20>
R_B_SD3_[0..7]<20>
R_B_SD4_[0..7]<20>
R_B_SD5_[0..7]<20>
R_B_SD6_[0..7]<20>
R_B_SD7_[0..7]<20>
R_B_SD8_[0..7]<20>
R_B_DQS0_[0..1]<20>
R_B_DQS1_[0..1]<20>
R_B_DQS2_[0..1]<20>
R_B_DQS3_[0..1]<20>
R_B_DQS4_[0..1]<20>
R_B_DQS5_[0..1]<20>
R_B_DQS6_[0..1]<20>
R_B_DQS7_[0..1]<20>
R_B_DQS8_[0..1]<20>
R_A_SD0_[0..7]<20>
R_A_SD1_[0..7]<20>
R_A_SD2_[0..7]<20>
R_A_SD3_[0..7]<20>
R_A_SD4_[0..7]<20>
R_A_SD5_[0..7]<20>
R_A_SD6_[0..7]<20>
R_A_SD7_[0..7]<20>
R_A_SD8_[0..7]<20>
R_A_DQS0_[0..1]<20>
R_A_DQS1_[0..1]<20>
R_A_DQS2_[0..1]<20>
R_A_DQS3_[0..1]<20>
R_A_DQS4_[0..1]<20>
R_A_DQS5_[0..1]<20>
R_A_DQS6_[0..1]<20>
R_A_DQS7_[0..1]<20>
R_A_DQS8_[0..1]<20>
R_B_SD0_[0..7]
R_B_SD1_[0..7]
R_B_SD2_[0..7]
R_B_SD3_[0..7]
R_B_SD4_[0..7]
R_B_SD5_[0..7]
R_B_SD6_[0..7]
R_B_SD7_[0..7]
R_B_SD8_[0..7]
R_B_DQS0_[0..1]
R_B_DQS1_[0..1]
R_B_DQS2_[0..1]
R_B_DQS3_[0..1]
R_B_DQS4_[0..1]
R_B_DQS5_[0..1]
R_B_DQS6_[0..1]
R_B_DQS7_[0..1]
R_B_DQS8_[0..1]
R_A_SD0_[0..7]
R_A_SD1_[0..7]
R_A_SD2_[0..7]
R_A_SD3_[0..7]
R_A_SD4_[0..7]
R_A_SD5_[0..7]
R_A_SD6_[0..7]
R_A_SD7_[0..7]
R_A_SD8_[0..7]
R_A_DQS0_[0..1]
R_A_DQS1_[0..1]
R_A_DQS2_[0..1]
R_A_DQS3_[0..1]
R_A_DQS4_[0..1]
R_A_DQS5_[0..1]
R_A_DQS6_[0..1]
R_A_DQS7_[0..1]
R_A_DQS8_[0..1]
MA[0..14]
MA[0..14]<17,18,19,21>
A_CKE
A_CKE<17,19,21>
B_CKE
B_CKE<18,19,21>
WE#
WE#<17,18,19,21>
RAS#
RAS#<17,18,19,21>
CAS#
CAS#<17,18,19,21>
Micro Star Restricted Secret
Title
CMIC DDR Interface
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
14 62
Rev
0B
A
B
C
D
E
AVDD
AGNDVDD_2.5
RSVD
AB12
AB11
AB7
AB5
AB3
AC26
AC24
AC22
AC17
AC16
AC14
AC7
AC5
AC3
AD12
AD11
AE17
AE16
AF24
AF21
AF12
AF11
AF4
E26
G23
K19
K22
K24
K26
L22
L24
L26
M17
M19
P17
P19
P24
T17
T19
U22
U24
U26
V19
V24
V26
AB27
AC27T16
U9
W17
AG18
AD24
U19
VCC25
VDD_IMB
CMIC_AVDD
MEM_VREF_CMIC
CMIC_DCOMP
CMIC_RSVD
MEM_VREF_CMIC
MEM_VREF_CMIC
CMIC_RSVD <16>
MEM_VREF_CMIC
V23
GND91
V25
GND92
W9
GND93
W11
GND94
W13
GND95
W15
GND96
W19
GND98
W21
GND99
W23
GND100
W25
GND102
AA10
GND103
AA11
GND104
AA14
GND105
AB17
GND106
AB18
GND107
AC2
GND108
AC4
GND109
AC6
GND110
AC10
GND111
AC11
GND112
AC21
GND113
AC23
GND114
AC25
GND115
AD2
GND116
AD4
GND117
AD6
GND118
AD17
GND119
AD18
GND120
AD21
GND121
AD23
GND122
AD25
GND123
AE10
GND124
AE11
GND125
AF7
GND126
AF14
GND127
AF17
GND128
AF18
GND129
AG1
GND130
AG27
GND131
V5
GND133
V7
GND135
R12
GND72
R14
GND73
R16
GND74
R19
GND75
T11
GND76
T13
GND77
T15
GND78
T18
GND79
U3
GND80
U5
GND81
U7
GND83
U12
GND85
U14
GND86
U16
GND87
V3
GND89
V21
GND90
P6
GND65
P11
GND66
P13
GND67
P15
GND68
P22
GND69
VCC_P
C283
1u
VCC_P
SC20
0.1u
Put on Solder Side
U20D
CMIC-CE
C3011uC3001uC299
SC21
0.01u
1u
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND71
GND70
GND136
GND137GND139
VCC_P
A1
A27
B5
B6
B10
B11
B14
C17
C18
C25
D5
D6
D10
D11
D14
D21
D23
K16
E2
E17
E18
E22
E24
F10
F11
F14
G7
G17
G18
G26
J2
J4
J6
J9
J11
J13
J15
J17
J19
J21
J23
J25
K2
K4
K6
K21
K23
K25
L9
L12
L14
L16
L19
M11
M13
M15
M18
N9
N12
N14
N16
N19
P2
R9
P26
AA17
D25J7
12
+
EC64
150u
VCC25
R321
4.7
VCC25
1 2
CMIC_DCOMP
R303 255
SC1
0.1u
L17
47u
MEM_VREF_CMIC
SC2
0.1u
+
EC54
10u
MEM_VREF_CMIC
C255
C258
0.1u
1u
SC5
0.01u
VCC25
VCC25
CMIC_AVDD
C254
1u
R332
100
R327
100
SC4
0.01u
Put on Solder Side
4 4
3 3
2 2
VCC_P
VCC25
AA16
AA15
AB26
AB24
AB22
U20E
B2
VTT
B8
VTT
B16
VTT
B17
VTT
B22
VTT
B24
VTT
C4
VTT
C5
VTT
C11
VTT
C12
VTT
C21
VTT
C23
VTT
D16
VTT
D17
VTT
D26
VTT
E4
VTT
E5
VTT
E8
VTT
E11
VTT
E12
VTT
F16
VTT
F17
VTT
G4
VTT
G11
VTT
G12
VTT
G20
VTT
J10
VTT
J12
VTT
J14
VTT
J16
VTT
J18
VTT
K9
VDD_2.5
K7
VDD_2.5
K5
VDD_2.5
K3
VDD_2.5
L15
VDD_2.5
L13
VDD_2.5
L11
VDD_2.5
L7
VDD_2.5
L5
VDD_2.5
L3
VDD_2.5
M16
VDD_2.5
M14
VDD_2.5
M12
VDD_2.5
M9
VDD_2.5
N15
VDD_2.5
N13
VDD_2.5
N11
VDD_2.5
P16
VDD_2.5
P14
VDD_2.5
P12
VDD_2.5
P9
VDD_2.5
P4
VDD_2.5
R15
VDD_2.5
R13
VDD_2.5
T14
VDD_2.5
T12
VDD_2.5
T9
VDD_2.5
U15
VDD_2.5
U13
VDD_2.5
U11
VDD_2.5
V22
VDD_2.5
V9
VDD_2.5
V6
VDD_2.5
V4
VDD_2.5
V2
VDD_2.5
W18
VDD_2.5
W16
VDD_2.5
W14
VDD_2.5
W12
VDD_2.5
W10
VDD_2.5
W6
VDD_2.5
W4
VDD_2.5
W2
VDD_2.5
Y25
VDD_2.5
Y23
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
MEM_VREF
MEM_VREF
DCOMP
T_IMB_VREF
CMIC-CE
VDD_IMB
C265
C298
1000p-0805
VDD_IMB
SC6
1 1
0.01u
C279
0.1u
0.1u
SC19
SC3
0.1u
0.1u
Put on Solder Side
Micro Star Restricted Secret
Title
CMIC Power
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
15 62
Rev
0B
A
B
C
D
E
1 : 5 CLOCKs
0 : 6 CLOCKs
R286
2.7K
DETERMINISTIC_IMB
R285
X_R
Do not stuff
CMIC_RSVD<15>
VCC25
R265
2.7K
IMB_R_W_PTR_DLY
R264
X_R
Do not stuff
( Default )
CMIC_RSVD
VCC25
R304
2.7K
R313
X_R
Do not stuff
4 4
VCC25
R275
8.2K
JP3
D1x2
COMPATIBILITY IMB
1: A_IMB is Compatibility Bus
0: Thin IMB is Compatibility
Bus ( Default )
3 3
JP2
2
1
D1x2
DEFER ENABLE/DISABLE
OFF: Defer Enabled ( Default )
ON: Defer Disabled
2 2
2
1
CMIC_DEFER_EN
R276
1K
VCC25
R259
X_R
DO NOT STUFF
R261
2.7K
COMP_IMB
R292
JP3_12
2.7K
JC-D2-GN
VCC25
R263
8.2K
CMIC_PLL_EN#
CMIC PLL ENABLE/DISABLE
1: APLL Disabled
0: APLL Enabled
( Default )
IOQ DEPTH
OFF: IOQ Depth 1
ON: IOQ Depth
12 ( Default )
CMIC_PLL_EN#
CMIC_DEFER_EN
COMP_IMB
IOQ_DEPTH
IMB_TRAINING
IMB_CRC_PARITY ALERT#
IMB_R_W_PTR_DLY TESTMODE#
POWERGOOD_CMIC<13,49>
VCC25
R287
8.2K
JP4
IOQ_DEPTH
2
1
D1x2
R298
1K
JP4_12
JC-D2-GN
U15
2
1A1
4
1A2
6
1A3
8
1A4
11
2A1
13
2A2
15
2A3
17
2A4
1
1G
19
2G
74LVC244A-SO20
TSSOP-20
VCC25
C209
0.1u
CMIC_FATAL#
18
1Y1
WRMRST#
16
1Y2
MEMOFF#
14
1Y3
MEMOFFACK#
12
1Y4
RCC_SCLDETERMINISTIC_IMB
9
2Y1
RCC_SDA
7
2Y2
5
2Y3
3
2Y4
20
VDD
10
GND
VCC25
R273
2.7K
IMB_CRC_PARITY
R272
X_R
Do not stuff
VCC25
CMIC_FATAL# <12,39>
WRMRST# <12>
MEMOFF# <12,38>
MEMOFFACK# <12>
RCC_SCL <13,25,27,48,51>
RCC_SDA <13,25,27,48,51>
ALERT# <12,25,27,39>
TESTMODE# <13>
A/B_IMB CRC or PARITY
0 : PARITY is enabled forA&BIMBbuses (Default )
1 : CRC is enabled forA&BIMBbuses
( In final version Use CRC on IMB buses )
VCC25
R281
2.7K
IMB_TRAINING
R282
X_R
Do not stuff
IMB_TRAINING
0 : IMB TRAINING Disabled
1 : IMB TRAINING Enabled
( Default )
IMB_READ/WRITE POINTER DLY
VCC25
IMB - DETERMINISTIC/ NON
DETERMINISTIC
0 : Deterministic IMB
1 : Non Deterministic
IMB (Default )
Thin IMB FREQ.
1 = 100 MHz 2X
0 = 200 MHz 2X
1 1
Micro Star Restricted Secret
Title
CMIC Strapping Option
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
16 62
Rev
0B
A
B
C
D
E
11
665850
93
4234267418
89
MA0
48
A0
MA1
4 4
MEMB_SCL<19,23,51>
3 3
2 2
MEMB_SDA<19,23,51>
R392 330
VCC25
R370 4.7K
R375 4.7K
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
CS_0
CS_0<14,18> CS_2<14,18>
CS_1 CS_3
CS_1<14,18>
RAS#
CAS#
WE#
CLK0_P<23>
CLK0_N<23>
A_CKE
SSTLREF_D1 SSTLREF_D1
VCC25
MEMB_SCL
MEMB_SDA
DIMM_WP#1 DIMM_WP#2
DIMM_RST#
DIMM_WP#1
DIMM_WP#2
VCC25 VCC25
GND
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
A10
118
A11
115
A12
59
BA0
52
BA1
157
CS0_
158
CS1_
154
RAS_
65
CAS_
63
WE_
137
CLK0_P
138
CLK0_N
21
CLKE0
111
CLKE1
167
FETEN
1
VREF
184
VDDSPD
82
VDDID
92
SCL
91
SDA
181
SA0
182
SA1
183
SA2
90
WP
10
RESET_
102 56
NC1 DQS4
101
NC2
9
NC4
173
NC5
163
CS3_NU
71
CS2_NU
75
CLK2_N_DU
76
CLK2_P_DU
17
CLK1_N_DU
16
CLK1_P_DU
113
BA2_NU
103
A13_NU
168
VDD
148
VDD
120
VDD
108
VDD
85
VDD
70
VDD
46
VDD
38
VDD
7
VDD
136
VDDQ
180
VDDQ
156
VDDQ
112
VDDQ
164
VDDQ
143
VDDQ
128
VDDQ
104
VDDQ
96
VDDQ
172
VDDQ
77
VDDQ
62
VDDQ
54
VDDQ
30
VDDQ
22
VDDQ
15
VDDQ
81
GND
GND
GND
GND
GND
GND
GND
GND
I2C ADD. - 0
GND
GND
Pair 0
A_SD0_[0..7]<19,20,21>
A_SD1_[0..7]<19,20,21>
A_SD2_[0..7]<19,20,21>
A_SD3_[0..7]<19,20,21>
A_SD4_[0..7]<19,20,21>
A_SD5_[0..7]<19,20,21>
A_SD6_[0..7]<19,20,21>
A_SD7_[0..7]<19,20,21>
A_SD8_[0..7]<19,20,21>
A_DQS0_[0..1]<19,20,21>
A_DQS1_[0..1]<19,20,21>
A_DQS2_[0..1]<19,20,21>
A_DQS3_[0..1]<19,20,21>
A_DQS4_[0..1]<19,20,21>
1 1
A_DQS5_[0..1]<19,20,21>
A_DQS6_[0..1]<19,20,21>
A_DQS7_[0..1]<19,20,21>
A_DQS8_[0..1]<19,20,21>
132
124
116
100
GND
GND
GND
GND
A_SD0_[0..7]
A_SD1_[0..7]
A_SD2_[0..7]
A_SD3_[0..7]
A_SD4_[0..7]
A_SD5_[0..7]
A_SD6_[0..7]
A_SD7_[0..7]
A_SD8_[0..7]
A_DQS0_[0..1]
A_DQS1_[0..1]
A_DQS2_[0..1]
A_DQS3_[0..1]
A_DQS4_[0..1]
A_DQS5_[0..1]
A_DQS6_[0..1]
A_DQS7_[0..1]
A_DQS8_[0..1]
139
145
GND
GND
3
160
176
152
DIMM1
GND
GND
GND
GND
GND
2
D0
4
D1
6
D2
8
D3
5
DQS0
97
DM0_DQS9
94
D4
95
D5
98
D6
99
D7
12
D8
13
D9
19
D10
20
D11
14
DQS1
107
DM1_DQS10
105
D12
106
D13
109
D14
110
D15
23
D16
24
D17
28
D18
31
D19
25
DQS2
119
DM2_DQS11
114
D20
117
D21
121
D22
123
D23
33
D24
35
D25
39
D26
40
D27
36
DQS3
129
DM3_DQS12
126
D28
127
D29
131
D30
133
D31
53
D32
55
D33
57
D34
60
D35
149
DM4_DQS13
146
D36
147
D37
150
D38
151
D39
61
D40
64
D41
68
D42
69
D43
67
DQS5
159
DM5_DQS14
153
D44
155
D45
161
D46
162
D47
72
D48
73
D49
79
D50
80
D51
78
DQS6
169
DM6_DQS15
165
D52
166
D53
170
D54
171
D55
83
D56
84
D57
87
D58
88
D59
86
DQS7
177
DM7_DQS16
174
D60
175
D61
178
D62
179
D63
44
ECC0
45
ECC1
49
ECC2
51
ECC3
47
DQS8
140
DM9_DQS17
134
ECC4
135
ECC5
142
ECC6
144
ECC7
Salave Address : A0h
A_SD0_0
A_SD0_1
A_SD0_2
A_SD0_3
A_DQS0_0
A_DQS0_1
A_SD0_4
A_SD0_5
A_SD0_6
A_SD0_7
A_SD1_0
A_SD1_1
A_SD1_2
A_SD1_3
A_DQS1_0
A_DQS1_1
A_SD1_4
A_SD1_5
A_SD1_6
A_SD1_7
A_SD2_0
A_SD2_1
A_SD2_2
A_SD2_3
A_DQS2_0
A_DQS2_1
A_SD2_4
A_SD2_5
A_SD2_6
A_SD2_7
A_SD3_0
A_SD3_1
A_SD3_2
A_SD3_3
A_DQS3_0
A_DQS3_1
A_SD3_4
A_SD3_5
A_SD3_6
A_SD3_7
A_SD4_0
A_SD4_1
A_SD4_2
A_SD4_3
A_DQS4_0
A_DQS4_1
A_SD4_4
A_SD4_5
A_SD4_6
A_SD4_7
A_SD5_0
A_SD5_1
A_SD5_2
A_SD5_3
A_DQS5_0
A_DQS5_1
A_SD5_4
A_SD5_5
A_SD5_6
A_SD5_7
A_SD6_0
A_SD6_1
A_SD6_2
A_SD6_3
A_DQS6_0
A_DQS6_1
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7
A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_DQS7_0
A_DQS7_1
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7
A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_DQS8_0
A_DQS8_1
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7
R402 330
VCC25
DIMM_WP#2<18>
DIMM_WP#1<18>
DIMM_RST#<18,19,52>
CS_3<14,18>
CLK1_P<23>
CLK1_N<23>
A_CKE
VCC25
MEMB_SCL
MEMB_SDA
R401 4.7K
DIMM_RST#
MA[0..14]<14,18,19,21>
A_CKE<14,19,21>
WE#<14,18,19,21>
RAS#<14,18,19,21>
CAS#<14,18,19,21>
11
665850
MA0
MA1
MA2
MA3
130
MA4
MA5
MA6
125
MA7
MA8
122
MA9
MA10
141
MA11
118
MA12
115
MA13
MA14
CS_2
157
158
RAS#
154
CAS#
WE#
137
138
111
167
184
181
182
183
102 56
101
173
163
113
103
168
148
120
108
136
180
156
112
164
143
128
104
172
MA[0..14]
A_CKE
WE#
RAS#
CAS#
DIMM_WP#2
DIMM_WP#1
DIMM_RST#
4234267418
48
A0
GND
GND
GND
GND
GND
GND
GND
43
A1
41
A2
A3
37
A4
32
A5
A6
29
A7
A8
27
A9
A10
A11
A12
59
BA0
52
BA1
CS0_
CS1_
RAS_
65
CAS_
63
WE_
CLK0_P
CLK0_N
21
CLKE0
CLKE1
FETEN
1
VREF
VDDSPD
82
VDDID
92
SCL
91
SDA
I2C ADD. - 2
SA0
SA1
SA2
90
WP
10
RESET_
NC1 DQS4
NC2
9
NC4
NC5
CS3_NU
71
CS2_NU
75
CLK2_N_DU
76
CLK2_P_DU
17
CLK1_N_DU
16
CLK1_P_DU
BA2_NU
A13_NU
VDD
VDD
VDD
VDD
85
VDD
70
VDD
46
VDD
38
VDD
7
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
96
VDDQ
VDDQ
77
VDDQ
62
VDDQ
54
VDDQ
30
VDDQ
22
VDDQ
15
VDDQ
VCC25
R125
100
R115
100
116
100
93
89
81
GND
GND
GND
GND
GND
GND
Pair 1
C90
1000p-0805
C89
1000p-0805
132
124
GND
GND
DIMM3
3
139
145
160
176
152
GND
GND
GND
GND
GND
GND
GND
D0
D1
D2
D3
DQS0
DM0_DQS9
D4
D5
D6
D7
D8
D9
D10
D11
DQS1
DM1_DQS10
D12
D13
D14
D15
D16
D17
D18
D19
DQS2
DM2_DQS11
D20
D21
D22
D23
D24
D25
D26
D27
DQS3
DM3_DQS12
D28
D29
D30
D31
D32
D33
D34
D35
DM4_DQS13
D36
D37
D38
D39
D40
D41
D42
D43
DQS5
DM5_DQS14
D44
D45
D46
D47
D48
D49
D50
D51
DQS6
DM6_DQS15
D52
D53
D54
D55
D56
D57
D58
D59
DQS7
DM7_DQS16
D60
D61
D62
D63
ECC0
ECC1
ECC2
ECC3
DQS8
DM9_DQS17
ECC4
ECC5
ECC6
ECC7
Salave Address : A4h
C88
1u
SSTLREF_D1
C82
C74
0.1u
1u
A_SD0_0
2
A_SD0_1
4
A_SD0_2
6
A_SD0_3
8
A_DQS0_0
5
A_DQS0_1
97
A_SD0_4
94
A_SD0_5
95
A_SD0_6
98
A_SD0_7
99
A_SD1_0
12
A_SD1_1
13
A_SD1_2
19
A_SD1_3
20
A_DQS1_0
14
A_DQS1_1
107
A_SD1_4
105
A_SD1_5
106
A_SD1_6
109
A_SD1_7
110
A_SD2_0
23
A_SD2_1
24
A_SD2_2
28
A_SD2_3
31
A_DQS2_0
25
A_DQS2_1
119
A_SD2_4
114
A_SD2_5
117
A_SD2_6
121
A_SD2_7
123
A_SD3_0
33
A_SD3_1
35
A_SD3_2
39
A_SD3_3
40
A_DQS3_0
36
A_DQS3_1
129
A_SD3_4
126
A_SD3_5
127
A_SD3_6
131
A_SD3_7
133
A_SD4_0
53
A_SD4_1
55
A_SD4_2
57
A_SD4_3
60
A_DQS4_0
A_DQS4_1
149
A_SD4_4
146
A_SD4_5
147
A_SD4_6
150
A_SD4_7
151
A_SD5_0
61
A_SD5_1
64
A_SD5_2
68
A_SD5_3
69
A_DQS5_0
67
A_DQS5_1
159
A_SD5_4
153
A_SD5_5
155
A_SD5_6
161
A_SD5_7
162
A_SD6_0
72
A_SD6_1
73
A_SD6_2
79
A_SD6_3
80
A_DQS6_0
78
A_DQS6_1
169
A_SD6_4
165
A_SD6_5
166
A_SD6_6
170
A_SD6_7
171
A_SD7_0
83
A_SD7_1
84
A_SD7_2
87
A_SD7_3
88
A_DQS7_0
86
A_DQS7_1
177
A_SD7_4
174
A_SD7_5
175
A_SD7_6
178
A_SD7_7
179
A_SD8_0
44
A_SD8_1
45
A_SD8_2
49
A_SD8_3
51
A_DQS8_0
47
A_DQS8_1
140
A_SD8_4
134
A_SD8_5
135
A_SD8_6
142
A_SD8_7
144
VCC25
VCC25
VCC25
VCC25
VCC25
C97
1000p-0805
C140
1000p-0805
C196
1000p-0805
C230
1000p-0805
C341
1000p-0805
C101
1000p-0805
C156
1000p-0805
C195
1000p-0805
C249
1000p-0805
C123
1000p-0805
C177
1000p-0805
C210
1000p-0805
C263
1000p-0805
C287
1000p-0805
C138
1000p-0805
C211
1000p-0805
C212
1000p-0805
C285
1000p-0805
C323
1000p-0805
Micro Star Restricted Secret
Title
DIMM1 & DIMM3
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
A
B
C
D
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
of
17 62
Rev
0B
A
B
C
D
E
11
665850
93
4234267418
89
11
665850
93
4234267418
89
4 4
3 3
2 2
MEMA_SCL<19,51>
MEMA_SDA<19,51>
MA0
48
A0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
CS_0<14,17>
CS_1<14,17>
RAS#
CAS#
WE#
CLK2_P<23>
CLK2_N<23>
B_CKE
SSTLREF_D2
VCC25 VCC25
MEMA_SCL
MEMA_SDA
R374 330
DIMM_WP#1
DIMM_RST#
VCC25 VCC25
GND
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
A10
118
A11
115
A12
59
BA0
52
BA1
157
CS0_
158
CS1_
154
RAS_
65
CAS_
63
WE_
137
CLK0_P
138
CLK0_N
21
CLKE0
111
CLKE1
167
FETEN
1
VREF
184
VDDSPD
82
VDDID
92
SCL
91
SDA
181
SA0
182
SA1
183
SA2
90
WP
10
RESET_
102 56
NC1 DQS4
101
NC2
9
NC4
173
NC5
163
CS3_NU
71
CS2_NU
75
CLK2_N_DU
76
CLK2_P_DU
17
CLK1_N_DU
16
CLK1_P_DU
113
BA2_NU
103
A13_NU
168
VDD
148
VDD
120
VDD
108
VDD
85
VDD
70
VDD
46
VDD
38
VDD
7
VDD
136
VDDQ
180
VDDQ
156
VDDQ
112
VDDQ
164
VDDQ
143
VDDQ
128
VDDQ
104
VDDQ
96
VDDQ
172
VDDQ
77
VDDQ
62
VDDQ
54
VDDQ
30
VDDQ
22
VDDQ
15
VDDQ
81
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I2C ADD. - 0 I2C ADD. - 2
Pair 0 Pair 1
B_SD0_[0..7]<19,20,21>
B_SD1_[0..7]<19,20,21>
B_SD2_[0..7]<19,20,21>
B_SD3_[0..7]<19,20,21>
B_SD4_[0..7]<19,20,21>
B_SD5_[0..7]<19,20,21>
B_SD6_[0..7]<19,20,21>
B_SD7_[0..7]<19,20,21>
B_SD8_[0..7]<19,20,21>
B_DQS0_[0..1]<19,20,21>
1 1
A
B_DQS1_[0..1]<19,20,21>
B_DQS2_[0..1]<19,20,21>
B_DQS3_[0..1]<19,20,21>
B_DQS4_[0..1]<19,20,21>
B_DQS5_[0..1]<19,20,21>
B_DQS6_[0..1]<19,20,21>
B_DQS7_[0..1]<19,20,21>
B_DQS8_[0..1]<19,20,21>
B_SD0_[0..7]
B_SD1_[0..7]
B_SD2_[0..7]
B_SD3_[0..7]
B_SD4_[0..7]
B_SD5_[0..7]
B_SD6_[0..7]
B_SD7_[0..7]
B_SD8_[0..7]
B_DQS0_[0..1]
B_DQS1_[0..1]
B_DQS2_[0..1]
B_DQS3_[0..1]
B_DQS4_[0..1]
B_DQS5_[0..1]
B_DQS6_[0..1]
B_DQS7_[0..1]
B_DQS8_[0..1]
B
3
139
132
124
116
100
145
160
176
152
DIMM2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DM0_DQS9
DM1_DQS10
DM2_DQS11
DM3_DQS12
DM4_DQS13
DM5_DQS14
DM6_DQS15
DM7_DQS16
DM9_DQS17
DQS0
DQS1
DQS2
DQS3
DQS5
DQS6
DQS7
ECC0
ECC1
ECC2
ECC3
DQS8
ECC4
ECC5
ECC6
ECC7
B_SD0_0
2
D0
B_SD0_1
4
D1
B_SD0_2
6
D2
B_SD0_3
8
D3
B_DQS0_0
5
B_DQS0_1
97
B_SD0_4
94
D4
B_SD0_5
95
D5
B_SD0_6
98
D6
B_SD0_7
99
D7
B_SD1_0
12
D8
B_SD1_1
13
D9
B_SD1_2
19
D10
B_SD1_3
20
D11
B_DQS1_0
14
B_DQS1_1
107
B_SD1_4
105
D12
B_SD1_5
106
D13
B_SD1_6
109
D14
B_SD1_7
110
D15
B_SD2_0
23
D16
B_SD2_1
24
D17
B_SD2_2
28
D18
B_SD2_3
31
D19
B_DQS2_0
25
B_DQS2_1
119
B_SD2_4
114
D20
B_SD2_5
117
D21
B_SD2_6
121
D22
B_SD2_7
123
D23
B_SD3_0
33
D24
B_SD3_1
35
D25
B_SD3_2
39
D26
B_SD3_3
40
D27
B_DQS3_0
36
B_DQS3_1
129
B_SD3_4
126
D28
B_SD3_5
127
D29
B_SD3_6
131
D30
B_SD3_7
133
D31
B_SD4_0
53
D32
B_SD4_1
55
D33
B_SD4_2
57
D34
B_SD4_3
60
D35
B_DQS4_0
B_DQS4_1
149
B_SD4_4
146
D36
B_SD4_5
147
D37
B_SD4_6
150
D38
B_SD4_7
151
D39
B_SD5_0
61
D40
B_SD5_1
64
D41
B_SD5_2
68
D42
B_SD5_3
69
D43
B_DQS5_0
67
B_DQS5_1
159
B_SD5_4
153
D44
B_SD5_5
155
D45
B_SD5_6
161
D46
B_SD5_7
162
D47
B_SD6_0
72
D48
B_SD6_1
73
D49
B_SD6_2
79
D50
B_SD6_3
80
D51
B_DQS6_0
78
B_DQS6_1
169
B_SD6_4
165
D52
B_SD6_5
166
D53
B_SD6_6
170
D54
B_SD6_7
171
D55
B_SD7_0
83
D56
B_SD7_1
84
D57
B_SD7_2
87
D58
B_SD7_3
88
D59
B_DQS7_0
86
B_DQS7_1
177
B_SD7_4
174
D60
B_SD7_5
175
D61
B_SD7_6
178
D62
B_SD7_7
179
D63
B_SD8_0
44
B_SD8_1
45
B_SD8_2
49
B_SD8_3
51
B_DQS8_0
47
B_DQS8_1
140
B_SD8_4
134
B_SD8_5
135
B_SD8_6
142
B_SD8_7
144
VCC25
CS_2<14,17>
CS_3<14,17>
CLK3_P<23>
CLK3_N<23>
R432 4.7K
R458 330
DIMM_WP#2
DIMM_RST#
MA0
48
A0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
RAS#
CAS#
WE#
B_CKE
SSTLREF_D2
MEMA_SCL
MEMA_SDA
GND
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
A10
118
A11
115
A12
59
BA0
52
BA1
157
CS0_
158
CS1_
154
RAS_
65
CAS_
63
WE_
137
CLK0_P
138
CLK0_N
21
CLKE0
111
CLKE1
167
FETEN
1
VREF
184
VDDSPD
82
VDDID
92
SCL
91
SDA
181
SA0
182
SA1
183
SA2
90
WP
10
RESET_
102 56
NC1 DQS4
101
NC2
9
NC4
173
NC5
163
CS3_NU
71
CS2_NU
75
CLK2_N_DU
76
CLK2_P_DU
17
CLK1_N_DU
16
CLK1_P_DU
113
BA2_NU
103
A13_NU
168
VDD
148
VDD
120
VDD
108
VDD
85
VDD
70
VDD
46
VDD
38
VDD
7
VDD
136
VDDQ
180
VDDQ
156
VDDQ
112
VDDQ
164
VDDQ
143
VDDQ
128
VDDQ
104
VDDQ
96
VDDQ
172
VDDQ
77
VDDQ
62
VDDQ
54
VDDQ
30
VDDQ
22
VDDQ
15
VDDQ
Salave Address : A0h Salave Address : A4h
MA[0..14]
MA[0..14]<14,17,19,21>
B_CKE
B_CKE<14,19,21>
WE#
WE#<14,17,19,21>
RAS#
RAS#<14,17,19,21>
CAS#
CAS#<14,17,19,21>
DIMM_WP#2
DIMM_WP#2<17>
DIMM_WP#1
DIMM_WP#1<17>
DIMM_RST#
DIMM_RST#<17,19,52>
C
81
GND
GND
GND
GND
GND
GND
GND
GND
VCC25
R112
R117
100
GND
GND
100
GND
100
GND
124
116
GND
GND
C85
1000p-0805
C78
1000p-0805
3
139
132
145
160
176
152
DIMM4
GND
GND
GND
GND
GND
GND
GND
DQS0
DM0_DQS9
DQS1
DM1_DQS10
DQS2
DM2_DQS11
DQS3
DM3_DQS12
DM4_DQS13
DQS5
DM5_DQS14
DQS6
DM6_DQS15
DQS7
DM7_DQS16
ECC0
ECC1
ECC2
ECC3
DQS8
DM9_DQS17
ECC4
ECC5
ECC6
ECC7
C73
0.1u
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
C83
1u
SSTLREF_D2
C91
1u
D
B_SD0_0
2
B_SD0_1
4
B_SD0_2
6
B_SD0_3
8
B_DQS0_0
5
B_DQS0_1
97
B_SD0_4
94
B_SD0_5
95
B_SD0_6
98
B_SD0_7
99
B_SD1_0
12
B_SD1_1
13
B_SD1_2
19
B_SD1_3
20
B_DQS1_0
14
B_DQS1_1
107
B_SD1_4
105
B_SD1_5
106
B_SD1_6
109
B_SD1_7
110
B_SD2_0
23
B_SD2_1
24
B_SD2_2
28
B_SD2_3
31
B_DQS2_0
25
B_DQS2_1
119
B_SD2_4
114
B_SD2_5
117
B_SD2_6
121
B_SD2_7
123
B_SD3_0
33
B_SD3_1
35
B_SD3_2
39
B_SD3_3
40
B_DQS3_0
36
B_DQS3_1
129
B_SD3_4
126
B_SD3_5
127
B_SD3_6
131
B_SD3_7
133
B_SD4_0
53
B_SD4_1
55
B_SD4_2
57
B_SD4_3
60
B_DQS4_0
B_DQS4_1
149
B_SD4_4
146
B_SD4_5
147
B_SD4_6
150
B_SD4_7
151
B_SD5_0
61
B_SD5_1
64
B_SD5_2
68
B_SD5_3
69
B_DQS5_0
67
B_DQS5_1
159
B_SD5_4
153
B_SD5_5
155
B_SD5_6
161
B_SD5_7
162
B_SD6_0
72
B_SD6_1
73
B_SD6_2
79
B_SD6_3
80
B_DQS6_0
78
B_DQS6_1
169
B_SD6_4
165
B_SD6_5
166
B_SD6_6
170
B_SD6_7
171
B_SD7_0
83
B_SD7_1
84
B_SD7_2
87
B_SD7_3
88
B_DQS7_0
86
B_DQS7_1
177
B_SD7_4
174
B_SD7_5
175
B_SD7_6
178
B_SD7_7
179
B_SD8_0
44
B_SD8_1
45
B_SD8_2
49
B_SD8_3
51
B_DQS8_0
47
B_DQS8_1
140
B_SD8_4
134
B_SD8_5
135
B_SD8_6
142
B_SD8_7
144
VCC25
VCC25
VCC25
VCC25
VCC25
C100
1000p-0805
C139
1000p-0805
C175
1000p-0805
C247
1000p-0805
C286
1000p-0805
C124
1000p-0805
C173
1000p-0805
C231
1000p-0805
C276
1000p-0805
C264
1000p-0805
C129
C157
1000p-0805
1000p-0805
C155
C194
1000p-0805
1000p-0805
C250
C268
1000p-0805
1000p-0805
C275
C278
1000p-0805
1000p-0805
C329
C229
1000p-0805
1000p-0805
Micro Star Restricted Secret
Title
DIMM2 & DIMM4
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Tuesday, November 13, 2001
Sheet
of
18 62
Rev
0B
1 1
2 2
3 3
4 4
A
VCC25
163
173
NC5
D37
147
150
A_SD4_5
A_SD4_6
102 56218291181
101
9
NC1 DQS4D0SA1
NC4
NC2
DM4_DQS13
D36
149
146
A_DQS4_1
A_SD4_4
A_DQS4_0
RESET_
D34
D35
A_SD4_3
10
VCC25 VCC25
R925 4.7K
R923 330
DIMM_WP#3
DIMM_RST#
183
90
WP
SA2
D31
D32
D33
13353555760
A_SD3_7
A_SD4_0
A_SD4_1
A_SD4_2
R924 330
R926
DIMM_RST#
DIMM_WP#3
4.7K
MEMB_SDA<17,23,51>
SDA
SA0
D29
D30
131
A_SD3_6
MEMB_SCL<17,23,51>
MEMB_SCL
MEMB_SDA
92
82
VDDID
SCL
DM3_DQS12
DQS3
D28
129
36
126
127
A_SD3_5
A_DQS3_1
A_SD3_4
A_DQS3_0
MEMA_SDA
MEMA_SCL
VCC25
184
VDDSPD
D26
D27
A_SD3_2
A_SD3_3
VCC25
SSTLREF_D3
167
1
VREF
FETEN
D22
D23
D24
D25
12333353940
A_SD2_7
A_SD3_0
A_SD3_1
SSTLREF_D3
111
CLKE0
CLKE1
D20
D21
117
121
A_SD2_6
A_SD2_5
CLK4_N<23>
CLK4_P<23>
A_CKE
138
21
CLK0_N
CLK0_P
DM2_DQS11
DQS2
D19
119
25
114
A_DQS2_1
A_SD2_4
A_DQS2_0
CLK5_N<23>
CLK5_P<23>
B_CKE
137
WE_
D17
D18
A_SD2_2
A_SD2_3
CAS#
WE#
63
65
CAS_
RAS_
D15
D16
A_SD2_0
A_SD2_1
CAS#
WE#
CS_5<14>
RAS#
154
CS1_
D13
D14
109
11023242831
A_SD1_6
A_SD1_7
RAS#
CS_4<14>
CS_4
CS_5
157
158
CS0_
DM1_DQS10
D12
107
106
A_SD1_4
A_SD1_5
CS_4
CS_5
MA14
MA13
52
59
BA1
BA0
DQS1
D10
D11
14
A_DQS1_1
A_DQS1_0
A_SD1_3
MA13
MA14
MA12
115
A12
A11
D9
A_SD1_2
A_SD1_1
MA12
MA10
MA11
118
A10
A_SD0_7
A_SD1_0
MA11
MA10
MA8
MA9
A_SD0_5
A_SD0_6
MA8
MA9
MA5
MA7
MA6
1252912227141
32
DM0_DQS9
DQS0
97
5
A_DQS0_1
A_DQS0_0
A_SD0_4
MA5
MA6
MA7
MA3
MA4
130
37
D2D3D4D5D6D7D8
D1
689495989912131920105
A_SD0_2
A_SD0_3
MA3
MA4
MA1
MA2
43
41
A0
A1A2A3A4A5A6A7A8A9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
A_SD0_1
A_SD0_0
MA1
MA2
MA0
48
11
18
26
34
42
50
58
66
74
81
89
93
100
116
124
132
139
145
176
3
160
152
DIMM5
MEMA_SDA<18,51>
MEMA_SCL<18,51>
MEMA_SDA
MEMA_SCL
MA0
R927 4.7K
DIMM_WP#3
VCC25
172
77
22
307157062
54
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A_DQS8_[0..1]<17,20,21>
A_DQS7_[0..1]<17,20,21>
A_DQS6_[0..1]<17,20,21>
A_DQS5_[0..1]<17,20,21>
A_DQS4_[0..1]<17,20,21>
A_DQS2_[0..1]<17,20,21>
A_DQS3_[0..1]<17,20,21>
A_DQS1_[0..1]<17,20,21>
A_DQS0_[0..1]<17,20,21>
A_SD8_[0..7]<17,20,21>
B
A_DQS7_[0..1]
A_DQS5_[0..1]
A_DQS3_[0..1]
A_DQS0_[0..1]
A_DQS6_[0..1]
A_DQS4_[0..1]
A_DQS1_[0..1]
A_DQS8_[0..1]
A_DQS2_[0..1]
DIMM_WP#2<17,18>
DIMM_WP#1<17,18>
DIMM_RST#<17,18,52>
DIMM_WP#1
DIMM_RST#
C
CAS#<14,17,18,21>
DIMM_WP#2
CAS#
A_CKE<14,17,21>
RAS#<14,17,18,21>
WE#<14,17,18,21>
WE#
RAS#
A_SD5_[0..7]<17,20,21>
A_SD6_[0..7]<17,20,21>
A_SD7_[0..7]<17,20,21>
A_SD5_[0..7]
A_SD7_[0..7]
A_SD6_[0..7]
A_SD8_[0..7]
MA[0..14]<14,17,18,21>
MA[0..14]
A_CKE
A_SD2_[0..7]<17,20,21>
A_SD3_[0..7]<17,20,21>
A_SD4_[0..7]<17,20,21>
A_SD2_[0..7]
A_SD3_[0..7]
A_SD4_[0..7]
A_SD0_[0..7]<17,20,21>
A_SD1_[0..7]<17,20,21>
A_SD0_[0..7]
A_SD1_[0..7]
Pair 2
Salave Address : A8h
DM9_DQS17
DQS8
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
144
A_SD8_7
135
142
A_SD8_6
A_SD8_5
134
140
A_SD8_4
A_DQS8_1
47
A_DQS8_0
A_SD8_3
A_SD8_2
D63
A_SD8_0
A_SD8_1
D62
178
17944454951
A_SD7_7
A_SD7_6
96
VDDQ
VDDQ
D60
D61
175
A_SD7_5
VDDQ
VDDQ
VDDQ
DM7_DQS16
DQS7
D59
174
177
86
A_DQS7_0
A_SD7_4
A_DQS7_1
164
VDDQ
VDDQ
D57
D58
A_SD7_2
A_SD7_3
180
VDDQ
VDDQ
D55
D56
A_SD7_0
A_SD7_1
D53
D54
170
17183848788
A_SD6_7
A_SD6_6
VDD
VDD
DM6_DQS15
D52
165
166
A_SD6_4
A_SD6_5
38
46
VDD
VDD
DQS6
D51
169
78
A_DQS6_1
A_DQS6_0
A_SD6_3
85
VDD
D50
A_SD6_2
136
128
112
104
143
156
108
VDD
VDD
D48
D49
A_SD6_1
120
148
VDD
VDD
D46
D47
16272737980
A_SD5_7
A_SD6_0
168
D45
155
161
A_SD5_5
A_SD5_6
103
A13_NU
BA2_NU
DM5_DQS14
DQS5
D44
159
153
A_SD5_4
A_DQS5_1
VCC25
113
16
17
CLK2_P_DU
CLK1_N_DU
CLK1_P_DU
D41
D42
D43
67
A_SD5_2
A_DQS5_0
A_SD5_3
71
76
75
CLK2_N_DU
CS2_NU
D39
D40
15161646869
A_SD4_7
A_SD5_0
A_SD5_1
CS3_NU
D38
A
B
C
D
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
E
Last Revision Date:
Sheet
Tuesday, November 13, 2001
19 62
of
0B
R929
100
C712
1000p-0805
C713
0.1u
C714
1u
SSTLREF_D3
Title
Micro Star Restricted Secret
DIMM5 & DIMM6
Rev
R928
100
C710
1000p-0805
C711
1u
B_DQS5_[0..1]<18,20,21>
B_DQS6_[0..1]<18,20,21>
B_DQS7_[0..1]<18,20,21>
B_DQS8_[0..1]<18,20,21>
B_DQS5_[0..1]
B_DQS6_[0..1]
B_DQS7_[0..1]
B_DQS8_[0..1]
B_DQS1_[0..1]<18,20,21>
B_DQS2_[0..1]<18,20,21>
B_DQS3_[0..1]<18,20,21>
B_DQS4_[0..1]<18,20,21>
B_DQS1_[0..1]
B_DQS2_[0..1]
B_DQS3_[0..1]
B_DQS4_[0..1]
VCC25
Pair 2
Salave Address : A8h
B_DQS0_[0..1]<18,20,21>
B_SD8_[0..7]<18,20,21>
B_DQS0_[0..1]
ECC7
144
B_SD8_7
B_SD5_[0..7]<18,20,21>
B_SD6_[0..7]<18,20,21>
B_SD7_[0..7]<18,20,21>
B_SD5_[0..7]
B_SD6_[0..7]
B_SD7_[0..7]
B_SD8_[0..7]
ECC4
ECC5
ECC6
134
135
142
B_SD8_4
B_SD8_5
B_SD8_6
B_SD2_[0..7]<18,20,21>
B_SD3_[0..7]<18,20,21>
B_SD4_[0..7]<18,20,21>
B_SD2_[0..7]
B_SD3_[0..7]
B_SD4_[0..7]
22
VDDQ
VDDQ
VDDQ
DM9_DQS17
DQS8
ECC2
ECC3
47
140
B_SD8_3
B_DQS8_0
B_DQS8_1
B_SD0_[0..7]<18,20,21>
B_SD1_[0..7]<18,20,21>
B_SD0_[0..7]
B_SD1_[0..7]
307157062
54
VDDQ
VDDQ
ECC0
ECC1
B_SD8_1
B_SD8_2
DIMM_RST#<17,18,52>
172
77
96
VDDQ
VDDQ
VDDQ
D61
D62
D63
175
178
17944454951
B_SD7_5
B_SD7_6
B_SD7_7
B_SD8_0
DIMM_WP#1<17,18>
DIMM_WP#1
DIMM_RST#
128
104
143
VDDQ
VDDQ
VDDQ
DM7_DQS16
DQS7
D60
174
177
86
B_DQS7_0
B_DQS7_1
B_SD7_4
DIMM_WP#2<17,18>
DIMM_WP#2
112
156
164
VDDQ
VDDQ
VDDQ
VDDQ
D56
D57
D58
D59
B_SD7_1
B_SD7_2
B_SD7_3
RAS#<14,17,18,21>
CAS#<14,17,18,21>
WE#<14,17,18,21>
WE#
CAS#
RAS#
136
180
VDDQ
D54
D55
17183848788
B_SD6_7
B_SD7_0
B_CKE<14,18,21>
B_CKE
38
VDD
VDD
DM6_DQS15
D52
D53
169
165
166
170
B_DQS6_1
B_SD6_4
B_SD6_5
B_SD6_6
MA[0..14]<14,17,18,21>
MA[0..14]
46
VDD
VDD
VDD
DQS6
D50
D51
78
B_SD6_3
B_DQS6_0
108
85
VDD
D49
B_SD6_1
B_SD6_2
120
VDD
VDD
D47
D48
B_SD6_0
148
168
VDD
D45
D46
161
16272737980
B_SD5_6
B_SD5_7
A13_NU
DM5_DQS14
D44
153
155
B_SD5_4
B_SD5_5
113
103
16
BA2_NU
CLK1_P_DU
DQS5
D43
159
67
B_DQS5_0
B_DQS5_1
17
76
75
CLK2_P_DU
CLK2_N_DU
CLK1_N_DU
D40
D41
D42
B_SD5_1
B_SD5_2
B_SD5_3
163
71
CS2_NU
CS3_NU
D38
D39
150
15161646869
B_SD4_7
B_SD5_0
173
NC4
NC5
D36
D37
147
B_SD4_5
B_SD4_6
102 56218291181
101
9
NC1 DQS4D0SA1
NC2
DM4_DQS13
D35
149
146
B_SD4_3
B_DQS4_0
B_DQS4_1
B_SD4_4
10
90
WP
RESET_
D33
D34
B_SD4_2
183
SA2
D31
D32
13353555760
B_SD4_0
B_SD4_1
92
SDA
SA0
SCL
D28
D29
D30
126
127
131
B_SD3_5
B_SD3_6
B_SD3_7
1000p-0805
C706
1000p-0805
C707
1000p-0805
C708
1000p-0805
C709
184
82
VDDID
VDDSPD
DM3_DQS12
DQS3
D27
129
36
B_DQS3_0
B_DQS3_1
B_SD3_4
1
VREF
D25
D26
B_SD3_2
B_SD3_3
VCC25
167
FETEN
D23
D24
12333353940
B_SD3_0
B_SD3_1
1000p-0805
1000p-0805
1000p-0805
1000p-0805
CLKE1
D21
D22
121
B_SD2_6
B_SD2_7
C702
C703
C704
C705
111
21
CLKE0
DM2_DQS11
D20
114
117
B_SD2_4
B_SD2_5
138
137
CLK0_N
CLK0_P
DQS2
D19
119
25
B_SD2_3
B_DQS2_0
B_DQS2_1
VCC25
WE_
D17
D18
B_SD2_2
154
63
65
CAS_
RAS_
D14
D15
D16
11023242831
B_SD1_7
B_SD2_0
B_SD2_1
1000p-0805
C698
1000p-0805
C699
1000p-0805
C700
1000p-0805
C701
158
CS1_
D13
106
109
B_SD1_5
B_SD1_6
157
BA1
CS0_
DM1_DQS10
DQS1
D12
107
B_DQS1_1
B_SD1_4
VCC25
52
59
A12
BA0
D10
D11
D9
14
B_SD1_2
B_SD1_3
B_DQS1_0
1000p-0805
1000p-0805
1000p-0805
1000p-0805
115
118
A11
B_SD1_0
B_SD1_1
C694
C695
C696
C697
A10
B_SD0_7
B_SD0_5
B_SD0_6
1252912227141
32
DM0_DQS9
DQS0
97
5
B_DQS0_0
B_DQS0_1
B_SD0_4
VCC25
130
41
37
A1A2A3A4A5A6A7A8A9
D1
D2D3D4D5D6D7D8
4
689495989912131920105
B_SD0_1
B_SD0_2
B_SD0_3
1000p-0805
C690
1000p-0805
C691
1000p-0805
C692
1000p-0805
C693
48
43
A0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B_SD0_0
11
18
26
34
42
50
58
66
74
81
89
93
100
116
124
132
139
145
176
3
160
152
DIMM6
VCC25
D
E
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