MSI MS-9102 Schematic 0A

1

MS-9102

Dual Intel Foster Processor
ServerWorks GCLE + CIOB-X2 + CIOB-G + CSB5 Chipset

National Semiconductor PC87417 LPC IO Chip

Cover Sheet 1
Block Diagram
Clock & Reset Map

2
3
4,5,6,7Foster CPU #1 & #2

CSB5
PCI 32 Slot 1/2 (33MHz/32Bit)
LAN 82559ER(82550)

Interrupt Mapping Ckt
CPU GTLREF & SMBus Address 8
ITP Connector

A A

Ratio & Level Shift Circuit
CPU Level Shift Circuit
CMIC-LE
DDR Module 1/2/3/4 17,18
Memory Termination #1 & #2
Clock Synthesizer
PCI 33 Clock Buffer
DDR Clock Buffer
CIOB-X2

CIOB-X2 Clock Buffer
Thin IMB Termination
Stitching Capacitors
PCI 64 Slot 1/2 (66MHz/64Bit)
SCSI AIC7899W/7902

AGP Pro Slot

9
10
11
12,13,14,15,16

19,20
21
22
23
24,25,26
27,28,29CIOB-G
30
31
32
33
34,35,36,37,38
39PCI-X Slot 1/2
40

ATA-HDD Connector

XAD Bus/Flash ROM

NS PC87417 SIO & IO Connector

Hardware Monitor

Power OK Circuit

Front Panel

Extra FAN Control

IPMI Slot

I2C Switching & MTH

Reset Buffer Circuit

Power Requlator - 3VSB/USBPWR

VRM 9.0 for CPU1 & CPU2

VCC25 & AVTT

VDD_AGP & VAGP_CARD

VDD_IMB

Manual Part 67

Note 68 - 73

1

41,42
43
44,45
46
47USB Connector
48
49
50,51,52,53
54
55
56
57
58
59
60
61
62,63
64
65
66

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

Cover Sheet

Last Revision Date:

Wednesday, May 09, 2001

Sheet

1 73

of

Rev

0A

MS-9102 Block Diagram

Full ATX - 12"*13"*8 Layers (10 MTHole)

VRM1

1

BLOCK DIAGRAM

Scoket 603 CPU1

CTRL

ADDR

ADDR

DATA

CTRL

Scoket 630 CPU2 VRM2

DATA

CTRL

ADDR

GTL BUS

DATA

FSB Suport 100/133MHz Foster/Gullatin CPU Support
VRM1/VRM2 Support VRM 9.0/9.1

66MHz/64Bit or 33MHz/32Bit Support

P64 PCI CONN 2

P64 PCI CONN 1

PCI 66MHz/64Bit Bus

ServerWorks

CIOB-X2

IMB Bus

SM BUS

ServerWorks

CMIC-LE

4 DIMM

Modules

Support Register ECC DDR DIMM Only

AIC 7899W/7902

EMRL

Ultra160/320 SCSI

Ultra 160/320

Ultra 160/320

PCI-X Bus

PCI-X CONN 1

PCI-X Bus (Up to 133MHz)

PCI-X CONN 2

Thin IMB Bus

IMB Bus

ServerWorks

CIOB-G

CTRL

ADDR

DATA

AGP Pro Slot

A A

IDE Primary

IDE Secondary

USB Port 1/2

USB Port 3/4

W83782D HWM

LPC

Ultra DMA66

USB 1.1

SM BUS

ServerWorks

CSB5 2.0

LPC

LPC

LPC

XAD Bus

FLASH ROM

PCI-X Bus

PCI 32 CONN

Intel 82550/559
PCI LAN Chip

IPMI
Slot

Floopy

PC87417

Keyboard

1

NS

Mouse

Serial 1
Serial 2

Parallel

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

Block Diagram

Last Revision Date:

Wednesday, May 09, 2001

Sheet

2 73

Rev

0A

of

1

RESET SCHEME

WTX
POWER

PS_PWRGD

SUPPLY
CONN.

RESET SWITCH

ITP_RESET#

AND

INVERTER

RESET GEN

140mS PERIOD
RESET Vth =

4.5V

PS_PWRGD#

POWERGOOD

CPU_VRM_PWRGD

PS_PWRGD#

PLLRST

PCIRST#

CMIC CIOB'S

SRESET#

AND

RSB5

PLLRST

PCIRST#

PLLRST

PCIRST#

PCIRST#

P1/P2_PCIRST#

S1/S2_PCIRST#

RESET FOR RSB
PCI BUS

RESETS FOR PCI
BUSES

PROC_RESET# CPU RESET

RESETDLY# Config RESET - 4

BCLK delay w.r.t.
PROC_RESET#

CPU_PWRGD

POWER

t0

PSU PWR GOOD

PLL RST

t0+100mS

POWERGOOD

VRM POWERGOOD

PROCESSOR POWERGOOD

PROCESSOR RESET

PCI RESET

CONFIG RESET

t0+100mS

t0+50mS

t0+120mS

t0+120mS

t0+120mS+1mS

t0+120mS+1mS

t0+120mS+1mS+4 clocks

CLOCKING SCHEME

- CPU 0

- CPU1

- CMIC

A A

14.318 MHz
X-TAL

CLK SYNTH.

BCLK
BCLK#

33MHz

48MHz
48MHz
14MHz

- DIMM PLL

- ITP Connector

- PROBE Header

6 Pairs of 100MHz
Differential
CLOCKs

From CLK
SYNTH.

33MHz Low Skew
Buffer

DIMM PLL

BCLK
BCLK#

FBOUT#
FBOUT

8 Pairs of 100MHz
Differential CLOCKs
for 8 DIMMs

33MHz

CIOB

P1_CLKO

S1_CLKO

P1_FBCLK

TO PCI
CONNs.

PCI-X PLLs

n

33MHz CLOCK TO RSB and
DEVICES behind it.

S1_FBCLK

TO PCI
CONNs.

48MHz USB CLK to RSB

48MHz CLK to SIO

14 MHz CLK to RSB

33MHz

CIOB-G

FBCLK

66MHz

1

AGP CONN.

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

Clock & Reset Map

Last Revision Date:

Wednesday, May 09, 2001

Sheet

3 73

Rev

0A

of

A

P1_SM_ADDR[0..2]<8>
P1_SM_TS_ADDR[0..1]<8>

PD#[0..63]<6,12>

P1_VCCA<11>

P1_VCCIOPLL<11>

FSB_VCC_SENSE<6,62,63>

P1_VSSA<11>

FSB_GND_SENSE<6,62,63>

4 4

VCC_P

R7
1K

R9
X_1K

3 3

VCC3

2 2

Enable

P1_ODTEN

Disable

DON'T STUFF

OnDie
Termination

R10 X_4.7K

DON'T STUFF

VCC3

C1
102P

P1_SM_WP

HCLK1_N<21>

AP#0<6,12>
AP#1<6,12>

HCLK1<21>

P1_SM_ADDR[0..2]
P1_SM_TS_ADDR[0..1]

PD#[0..63]

P1_ODTEN

TP18

1

PD#0
PD#1
PD#2
PD#3
PD#4
PD#5
PD#6
PD#7
PD#8
PD#9
PD#10
PD#11
PD#12
PD#13
PD#14
PD#15
PD#16
PD#17
PD#18
PD#19
PD#20
PD#21
PD#22
PD#23
PD#24
PD#25
PD#26
PD#27
PD#28
PD#29
PD#30
PD#31
PD#32
PD#33
PD#34
PD#35
PD#36
PD#37
PD#38
PD#39
PD#40
PD#41
PD#42
PD#43
PD#44
PD#45
PD#46
PD#47
PD#48
PD#49
PD#50
PD#51
PD#52
PD#53
PD#54
PD#55
PD#56
PD#57
PD#58
PD#59
PD#60
PD#61
PD#62
PD#63

AP#0
AP#1

HCLK1
HCLK1_N

CPU1A

A3B5D26

AA5

B27

AD4

Y26

D0#

AA27

D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

AP0#
AP1#

BCLK0
BCLK1

ODTEN

SKTOCC#

VSSSENSE

A3#

A22

VSSA

VCCSENSE

A4#

A5#

A20

B18

VCCIOPLL

A6#

C18

Y24
AA25
AD27

Y23
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11

AE9
AD10

AD8

AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10

AC8

AD7

AE7

AC6

AC5

AA8

Y9

AB6

E10

D9
Y4

W5

FOSTER

AB4

A19

VCCA

A7#

C17

VCC3

P1_SM_WP

AD29

A8#

D17

AE29

AE28

SMB_WP

SM_VCC1

A9#

A10#

A13

B16

P1_SM_TS_ADDR0

P1_SM_TS_ADDR1

Y29

AA28

SM_VCC

SM_TS_A1

A11#

A12#

B14

B13

B

P1_SM_ADDR0

P1_SM_ADDR1

P1_SM_ADDR2

AB28

AB29

AA29

SM_TS_A0

SM_EP_A2

SM_EP_A1

A13#

A14#

A15#

A12

C15

C14

CPU_SDA <6,59>
CPU_SCL <6,59>
CPU_SMBALERT# <6>

45.3RST

R145.3RST

R2

P1_COMP0

P1_COMP1

AC29

AC28

AD28

E16

AD16

W6W7W8Y6AA7

COMP1

COMP0

SM_DAT

SM_CLK

SM_ALERT

TESTHI0

SM_EP_A0

FOSTER

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

D16

D15

A25#

F15

A10

B10

B11

C12

E14

D13A9B8

VCC_P

R3 180

TESTHI1

TESTHI2

A26#

A27#

E13

TESTHI3

TESTHI4

A28#

A29#

D12

R4 180

DP#3

AE17

AD5

AE5

DP3#

TESTHI5

TESTHI6

A30#

A31#

A32#

A33#

A34#

A35#

C11B7A6A7C9C8D20

DP#2

AC15

DP2#

BR0#

DP#1

AE19

F12

DP#0

AC18

DP1#

BR1#

E11

DP0#

BR2#

C

HREQ#[0..4]
DSTBP#[0..3]
DSTBN#[0..3]
BPM#[2..5]
VRM_VID[0..4]
DINV#[0..3]
DP#[0..3]

E19

F24

A25

E25

C24

E24

TDI

TDO

TCK

TMS

DBI3#

TRST#

TRDY#

DBI2#
DBI1#
DBI0#

VID0
VID1
VID2
VID3
VID4

GTLREF3
GTLREF2
GTLREF1
GTLREF0

DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

SLP#

STPCLK#

SMI#

THERMTRIP#

PWRGD

PR0CH0T#

INIT#
LINIT1
LINIT0
FERR#

IGNNE#

A20M#

RESET#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

LOCK#

MCERR#

RSP#

RS2#
RS1#
RS0#

IERR#

DEFER#

HITM#

HIT#

ADS#

ADSTB0#

D23

BPRI#

F11

BINIT#

DBSY#

F18

ADSTB1#

DRDY#

E18

BR3#

BNR#

D10

F20

AB9
AE12
AD22
AC27

F3
E3
D3
C3
B3

F9
F23
W9
W23

DSTBP#3

Y11

DSTBP#2

Y14

DSTBP#1

Y17

DSTBP#0

Y20

DSTBN#3

Y12

DSTBN#2

Y15

DSTBN#1

Y18

DSTBN#0

Y21
F6

F8
E7
F5
E8
E4

AE6
D4
C27
F26
AB7
B25
D6
G23
B24
E27
C26
F27

Y8
B19

B21
C21
C20
B22

A17
D7

C6
F21
D22
E21

E5
C23
A23
E22
D19
F17
F14

HREQ#[0..4] <6,12>
DSTBP#[0..3] <6,12>
DSTBN#[0..3] <6,12>
BPM#[2..5] <6,9,11>
VRM_VID[0..4] <6,54,62,63>
DINV#[0..3] <6,12>
DP#[0..3] <6,12>

P1_TDO <6,9>
P1_TDI <9>
P1_TCK <9>
P_TRDY# <6,12>
ITP_TRST# <6,9>
TMS <6,9>

DINV#3
DINV#2
DINV#1
DINV#0

VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3
VRM_VID4

BPM#2
BPM#3
BPM#2
BPM#3
BPM#4
BPM#5

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

P1_IERR#
DEFER#
HITM#
HIT#
ADS#
ADSTB#0
ADSTB#1

P1_GTLREF1 <8>
P1_GTLREF0 <8>

SLP# <6,11>
CPU_STPCLK# <6,11>
SMI# <6,11>
P1_THERMTRIP# <10>
CPU1_PWRGD <55>
P1_PROCHOT# <10>
INIT# <6,11>
LINT1 <6,10,11>
LINT0 <6,10,11>
FERR# <6,10,11>
IGNNE# <6,10,11>
A20M# <6,10,11>

PROC_RESET# <6,9,11,13>

LOCK# <6,11,12>
MCERR# <6,11>

RSP# <6,12>
RS#2 <6,12>
RS#1 <6,12>
RS#0 <6,12>

P1_IERR# <10>
DEFER# <6,12>
HITM# <6,11,12>
HIT# <6,11,12>
ADS# <6,12>
ADSTB#0 <6,12>
ADSTB#1 <6,12>

D

Check Which CPU is
close to ITP

VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3

RN1 8P4R-1K

VRM_VID4

R5 1K

PLACE NEAR CENTER OF
VCC_FSB PLANES

FSB_VCC_SENSE<6,62,63>

FSB_GND_SENSE<6,62,63>

FSB_VCC_SENSE

FSB_GND_SENSE

ALL SENSE LINES MEET AT
CENTRES OF PLANES

Route FSB_VCC/GND_SENSE,
VRM_ISHARE signals in 25/50
Mils trace width

TP1

1

TP2

1

12
34
56
78

E

VCC

R6 0

R8
0

VCC_P

PA#3

PA#4

PA#5

PA#6

PA#7

PA#8

PA#9

PA#10

PA#11

PA#12

PA#13

PA#14

PA#15

PA#16

PA#17

PA#18

PA#19

PA#20

PA#21

PA#22

PA#23

PA#24

PA#25

PA#26

PA#27

PA#28

PA#29

PA#30

PA#31

PA#32

PA#33

PA#34

PA#35

BREQ#0

BINIT#

DBSY#

BREQ#3

DRDY#

R11 39.2RST
R12 39.2RST
R13 39.2RST
R14 39.2RST

PLACE AT PROC 1

C

VCC_P

DRDY# <6,12>
DBSY# <6,12>
BINIT# <6,11,12>

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

D

http://www.msi.com.tw

Foster CPU #1

Last Revision Date:

Wednesday, May 09, 2001

Sheet

E

4 73

of

Rev

0A

BREQ#1

PA#[3..35]

PA#[3..35]<6,12>

BREQ#0<6,12>
BREQ#1<6>
BREQ#2<6>
BREQ#3<6>

BNR#<6,11,12>

1 1

BPRI#<6,12>

A

B

BREQ#2

A

VCC_P

4 4

3 3

2 2

1 1

A14
A18
A24
A28

B12
B20
B26
B29

C10
C16
C22
C28

D14
D18
D24
D29

E12
E20
E26
E28

F10
F16
F22
F29

G24
G26
G28

H23
H25
H27
H29

J24
J26
J28

K23
K25
K27
K29

L24
L26
L28

M23
M25
M27
M29

N23
N25
N27
N29

P24
P26
P28

R23
R25

R27
W27
W25

A2
A8

B6

C2
C4

D8

E2
E6

F4

G2
G4
G6
G8

H3
H5
H7
H9

J2
J4
J6
J8

K3
K5
K7
K9

L2
L4
L6
L8

M3
M5
M7
M9

N3
N5
N7
N9

P2
P4
P6
P8

R3
R5
R7
R9

CPU1B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOSTER

GND33

GND34

GND35

GND36

GND37

GND38

GND39

EMI_GND1

EMI_GND2

EMI_GND3

EMI_GND4

EMI_GND5

EMI_GND6

EMI_GND7

FOSTER_PWR

EMI_GND10

EMI_GND11

EMI_GND12

EMI_GND13

EMI_GND14

EMI_GND15

GND42

GND43

GND44

GND45

GND46

GND47

GND40

GND41

VSS
VSS
VSS
VSS
VSS

EMI_GND8

EMI_GND9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

EMI_GND16

GND48

A5
A11
A21
A27
A29
B2
B9
B15
B17
B23
B28
C7
C13
C19
C25
C29
D2
D5
D11
D21
D27
D28
E9
E15
E17
E23
E29
F2
F7
F13
F19
F25
F28
G3
G5
G7
G9
G25
G27
G29
H2
H4
H6
H8
H24
H26
H28
J3
J5
W29
Y2
Y10
Y16
Y22
AA4
AA6
AA12
AA20
AA26
AB2
AB8
AB14
AB18
AB24
AC3
AC4
AC10
AC16
AC22
AD2
AD6
AD12
AD20
AD26
AE3
AE8
AE14
AE18
AE24
R29
T2
T4
T6
T8
T24
T26
T28
U3
U5
U7
U9
U23
U25
U27
U29
V2
V4
V6
V8
V24
V26
V28

VCC_P

B

CPU1C

GND21

GND22

GND23

GND24

GND25

GND26

MTG_GND21

MTG_GND1

MTG_GND2

GND1

GND2

GND3

MTG_GND22

MTG_GND23

MTG_GND24

MTG_GND25

MTG_GND3

MTG_GND4

MTG_GND5

MTG_GND6

GND4

GND5

GND6

GND27

MTH_GND26

MTG_GND7

GND7

GND8

J7

VSS

J9

VSS

J23

VSS

J25

VSS

J27

VSS

J29

VSS

K2

VSS

K4

VSS

K6

VSS

K8

VSS

K24

VSS

K26

VSS

K28

VSS

L3

VSS

L5

VSS

L7

VSS

L9

VSS

L23

VSS

L25

VSS

L27

VSS

L29

VSS

M2

VSS

M4

VSS

M6

VSS

M8

VSS

M24

VSS

M26

VSS

M28

VSS

N2

VSS

N4

VSS

N6

VSS

N8

VSS

N24

VSS

N26

VSS

N28

VSS

P3

VSS

P5

VSS

P7

VSS

P9

VSS

P23

VSS

P25

VSS

P27

VSS

P29

VSS

R2

VSS

R4

VSS

R6

VSS

R8

VSS

R24

VSS

R26

VSS

R28

VSS

T3

VSS

T5

VSS

T7

VSS

T9

VSS

T23

VSS

T25

VSS

T27

VSS

T29

VSS

U2

VSS

U4

VSS

U6

VSS

U8

VSS

U24

VSS

U26

VSS

U28

VSS

V3

VSS

V5

VSS

V7

VSS

V9

VSS

V23

VSS

V25

VSS

V27

VSS

V29

VSS

W2

VSS

W4

VSS

W24

VSS

W26

VSS

W28

VSS

Y5

VSS

Y7

VSS

Y13

VSS

Y19

VSS

Y25

VSS

AA2

VSS

AA9

VSS

AA15

VSS

AA17

VSS

AA23

VSS

AB5

VSS

AB11

VSS

AB21

VSS

AB27

VSS

AC2

VSS

AC7

VSS

AC13

VSS

AC19

VSS

AC25 AD3

VSS VSS

FOSTER

GND28

GND29

GND30

MTG_GND27

MTG_GND28

MTG_GND29

MTG_GND30

MTG_GND8

MTG_GND9

MTG_GND10

MTG_GND11

GND9

GND10

GND11

A1

GND31

GND32

MTG_GND31

MTG_GND32

FOSTER_PWR

MTG_GND12

MTG_GND13

MTG_GND14

MTG_GND15

GND12

GND13

GND14

GND15

GND16

A4

GAL_VDD1
GAL_VDD2
GAL_VDD3

RSVD1

RSVD2

GAL_VDD4
GAL_VDD5
GAL_VDD6
GAL_VDD7
GAL_VDD8

GAL_VDD9
GAL_VDD10
GAL_VDD11
GAL_VDD12
GAL_VDD13
GAL_VDD14
GAL_VDD15
GAL_VDD16
GAL_VDD17
GAL_VDD18
GAL_VDD19
GAL_VDD20
GAL_VDD21
GAL_VDD22
GAL_VDD23
GAL_VDD24
GAL_VDD25
GAL_VDD26
GAL_VDD27
GAL_VDD28
GAL_VDD29
GAL_VDD30
GAL_VDD31
GAL_VDD32
GAL_VDD33
GAL_VDD34
GAL_VDD35

GAL_VSS1

GAL_VSS2

GAL_VSS3

GAL_VSS4

GAL_VSS5

GAL_VSS6

GAL_VSS7

GAL_VSS8

GAL_VSS9
GAL_VSS10
GAL_VSS11
GAL_VSS12
GAL_VSS13
GAL_VSS14
GAL_VSS15
GAL_VSS16
GAL_VSS17
GAL_VSS18
GAL_VSS19
GAL_VSS20
GAL_VSS21
GAL_VSS22
GAL_VSS23
GAL_VSS24
GAL_VSS25
GAL_VSS26
GAL_VSS27
GAL_VSS28
GAL_VSS29
GAL_VSS30
GAL_VSS31
GAL_VSS32
GAL_VSS33
GAL_VSS34

MTG_GND16

MTG_GND17

MTG_GND18

GND17

GND18

RSVD3
RSVD4
RSVD5

RSVD8
RSVD13
RSVD17
RSVD63
RSVD67
RSVD68
RSVD69
RSVD73
RSVD77
RSVD80
RSVD83
RSVD86
RSVD87
RSVD88

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MTG_GND19

MTG_GND20

GND19

GND20

C

VCC_P

A30
B4
B31
C30
D1
D31
E30
F1
F31
G30
H1
H31
J30
K1
K31
L30
M1
M31
N1
N31
P30
R1
R31
T30
U1
U31
V30
W1
W31
Y30
AA1
AA31
AB30
AC31
AD30

A31
B30
C1
C31
D30
E1
E31
F30
G1
G31
H30
J1
J31
K30
L1
L31
M30
N30
P1
P31
R30
T1
T31
U30
V1
V31
W30
Y1
Y31
AA30
AB1
AB31
AC30
AD31

A15
A16
A26
B1
C5
D25
W3
Y3
Y27
Y28
AA3
AB3
AC1
AD1
AE4
AE15
AE16
AE27
AE21
AE11
AE2
AD23
AD17
AD15
AD9

R15
X_0

DON'T STUFF

D

CPU1 CORE
DECOUPLING

4.7U/0805

4.7U/0805C44.7U/0805

C2

C3

4.7U/0805

4.7U/0805
C10

C9

4.7U/0805

4.7U/0805

C16

C17

4.7U/0805

4.7U/0805

C23

C24

PLACE AROUND P1 SOCKET

C30
105P

C32

C31

105P

105P

4.7U/0805
C11

4.7U/0805
C18

4.7U/0805
C25

C33
105P

4.7U/0805
C5

4.7U/0805
C12

4.7U/0805
C19

4.7U/0805
C26

C34
105P

C38
104P

4.7U/0805
C6

4.7U/0805
C13

4.7U/0805
C20

4.7U/0805
C27

C35
105P

C39
104P

E

4.7U/0805
C7

4.7U/0805
C14

4.7U/0805
C21

4.7U/0805
C28

C36
105P

C40
104P

VCC_P

VCC_P

VCC_P

VCC_P

VCC_P

VCC_P

4.7U/0805
C8

4.7U/0805
C15

4.7U/0805
C22

4.7U/0805
C29

C37
105P

C41
104P

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

A

B

C

D

http://www.msi.com.tw

Foster CPU #1 PWR

Last Revision Date:

Sheet

Wednesday, May 09, 2001

E

5 73

of

Rev

0A

A

P2_SM_ADDR[0..2]<8>

P2_SM_TS_ADDR[0..1]<8>

PD#[0..63]<4,12>

P2_VCCA<11>

P2_VCCIOPLL<11>

FSB_VCC_SENSE<4,62,63>

P2_VSSA<11>

FSB_GND_SENSE<4,62,63>

4 4

VCC_P

R20

Enable

X_1K

DON'T STUFF

P2_ODTEN

R21
1K

Disable

OnDie
Termination

3 3

VCC3

R22
X_4.7K

DON'T STUFF

P2_SM_WP

VCC3

102P
C42

2 2

1 1

P2_SM_ADDR[0..2]
P2_SM_TS_ADDR[0..1]

PD#[0..63]

P2_ODTEN

TP17

1

CPU2A

A3B5D26

AA5

B27

PD#0

Y26

PD#1
PD#2
PD#3
PD#4
PD#5
PD#6
PD#7
PD#8
PD#9
PD#10
PD#11
PD#12
PD#13
PD#14
PD#15
PD#16
PD#17
PD#18
PD#19
PD#20
PD#21
PD#22
PD#23
PD#24
PD#25
PD#26
PD#27
PD#28
PD#29
PD#30
PD#31
PD#32
PD#33
PD#34
PD#35
PD#36
PD#37
PD#38
PD#39
PD#40
PD#41
PD#42
PD#43
PD#44
PD#45
PD#46
PD#47
PD#48
PD#49
PD#50
PD#51
PD#52
PD#53
PD#54
PD#55
PD#56
PD#57
PD#58
PD#59
PD#60
PD#61
PD#62
PD#63

AP#0

AP#0<4,12>

AP#1

AP#1<4,12>

HCLK2

HCLK2<21>

HCLK2_N

HCLK2_N<21>

PA#[3..35]<4,12>

BREQ#1<4>
BREQ#0<4,12>
BREQ#2<4>
BREQ#3<4>

D0#

AA27

D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

AP0#
AP1#

BCLK0
BCLK1

ODTEN

SKTOCC#

VSSSENSE

A3#

A22

A20

PA#3

VSSA

VCCSENSE

A4#

A5#

B18

PA#4

PA#5

Y24

AA25
AD27

Y23

AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11

AE9

AD10

AD8

AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10

AC8

AD7

AE7

AC6

AC5

AA8

Y9

AB6

E10

D9
Y4

W5

FOSTER

PA#[3..35]

BNR#<4,11,12>
BPRI#<4,12>

VCC3

AD4

AB4

VCCA

VCCIOPLL

A6#

A7#

C18

A19

C17

PA#6

PA#7

PA#8

P2_SM_WP

AD29

A8#

D17

PA#9

AE29

AE28

SMB_WP

SM_VCC1

A9#

A10#

A13

B16

PA#10

PA#11

B

P2_SM_TS_ADDR1

P2_SM_TS_ADDR0

P2_SM_ADDR2

Y29

AA28

AB28

SM_VCC

SM_TS_A1

SM_TS_A0

A11#

A12#

A13#

B14

B13

A12

PA#12

PA#13

PA#14

P2_SM_ADDR0

P2_SM_ADDR1

AB29

AA29

SM_EP_A2

SM_EP_A1

A14#

A15#

C15

C14

PA#15

PA#16

CPU_SDA <4,59>
CPU_SCL <4,59>
CPU_SMBALERT# <4>

45.3RST

45.3RST

R16

R17

P2_COMP0

P2_COMP1

AC29

AC28

AD28

E16

AD16

W6W7W8Y6AA7

COMP1

COMP0

SM_DAT

SM_CLK

SM_ALERT

TESTHI0

SM_EP_A0

FOSTER

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

D16

D15

PA#17

PA#18

A25#

F15

A10

B10

B11

C12

E14

D13A9B8

PA#19

PA#20

PA#21

PA#22

PA#23

PA#24

PA#25

PA#26

VCC_P

180

R18

R19

AD5

TESTHI1

TESTHI2

TESTHI3

TESTHI4

A26#

A27#

A28#

A29#

E13

D12

C11B7A6A7C9C8D20

PA#27

PA#28

PA#29

PA#30

180

AE5

TESTHI5

TESTHI6

A30#

A31#

PA#31

PA#32

A32#

C

HREQ#[0..4]
DSTBP#[0..3]
DSTBN#[0..3]
BPM#[2..5]
VRM_VID[0..4]
DINV#[0..3]
DP#[0..3]

DP#1

DP#0

DP#2

DP#3

E25

C24

E24

AE17

AC15

AE19

AC18

TDI

TDO

TCK

DP3#

DP2#

DP1#

DP0#

A33#

A34#

A35#

BR0#

BR1#

BR2#

BR3#

BNR#

BPRI#

BINIT#

F12

E11

D10

F20

D23

F11

BINIT#

BNR#

PA#35

BPRI#

BREQ#2

BREQ#1

BREQ#3

BREQ#0

PA#33

PA#34

HREQ#[0..4] <4,12>
DSTBP#[0..3] <4,12>
DSTBN#[0..3] <4,12>
BPM#[2..5] <4,9,11>
VRM_VID[0..4] <4,54,62,63>
DINV#[0..3] <4,12>
DP#[0..3] <4,12>

P2_TDO <9>
P1_TDO <4,9>
P2_TCK <9>
P_TRDY# <4,12>
ITP_TRST# <4,9>
TMS <4,9>

E19

F24

A25

TMS

AB9

DBI3#

TRST#

TRDY#

DBSY#

F18

DBSY#

AE12

DBI2#

AD22

DBI1#

AC27

DBI0#

F3

VID0

E3

VID1

D3

VID2

C3

VID3

B3

VID4

F9

GTLREF3

F23

GTLREF2

W9

GTLREF1

W23

GTLREF0

Y11

DSTBP3#

Y14

DSTBP2#

Y17

DSTBP1#

Y20

DSTBP0#

Y12

DSTBN3#

Y15

DSTBN2#

Y18

DSTBN1#

Y21

DSTBN0#

F6

BPM0#

F8

BPM1#

E7

BPM2#

F5

BPM3#

E8

BPM4#

E4

BPM5#

AE6

SLP#

D4

STPCLK#

C27

SMI#

F26

THERMTRIP#

AB7

PWRGD

B25

PR0CH0T#

D6

INIT#

G23

LINIT1

B24

LINIT0

E27

FERR#

C26

IGNNE#

F27

A20M#

Y8

RESET#

B19

REQ0#

B21

REQ1#

C21

REQ2#

C20

REQ3#

B22

REQ4#

A17

LOCK#

D7

MCERR#

C6

RSP#

F21

RS2#

D22

RS1#

E21

RS0#

E5

IERR#

C23

DEFER#

A23

HITM#

E22

HIT#

D19

ADS#

F17

ADSTB0#

F14

ADSTB1#

DRDY#

E18

Place these close to CPU2

DRDY#

R23 40.2RST
R24 40.2RST

Check Which CPU is
close to ITP

DINV#3
DINV#2
DINV#1
DINV#0

VRM_VID0
VRM_VID1
VRM_VID2
VRM_VID3
VRM_VID4

DSTBP#3
DSTBP#2
DSTBP#1
DSTBP#0
DSTBN#3
DSTBN#2
DSTBN#1
DSTBN#0

BPM#2
BPM#3
BPM#2
BPM#3
BPM#4
BPM#5

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

P2_IERR#
DEFER#
HITM#
HIT#
ADS#
ADSTB#0
ADSTB#1

DRDY# <4,12>
DBSY# <4,12>
BINIT# <4,11,12>

D

P2_GTLREF1 <8>
P2_GTLREF0 <8>

SLP# <4,11>
CPU_STPCLK# <4,11>
SMI# <4,11>
P2_THERMTRIP# <10>
CPU2_PWRGD <55>
P2_PROCHOT# <10>
INIT# <4,11>
LINT1 <4,10,11>
LINT0 <4,10,11>
FERR# <4,10,11>
IGNNE# <4,10,11>
A20M# <4,10,11>

PROC_RESET# <4,9,11,13>

LOCK# <4,11,12>
MCERR# <4,11>

RSP# <4,12>
RS#2 <4,12>
RS#1 <4,12>
RS#0 <4,12>

P2_IERR# <10>
DEFER# <4,12>
HITM# <4,11,12>
HIT# <4,11,12>
ADS# <4,12>
ADSTB#0 <4,12>
ADSTB#1 <4,12>

VCC_P

E

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

A

B

C

D

http://www.msi.com.tw

Foster CPU #2

Last Revision Date:

Wednesday, May 09, 2001

Sheet

E

6 73

of

Rev

0A

A

VCC_P

CPU2B

GND33

GND34

GND35

GND36

GND37

GND38

GND39

GND40

EMI_GND1

EMI_GND2

EMI_GND3

EMI_GND10

EMI_GND11

GND42

GND43

GND44

EMI_GND4

EMI_GND5

EMI_GND6

EMI_GND7

EMI_GND12

EMI_GND13

EMI_GND14

EMI_GND15

GND45

GND46

GND47

GND41

EMI_GND8

EMI_GND9

EMI_GND16

GND48

A5

VSS

A11

VSS

A21

VSS

A27

VSS

A29

VSS

B2

VSS

B9

VSS

B15

VSS

B17

VSS

B23

VSS

B28

VSS

C7

VSS

C13

VSS

C19

VSS

C25

VSS

C29

VSS

D2

VSS

D5

VSS

D11

VSS

D21

VSS

D27

VSS

D28

VSS

E9

VSS

E15

VSS

E17

VSS

E23

VSS

E29

VSS

F2

VSS

F7

VSS

F13

VSS

F19

VSS

F25

VSS

F28

VSS

G3

VSS

G5

VSS

G7

VSS

G9

VSS

G25

VSS

G27

VSS

G29

VSS

H2

VSS

H4

VSS

H6

VSS

H8

VSS

H24

VSS

H26

VSS

H28

VSS

J3

VSS

J5

VSS

W29

VCC

Y2

VCC

Y10

VCC

Y16

VCC

Y22

VCC

AA4

VCC

AA6

VCC

AA12

VCC

AA20

VCC

AA26

VCC

AB2

VCC

AB8

VCC

AB14

VCC

AB18

VCC

AB24

VCC

AC3

VCC

AC4

VCC

AC10

VCC

AC16

VCC

AC22

VCC

AD2

VCC

AD6

VCC

AD12

VCC

AD20

VCC

AD26

VCC

AE3

VCC

AE8

VCC

AE14

VCC

AE18

VCC

AE24

VCC

R29

VCC

T2

VCC

T4

VCC

T6

VCC

T8

VCC

T24

VCC

T26

VCC

T28

VCC

U3

VCC

U5

VCC

U7

VCC

U9

VCC

U23

VCC

U25

VCC

U27

VCC

U29

VCC

V2

VCC

V4

VCC

V6

VCC

V8

VCC

V24

VCC

V26

VCC

V28

VCC

VCC_P

A2

VCC

A8

VCC

A14

VCC

A18

VCC

A24

VCC

A28

VCC

B6

VCC

B12

VCC

B20

VCC

B26

VCC

B29

4 4

3 3

2 2

FOSTER

1 1

C10
C16
C22
C28

D14
D18
D24
D29

E12
E20
E26
E28

F10
F16
F22
F29
G2
G4
G6

G8
G24
G26
G28

H23
H25
H27
H29

J24

J26

J28

K23
K25
K27
K29

L24

L26

L28

M3

M5

M7

M9
M23
M25
M27
M29

N23
N25
N27
N29

P24
P26
P28

R23
R25
R27
W27
W25

C2
C4

D8

E2
E6

F4

H3
H5
H7
H9

J2
J4
J6
J8

K3
K5
K7
K9

L2
L4
L6
L8

N3
N5
N7
N9

P2
P4
P6
P8

R3
R5
R7
R9

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

FOSTER_PWR

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

B

CPU2C

GND21

GND22

GND23

GND24

GND25

GND26

MTG_GND21

MTG_GND1

MTG_GND2

GND1

GND2

GND3

MTG_GND22

MTG_GND23

MTG_GND24

MTG_GND25

MTG_GND3

MTG_GND4

MTG_GND5

MTG_GND6

GND4

GND5

GND6

GND7

GND27

MTG_GND26

MTG_GND27

MTG_GND7

MTG_GND8

GND8

J7

VSS

J9

VSS

J23

VSS

J25

VSS

J27

VSS

J29

VSS

K2

VSS

K4

VSS

K6

VSS

K8

VSS

K24

VSS

K26

VSS

K28

VSS

L3

VSS

L5

VSS

L7

VSS

L9

VSS

L23

VSS

L25

VSS

L27

VSS

L29

VSS

M2

VSS

M4

VSS

M6

VSS

M8

VSS

M24

VSS

M26

VSS

M28

VSS

N2

VSS

N4

VSS

N6

VSS

N8

VSS

N24

VSS

N26

VSS

N28

VSS

P3

VSS

P5

VSS

P7

VSS

P9

VSS

P23

VSS

P25

VSS

P27

VSS

P29

VSS

R2

VSS

R4

VSS

R6

VSS

R8

VSS

R24

VSS

R26

VSS

R28

VSS

T3

VSS

T5

VSS

T7

VSS

T9

VSS

T23

VSS

T25

VSS

T27

VSS

T29

VSS

U2

VSS

U4

VSS

U6

VSS

U8

VSS

U24

VSS

U26

VSS

U28

VSS

V3

VSS

V5

VSS

V7

VSS

V9

VSS

V23

VSS

V25

VSS

V27

VSS

V29

VSS

W2

VSS

W4

VSS

W24

VSS

W26

VSS

W28

VSS

Y5

VSS

Y7

VSS

Y13

VSS

Y19

VSS

Y25

VSS

AA2

VSS

AA9

VSS

AA15

VSS

AA17

VSS

AA23

VSS

AB5

VSS

AB11

VSS

AB21

VSS

AB27

VSS

AC2

VSS

AC7

VSS

AC13

VSS

AC19

VSS

AC25 AD3

VSS VSS

FOSTER

GND28

GND29

GND30

MTG_GND28

MTG_GND29

MTG_GND30

MTG_GND9

MTG_GND10

MTG_GND11

GND9

GND10

GND11

GND31

GND32

MTG_GND31

MTG_GND32

FOSTER_PWR

MTG_GND12

MTG_GND13

MTG_GND14

MTG_GND15

GND12

GND13

GND14

GND15

A1

RSVD1

MTG_GND16

GND16

A4

GAL_VDD1
GAL_VDD2
GAL_VDD3

RSVD2

GAL_VDD4
GAL_VDD5
GAL_VDD6
GAL_VDD7
GAL_VDD8

GAL_VDD9
GAL_VDD10
GAL_VDD11
GAL_VDD12
GAL_VDD13
GAL_VDD14
GAL_VDD15
GAL_VDD16
GAL_VDD17
GAL_VDD18
GAL_VDD19
GAL_VDD20
GAL_VDD21
GAL_VDD22
GAL_VDD23
GAL_VDD24
GAL_VDD25
GAL_VDD26
GAL_VDD27
GAL_VDD28
GAL_VDD29
GAL_VDD30
GAL_VDD31
GAL_VDD32
GAL_VDD33
GAL_VDD34
GAL_VDD35

GAL_VSS1

GAL_VSS2

GAL_VSS3

GAL_VSS4

GAL_VSS5

GAL_VSS6

GAL_VSS7

GAL_VSS8

GAL_VSS9
GAL_VSS10
GAL_VSS11
GAL_VSS12
GAL_VSS13
GAL_VSS14
GAL_VSS15
GAL_VSS16
GAL_VSS17
GAL_VSS18
GAL_VSS19
GAL_VSS20
GAL_VSS21
GAL_VSS22
GAL_VSS23
GAL_VSS24
GAL_VSS25
GAL_VSS26
GAL_VSS27
GAL_VSS28
GAL_VSS29
GAL_VSS30
GAL_VSS31
GAL_VSS32
GAL_VSS33
GAL_VSS34

RSVD13
RSVD17
RSVD63
RSVD67
RSVD68
RSVD69
RSVD73
RSVD77
RSVD80
RSVD83
RSVD86
RSVD87
RSVD88

MTG_GND17

MTG_GND18

MTG_GND19

GND17

GND18

GND19

RSVD3
RSVD4
RSVD5
RSVD8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MTG_GND20

GND20

C

VCC_P

A30
B4
B31
C30
D1
D31
E30
F1
F31
G30
H1
H31
J30
K1
K31
L30
M1
M31
N1
N31
P30
R1
R31
T30
U1
U31
V30
W1
W31
Y30
AA1
AA31
AB30
AC31
AD30

A31
B30
C1
C31
D30
E1
E31
F30
G1
G31
H30
J1
J31
K30
L1
L31
M30
N30
P1
P31
R30
T1
T31
U30
V1
V31
W30
Y1
Y31
AA30
AB1
AB31
AC30
AD31

A15
A16
A26
B1
C5
D25
W3
Y3
Y27
Y28
AA3
AB3
AC1
AD1
AE4
AE15
AE16
AE27
AE21
AE11
AE2
AD23
AD17
AD15
AD9

R25
X_0

DON'T STUFF

D

CPU2 CORE
DECOUPLING

4.7U/0805

4.7U/0805
C44

C43

4.7U/0805

4.7U/0805

C50

C51

4.7U/0805

4.7U/0805

C57

C58

4.7U/0805

4.7U/0805

C64

C65

PLACE AROUND P2 SOCKET

C71
105P

C73

C72

105P

105P

4.7U/0805
C45

4.7U/0805
C52

4.7U/0805
C59

4.7U/0805
C66

C74
105P

4.7U/0805
C46

4.7U/0805
C53

4.7U/0805
C60

4.7U/0805
C67

C75
105P

C79
104P

4.7U/0805
C47

4.7U/0805
C54

4.7U/0805
C61

4.7U/0805
C68

C76
105P

C80
104P

E

4.7U/0805
C48

4.7U/0805
C55

4.7U/0805
C62

4.7U/0805
C69

C77
105P

C81
104P

VCC_P

VCC_P

VCC_P

VCC_P

VCC_P

VCC_P

4.7U/0805
C49

4.7U/0805
C56

4.7U/0805
C63

4.7U/0805
C70

C78
105P

C82
104P

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

A

B

C

D

http://www.msi.com.tw

Foster CPU #2 PWR

Last Revision Date:

Sheet

Wednesday, May 09, 2001

E

7 73

of

Rev

0A

A

B

C

D

E

R26
X_1K

R38
X_1K

DON'T STUFF

VCC3

P1_SM_ADDR[0..2]

R27
X_1K

R33

R35

1K

VCC3

R39

R43

R45
1K

VCC_P

1K

X_1K

1K

R28
X_1K

DON'T STUFF

P1_SM_ADDR0
P1_SM_ADDR1P1_SM_TS_ADDR0
P1_SM_ADDR2

R34
1K

Addr._0 : 1010 000Z

Z = R/W bit

R40
1K

P2_SM_ADDR0
P2_SM_ADDR1
P2_SM_ADDR2

R44
X_1K

DON'T STUFF

Addr._1 : 1010 001Z

P2_SM_ADDR[0..2]

P1_SM_TS_ADDR[0..1]
P2_SM_TS_ADDR[0..1]

P1_SM_ADDR[0..2] <4>
P2_SM_ADDR[0..2] <6>
P1_SM_TS_ADDR[0..1] <4>
P2_SM_TS_ADDR[0..1] <6>

Z = R/W bit

CPU_0 Thermal Sensor SM Bus

4 4

3 3

Addr._0 : 0011X00Z
: 1001X00Z
: 0101X00Z

OR
OR

CPU_1 Thermal Sensor SM Bus

Addr._1 : 0011X01Z
: 1001X01Z
: 0101X01Z

OR
OR

R29
X_1K

DON'T STUFF

R31

R36
X_1K

DON'T STUFF

R41

1K

VCC3

1K

VCC3

VCC_P

R30
X_1K

P1_SM_TS_ADDR1

R32
1K

R37
1K

P2_SM_TS_ADDR0
P2_SM_TS_ADDR1

R42
X_1K

DON'T STUFF

R46

49.9RST

2 2

C83

C84

104P

104P

VCC_P

R50

49.9RST

1 1

A

C89
104P

C90
104P

P1_GTLREF0

R48

C85
105P

100

P2_GTLREF0 P2_GTLREF1

R52

C91
105P

100

B

PLACE EACH 220pf OF
GTLREF NEAR PROC PIN

R47

49.9RST

P1_GTLREF1

C86

C87

104P

104P

VCC_P

R51

49.9RST

C92

C93

104P

104P

C

R49
100

R53
100

C88
105P

C94
105P

P1_GTLREF1 <4>P1_GTLREF0 <4>

P2_GTLREF1 <6>P2_GTLREF0 <6>

Micro Star Restricted Secret

Title
Document Number

D

CPU GTLREF & SM Bus Slave Address

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

8 73

E

Rev

0A

of

A

B

C

D

E

VCC_P

VCC_P

VCC_P

RES. TO BE WITHIN
1" OF ITP CONN.

4 4

BPM#2<4,6,11>
BPM#3<4,6,11>
BPM#4<4,6,11>
BPM#5<4,6,11>

PROC_RESET#<4,6,11,13>

CLK_100M_ITP0<21>
CLK_100M_ITP1<21>

CLK_100M_ITP = BCLK (to
processors) + Length of
BPM# trace from ITP
connector to first CPU.

3 3

RES. TO BE WITHIN
1" OF ITP CONN.

2 2

JP1

1
2
3

YJ103

Place this HDR next to the
CPU nearest to ITP conn.

FBO

R64
X_1K

R71
150

VCC_P

R54 40.2RST

R55 40.2RST

R65
X_1K

R56 40.2RST

R72
330

P1_TDI
P1_TDO
P2_TDO

R57 40.2RST

VCC_P

PLACE NEAR CPU1

R58 40.2RST

J1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

CON25A

R73

RES. TO BE WITHIN

75

1" OF ITP CONN.

P1_TDI <4>
P1_TDO <4,6>
P2_TDO <6>

R62

RES. TO BE WITHIN
1" OF ITP CONN.

2

2

DBA#

4

4

6

6

8

8

P1_TDI

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

R63 0

Place it as close to

P2_TDO

ITP Conn. as possible

TCK

R66
680

R74 1K

R75 1K

R76 1K

R61

39.2RST

RES. TO BE WITHIN
1" OF ITP CONN.

2

TCK

4
6

8
11
13
15
17

1
19

R77 1K

R79 330

R78 1K

1KRST

U1

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

1G
2G

74LVCH244A

VCC
GND

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

R59
150

VCC3

R60

DON'T STUFF

X_150

ITP_RESET# <55>

TMS <4,6>
ITP_TRST# <4,6>

THIS NET TO BE DAISY
CHAINED ALONG PROCS.

R67

Within 1" of the last

150

device on this Net

Length of
P1_TCK =
P2_TCK

R_P1_TCK

18

R_P2_TCK

16

R_FBO

14
12
9
7
5
3

20

VCC_P

10

R68 22
R69 22
R70 22

VCC_P

C97

104P

FBO = TCK (to
processors) + Length of
BPM# trace from ITP
connector to first CPU.

FBO

C95

X_10P

P1_TCK <4>
P2_TCK <6>

C96

X_10P

C98

X_10P

Look at Routing guidelines while

1 1

A

Placing components from this
sheet

LAYOUT NOTE:

B

BPM#[0..5], RST#, FBO, BCKN, BCKP, TCK, AND FBI
ARE CRITICAL ROUTES.

C

Micro Star Restricted Secret

Title
Document Number

D

CPU GTLREF & SM Bus Slave Address

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

9 73

E

Rev

0A

of

5

4

3

2

1

VCC3

RN2

D D

C C

8P4R-330

INTR

INTR<42>

RSB_IGNNE#<42>

RSB_IGNNE#

R82
0

P1_THERMTRIP#<4>
P2_THERMTRIP#<6>

12
34
56
78

NMI
RESETDLY#

RSB_A20M#

P6_CGF1
P6_CGF2
P6_CGF3
P6_CGF4

11
10
14
13

15

R81
330

2
3
5
6

1

B1
B2
B3
B4

VCC

168

U3

1A

1Y

1B

VCCGND

2A

2Y
2B
3A

3Y
3B
4A

4Y
4B

A/B
G

74F157

RESETDLY# <12>
NMI <41>

RSB_A20M# <42>

VCC_P

R86 49.9RST

R87 49.9RST

SW1

YJ204

4
7
9
12

A1
A2
A3
A4

LINT0_3V
IGNNE#_3V
A20M#_3V
LINT1_3V

GTLREF_1

GTLREF_1

RN3

8P4R-330

C101
102P

12
34
56
78

11

8
4 1

9
10
12
13

C99
102P

VCC_P

C102
104P

U2

GND
GND

GTLREF DIRB-A
B4

B3
B2
B1

GTL2005

VCC3VCC

R83

49.9RST

GTLREF_1

R89
100

VCC3

R80

LINT0
IGNNE#
A20M#
LINT1

1K

LINT0 <4,6,11>
IGNNE# <4,6,11>
A20M# <4,6,11>
LINT1 <4,6,11>

7

GND

14

VDD

6

A4

5

A3

3

A2

2

A1

C100
102P

C103
104P

X8 H H H H
X9/X23 H H H L
X20 H H L H
X10 H H L L
X12 H L H H
X13 H L H L
X14 H L L H
X15 H L L L
X16 L H H H
X17 L H H L
X18 L H L H
X19 L H L L
X20 L L H H
X21 L L H L
X22 L L L H
X24 L L L L

FERR#<4,6,11>

NMI A20M# IGNNE# INTR
LINT1 LINT0

VCC3

R84

Q1
PMBT2369

330

RSB_FERR# <41>

R85
330

VCC_P

VCC_P

R88
330

B B

P1_PROCHOT#<4>
P2_PROCHOT#<6>

P1_IERR#<4>
P2_IERR#<6>

A A

5

VCC_P

VCC3

VCC3

123456

GTLREF_1

78

RN4
8P4R-1K

RSB_P1_PROCHOT# <42>
RSB_P2_PROCHOT# <42>
RSB_P1_IERR# <42>
RSB_P2_IERR# <42>

GTLREF_1

C105
102P

Micro Star Restricted Secret

Title

Ratio & Level Shift Circuit

Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

1

10 73

of

Rev

0A

C104
102P

R90 49.9RST

R91 49.9RST

R93 49.9RST

R92 49.9RST

VCC3

R94
330

U4

2

A1

3

A2

5

A3

6

A4

14

VDD

7

GND

GTL2005

4

13

B1

12

B2

10

B3

9

B4

41

GTLREFDIRB-A

8

GND

11

GND

A

B

C

D

E

VCC_P

4 4

PROC_RESET#<4,6,9,13>

FERR#<4,6,10>
BINIT#<4,6,12>

SMI#

SMI#<4,6>

IGNNE#<4,6,10>

CPU_STPCLK#<4,6>

BPM#[2..5]<4,6,9>

3 3

2 2

INIT#

INIT#<4,6>

CPU_STPCLK#

LINT0<4,6,10>
LINT1<4,6,10>

A20M#<4,6,10>

SLP#

SLP#<4,6>

BNR#<4,6,12>

HIT#<4,6,12>

HITM#<4,6,12>

LOCK#<4,6,12>

MCERR#<4,6>

EXT_SMI#<42,50>

CMIC_PINIT#<12,42>

PLACE NEAR CPU1

R95 40.2RST

R96 40.2RST

R99 40.2RST

R98 40.2RST

R100 40.2RST

R101 40.2RST

PLACE THESE
CLOSE TO CPU2

BINIT#

VCC3

VCC25

R120 1K

R121 1K

R102 40.2RST

(Make small Cu Islands for P1/P2_VCCA, P1/P2_VSSA and P1/P2_VCCIOPLL nets )

Place these Close to CPU1

VCC_P VCC_P

1 2

1 2

A

L1 4.7uH/1206

EC1

10U/16V/S

EC3

10U/16V/S

L3 4.7uH/1206

12

+

+

1 2

R122 0

1 1

R124 0

C113
105P

C115
105P

P1_VCCA <4>

P1_VSSA <4>

P1_VCCIOPLL <4>

DON'T STUFF PLACE NEAR CPU2

R103 40.2RST

VCC_P

R112 150

R113 150

5 6

9 8

R114 150

U5C

74F07S

U5D

74F07S

BPM#4

R115 150

R107 X_40.2RST

R117 150

R116 150

SMI#

INIT#

R97 X_2K

R106 X_40.2RST

R105 40.2RST

R104 40.2RST

Place these Close to CPU2

R123 0

R125 0

B

R109 40.2RST

R108 40.2RST

R110 40.2RST

BPM#3

BPM#4

BPM#5

1 2

L2 4.7uH/1206

EC2

10U/16V/S

EC4

10U/16V/S

1 2

L4 4.7uH/1206

R111 40.2RST

BPM#2

12

+

+

1 2

VCC_P VCC_P

C110
104P

CPU_STPCLK#

SLP#

U5E

11 10

74F07S

U5F

13 12

74F07S

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

U5A

1 2

74F07S

U5B

3 4

74F07S

D

C109
104P

C106
104P

P2_VCCA <6>

C114
105P

P2_VSSA <6>

C116
105P

P2_VCCIOPLL <6>

C

C107
104P

PLACE THE TERM CAPS NEAR THE TERMINATION
RESISTORS

RSB_STPCLK#<42>

RSB_SLP#<42>

VCC3

VCC3

R118

1K

R119

1K

C108
104P

C111
104P

VCC

C112
104P

Micro Star Restricted Secret

CPU Level Shift Circuit

Last Revision Date:

Wednesday, May 09, 2001

Sheet

11 73

E

Rev

0A

of

A

B

C

D

E

MEMOFFACK#

WRMRST#

CMIC_FATAL#

MEMOFF#

ALERT#

GTL_COMP_PD
GTL_COMP_PU
GTL_RCOMP

PA#[3..35]
PD#[0..63]
DINV#[0..3]
DP#[0..3]
DSTBN#[0..3]
DSTBP#[0..3]

22

PA#3
PA#4
PA#5
PA#6
PA#7
PA#8
PA#9
PA#10
PA#11
PA#12
PA#13
PA#14
PA#15
PA#16
PA#17
PA#18
PA#19
PA#20
PA#21
PA#22
PA#23
PA#24
PA#25
PA#26
PA#27
PA#28
PA#29
PA#30
PA#31
PA#32
PA#33
PA#34
PA#35

ADSTB#0<4,6>
ADSTB#1<4,6>

DRDY#<4,6>

P_TRDY#<4,6>

DEFER#<4,6>
BREQ#0<4,6>

PS_PWRGD#<25,27,42,55>

RESETDLY#<10>

WRMRST#<16>

HREQ#0<4,6>
HREQ#1<4,6>
HREQ#2<4,6>
HREQ#3<4,6>
HREQ#4<4,6>

ALERT#<16,25,27,42>

CMIC_PINIT#<11,42>

HCLK_CMIC<21>

HCLK_CMIC_N<21>

CMIC_FATAL#<16,42>

MEMOFF#<16,41>

MEMOFFACK#<16>

ADSTB#0
ADSTB#1

ADS#

ADS#<4,6>

BNR#

BNR#<4,6,11>

BPRI#

BPRI#<4,6>

DBSY#

DBSY#<4,6>

DRDY#
HIT#

HIT#<4,6,11>

HITM#

HITM#<4,6,11>

LOCK#

LOCK#<4,6,11>

P_TRDY#
DEFER#
BREQ#0

RESETDLY#

R_PCIRST_X#

WRMRST#
RS#0

RS#0<4,6>

RS#1

RS#1<4,6>

RS#2

RS#2<4,6>

RSP#

RSP#<4,6>

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

AP#0

AP#0<4,6>

AP#1

AP#1<4,6>

ALERT#

BINIT#<4,6,11>

CMIC_FATAL#
MEMOFF#

MEMOFFACK#

GTL_VREF_CMIC

GTL_COMP_PU
GTL_COMP_PD
GTL_RCOMP

AE25
AE24

AF26

AE26

AF27

AF23
AD27
AE27
AG25

AG24
AG26

K15
A17
A19
B18
A18
B19
A20
G16
C19
E19
H17
H16
D19
F18
H18
G19
F19
A23
B23
A22
A21
F20
B20
A24
A25
D20
B21
E20
B25
B27
A26
C22
D22

D18
C20

H19
K17

F23

D24
E16

G15
F15
C16
H15

E23
C24

F21

K18
G21

F22
H20

F1
G2
H5

C1
D1
G3

F4
E1

B1
G1

F2

H9

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

ADSTB0#
ADSTB1#

ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
LOCK#
TRDY#
DEFER#
BREQ0#

PLLRST
DLYRST
PCIRST#
WRMRST#

RS0#
RS1#
RS2#
RSP#

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

AP0#
AP1#

ALERT#
BINIT#
HINIT#
BCLKP
BCLKN
FATAL#

MEMOFF#
MEMOFFACK#

GTL_VREF
GTL_VREF

GTL_COMP_PU
GTL_COMP_PD
GTL_RCOMP

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DP0#
DP1#
DP2#
DP3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#

DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

C2
E3
B3
C3
F3
D4
A2
D2
D3
A3
H6
F6
G8
F5
H8
H10
F7
G9
E7
E6
A4
B4
D7
A5
G10
K11
B7
C6
F8
C7
E9
K12
D8
C8
D9
B9
E10
A7
A10
A8
B12
A11
F12
A12
G13
F13
K13
H12
B13
D12
A13
E13
C13
C14
A15
B15
D15
E14
E15
H14
K14
C15
A16
G14

G5
A6
C10
H13

C26
B26
E21
E25

G6
F9
C9
D13

H7
H11
A9
A14

PD#0
PD#1
PD#2
PD#3
PD#4
PD#5
PD#6
PD#7
PD#8
PD#9
PD#10
PD#11
PD#12
PD#13
PD#14
PD#15
PD#16
PD#17
PD#18
PD#19
PD#20
PD#21
PD#22
PD#23
PD#24
PD#25
PD#26
PD#27
PD#28
PD#29
PD#30
PD#31
PD#32
PD#33
PD#34
PD#35
PD#36
PD#37
PD#38
PD#39
PD#40
PD#41
PD#42
PD#43
PD#44
PD#45
PD#46
PD#47
PD#48
PD#49
PD#50
PD#51
PD#52
PD#53
PD#54
PD#55
PD#56
PD#57
PD#58
PD#59
PD#60
PD#61
PD#62
PD#63

DINV#0
DINV#1
DINV#2
DINV#3

DP#0
DP#1
DP#2
DP#3

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

C120
104P

GTL_VREF_CMIC

C117

105P

C122

C121

104P

104P

C118
104P

C123
104P

C119
104P

C124
104P

VCC_P

VCC25

VCC25

R126

49.9RST

R127
100RST

C126
104P

C128
105P

VCC25

CMIC_LE

U6A

12

+

EC6
820U/4V

B

C136
105P

C137
102P

C138
102P

C

D

Micro Star Restricted Secret

Title
Document Number

CMIC Foster Interface

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

12 73

E

of

Rev

0A

PA#[3..35]<4,6>

PD#[0..63]<4,6>

DINV#[0..3]<4,6>

DP#[0..3]<4,6>
DSTBN#[0..3]<4,6>
DSTBP#[0..3]<4,6>

4 4

3 3

PCIRST_X#<60>

2 2

R129

VCC25

R130

VCC25

R131

VCC25

R132

VCC_P

VCC25

VCC25

R133

R134 250RST
R135 250RST
R136 20.5RST

*** Difference
with Rev:A1.0 Ckt

A

1 1

R128

C134
22P

4.7K

10K

4.7K

4.7K

4.7K

A

B_IMB_D_R[0..15]<27>

B_IMB_D_T[0..15]<27>

A_IMB_D_R[0..15]<25>

A_IMB_D_T[0..15]<25>

T_IMB_D_R[0..3]<31,42>

T_IMB_D_T[0..3]<31,42>

4 4

3 3

T_IMB_CLK_T<31,42>

T_IMB_CON_T<31,42>

T_IMB_PAR_T<31,42>

T_IMB_D_T0
T_IMB_D_T1

T_IMB_D_T3

B_IMB_D_R[0..15]
B_IMB_D_T[0..15]

A_IMB_D_R[0..15]
A_IMB_D_T[0..15]

T_IMB_D_R[0..3]
T_IMB_D_T[0..3]

B_IMB_CON_R<27>
B_IMB_CLK_R_P<27>
B_IMB_CLK_R_N<27>

B_IMB_PAR_R<27>

B_IMB_CON_T<27>

B_IMB_CLK_T_P_R<27>
B_IMB_CLK_T_N_R<27>

B_IMB_PAR_T<27>

R137 24
R138 24
R139 24
R140 24

R141 24
R142 24
R143 24

IMB_VREF_CMIC

B

B_IMB_D_R0
B_IMB_D_R1
B_IMB_D_R2
B_IMB_D_R3
B_IMB_D_R4
B_IMB_D_R5
B_IMB_D_R6
B_IMB_D_R7
B_IMB_D_R8
B_IMB_D_R9
B_IMB_D_R10
B_IMB_D_R11
B_IMB_D_R12
B_IMB_D_R13
B_IMB_D_R14
B_IMB_D_R15

B_IMB_D_T0
B_IMB_D_T1
B_IMB_D_T2
B_IMB_D_T3
B_IMB_D_T4
B_IMB_D_T5
B_IMB_D_T6
B_IMB_D_T7
B_IMB_D_T8
B_IMB_D_T9
B_IMB_D_T10
B_IMB_D_T11
B_IMB_D_T12
B_IMB_D_T13
B_IMB_D_T14
B_IMB_D_T15

R_TIMB_D_T0
R_TIMB_D_T1
R_TIMB_D_T2T_IMB_D_T2
R_TIMB_D_T3

R_TIMB_CLKT
R_TIMB_CONT
R_TIMB_PART

IMB_VREF_CMIC

CMIC_IMB_COMP_PD
CMIC_IMB_COMP_PU
CMIC_IMB_RCOMP

C

U6B

R25

BIMBD_R0

T23

B IMBD_R1

R26

BIMBD_R2

R27

BIMBD_R3

R22

BIMBD_R4

P23

BIMBD_R5

R24

BIMBD_R6

R23

BIMBD_R7

N25

BIMBD_R8

N22

BIMBD_R9

P21

BIMBD_R10

N23

BIMBD_R11

N24

BIMBD_R12

P20

BIMBD_R13

R18

BIMBD_R14

R17

BIMBD_R15

N20

BIMBCON_R

P25

BIMBCLK_R_P

P27

BIMBCLK_R_N

N21

BMBPAR_R

U21

BIMBD_T0

U23

BIMBD_T1

T20

BIMBD_T2

U18

BIMBD_T3

U17

BIMBD_T4

V20

BIMBD_T5

U20

BIMBD_T6

T22

BIMBD_T7

T21

BIMBD_T8

R21

BIMBD_T9

T25

BIMBD_T10

U27

BIMBD_T11

T24

BIMBD_T12

U25

BIMBD_T13

T27

BIMBD_T14

T26

BIMBD_T15

R20

BIMBCON_T

W26 L25

BIMBCLK_T_P AIMBCLK_T_P

W27

BIMBCLK_T_N

V27

BIMBDPAR_T

Y22

T_IMBD_T0

AA25

T_IMBD_T1

Y21

T_IMBD_T2

Y24

T_IMBD_T3

P18

IMB_VREF

D27

IMB_COMP_PD

H21

IMB_COMP_PU

G22

IMB_RCOMP

AIMBD_R0
AIMBD_R1
AIMBD_R2
AIMBD_R3
AIMBD_R4
AIMBD_R5
AIMBD_R6
AIMBD_R7
AIMBD_R8

AIMBD_R9
AIMBD_R10
AIMBD_R11
AIMBD_R12
AIMBD_R13
AIMBD_R14
AIMBD_R15

AIMBCON_R
AIMBCLK_R_P
AIMBCLK_R_N

AIMBPAR_R

AIMBD_T0
AIMBD_T1
AIMBD_T2
AIMBD_T3
AIMBD_T4
AIMBD_T5
AIMBD_T6
AIMBD_T7
AIMBD_T8

AIMBD_T9
AIMBD_T10
AIMBD_T11
AIMBD_T12
AIMBD_T13
AIMBD_T14
AIMBD_T15

AIMBCON_T

AIMBCLK_T_N

AIMBPAR_T

T_IMBD_R0
T_IMBD_R1
T_IMBD_R2
T_IMBD_R3

T_IMBCLK_RT_IMBCLK_T

T_IMBCON_RT_IMBCON_T

T_IMBPAR_RT_IMBPAR_T

CPURST#
SRESET#

TESTMODE#

SDA

SCLK

D

A_IMB_D_R0

L20

A_IMB_D_R1

L17

A_IMB_D_R2

L18

A_IMB_D_R3

K20

A_IMB_D_R4

J24

A_IMB_D_R5

H23

A_IMB_D_R6

H22

A_IMB_D_R7

J22

A_IMB_D_R8

H26

A_IMB_D_R9

F27

A_IMB_D_R10

G24

A_IMB_D_R11

G27

A_IMB_D_R12

G25

A_IMB_D_R13

E27

A_IMB_D_R14

F24

A_IMB_D_R15

J20
F25

H25
H24
F26

A_IMB_D_T0

M26

A_IMB_D_T1

M25

A_IMB_D_T2

N27

A_IMB_D_T3

N18

A_IMB_D_T4

N17

A_IMB_D_T5

M24

A_IMB_D_T6

N26

A_IMB_D_T7

L27

A_IMB_D_T8

M27

A_IMB_D_T9

L21

A_IMB_D_T10

M22

A_IMB_D_T11

H27

A_IMB_D_T12

J27

A_IMB_D_T13

K27

A_IMB_D_T14

J26

A_IMB_D_T15

M21
M20
M23

L23

T_IMB_D_R0

Y26

T_IMB_D_R1

W24

T_IMB_D_R2

AA26

T_IMB_D_R3

W22
Y27AA24

AA27AA23
W20AB25

C27
AF25
AD26

AE23
AG23

R144 1K

A_IMB_CON_R <25>
A_IMB_CLK_R_P <25>
A_IMB_CLK_R_N <25>
A_IMB_PAR_R <25>

A_IMB_CON_T <25>
A_IMB_CLK_T_P_R <25>
A_IMB_CLK_T_N_R <25>
A_IMB_PAR_T <25>

T_IMB_CLK_R <31,42>
T_IMB_CON_R <31,42>
T_IMB_PAR_R <31,42>

PROC_RESET# <4,6,9,11>
POWERGOOD_CMIC <16,55>

VCC25

TESTMODE# <16>
RCC_SDA <16,25,27,54,59>
RCC_SCL <16,25,27,54,59>

E

CMIC_LE

2 2

VDD_IMB

R146 250RST
R147 100RST
R148 250RST

*** Difference with
Rev:A1.0 Ckt

1 1

A

CMIC_IMB_COMP_PD
CMIC_IMB_RCOMP
CMIC_IMB_COMP_PU

IMB_VREF_CMIC

B

IMB_VREF_CMIC

C145

105P

C146
104P

VDD_IMB

R145
100RST

C147

R149

102P

100RST

Micro Star Restricted Secret

Title

CMIC IMB Interface

Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

C

D

http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

E

13 73

of

Rev

0A

A

R_A_SD0_0
R_A_SD0_1
R_A_SD0_2
R_A_SD0_3
R_A_SD0_4

4 4

3 3

2 2

1 1

A

R_A_SD0_5
R_A_SD0_6
R_A_SD0_7

R_A_SD1_0
R_A_SD1_1
R_A_SD1_2
R_A_SD1_3
R_A_SD1_4
R_A_SD1_5
R_A_SD1_6
R_A_SD1_7

R_A_SD2_0
R_A_SD2_1
R_A_SD2_2
R_A_SD2_3
R_A_SD2_4
R_A_SD2_5
R_A_SD2_6
R_A_SD2_7

R_A_SD3_0
R_A_SD3_1
R_A_SD3_2
R_A_SD3_3
R_A_SD3_4
R_A_SD3_5
R_A_SD3_6
R_A_SD3_7

R_A_SD4_0
R_A_SD4_1
R_A_SD4_2
R_A_SD4_3
R_A_SD4_4
R_A_SD4_5
R_A_SD4_6
R_A_SD4_7

R_A_SD5_0
R_A_SD5_1
R_A_SD5_2
R_A_SD5_3
R_A_SD5_4
R_A_SD5_5
R_A_SD5_6
R_A_SD5_7

R_A_SD6_0
R_A_SD6_1
R_A_SD6_2
R_A_SD6_3
R_A_SD6_4
R_A_SD6_5
R_A_SD6_6
R_A_SD6_7

R_A_SD7_0
R_A_SD7_1
R_A_SD7_2
R_A_SD7_3
R_A_SD7_4
R_A_SD7_5
R_A_SD7_6
R_A_SD7_7

R_A_SD8_0
R_A_SD8_1
R_A_SD8_2
R_A_SD8_3
R_A_SD8_4
R_A_SD8_5
R_A_SD8_6
R_A_SD8_7

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11

MA12
MA13
MA14

CMIC_LE

B

R_A_DQS0_0

R_A_DQS0_1

R_A_DQS1_0

R_A_DQS1_1

R_A_DQS2_0

R_A_DQS2_1

R_A_DQS3_0

R_A_DQS3_1

R_A_DQS4_0

R_A_DQS4_1

R_A_DQS5_0

R_A_DQS5_1

R_A_DQS6_0

R_A_DQS6_1

R_A_DQS7_0

R_A_DQS7_1

R_A_DQS8_0

R_A_DQS8_1

U6C

AC20

AG20

AB13

AE9Y2T4

AC13

AF8W1P7N7H3

A_DQS3_0

A_DQS4_0

A_DQS5_0

A_DQS2_1

A_DQS3_1

A_DQS4_1

B_DQS2_0

B_DQS3_0

B_DQS4_0

B_DQS2_1

B_DQS3_1

B_DQS4_1

AE15

AG11

AA4P1R10L4AC9

AD15

AG10Y5P3U2M7

R_B_DQS2_0

R_B_DQS2_1

R_B_DQS3_0

R_B_DQS3_1

R_B_DQS4_0

R_B_DQS4_1

N10H4Y11

A_DQS6_0

A_DQS5_1

B_DQS5_0

B_DQS5_1

R_B_DQS5_0

R_B_DQS5_1

R_B_DQS6_0

A_DQS7_0

A_DQS6_1

A_DQS7_1

B_DQS6_0

B_DQS7_0

B_DQS6_1

R_B_DQS6_1

R_B_DQS7_0

R_B_DQS7_1

V11

A_DQS8_0

A_DQS8_1

B_DQS8_0

B_DQS7_1

B_DQS8_1

AF6

R_B_DQS8_0

R_B_DQS8_1

AD20

AA22

A_SD0_0

AD22

A_SD0_1

AC19

A_SD0_2

AA18

A_SD0_3

AB23

A_SD0_4

AB19

A_SD0_5

AD19

A_SD0_6

Y16

A_SD0_7

V15

A_SD1_0

AG22

A_SD1_1

AB15

A_SD1_2

AD16

A_SD1_3

AG21

A_SD1_4

AF19

A_SD1_5

AG17

A_SD1_6

AB16

A_SD1_7

AG14

A_SD2_0

Y14

A_SD2_1

AF13

A_SD2_2

AG12

A_SD2_3

AE14

A_SD2_4

V14

A_SD2_5

AG13

A_SD2_6

AE13

A_SD2_7

Y13

A_SD3_0

AF9

A_SD3_1

AE8

A_SD3_2

AD10

A_SD3_3

AA12

A_SD3_4

AG8

A_SD3_5

AG6

A_SD3_6

AG5

A_SD3_7

T10

A_SD4_0

Y4

A_SD4_1

R11

A_SD4_2

T7

A_SD4_3

W5

A_SD4_4

Y3

A_SD4_5

U6

A_SD4_6

U1

A_SD4_7

T3

A_SD5_0

R2

A_SD5_1

R4

A_SD5_2

R5

A_SD5_3

T5

A_SD5_4

R1

A_SD5_5

K8

A_SD5_6

R6

A_SD5_7

N3

A_SD6_0

N1

A_SD6_1

M2

A_SD6_2

M4

A_SD6_3

N8

A_SD6_4

N4

A_SD6_5

L1

A_SD6_6

M3

A_SD6_7

H1

A_SD7_0

H2

A_SD7_1

L6

A_SD7_2

M10

A_SD7_3

J5

A_SD7_4

J3

A_SD7_5

L8

A_SD7_6

K10

A_SD7_7

AF3

A_SD8_0

AG2

A_SD8_1

AB10

A_SD8_2

AA9

A_SD8_3

AE6

A_SD8_4

AF5

A_SD8_5

AC8

A_SD8_6

AB9

A_SD8_7

AD5

MA0

AE5

MA1

Y10

MA2

AA8

MA3

Y9

MA4

Y7

MA5

AF1

MA6

AE2

MA7

AD3

MA8

AE3

MA9

AF2

MA10

Y8

MA11

AG19

A_DQS0_0

A_DQS1_0

A_DQS2_0

A_DQS0_1

A_DQS1_1

B_DQS0_0

B_DQS1_0

B_DQS0_1

B_DQS1_1

MA12

MA13

MA14

AA20

AF20

AB21

AE19

V10

AA7

AB6

R_B_DQS0_0

R_B_DQS0_1

R_B_DQS1_0

R_B_DQS1_1

B

C

R_B_SD0_0

Y20

B_SD0_0
B_SD0_1
B_SD0_2
B_SD0_3
B_SD0_4
B_SD0_5
B_SD0_6
B_SD0_7

B_SD1_0
B_SD1_1
B_SD1_2
B_SD1_3
B_SD1_4
B_SD1_5
B_SD1_6
B_SD1_7

B_SD2_0
B_SD2_1
B_SD2_2
B_SD2_3
B_SD2_4
B_SD2_5
B_SD2_6
B_SD2_7

B_SD3_0
B_SD3_1
B_SD3_2
B_SD3_3
B_SD3_4
B_SD3_5
B_SD3_6
B_SD3_7

B_SD4_0
B_SD4_1
B_SD4_2
B_SD4_3
B_SD4_4
B_SD4_5
B_SD4_6
B_SD4_7

B_SD5_0
B_SD5_1
B_SD5_2
B_SD5_3
B_SD5_4
B_SD5_5
B_SD5_6
B_SD5_7

B_SD6_0
B_SD6_1
B_SD6_2
B_SD6_3
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_7

B_SD7_0
B_SD7_1
B_SD7_2
B_SD7_3
B_SD7_4
B_SD7_5
B_SD7_6
B_SD7_7

B_SD8_0
B_SD8_1
B_SD8_2
B_SD8_3
B_SD8_4
B_SD8_5
B_SD8_6
B_SD8_7

CS7

CS6

Y6

AA6

1

TP5

1

TP6

A_CKE
B_CKE

R_B_SD0_1

AA21

R_B_SD0_2

AA19

R_B_SD0_3

V17

R_B_SD0_4

V18

R_B_SD0_5

Y19

R_B_SD0_6

AB20

R_B_SD0_7

Y18

R_B_SD1_0

AF22

R_B_SD1_1

AE21

R_B_SD1_2

Y17

R_B_SD1_3

V16

R_B_SD1_4

AE22

R_B_SD1_5

AE20

R_B_SD1_6

AC18

R_B_SD1_7

AE18

R_B_SD2_0

AF16

R_B_SD2_1

AF15

R_B_SD2_2

AC15

R_B_SD2_3

AB14

R_B_SD2_4

AG16

R_B_SD2_5

AG15

R_B_SD2_6

AD14

R_B_SD2_7

Y15

R_B_SD3_0

AA13

R_B_SD3_1

AD13

R_B_SD3_2

AC12

R_B_SD3_3

AG9

R_B_SD3_4

V13

R_B_SD3_5

AE12

R_B_SD3_6

AF10

R_B_SD3_7

AG7

R_B_SD4_0

AB4

R_B_SD4_1

AB2

R_B_SD4_2

AA1

R_B_SD4_3

T8

R_B_SD4_4

AA3

R_B_SD4_5

AA2

R_B_SD4_6

Y1

R_B_SD4_7

AA5

R_B_SD5_0

P8

R_B_SD5_1

R3

R_B_SD5_2

P5

R_B_SD5_3

J8

R_B_SD5_4

P10

R_B_SD5_5

N2

R_B_SD5_6

N5

R_B_SD5_7

N6

R_B_SD6_0

W3

R_B_SD6_1

V1

R_B_SD6_2

T2

R_B_SD6_3

T1

R_B_SD6_4

T6

R_B_SD6_5

U4

R_B_SD6_6

R7

R_B_SD6_7

R8

R_B_SD7_0

M1

R_B_SD7_1

J1

R_B_SD7_2

M5

R_B_SD7_3

L10

R_B_SD7_4

K1

R_B_SD7_5

L2

R_B_SD7_6

M6

R_B_SD7_7

M8

R_B_SD8_0

AD9

R_B_SD8_1

AD8

R_B_SD8_2

AG4

R_B_SD8_3

AD7

R_B_SD8_4

V12

R_B_SD8_5

Y12

R_B_SD8_6

AE7

R_B_SD8_7

AG3

WE#

AB1

WE#

RAS#

AC1

RAS#

CAS#

W8

CAS#

A_CKE

AB8

B_CKE

AE4

R_CS_0

U8

CS0

R_CS_1

U10

CS1

R_CS_2

W7

CS2

R_CS_3

V8

CS3

AE1

CS4

AD1

CS5

C

1

TP3

1

TP4

CS_0

R15039.2RST

CS_1

R15139.2RST

CS_2

R15239.2RST

CS_3

R15339.2RST

CS_0 <17,18>
CS_1 <17,18>
CS_2 <17,18>
CS_3 <17,18>

D

R_B_SD0_[0..7]<19>
R_B_SD1_[0..7]<19>
R_B_SD2_[0..7]<19>
R_B_SD3_[0..7]<19>
R_B_SD4_[0..7]<19>
R_B_SD5_[0..7]<19>
R_B_SD6_[0..7]<19>
R_B_SD7_[0..7]<19>
R_B_SD8_[0..7]<19>

R_B_DQS0_[0..1]<19>
R_B_DQS1_[0..1]<19>
R_B_DQS2_[0..1]<19>
R_B_DQS3_[0..1]<19>
R_B_DQS4_[0..1]<19>
R_B_DQS5_[0..1]<19>
R_B_DQS6_[0..1]<19>
R_B_DQS7_[0..1]<19>
R_B_DQS8_[0..1]<19>

R_A_SD0_[0..7]<19>
R_A_SD1_[0..7]<19>
R_A_SD2_[0..7]<19>
R_A_SD3_[0..7]<19>
R_A_SD4_[0..7]<19>
R_A_SD5_[0..7]<19>
R_A_SD6_[0..7]<19>
R_A_SD7_[0..7]<19>
R_A_SD8_[0..7]<19>

R_A_DQS0_[0..1]<19>
R_A_DQS1_[0..1]<19>
R_A_DQS2_[0..1]<19>
R_A_DQS3_[0..1]<19>
R_A_DQS4_[0..1]<19>
R_A_DQS5_[0..1]<19>
R_A_DQS6_[0..1]<19>
R_A_DQS7_[0..1]<19>
R_A_DQS8_[0..1]<19>

MA[0..14]<17,18,19>

A_CKE<17,19>
B_CKE<18,19>

WE#<17,18,19>
RAS#<17,18,19>
CAS#<17,18,19>

Micro Star Restricted Secret

Title

CMIC DDR Interface

Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

D

http://www.msi.com.tw

R_B_SD0_[0..7]
R_B_SD1_[0..7]
R_B_SD2_[0..7]
R_B_SD3_[0..7]
R_B_SD4_[0..7]
R_B_SD5_[0..7]
R_B_SD6_[0..7]
R_B_SD7_[0..7]
R_B_SD8_[0..7]

R_B_DQS0_[0..1]
R_B_DQS1_[0..1]
R_B_DQS2_[0..1]
R_B_DQS3_[0..1]
R_B_DQS4_[0..1]
R_B_DQS5_[0..1]
R_B_DQS6_[0..1]
R_B_DQS7_[0..1]
R_B_DQS8_[0..1]

R_A_SD0_[0..7]
R_A_SD1_[0..7]
R_A_SD2_[0..7]
R_A_SD3_[0..7]
R_A_SD4_[0..7]
R_A_SD5_[0..7]
R_A_SD6_[0..7]
R_A_SD7_[0..7]
R_A_SD8_[0..7]

R_A_DQS0_[0..1]
R_A_DQS1_[0..1]
R_A_DQS2_[0..1]
R_A_DQS3_[0..1]
R_A_DQS4_[0..1]
R_A_DQS5_[0..1]
R_A_DQS6_[0..1]
R_A_DQS7_[0..1]
R_A_DQS8_[0..1]

MA[0..14]
A_CKE
B_CKE
WE#
RAS#
CAS#

E

Last Revision Date:

Wednesday, May 09, 2001

Sheet

14 73

E

Rev

0A

of

A

B

C

D

E

AVDD
AGNDVDD_2.5

RSVD

AB12
AB11
AB7
AB5
AB3
AC26
AC24
AC22
AC17
AC16
AC14
AC7
AC5
AC3
AD12
AD11
AE17
AE16
AF24
AF21
AF12
AF11
AF4

E26
G23
K19
K22
K24
K26
L22
L24
L26
M17
M19
P17
P19
P24
T17
T19
U22
U24
U26
V19
V24
V26

AB27
AC27T16
U9

W17
AG18

AD24
U19

VCC25

VDD_IMB

CMIC_AVDD

MEM_VREF_CMIC
CMIC_DCOMP

CMIC_RSVD
MEM_VREF_CMIC

MEM_VREF_CMIC

CMIC_RSVD <16>

MEM_VREF_CMIC

VCC_P

VCC_P

U6D

V23

GND91

V25

GND92

W9

GND93

W11

GND94

W13

GND95

W15

GND96

W19

GND98

W21

GND99

W23

GND100

W25

GND102

AA10

GND103

AA11

GND104

AA14

GND105

AB17

GND106

AB18

GND107

AC2

GND108

AC4

GND109

AC6

GND110

AC10

GND111

AC11

GND112

AC21

GND113

AC23

GND114

AC25

GND115

AD2

GND116

AD4

GND117

AD6

GND118

AD17

GND119

AD18

GND120

AD21

GND121

AD23

GND122

AD25

GND123

AE10

GND124

AE11

GND125

AF7

GND126

AF14

GND127

AF17

GND128

AF18

GND129

AG1

GND130

AG27

GND131

V5

GND133

V7

GND135

R12

GND72

R14

GND73

R16

GND74

R19

GND75

T11

GND76

T13

GND77

T15

GND78

T18

GND79

U3

GND80

U5

GND81

U7

GND83

U12

GND85

U14

GND86

U16

GND87

V3

GND89

V21

GND90

P6

GND65

P11

GND66

P13

GND67

P15

GND68

P22

GND69

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND71
GND70

GND136
GND137GND139

A1
A27
B5
B6
B10
B11
B14
C17
C18
C25
D5
D6
D10
D11
D14
D21
D23
K16
E2
E17
E18
E22
E24
F10
F11
F14
G7
G17
G18
G26
J2
J4
J6
J9
J11
J13
J15
J17
J19
J21
J23
J25
K2
K4
K6
K21
K23
K25
L9
L12
L14
L16
L19
M11
M13
M15
M18
N9
N12
N14
N16
N19
P2
R9
P26
AA17
D25J7

VCC25

R154

2

MEM_VREF_CMIC

C149

102P

CMIC_DCOMP

L5

1 2

47UH/1206

+

MEM_VREF_CMIC

C151

C150

104P

104P

R157 250RST

GND_SIGNAL

GND SIGNAL

EC8
10U/16V/S

CMIC_AVDD

C148
105P

VCC25

R155
100RST

C152

R156

105P

100RST

VCC25

GND

CMIC_LE

VCC_P

C156
105P

C158

C157

105P

105P

12

+

EC9
820U/4V

C159
105P

VCC25

SC1
104P

Put on Solder Side

SC2
104P

SC4

SC3

103P

103P

VCC_P

4 4

3 3

VCC25

2 2

VDD_IMB

U6E

B2

VTT

B8

VTT

B16

VTT

B17

VTT

B22

VTT

B24

VTT

C4

VTT

C5

VTT

C11

VTT

C12

VTT

C21

VTT

C23

VTT

D16

VTT

D17

VTT

D26

VTT

E4

VTT

E5

VTT

E8

VTT

E11

VTT

E12

VTT

F16

VTT

F17

VTT

G4

VTT

G11

VTT

G12

VTT

G20

VTT

J10

VTT

J12

VTT

J14

VTT

J16

VTT

J18

VTT

K9

VDD_2.5

K7

VDD_2.5

K5

VDD_2.5

K3

VDD_2.5

L15

VDD_2.5

L13

VDD_2.5

L11

VDD_2.5

L7

VDD_2.5

L5

VDD_2.5

L3

VDD_2.5

M16

VDD_2.5

M14

VDD_2.5

M12

VDD_2.5

M9

VDD_2.5

N15

VDD_2.5

N13

VDD_2.5

N11

VDD_2.5

P16

VDD_2.5

P14

VDD_2.5

P12

VDD_2.5

P9

VDD_2.5

P4

VDD_2.5

R15

VDD_2.5

R13

VDD_2.5

T14

VDD_2.5

T12

VDD_2.5

T9

VDD_2.5

U15

VDD_2.5

U13

VDD_2.5

U11

VDD_2.5

V22

VDD_2.5

V9

VDD_2.5

V6

VDD_2.5

V4

VDD_2.5

V2

VDD_2.5

W18

VDD_2.5

W16

VDD_2.5

W14

VDD_2.5

W12

VDD_2.5

W10

VDD_2.5

W6

VDD_2.5

W4

VDD_2.5

W2

VDD_2.5

Y25

VDD_2.5

Y23

VDD_2.5

AA16

VDD_2.5

AA15

VDD_2.5

AB26

VDD_2.5

AB24

VDD_2.5

AB22

VDD_2.5

VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5
VDD_2.5

VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB
VDD_IMB

MEM_VREF
MEM_VREF

DCOMP

T_IMB_VREF

CMIC_LE

C160

C165

102P

1 1

VDD_IMB

SC9
103P

C167

104P

104P

SC12

SC11

SC10
103P

104P

104P

SC5

SC6

104P

104P

Put on Solder Side

Put on Solder Side

A

B

C

SC8

SC7

103P

103P

Micro Star Restricted Secret

Title

CMIC Power

Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

D

http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

E

15 73

of

Rev

0A

A

B

C

D

E

VCC25

4 4

COMPATIBILITY IMB

1: A_IMB is Compatibility Bus
0: Thin IMB is Compatibility
Bus ( Default )

3 3

JP3

YJ102

DEFER ENABLE/DISABLE

2 2

OFF: Defer Enabled ( Default )
ON: Defer Disabled

2
1

JP2

YJ102

2
1

VCC25

R159

2.2K

COMP_IMB

R161

2.2K

CMIC_DEFER_EN

R166
1K

VCC25

R164

8.2K

CMIC_PLL_EN#
CMIC_DEFER_EN
COMP_IMB
IOQ_DEPTH

IMB_TRAINING
IMB_CRC_PARITY ALERT#
IMB_R_W_PTR_DLY TESTMODE#

POWERGOOD_CMIC<13,55>

VCC25

R163

2.2K

CPURST#_DEASS

R168
X_2.2K

Do not stuff

CPURST# DEASSERTION

0 : Deassert CPURST# with SRESET#
1 : Deassert CPURST# after 1ms of SRESET# (Default )

U7

2

1A1

4

1A2

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

74LVC244A

TSSOP-20

C183
104P

CMIC_FATAL#

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

VDD
GND

18
16
14
12
9
7
5
3

20
10

WRMRST#
MEMOFF#
MEMOFFACK#
RCC_SCLDETERMINISTIC_IMB
RCC_SDA

VCC25

R165

2.2K

IMB_CRC_PARITY

R169
X_2.2K

Do not stuff

VCC25

CMIC_FATAL# <12,42>
WRMRST# <12>
MEMOFF# <12,41>
MEMOFFACK# <12>
RCC_SCL <13,25,27,54,59>
RCC_SDA <13,25,27,54,59>
ALERT# <12,25,27,42>
TESTMODE# <13>

A/B_IMB CRC or PARITY

0 : PARITY is enabled for A & B IMB buses (Default )
1 : CRC is enabled for A & B IMB buses

IMB_READ/WRITE POINTER DLY

1 : 5 CLOCKs
0 : 6 CLOCKs

VCC25

IMB - DETERMINISTIC/ NON
DETERMINISTIC

0 : Deterministic IMB
1 : Non Deterministic IMB (Default )

VCC25

R162

2.2K

DETERMINISTIC_IMB

R167
X_2.2K

Do not stuff

R158

2.2K

IMB_R_W_PTR_DLY

R160
X_2.2K

Do not stuff

( Default )

( In final version Use CRC on IMB buses )

VCC25

R172
X_2.2K

DO NOT STUFF

CMIC_PLL_EN#

R175

CMIC PLL ENABLE/DISABLE

2.2K

1 1

1: APLL Disabled
0: APLL Enabled ( Default )

JP4

YJ102

2
1

IOQ_DEPTH

R176
1K

VCC25

R173

8.2K

IOQ DEPTH

OFF: IOQ Depth 1
ON: IOQ Depth
12 ( Default )

A

B

VCC25

R171

2.2K

IMB_TRAINING

R177
X_2.2K

Do not stuff

IMB_TRAINING

0 : IMB TRAINING Disabled
1 : IMB TRAINING Enabled
( Default )

C

D

Thin IMB FREQ.

1 = 100 MHz 2X
0 = 200 MHz 2X

CMIC_RSVD<15>

Micro Star Restricted Secret

Title
Document Number

CMIC Strapping Option

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

CMIC_RSVD

VCC25

R170

2.2K

R174

X_2.2K

Do not stuff

Last Revision Date:

Wednesday, May 09, 2001

Sheet

16 73

E

of

Rev

0A

A

B

C

D

E

11

665850

93

4234267418

89

81

MA0

48

A0

GND

GND

GND

GND

GND

GND

GND

GND

GND

MA1
MA2
MA3
MA4
MA5
MA6
MA7

4 4

MEMB_SCL<23,59>

3 3

2 2

MEMB_SDA<23,59>

R179 330

VCC25

R181 4.7K

R182 4.7K

MA8
MA9
MA10
MA11
MA12

MA13
MA14

CS_0

CS_0<14,18> CS_2<14,18>

CS_1 CS_3

CS_1<14,18>

RAS#
CAS#
WE#

CLK0_P<23>

CLK0_N<23>

A_CKE

SSTLREF_D1 SSTLREF_D1

VCC25

MEMB_SCL
MEMB_SDA

DIMM_WP#1 DIMM_WP#2
DIMM_RST#

DIMM_WP#1

DIMM_WP#2

VCC25 VCC25

GND

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS0_

158

CS1_

154

RAS_

65

CAS_

63

WE_

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

182

SA1

183

SA2

90

WP

10

RESET_

102 56

NC1 DQS4

101

NC2

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

75

CLK2_N_DU

76

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD

148

VDD

120

VDD

108

VDD

85

VDD

70

VDD

46

VDD

38

VDD

7

VDD

136

VDDQ

180

VDDQ

156

VDDQ

112

VDDQ

164

VDDQ

143

VDDQ

128

VDDQ

104

VDDQ

96

VDDQ

172

VDDQ

77

VDDQ

62

VDDQ

54

VDDQ

30

VDDQ

22

VDDQ

15

VDDQ

GND

GND

I2C ADD. - 0

Pair 0

A_SD0_[0..7]<19,20>
A_SD1_[0..7]<19,20>
A_SD2_[0..7]<19,20>
A_SD3_[0..7]<19,20>
A_SD4_[0..7]<19,20>
A_SD5_[0..7]<19,20>

1 1

A

A_SD6_[0..7]<19,20>
A_SD7_[0..7]<19,20>
A_SD8_[0..7]<19,20>

A_DQS0_[0..1]<19,20>
A_DQS1_[0..1]<19,20>
A_DQS2_[0..1]<19,20>
A_DQS3_[0..1]<19,20>
A_DQS4_[0..1]<19,20>
A_DQS5_[0..1]<19,20>
A_DQS6_[0..1]<19,20>
A_DQS7_[0..1]<19,20>
A_DQS8_[0..1]<19,20>

132

124

116

100

GND

GND

GND

A_SD0_[0..7]
A_SD1_[0..7]
A_SD2_[0..7]
A_SD3_[0..7]
A_SD4_[0..7]
A_SD5_[0..7]
A_SD6_[0..7]
A_SD7_[0..7]
A_SD8_[0..7]

A_DQS0_[0..1]
A_DQS1_[0..1]
A_DQS2_[0..1]
A_DQS3_[0..1]
A_DQS4_[0..1]
A_DQS5_[0..1]
A_DQS6_[0..1]
A_DQS7_[0..1]
A_DQS8_[0..1]

3

139

145

160

176

152

DIMM1

GND

GND

GND

GND

GND

GND

B

GND

DM0_DQS9

DM1_DQS10

DM2_DQS11

DM3_DQS12

DM4_DQS13

DM5_DQS14

DM6_DQS15

DM7_DQS16

DM9_DQS17

DQS0

DQS1

DQS2

DQS3

DQS5

DQS6

DQS7

ECC0
ECC1
ECC2
ECC3
DQS8

ECC4
ECC5
ECC6
ECC7

A_SD0_0

2

D0

A_SD0_1

4

D1

A_SD0_2

6

D2

A_SD0_3

8

D3

A_DQS0_0

5

A_DQS0_1

97

A_SD0_4

94

D4

A_SD0_5

95

D5

A_SD0_6

98

D6

A_SD0_7

99

D7

A_SD1_0

12

D8

A_SD1_1

13

D9

A_SD1_2

19

D10

A_SD1_3

20

D11

A_DQS1_0

14

A_DQS1_1

107

A_SD1_4

105

D12

A_SD1_5

106

D13

A_SD1_6

109

D14

A_SD1_7

110

D15

A_SD2_0

23

D16

A_SD2_1

24

D17

A_SD2_2

28

D18

A_SD2_3

31

D19

A_DQS2_0

25

A_DQS2_1

119

A_SD2_4

114

D20

A_SD2_5

117

D21

A_SD2_6

121

D22

A_SD2_7

123

D23

A_SD3_0

33

D24

A_SD3_1

35

D25

A_SD3_2

39

D26

A_SD3_3

40

D27

A_DQS3_0

36

A_DQS3_1

129

A_SD3_4

126

D28

A_SD3_5

127

D29

A_SD3_6

131

D30

A_SD3_7

133

D31

A_SD4_0

53

D32

A_SD4_1

55

D33

A_SD4_2

57

D34

A_SD4_3

60

D35

A_DQS4_0
A_DQS4_1

149

A_SD4_4

146

D36

A_SD4_5

147

D37

A_SD4_6

150

D38

A_SD4_7

151

D39

A_SD5_0

61

D40

A_SD5_1

64

D41

A_SD5_2

68

D42

A_SD5_3

69

D43

A_DQS5_0

67

A_DQS5_1

159

A_SD5_4

153

D44

A_SD5_5

155

D45

A_SD5_6

161

D46

A_SD5_7

162

D47

A_SD6_0

72

D48

A_SD6_1

73

D49

A_SD6_2

79

D50

A_SD6_3

80

D51

A_DQS6_0

78

A_DQS6_1

169

A_SD6_4

165

D52

A_SD6_5

166

D53

A_SD6_6

170

D54

A_SD6_7

171

D55

A_SD7_0

83

D56

A_SD7_1

84

D57

A_SD7_2

87

D58

A_SD7_3

88

D59

A_DQS7_0

86

A_DQS7_1

177

A_SD7_4

174

D60

A_SD7_5

175

D61

A_SD7_6

178

D62

A_SD7_7

179

D63

A_SD8_0

44

A_SD8_1

45

A_SD8_2

49

A_SD8_3

51

A_DQS8_0

47

A_DQS8_1

140

A_SD8_4

134

A_SD8_5

135

A_SD8_6

142

A_SD8_7

144

VCC25

CS_3<14,18>

CLK1_P<23>
CLK1_N<23>

A_CKE

VCC25

MEMB_SCL
MEMB_SDA

R178 330

R180 4.7K

DIMM_RST#

MA[0..14]<14,18,19>

A_CKE<14,19>

WE#<14,18,19>
RAS#<14,18,19>
CAS#<14,18,19>

DIMM_WP#2<18>
DIMM_WP#1<18>
DIMM_RST#<18,60>

C

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12

MA13
MA14

CS_2

RAS#
CAS#
WE#

DIMM_WP#2
DIMM_WP#1
DIMM_RST#

11

665850

4234267418

48

A0

GND

GND

GND

GND

GND

GND

GND

GND

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS0_

158

CS1_

154

RAS_

65

CAS_

63

WE_

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

I2C ADD. - 2

182

SA1

183

SA2

90

WP

10

RESET_

102 56

NC1 DQS4

101

NC2

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

75

CLK2_N_DU

76

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD

148

VDD

120

VDD

108

VDD

85

VDD

70

VDD

46

VDD

38

VDD

7

VDD

136

VDDQ

180

VDDQ

156

VDDQ

112

VDDQ

164

VDDQ

143

VDDQ

128

VDDQ

104

VDDQ

96

VDDQ

172

VDDQ

77

VDDQ

62

VDDQ

54

VDDQ

30

VDDQ

22

VDDQ

15

VDDQ

MA[0..14]
A_CKE
WE#

RAS#
CAS#

VCC25

R183

100RST

R184
100RST

124

116

100

93

89

81

GND

GND

GND

GND

GND

GND

GND

Pair 1

C204
102P

C206
102P

132

GND

DIMM2

3

139

145

160

176

152

GND

GND

GND

GND

GND

GND

DQS0

DM0_DQS9

DQS1

DM1_DQS10

DQS2

DM2_DQS11

DQS3

DM3_DQS12

DM4_DQS13

DQS5

DM5_DQS14

DQS6

DM6_DQS15

DQS7

DM7_DQS16

ECC0
ECC1
ECC2
ECC3
DQS8

DM9_DQS17

ECC4
ECC5
ECC6
ECC7

C205
105P

SSTLREF_D1

C208

C207

105P

104P

D

A_SD0_0

2

D0

A_SD0_1

4

D1

A_SD0_2

6

D2

A_SD0_3

8

D3

A_DQS0_0

5

A_DQS0_1

97

A_SD0_4

94

D4

A_SD0_5

95

D5

A_SD0_6

98

D6

A_SD0_7

99

D7

A_SD1_0

12

D8

A_SD1_1

13

D9

A_SD1_2

19

D10

A_SD1_3

20

D11

A_DQS1_0

14

A_DQS1_1

107

A_SD1_4

105

D12

A_SD1_5

106

D13

A_SD1_6

109

D14

A_SD1_7

110

D15

A_SD2_0

23

D16

A_SD2_1

24

D17

A_SD2_2

28

D18

A_SD2_3

31

D19

A_DQS2_0

25

A_DQS2_1

119

A_SD2_4

114

D20

A_SD2_5

117

D21

A_SD2_6

121

D22

A_SD2_7

123

D23

A_SD3_0

33

D24

A_SD3_1

35

D25

A_SD3_2

39

D26

A_SD3_3

40

D27

A_DQS3_0

36

A_DQS3_1

129

A_SD3_4

126

D28

A_SD3_5

127

D29

A_SD3_6

131

D30

A_SD3_7

133

D31

A_SD4_0

53

D32

A_SD4_1

55

D33

A_SD4_2

57

D34

A_SD4_3

60

D35

A_DQS4_0
A_DQS4_1

149

A_SD4_4

146

D36

A_SD4_5

147

D37

A_SD4_6

150

D38

A_SD4_7

151

D39

A_SD5_0

61

D40

A_SD5_1

64

D41

A_SD5_2

68

D42

A_SD5_3

69

D43

A_DQS5_0

67

A_DQS5_1

159

A_SD5_4

153

D44

A_SD5_5

155

D45

A_SD5_6

161

D46

A_SD5_7

162

D47

A_SD6_0

72

D48

A_SD6_1

73

D49

A_SD6_2

79

D50

A_SD6_3

80

D51

A_DQS6_0

78

A_DQS6_1

169

A_SD6_4

165

D52

A_SD6_5

166

D53

A_SD6_6

170

D54

A_SD6_7

171

D55

A_SD7_0

83

D56

A_SD7_1

84

D57

A_SD7_2

87

D58

A_SD7_3

88

D59

A_DQS7_0

86

A_DQS7_1

177

A_SD7_4

174

D60

A_SD7_5

175

D61

A_SD7_6

178

D62

A_SD7_7

179

D63

A_SD8_0

44

A_SD8_1

45

A_SD8_2

49

A_SD8_3

51

A_DQS8_0

47

A_DQS8_1

140

A_SD8_4

134

A_SD8_5

135

A_SD8_6

142

A_SD8_7

144

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

VCC25

C184

C185

C186

102P

102P

C189

C190

102P

102P

C193

C194

102P

102P

C197

C198

102P

102P

C201

C202

102P

102P

VCC25

VCC25

VCC25

VCC25

102P

C188

102P

C192

102P

C196

102P

C200

102P

Micro Star Restricted Secret

DIMM1 & DIMM3

Last Revision Date:

Wednesday, May 09, 2001

Sheet

17 73

of

E

C187

102P

C191

102P

C195

102P

C199

102P

C203

102P

Rev

0A

A

B

C

D

E

11

665850

93

4234267418

89

81

MA0

48

A0

GND

GND

GND

GND

GND

GND

GND

GND

GND

MA1
MA2
MA3
MA4
MA5
MA6
MA7

4 4

MEMA_SCL<59>

3 3

2 2

MEMA_SDA<59>

MA8
MA9
MA10
MA11
MA12

MA13
MA14

CS_0<14,17>
CS_1<14,17>

RAS#
CAS#
WE#

CLK2_P<23>

CLK2_N<23>

B_CKE

SSTLREF_D2

VCC25 VCC25

MEMA_SCL
MEMA_SDA

R186 330

DIMM_WP#1
DIMM_RST#

VCC25 VCC25

GND

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS0_

158

CS1_

154

RAS_

65

CAS_

63

WE_

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

182

SA1

183

SA2

90

WP

10

RESET_

102 56

NC1 DQS4

101

NC2

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

75

CLK2_N_DU

76

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD

148

VDD

120

VDD

108

VDD

85

VDD

70

VDD

46

VDD

38

VDD

7

VDD

136

VDDQ

180

VDDQ

156

VDDQ

112

VDDQ

164

VDDQ

143

VDDQ

128

VDDQ

104

VDDQ

96

VDDQ

172

VDDQ

77

VDDQ

62

VDDQ

54

VDDQ

30

VDDQ

22

VDDQ

15

VDDQ

GND

GND

I2C ADD. - 0 I2C ADD. - 2

Pair 0 Pair 1

B_SD0_[0..7]<19,20>
B_SD1_[0..7]<19,20>
B_SD2_[0..7]<19,20>
B_SD3_[0..7]<19,20>
B_SD4_[0..7]<19,20>
B_SD5_[0..7]<19,20>
B_SD6_[0..7]<19,20>

1 1

A

B_SD7_[0..7]<19,20>
B_SD8_[0..7]<19,20>

B_DQS0_[0..1]<19,20>
B_DQS1_[0..1]<19,20>
B_DQS2_[0..1]<19,20>
B_DQS3_[0..1]<19,20>
B_DQS4_[0..1]<19,20>
B_DQS5_[0..1]<19,20>
B_DQS6_[0..1]<19,20>
B_DQS7_[0..1]<19,20>
B_DQS8_[0..1]<19,20>

B_SD0_[0..7]
B_SD1_[0..7]
B_SD2_[0..7]
B_SD3_[0..7]
B_SD4_[0..7]
B_SD5_[0..7]
B_SD6_[0..7]
B_SD7_[0..7]
B_SD8_[0..7]

B_DQS0_[0..1]
B_DQS1_[0..1]
B_DQS2_[0..1]
B_DQS3_[0..1]
B_DQS4_[0..1]
B_DQS5_[0..1]
B_DQS6_[0..1]
B_DQS7_[0..1]
B_DQS8_[0..1]

3

139

132

124

116

100

145

160

176

152

DIMM3

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DQS0

DM0_DQS9

DQS1

DM1_DQS10

DQS2

DM2_DQS11

DQS3

DM3_DQS12

DM4_DQS13

DQS5

DM5_DQS14

DQS6

DM6_DQS15

DQS7

DM7_DQS16

DQS8

DM9_DQS17

B

B_SD0_0

2

D0

B_SD0_1

4

D1

B_SD0_2

6

D2

B_SD0_3

8

D3

B_DQS0_0

5

B_DQS0_1

97

B_SD0_4

94

D4

B_SD0_5

95

D5

B_SD0_6

98

D6

B_SD0_7

99

D7

B_SD1_0

12

D8

B_SD1_1

13

D9

B_SD1_2

19

D10

B_SD1_3

20

D11

B_DQS1_0

14

B_DQS1_1

107

B_SD1_4

105

D12

B_SD1_5

106

D13

B_SD1_6

109

D14

B_SD1_7

110

D15

B_SD2_0

23

D16

B_SD2_1

24

D17

B_SD2_2

28

D18

B_SD2_3

31

D19

B_DQS2_0

25

B_DQS2_1

119

B_SD2_4

114

D20

B_SD2_5

117

D21

B_SD2_6

121

D22

B_SD2_7

123

D23

B_SD3_0

33

D24

B_SD3_1

35

D25

B_SD3_2

39

D26

B_SD3_3

40

D27

B_DQS3_0

36

B_DQS3_1

129

B_SD3_4

126

D28

B_SD3_5

127

D29

B_SD3_6

131

D30

B_SD3_7

133

D31

B_SD4_0

53

D32

B_SD4_1

55

D33

B_SD4_2

57

D34

B_SD4_3

60

D35

B_DQS4_0
B_DQS4_1

149

B_SD4_4

146

D36

B_SD4_5

147

D37

B_SD4_6

150

D38

B_SD4_7

151

D39

B_SD5_0

61

D40

B_SD5_1

64

D41

B_SD5_2

68

D42

B_SD5_3

69

D43

B_DQS5_0

67

B_DQS5_1

159

B_SD5_4

153

D44

B_SD5_5

155

D45

B_SD5_6

161

D46

B_SD5_7

162

D47

B_SD6_0

72

D48

B_SD6_1

73

D49

B_SD6_2

79

D50

B_SD6_3

80

D51

B_DQS6_0

78

B_DQS6_1

169

B_SD6_4

165

D52

B_SD6_5

166

D53

B_SD6_6

170

D54

B_SD6_7

171

D55

B_SD7_0

83

D56

B_SD7_1

84

D57

B_SD7_2

87

D58

B_SD7_3

88

D59

B_DQS7_0

86

B_DQS7_1

177

B_SD7_4

174

D60

B_SD7_5

175

D61

B_SD7_6

178

D62

B_SD7_7

179

D63

B_SD8_0

44

ECC0

B_SD8_1

45

ECC1

B_SD8_2

49

ECC2

B_SD8_3

51

ECC3

B_DQS8_0

47

B_DQS8_1

140

B_SD8_4

134

ECC4

B_SD8_5

135

ECC5

B_SD8_6

142

ECC6

B_SD8_7

144

ECC7

VCC25

CS_2<14,17>
CS_3<14,17>

CLK3_P<23>

CLK3_N<23>

R185 4.7K
R187 330

DIMM_WP#2
DIMM_RST#

DIMM_WP#2<17>
DIMM_WP#1<17>
DIMM_RST#<17,60>

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12

MA13
MA14

RAS#
CAS#
WE#

B_CKE

SSTLREF_D2

MEMA_SCL
MEMA_SDA

MA[0..14]<14,17,19>

B_CKE<14,19>

WE#<14,17,19>
RAS#<14,17,19>
CAS#<14,17,19>

C

11

665850

93

4234267418

89

81

48

A0

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141

A10

118

A11

115

A12

59

BA0

52

BA1

157

CS0_

158

CS1_

154

RAS_

65

CAS_

63

WE_

137

CLK0_P

138

CLK0_N

21

CLKE0

111

CLKE1

167

FETEN

1

VREF

184

VDDSPD

82

VDDID

92

SCL

91

SDA

181

SA0

182

SA1

183

SA2

90

WP

10

RESET_

102 56

NC1 DQS4

101

NC2

9

NC4

173

NC5

163

CS3_NU

71

CS2_NU

75

CLK2_N_DU

76

CLK2_P_DU

17

CLK1_N_DU

16

CLK1_P_DU

113

BA2_NU

103

A13_NU

168

VDD

148

VDD

120

VDD

108

VDD

85

VDD

70

VDD

46

VDD

38

VDD

7

VDD

136

VDDQ

180

VDDQ

156

VDDQ

112

VDDQ

164

VDDQ

143

VDDQ

128

VDDQ

104

VDDQ

96

VDDQ

172

VDDQ

77

VDDQ

62

VDDQ

54

VDDQ

30

VDDQ

22

VDDQ

15

VDDQ

MA[0..14]
B_CKE
WE#

RAS#
CAS#

DIMM_WP#2
DIMM_WP#1
DIMM_RST#

VCC25

R188

100RST

R189
100RST

GND

GND

3

139

132

124

116

100

145

160

176

GND

GND

GND

GND

GND

GND

GND

GND

DM0_DQS9

DM1_DQS10

DM2_DQS11

DM3_DQS12

DM4_DQS13

DM5_DQS14

DM6_DQS15

DM7_DQS16

DM9_DQS17

C229
102P

C232

C231

104P

102P

D

152

DIMM4

GND

GND

DQS0

DQS1

DQS2

DQS3

DQS5

DQS6

DQS7

ECC0
ECC1
ECC2
ECC3

DQS8

ECC4
ECC5
ECC6
ECC7

D0
D1
D2
D3

D4
D5
D6
D7
D8

D9
D10
D11

D12
D13
D14
D15
D16
D17
D18
D19

D20
D21
D22
D23
D24
D25
D26
D27

D28
D29
D30
D31
D32
D33
D34
D35

D36
D37
D38
D39
D40
D41
D42
D43

D44
D45
D46
D47
D48
D49
D50
D51

D52
D53
D54
D55
D56
D57
D58
D59

D60
D61
D62
D63

C230
105P

SSTLREF_D2

C233
105P

B_SD0_0

2

B_SD0_1

4

B_SD0_2

6

B_SD0_3

8

B_DQS0_0

5

B_DQS0_1

97

B_SD0_4

94

B_SD0_5

95

B_SD0_6

98

B_SD0_7

99

B_SD1_0

12

B_SD1_1

13

B_SD1_2

19

B_SD1_3

20

B_DQS1_0

14

B_DQS1_1

107

B_SD1_4

105

B_SD1_5

106

B_SD1_6

109

B_SD1_7

110

B_SD2_0

23

B_SD2_1

24

B_SD2_2

28

B_SD2_3

31

B_DQS2_0

25

B_DQS2_1

119

B_SD2_4

114

B_SD2_5

117

B_SD2_6

121

B_SD2_7

123

B_SD3_0

33

B_SD3_1

35

B_SD3_2

39

B_SD3_3

40

B_DQS3_0

36

B_DQS3_1

129

B_SD3_4

126

B_SD3_5

127

B_SD3_6

131

B_SD3_7

133

B_SD4_0

53

B_SD4_1

55

B_SD4_2

57

B_SD4_3

60

B_DQS4_0
B_DQS4_1

149

B_SD4_4

146

B_SD4_5

147

B_SD4_6

150

B_SD4_7

151

B_SD5_0

61

B_SD5_1

64

B_SD5_2

68

B_SD5_3

69

B_DQS5_0

67

B_DQS5_1

159

B_SD5_4

153

B_SD5_5

155

B_SD5_6

161

B_SD5_7

162

B_SD6_0

72

B_SD6_1

73

B_SD6_2

79

B_SD6_3

80

B_DQS6_0

78

B_DQS6_1

169

B_SD6_4

165

B_SD6_5

166

B_SD6_6

170

B_SD6_7

171

B_SD7_0

83

B_SD7_1

84

B_SD7_2

87

B_SD7_3

88

B_DQS7_0

86

B_DQS7_1

177

B_SD7_4

174

B_SD7_5

175

B_SD7_6

178

B_SD7_7

179

B_SD8_0

44

B_SD8_1

45

B_SD8_2

49

B_SD8_3

51

B_DQS8_0

47

B_DQS8_1

140

B_SD8_4

134

B_SD8_5

135

B_SD8_6

142

B_SD8_7

144

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

VCC25

C211

C210

VCC25

VCC25

VCC25

VCC25

C209

102P

C213

102P

C217

102P

C221

102P

C225

102P

102P

102P

C215

C214

102P

102P

C219

C218

102P

102P

C223

C222

102P

102P

C227

C226

102P

102P

Micro Star Restricted Secret

DIMM2 & DIMM4

Last Revision Date:

Wednesday, May 09, 2001

Sheet

18 73

of

E

C212

102P

C216

102P

C220

102P

C224

102P

C228

102P

Rev

0A

5

4

3

2

1

A_SD2_5

RN5

A_SD2_1

D D

C C

B B

A A

5

A_SD2_4
A_SD2_0
A_SD2_7
A_SD2_3
A_SD2_6
A_SD2_2

A_SD1_5
A_SD1_4
A_SD1_1
A_SD1_0
A_SD1_2
A_SD1_3
A_SD1_7
A_SD1_6

A_SD0_5
A_SD0_1
A_SD0_4
A_SD0_0
A_SD0_7
A_SD0_3
A_SD0_6
A_SD0_2

A_SD3_4
A_SD3_0
A_SD3_1
A_SD3_5
A_SD3_3
A_SD3_7
A_SD3_6
A_SD3_2

A_SD8_1
A_SD8_0
A_SD8_4
A_SD8_5
A_SD8_3
A_SD8_7
A_SD8_6
A_SD8_2

R_A_DQS3_0
R_A_DQS3_1
R_A_DQS1_0
R_A_DQS1_1
R_A_DQS0_0
R_A_DQS0_1

R_A_DQS2_1
R_A_DQS8_0
R_A_DQS8_1

R_B_SD0_[0..7]<14>
R_B_SD1_[0..7]<14>
R_B_SD2_[0..7]<14>
R_B_SD3_[0..7]<14>
R_B_SD4_[0..7]<14>
R_B_SD5_[0..7]<14>
R_B_SD6_[0..7]<14>
R_B_SD7_[0..7]<14>
R_B_SD8_[0..7]<14>

R_B_DQS0_[0..1]<14>
R_B_DQS1_[0..1]<14>
R_B_DQS2_[0..1]<14>
R_B_DQS3_[0..1]<14>
R_B_DQS4_[0..1]<14>
R_B_DQS5_[0..1]<14>
R_B_DQS6_[0..1]<14>
R_B_DQS7_[0..1]<14>
R_B_DQS8_[0..1]<14>

R_A_SD0_[0..7]<14>
R_A_SD1_[0..7]<14>
R_A_SD2_[0..7]<14>
R_A_SD3_[0..7]<14>
R_A_SD4_[0..7]<14>
R_A_SD5_[0..7]<14>
R_A_SD6_[0..7]<14>
R_A_SD7_[0..7]<14>
R_A_SD8_[0..7]<14>

R_A_DQS0_[0..1]<14>
R_A_DQS1_[0..1]<14>
R_A_DQS2_[0..1]<14>
R_A_DQS3_[0..1]<14>
R_A_DQS4_[0..1]<14>
R_A_DQS5_[0..1]<14>
R_A_DQS6_[0..1]<14>
R_A_DQS7_[0..1]<14>
R_A_DQS8_[0..1]<14>

8P4R-12

RN9
8P4R-12

RN13
8P4R-12

RN17
8P4R-12

RN21
8P4R-12

RN25
8P4R-12

RN29
8P4R-12

RN33
8P4R-12

RN37
8P4R-12

RN39
8P4R-12

R207 12
R209 12
R211 12
R213 12
R215 12
R217 12
R219 12
R221 12
R223 12
R225 12

R_A_SD2_5

12

R_A_SD2_1

34

R_A_SD2_4

56

R_A_SD2_0

78

R_A_SD2_7

12

R_A_SD2_3

34

R_A_SD2_6

56

R_A_SD2_2

78

R_A_SD1_5

12

R_A_SD1_4

34

R_A_SD1_1

56

R_A_SD1_0

78

R_A_SD1_2

12

R_A_SD1_3

34

R_A_SD1_7

56

R_A_SD1_6

78

R_A_SD0_5

12

R_A_SD0_1

34

R_A_SD0_4

56

R_A_SD0_0

78

R_A_SD0_7

12

R_A_SD0_3

34

R_A_SD0_6

56

R_A_SD0_2

78

R_A_SD3_4

12

R_A_SD3_0

34

R_A_SD3_1

56

R_A_SD3_5

78

R_A_SD3_3

12

R_A_SD3_7

34

R_A_SD3_6

56

R_A_SD3_2

78

R_A_SD8_1

12

R_A_SD8_0

34

R_A_SD8_4

56

R_A_SD8_5

78

R_A_SD8_3

12

R_A_SD8_7

34

R_A_SD8_6

56

R_A_SD8_2

78

A_DQS3_0
A_DQS3_1
A_DQS1_0
A_DQS1_1
A_DQS0_0
A_DQS0_1
A_DQS2_0R_A_DQS2_0
A_DQS2_1
A_DQS8_0
A_DQS8_1

R_B_SD0_[0..7]
R_B_SD1_[0..7]
R_B_SD2_[0..7]
R_B_SD3_[0..7]
R_B_SD4_[0..7]
R_B_SD5_[0..7]
R_B_SD6_[0..7]
R_B_SD7_[0..7]
R_B_SD8_[0..7]

R_B_DQS0_[0..1]
R_B_DQS1_[0..1]
R_B_DQS2_[0..1]
R_B_DQS3_[0..1]
R_B_DQS4_[0..1]
R_B_DQS5_[0..1]
R_B_DQS6_[0..1]
R_B_DQS7_[0..1]
R_B_DQS8_[0..1]

R_A_SD0_[0..7]
R_A_SD1_[0..7]
R_A_SD2_[0..7]
R_A_SD3_[0..7]
R_A_SD4_[0..7]
R_A_SD5_[0..7]
R_A_SD6_[0..7]
R_A_SD7_[0..7]
R_A_SD8_[0..7]

R_A_DQS0_[0..1]
R_A_DQS1_[0..1]
R_A_DQS2_[0..1]
R_A_DQS3_[0..1]
R_A_DQS4_[0..1]
R_A_DQS5_[0..1]
R_A_DQS6_[0..1]
R_A_DQS7_[0..1]
R_A_DQS8_[0..1]

4

A_SD4_0
A_SD4_4
A_SD4_1
A_SD4_5
A_SD4_2
A_SD4_6
A_SD4_3
A_SD4_7

A_SD5_5
A_SD5_1
A_SD5_4
A_SD5_0
A_SD5_6
A_SD5_7
A_SD5_2
A_SD5_3

A_SD6_5
A_SD6_1
A_SD6_0
A_SD6_3
A_SD6_7
A_SD6_6
A_SD6_2

A_SD7_0
A_SD7_1
A_SD7_5
A_SD7_4
A_SD7_7
A_SD7_3
A_SD7_2
A_SD7_6

R_A_DQS4_0
R_A_DQS4_1
R_A_DQS5_0
R_A_DQS5_1
R_A_DQS7_0
R_A_DQS7_1
R_A_DQS6_0
R_A_DQS6_1

RN6
8P4R-12

RN10
8P4R-12

RN14
8P4R-12

RN18
8P4R-12

RN22
8P4R-12

RN26
8P4R-12

RN30
8P4R-12

RN34
8P4R-12

R190 12
R192 12
R194 12
R196 12
R198 12
R200 12
R202 12
R204 12

R_A_SD4_0

12

R_A_SD4_4

34

R_A_SD4_1

56

R_A_SD4_5

78

R_A_SD4_2

12

R_A_SD4_6

34

R_A_SD4_3

56

R_A_SD4_7

78

R_A_SD5_5

12

R_A_SD5_1

34

R_A_SD5_4

56

R_A_SD5_0

78

R_A_SD5_6

12

R_A_SD5_7

34

R_A_SD5_2

56

R_A_SD5_3

78

R_A_SD6_4A_SD6_4

12

R_A_SD6_5

34

R_A_SD6_1

56

R_A_SD6_0

78

R_A_SD6_3

12

R_A_SD6_7

34

R_A_SD6_6

56

R_A_SD6_2

78

R_A_SD7_0

12

R_A_SD7_1

34

R_A_SD7_5

56

R_A_SD7_4

78

R_A_SD7_7

12

R_A_SD7_3

34

R_A_SD7_2

56

R_A_SD7_6

78

A_DQS4_0
A_DQS4_1
A_DQS5_0
A_DQS5_1
A_DQS7_0
A_DQS7_1
A_DQS6_0
A_DQS6_1

A_SD0_[0..7]<17,20>
A_SD1_[0..7]<17,20>
A_SD2_[0..7]<17,20>
A_SD3_[0..7]<17,20>
A_SD4_[0..7]<17,20>
A_SD5_[0..7]<17,20>
A_SD6_[0..7]<17,20>
A_SD7_[0..7]<17,20>
A_SD8_[0..7]<17,20>

A_DQS0_[0..1]<17,20>
A_DQS1_[0..1]<17,20>
A_DQS2_[0..1]<17,20>
A_DQS3_[0..1]<17,20>
A_DQS4_[0..1]<17,20>
A_DQS5_[0..1]<17,20>
A_DQS6_[0..1]<17,20>
A_DQS7_[0..1]<17,20>
A_DQS8_[0..1]<17,20>

B_SD0_[0..7]<18,20>
B_SD1_[0..7]<18,20>
B_SD2_[0..7]<18,20>
B_SD3_[0..7]<18,20>
B_SD4_[0..7]<18,20>
B_SD5_[0..7]<18,20>
B_SD6_[0..7]<18,20>
B_SD7_[0..7]<18,20>
B_SD8_[0..7]<18,20>

B_DQS0_[0..1]<18,20>
B_DQS1_[0..1]<18,20>
B_DQS2_[0..1]<18,20>
B_DQS3_[0..1]<18,20>
B_DQS4_[0..1]<18,20>
B_DQS5_[0..1]<18,20>
B_DQS6_[0..1]<18,20>
B_DQS7_[0..1]<18,20>
B_DQS8_[0..1]<18,20>

A_SD0_[0..7]
A_SD1_[0..7]
A_SD2_[0..7]
A_SD3_[0..7]
A_SD4_[0..7]
A_SD5_[0..7]
A_SD6_[0..7]
A_SD7_[0..7]
A_SD8_[0..7]

A_DQS0_[0..1]
A_DQS1_[0..1]
A_DQS2_[0..1]
A_DQS3_[0..1]
A_DQS4_[0..1]
A_DQS5_[0..1]
A_DQS6_[0..1]
A_DQS7_[0..1]
A_DQS8_[0..1]

B_SD0_[0..7]
B_SD1_[0..7]
B_SD2_[0..7]
B_SD3_[0..7]
B_SD4_[0..7]
B_SD5_[0..7]
B_SD6_[0..7]
B_SD7_[0..7]
B_SD8_[0..7]

B_DQS0_[0..1]
B_DQS1_[0..1]
B_DQS2_[0..1]
B_DQS3_[0..1]
B_DQS4_[0..1]
B_DQS5_[0..1]
B_DQS6_[0..1]
B_DQS7_[0..1]
B_DQS8_[0..1]

3

B_SD1_5
B_SD1_1
B_SD1_4
B_SD1_0
B_SD1_3
B_SD1_2
B_SD1_7
B_SD1_6

B_SD0_1
B_SD0_5
B_SD0_4
B_SD0_0
B_SD0_2
B_SD0_6
B_SD0_7
B_SD0_3

B_SD2_5
B_SD2_1
B_SD2_0
B_SD2_4
B_SD2_7
B_SD2_3
B_SD2_6
B_SD2_2

B_SD3_0
B_SD3_4
B_SD3_1
B_SD3_5
B_SD3_7
B_SD3_3
B_SD3_6
B_SD3_2

B_SD8_1
B_SD8_0
B_SD8_5
B_SD8_4
B_SD8_7
B_SD8_3
B_SD8_6
B_SD8_2

RN7
8P4R-12

RN11
8P4R-12

RN15
8P4R-12

RN19
8P4R-12

RN23
8P4R-12

RN27
8P4R-12

RN31
8P4R-12

RN35
8P4R-12

RN38
8P4R-12

RN40
8P4R-12

R_B_SD1_5

12

R_B_SD1_1

34

R_B_SD1_4

56

R_B_SD1_0

78

R_B_SD1_3

12

R_B_SD1_2

34

R_B_SD1_7

56

R_B_SD1_6

78

R_B_SD0_1

12

R_B_SD0_5

34

R_B_SD0_4

56

R_B_SD0_0

78

R_B_SD0_2

12

R_B_SD0_6

34

R_B_SD0_7

56

R_B_SD0_3

78

R_B_SD2_5

12

R_B_SD2_1

34

R_B_SD2_0

56

R_B_SD2_4

78

R_B_SD2_7

12

R_B_SD2_3

34

R_B_SD2_6

56

R_B_SD2_2

78

R_B_SD3_0

12

R_B_SD3_4

34

R_B_SD3_1

56

R_B_SD3_5

78

R_B_SD3_7

12

R_B_SD3_3

34

R_B_SD3_6

56

R_B_SD3_2

78

R_B_SD8_1

12

R_B_SD8_0

34

R_B_SD8_5

56

R_B_SD8_4

78

R_B_SD8_7

12

R_B_SD8_3

34

R_B_SD8_6

56

R_B_SD8_2

78

MA[0..14]<14,17,18>

A_CKE<14,17>
B_CKE<14,18>

RAS#<14,17,18>
CAS#<14,17,18>

MA[0..14]
A_CKE

B_CKE
WE#

WE#<14,17,18>

RAS#
CAS#

2

B_SD4_0
B_SD4_4
B_SD4_5
B_SD4_1
B_SD4_2
B_SD4_6
B_SD4_7
B_SD4_3

B_SD6_0
B_SD6_4
B_SD6_1
B_SD6_5
B_SD6_6
B_SD6_2
B_SD6_7
B_SD6_3

B_SD7_4
B_SD7_0
B_SD7_5
B_SD7_1
B_SD7_6
B_SD7_2
B_SD7_3
B_SD7_7

B_SD5_1
B_SD5_5
B_SD5_4
B_SD5_0
B_SD5_7
B_SD5_6
B_SD5_3
B_SD5_2

R_B_DQS4_0
R_B_DQS4_1
R_B_DQS5_0
R_B_DQS5_1
R_B_DQS7_0
R_B_DQS7_1
R_B_DQS6_0
R_B_DQS6_1
R_B_DQS2_0
R_B_DQS2_1
R_B_DQS1_0
R_B_DQS1_1
R_B_DQS0_0
R_B_DQS0_1
R_B_DQS3_0
R_B_DQS3_1
R_B_DQS8_0
R_B_DQS8_1

RN8
8P4R-12

RN12
8P4R-12

RN16
8P4R-12

RN20
8P4R-12

RN24
8P4R-12

RN28
8P4R-12

RN32
8P4R-12

RN36
8P4R-12

R191 12
R193 12
R195 12
R197 12
R199 12
R201 12
R203 12
R205 12
R206 12
R208 12
R210 12
R212 12
R214 12
R216 12
R218 12
R220 12
R222 12
R224 12

CAS#
WE#
RAS#
MA13

MA6
MA4
MA3
MA2

MA5
MA8
MA7
MA9

A_CKE
B_CKE
MA12
MA11

MA14
MA10
MA0
MA1

Title
Document Number

R_B_SD4_0

12

R_B_SD4_4

34

R_B_SD4_5

56

R_B_SD4_1

78

R_B_SD4_2

12

R_B_SD4_6

34

R_B_SD4_7

56

R_B_SD4_3

78

R_B_SD5_0

12

R_B_SD5_4

34

R_B_SD5_1

56

R_B_SD5_5

78

R_B_SD5_6

12

R_B_SD5_2

34

R_B_SD5_7

56

R_B_SD5_3

78

R_B_SD7_4

12

R_B_SD7_0

34

R_B_SD7_5

56

R_B_SD7_1

78

R_B_SD7_6

12

R_B_SD7_2

34

R_B_SD7_3

56

R_B_SD7_7

78

R_B_SD6_1

12

R_B_SD6_5

34

R_B_SD6_4

56

R_B_SD6_0

78

R_B_SD6_7

12

R_B_SD6_6

34

R_B_SD6_3

56

R_B_SD6_2

78

B_DQS4_0
B_DQS4_1
B_DQS6_0
B_DQS6_1
B_DQS7_0
B_DQS7_1
B_DQS5_0
B_DQS5_1
B_DQS2_0
B_DQS2_1
B_DQS1_0
B_DQS1_1
B_DQS0_0
B_DQS0_1
B_DQS3_0
B_DQS3_1
B_DQS8_0
B_DQS8_1

RN41

8P4R-50

RN42

8P4R-50

RN43

8P4R-50

RN44

8P4R-50

RN45

8P4R-50

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

Micro Star Restricted Secret

Termination #1

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

*

*

*

*

AVTT

Last Revision Date:

Wednesday, May 09, 2001

Sheet

19 73

1

Rev

0A

of

5

4

3

2

1

AVTT AVTT AVTT

A_SD0_3
A_SD0_7
A_SD0_2
A_SD0_6

D D

C C

B B

A_SD0_1
A_SD0_5
A_SD0_4
A_SD0_0

A_SD1_6
A_SD1_7
A_SD1_2
A_SD1_3
A_SD1_5
A_SD1_4
A_SD1_1
A_SD1_0
B_SD2_5
A_SD2_5
B_SD2_1
B_SD2_0
A_SD2_6
B_SD2_2
A_SD2_2
B_SD2_6
A_SD3_3
B_SD3_3
A_SD3_2
B_SD3_6
A_SD3_5
A_SD3_4
B_SD3_0
A_SD3_0
A_SD4_5
A_SD4_1
A_SD4_4
A_SD4_0
A_SD4_3
A_SD4_7
A_SD4_6
A_SD4_2
A_SD5_1
A_SD5_5
A_SD5_0
A_SD5_4
A_SD5_7
A_SD5_3
A_SD5_6
A_SD5_2
A_SD6_3
A_SD6_7
A_SD6_2
A_SD6_6
A_SD6_1
A_SD6_5
A_SD6_4
A_SD6_0
A_SD7_1
A_SD7_0
A_SD7_5
A_SD7_4
A_SD7_3
A_SD7_2
A_SD7_7
A_SD7_6
A_SD8_2
A_SD8_6
B_SD8_6
B_SD8_2
A_SD8_7
A_SD8_3
B_SD8_7
B_SD8_3

RN46
8P4R-22

RN48
8P4R-22

RN50
8P4R-22

RN52
8P4R-22

RN54
8P4R-22

RN56
8P4R-22

RN58
8P4R-22

RN60
8P4R-22

RN62
8P4R-22

RN64
8P4R-22

RN66
8P4R-22

RN68
8P4R-22

RN70
8P4R-22

RN72
8P4R-22

RN74
8P4R-22

RN76
8P4R-22

RN78
8P4R-22

RN80
8P4R-22

12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78

B_SD0_2
B_SD0_6
B_SD0_7
B_SD0_3
B_SD0_0
B_SD0_4
B_SD0_5
B_SD0_1
B_SD1_2
B_SD1_7
B_SD1_6
A_SD2_4
B_SD1_0
B_SD1_4
B_SD1_1
B_SD1_5
B_SD2_4
A_SD2_1
A_SD2_0
B_SD1_3
B_SD2_7
B_SD2_3
A_SD2_7
A_SD2_3
A_SD3_7
B_SD3_7
B_SD3_2
A_SD3_6
A_SD3_1
B_SD3_4
B_SD3_1
B_SD3_5
B_SD4_0
B_SD4_4
B_SD4_1
B_SD4_5
B_SD4_2
B_SD4_6
B_SD4_7
B_SD4_3
B_SD5_4
B_SD5_0
B_SD5_5
B_SD5_1
B_SD5_2
B_SD5_3
B_SD5_6
B_SD5_7
B_SD6_0
B_SD6_1
B_SD6_4
B_SD6_5
B_SD6_6
B_SD6_2
B_SD6_7
B_SD6_3
B_SD7_6
B_SD7_7
B_SD7_2
B_SD7_3
B_SD7_4
B_SD7_5
B_SD7_0
B_SD7_1
B_SD8_0
A_SD8_0
B_SD8_1
A_SD8_1
A_SD8_5
B_SD8_5
A_SD8_4
B_SD8_4

RN47
8P4R-22

RN49
8P4R-22

RN51
8P4R-22

RN53
8P4R-22

RN55
8P4R-22

RN57
8P4R-22

RN59
8P4R-22

RN61
8P4R-22

RN63
8P4R-22

RN65
8P4R-22

RN67
8P4R-22

RN69
8P4R-22

RN71
8P4R-22

RN73
8P4R-22

RN75
8P4R-22

RN77
8P4R-22

RN79
8P4R-22

RN81
8P4R-22

A_DQS0_1

12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78

A_DQS0_0
A_DQS1_1

A_DQS1_0
B_DQS2_0
A_DQS2_1
A_DQS3_0
A_DQS3_1
A_DQS4_0
A_DQS4_1
A_DQS5_0
A_DQS5_1
A_DQS6_0
A_DQS6_1

A_DQS7_0
A_DQS7_1
A_DQS8_0
A_DQS8_1
B_DQS0_0
B_DQS0_1
B_DQS1_0
B_DQS1_1
A_DQS2_0
B_DQS2_1
B_DQS3_1
B_DQS3_0
B_DQS4_1
B_DQS4_0
B_DQS5_0
B_DQS5_1
B_DQS6_0
B_DQS6_1
B_DQS7_0
B_DQS7_1
B_DQS8_0
B_DQS8_1

R226 22
R227 22
R228 22
R229 22
R230 22
R231 22
R232 22
R233 22
R234 22
R235 22
R236 22
R237 22
R238 22
R239 22
R240 22
R241 22
R242 22
R243 22
R244 22
R245 22
R246 22
R247 22
R248 22
R249 22
R250 22
R251 22
R252 22
R253 22
R254 22
R255 22
R256 22
R257 22
R258 22
R259 22
R260 22
R261 22

AVTT

AVTT

AVTT

AVTT

AVTT

C234
104P

C242
104P

C250
104P

C258
104P

C266
104P

C235
104P

C243
104P

C251
104P

C259
104P

C267
104P

C236
104P

C244
104P

C252
104P

C260
104P

C268
104P

C237
104P

C245
104P

C253
104P

C261
104P

C269
104P

C238
104P

C246
104P

C254
104P

C262
104P

C270
104P

C239
104P

C247
104P

C255
104P

C263
104P

C271
104P

C240
104P

C248
104P

C256
104P

C264
104P

C272
104P

C241
104P

C249
104P

C257
104P

C265
104P

C273
104P

AVTT

+

10U/16V/S

AVTT

+

10U/16V/S

AVTT

+

10U/16V/S

EC13

EC14

EC15

A_SD0_[0..7]<17,19>
A_SD1_[0..7]<17,19>
A_SD2_[0..7]<17,19>
A_SD3_[0..7]<17,19>
A_SD4_[0..7]<17,19>
A_SD5_[0..7]<17,19>
A_SD6_[0..7]<17,19>
A_SD7_[0..7]<17,19>
A_SD8_[0..7]<17,19>

A_DQS0_[0..1]<17,19>

A A

A_DQS1_[0..1]<17,19>
A_DQS2_[0..1]<17,19>
A_DQS3_[0..1]<17,19>
A_DQS4_[0..1]<17,19>
A_DQS5_[0..1]<17,19>
A_DQS6_[0..1]<17,19>
A_DQS7_[0..1]<17,19>
A_DQS8_[0..1]<17,19>

5

A_SD0_[0..7]
A_SD1_[0..7]
A_SD2_[0..7]
A_SD3_[0..7]
A_SD4_[0..7]
A_SD5_[0..7]
A_SD6_[0..7]
A_SD7_[0..7]
A_SD8_[0..7]

A_DQS0_[0..1]
A_DQS1_[0..1]
A_DQS2_[0..1]
A_DQS3_[0..1]
A_DQS4_[0..1]
A_DQS5_[0..1]
A_DQS6_[0..1]
A_DQS7_[0..1]
A_DQS8_[0..1]

B_SD0_[0..7]<18,19>
B_SD1_[0..7]<18,19>
B_SD2_[0..7]<18,19>
B_SD3_[0..7]<18,19>
B_SD4_[0..7]<18,19>
B_SD5_[0..7]<18,19>
B_SD6_[0..7]<18,19>
B_SD7_[0..7]<18,19>
B_SD8_[0..7]<18,19>

B_DQS0_[0..1]<18,19>
B_DQS1_[0..1]<18,19>
B_DQS2_[0..1]<18,19>
B_DQS3_[0..1]<18,19>
B_DQS4_[0..1]<18,19>
B_DQS5_[0..1]<18,19>
B_DQS6_[0..1]<18,19>
B_DQS7_[0..1]<18,19>
B_DQS8_[0..1]<18,19>

4

B_SD0_[0..7]
B_SD1_[0..7]
B_SD2_[0..7]
B_SD3_[0..7]
B_SD4_[0..7]
B_SD5_[0..7]
B_SD6_[0..7]
B_SD7_[0..7]
B_SD8_[0..7]

B_DQS0_[0..1]
B_DQS1_[0..1]
B_DQS2_[0..1]
B_DQS3_[0..1]
B_DQS4_[0..1]
B_DQS5_[0..1]
B_DQS6_[0..1]
B_DQS7_[0..1]
B_DQS8_[0..1]

Micro Star Restricted Secret

Title
Document Number

3

2

Termination #2

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Last Revision Date:

Wednesday, May 09, 2001

Sheet

20 73

1

Rev

0A

of

A

4 4

REF_CLK_33MHZ<22>

HWM_14318M<54>

RSB_CLK_14MHZ<42>

USBCLK48M<41>

SIOCLK48M<50>

3 3

VCC3

JSPD1

R292 1K

2
1

YJ102

2 2

VCC3

+

EC16

10U/16V/S

VCC3

+

EC17

10U/16V/S

1 1

L6
80/0805S

1 2

C277
104P

L7
80/0805S

1 2

C286
104P

A

C287

4.7U/0805

DEFAULT - SHORT

CLK_SYNTH_VDD2

C278

C281

4.7U/0805

104P

C288
105P

JSD1_12
YJUMPER-MG

C289
105P

Y1

1 2

14_318MHz

C274
10P

REF_CLK_33MHZ

HWM_14318M
RSB_CLK_14MHZ

USBCLK48M

R281
10K

SPREAD#

C290
104P

B

C291
104P

B

XTAL_X1
XTAL_X2

C275
10P

R266 22

R269 22
R270 22

R271 475RST
R272 22

R273 22

VCC3

C292
104P

R279 10K

CLK_SYNTH_VDD1

CLK_SYNTH_VDD2

CLK_SYNTH_VDD1

C293

C294

104P

104P

C

VCC3

OPEN: 133MHz
SHORT: 100MHz

R263

1K

XTAL_X1
XTAL_X2

R_REF_CLK_33

SEL

R_REFCLK_14

R_USBCLK
R_SIOCLKSIOCLK48M

MULT_SEL_0
MULT_SEL_1

SPREAD#

22

23

1
48
19
26

3

4
30

29
20
44

2

6
12
18
24
31
37
43

25
46

CDC950

SSOP48

DO NOT STUFF

VCC3

JP5

1 2

DEFAULT - SHORT

U8

XTALI
XTALO

CLK33
SEL100/133
REFCLK
IREF
48MHZ/SELA

48MHZ_/SELB
MULTSEL0

MULTSEL1
SPREAD#
PWRDN#
VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDA
VDDA

SELC

SELA

SELB

R295 X_10K

R297 10K

HCLK0

HCLK0_bar

HCLK1

HCLK1_bar

HCLK2

HCLK2_bar

HCLK3

HCLK3_bar

HCLK4

HCLK4_bar

HCLK5

HCLK5_bar

HCLK6

HCLK6_bar

HCLK7

HCLK7_bar

GND
GND
GND
GND
GND
GND
GND

GNDA
GNDAVSS

R_REFCLK_14

R_USBCLK

R_SIOCLK

MULT_SEL_0

MULT_SEL_1

R262
10K

SEL

JP5_12
YJUMPER-MG

7
8

10
11

13
14

16
17

42
41

39
38

36
35

33
32

5
9
15
28
34
40
47

27
4521

HCLKITPRP
HCLKITPRN

HCLKR2P
HCLKR2N

HCLKCMICRP
HCLKCMICRN

HCLKR1P
HCLKR1N

DIMMPLLRP
DIMMPLLRN

R908 1K

R293 1K

R294 1K

R296 1K

R298 X_1K

R264 22
R265 22

R267 22
R268 22

R274 22
R275 22

R276 22
R277 22

R278 22
R280 22

DO NOT STUFF

* Host swing select functions

MULTSEL0 MULTSEL1 BOARD IMPEDANCE I(REF) I(OH) V(OH)@I(REF)=2.32 mA

0 0 60 R(REF)=475 1% IOH=5*I(REF) 0.71 V
I(REF)=2.32mA
0 0 50 R(REF)=475 1% IOH=5*I(REF) 0.59 V
I(REF)=2.32mA
0 1 60 R(REF)=475 1% IOH=6*I(REF) 0.85 V
I(REF)=2.32mA
0 1 50 R(REF)=475 1% IOH=6*I(REF) 0.71 V
I(REF)=2.32mA
1 0 60 R(REF)=475 1% IOH=4*I(REF) 0.56 V
I(REF)=2.32mA
1 0 50 R(REF)=475 1% IOH=4*I(REF) 0.47 V
I(REF)=2.32mA
1 1 60 R(REF)=475 1% IOH=7*I(REF) 0.99 V
I(REF)=2.32mA
1 1 50 R(REF)=475 1% IOH=7*I(REF) 0.82 V
I(REF)=2.32mA

C

D

SEL100/133 SELA SELB SELC HOST 48MHz IOCLK REFCLK

0 0 0 0 100 MHz 48 MHz 33.3 MHz 14.318 MHz
0 0 0 1 100 MHz 48 MHz 66.7 MHz 14.318 MHz
0 0 1 0 100 MHz Hi-Z 33.3 MHz 14.318 MHz
0 0 1 1 100 MHz Hi-Z 66.7 MHz 14.318 MHz
0 1 0 0 100 MHz Hi-Z Low Low
0 1 0 1 100 MHz 48 MHz 33.3 MHz 14.318 MHz
0 1 1 0 Hi-Z Hi-Z Hi-Z Hi-Z
0 1 1 1 100 MHz 48 MHz 66.7 MHz 14.318 MHz
1 0 0 0 133 MHz 48 MHz 33.3 MHz 14.318 MHz
1 0 0 1 133 MHz 48 MHz 66.7 MHz 14.318 MHz
1 0 1 0 133 MHz Hi-Z 33.3 MHz 14.318 MHz
1 0 1 1 133 MHz Hi-Z 66.7 MHz 14.318 MHz
1 1 0 0 200 MHz 48 MHz 33.3 MHz 14.318 MHz
1 1 0 1 133 MHz 48 MHz 33.3 MHz 14.318 MHz
1 1 1 0 TCLK/2 TCLK/4 TCLK/4 TCLK
1 1 1 1 133 MHz 48 MHz 66.7 MHz 14.318 MHz

CLK_100M_ITP0
CLK_100M_ITP1

HCLK2
HCLK2_N

HCLK_CMIC
HCLK_CMIC_N

HCLK1
HCLK1_N

DIMM_PLL_P
DIMM_PLL_N

R29149.9RST

R29049.9RST

R28949.9RST

R28849.9RST

R28549.9RST

R28449.9RST

R28749.9RST

R28649.9RST

R28349.9RST

R28249.9RST

REF_CLK_33MHZ

RSB_CLK_14MHZ

USBCLK48M

SIOCLK48M

HWM_14318M

D

C276 10P

C282 10P

C283 10P

C284 10P

C285 10P

Micro Star Restricted Secret

Title
Document Number

Clock Synthesizer

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

E

Last Revision Date:

Wednesday, May 09, 2001

Sheet

E

CLK_100M_ITP0 <9>
CLK_100M_ITP1 <9>

HCLK2 <6>
HCLK2_N <6>

HCLK_CMIC <12>
HCLK_CMIC_N <12>

HCLK1 <4>
HCLK1_N <4>

DIMM_PLL_P <23>
DIMM_PLL_N <23>

21 73

of

Rev

0A

A

4 4

B

C

D

E

DO NO STUFF

C302
102P

R308 0

VCC3

C295 X_10P

FB_PCICLK33_BUFF

R304
X_0

PLL Mode

R311 4.7K

U9

CLK
FBIN
VCC

VCC
VCC
VCC

AGND
AVCC
GND

GND
GND
GND

G

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9

FBOUT

24
13

2
10
14
22

1
23

6

7
18
19

11

PCICLK_CIOBR PCICLK_CIOB

3

PCICLK_CIOB-GR

4
5

R_PCICLK_ETHER1 LAN1PCLK

8

D_PCICLKR D_PCICLK

9

PCICLK_IRQ0R PCICLK_IRQ0

15

IPMIPCLK_R IPMIPCLK

16

R300 33
R301 33
R302 33
R303 33
R305 33
R306 33
R307 33

17

LPC_CLK_SIO_R

20

PCICLK_RSBR PCICLK_RSB

21
12

R309 33
R310 33
R312

22

PCICLK_CIOB-G
PCICLK_IRQ1PCICLK_IRQ1R

LPC_CLK_SIO

FB_PCICLK33_BUFF

PCICLK_CIOB <25>
PCICLK_CIOB-G <27>
PCICLK_IRQ1 <46>
LAN1PCLK <44>
D_PCICLK <43>
PCICLK_IRQ0 <46>
IPMIPCLK <58>

LPC_CLK_SIO <50>
PCICLK_RSB <41>

IDT2510C

REF_CLK_33MHZ<21>

R299 X_10

VCC3

3 3

EC18

+

10U/16V/S

1 2

L8
80/0805S

C297
103P

+

C296

4.7U/0805

* RCC Design *

PLL Disable and Bypass

C298
105P

VDD_PCICLK_BUFF_5

C299

C300

105P

103P

C301
103P

PCICLK_IRQ0

2 2

PCICLK_IRQ1
LPC_CLK_SIO
LAN1PCLK
D_PCICLK
PCICLK_CIOB
PCICLK_CIOB-G
PCICLK_RSB
FB_PCICLK33_BUFF
IPMIPCLK

1 1

Micro Star Restricted Secret

Title
Document Number

A

B

C

D

PCI Clock Buffer

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

C831 10P
C832 10P
C833 10P
C834 10P
C303 10P
C304 10P
C305 10P
C306 10P
C307 10P
C308 10P

Last Revision Date:

Wednesday, May 09, 2001

Sheet

22 73

E

Rev

0A

of