MSI MS-7779 Schematics rev0B

1

Cover Sheet
BLOCK DIAGRAM

Clock Distribution
PWRGD&RESET Map
GPIO/MSIC TABLE
VRM Intersil 6277/6377 3+1 PHASE
AMD FM2

DDR3 DIMM CH-A

DDR3 DIMM CH-B
DDR REF POWER AND CAPS
EMI Reserved

AMD HUDSON D2/3

A A

SWITCH/HDMI CONN.

TRAVIS & VGA CONN.
SATA//eSATA/PS2/ FAN
LAN RTL8111F
SUPER I/O NCT5533D
ACPI UPI & SYS POWER
FCH CORE & DDR POWER
Azalia CODEC ALC892/662
USB 2.0/3.0CONN.

1
2
3 Power Deliver Chart
4
5
6
7
8 ~ 11
12
13
14
15
16~20
21
22
23
24
25
26
27
28
29

(MS-7779L2 Ver:0B )

CPU:

AMD FM2(Trinity uPGA FAMILIES)

System Chipset:

AMD - Hudson D4/D3/D2

On Board Chipset:

CLOCK GEN --FCH internal clock gen
LPC Super I/O --NCT5533D
LAN-Realtek 8111F

Azalia CODEC - Realtek ALC892/662/888/

Main Memory:

DDR III * 4 (max 32G)

Expansion Slots:

PCI Express X16 Slot * 1
PCI Express X1 Slot * 3
PCI Express X1 Slot *1 for front USB3.0

mini PCI Express X1 Slot *1 for wifi LAN

mATX: 244mm * 244mm

VIRGO

USB POWER/DISCHARGE
PCI EXPRESS X16 SLOT
PCIE X1 SLOTs
ATX & Front Panel
Auto BOM Manual
MINI PCIE CONN,

30
31
32
33
34
35

VRM

Controller - Intersil 6277/6377 3/4+2 Phase

1

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Title

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COVER SHEET

COVER SHEET

COVER SHEET

Size Document Number Rev

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Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

136Tuesday, November 22, 2011

136Tuesday, November 22, 2011

136Tuesday, November 22, 2011

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Virgo BLOCK DIAGRAM

D D

VGA CONNECTOR

22

VGA

HUDSON D3

18

VGA MAIN LINK

HDMI CON

PCIE GFX x16

C C

PCIE INTERFACE

10/100/Giga bit
ETHERNET
8111F

B B

CPU CORE POWER
NB CORE POWERACPI CONTROLLER
Intersil ISL6323
Intersil ISL6277

7

PCIE x1 SLOT1,2,3

24

PCIE INTERFACE

31

26

CPU VDDP Power
CPU VDDR Power
CPU VDDA Power
DUAL POWER

A A

DDR3 DRAM POWER
FCH CORE POWER

ATX CON

5

26

27

32

4

DP 1

DP0

21

PCIE x16

30

USB
REAR

/HDR

USB
REAR

29

Only D3 support USB3.0

F_USB_30

29

Only D3 support USB3.0

MINI PCIe x1 slot

USB 2.0

USB 3.0

USB 3.0

33

FM2

8~11

UMI

HUDSON
D4. D3/D2

16~20

SUPER I/O NCT5533D

SERIAL
PORT

3

25

DDRIII 1333~1866

DDRIII 1333~1866

AZALIA

SERIAL ATA 3.0

SPI Bus

25

CHA

CHB

UNBUFFERED
DDRIII DIMM1 2

UNBUFFERED
DDRIII DIMM3 4

ALC662/888/892

i-SATA [4:1]

23

e-SATA 5

23

SPI ROM 16M

18

2

12

13

28

MICRO-START INT'L CO.,LTD.

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Title

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BLOCK Diagram

BLOCK Diagram

BLOCK Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

236Tuesday, November 22, 2011

236Tuesday, November 22, 2011

236Tuesday, November 22, 2011

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Power Deliver Chart

2.5V Shunt
Regulator

VRM SW

D D

ATX P/S WITH 1A STBY CURRENT

5V

5VSB

+/-5%

+/-5%

C C

3.3V
+/-5%

12V
+/-5%

-12V
+/-5%

CPU
PW
12V
+/-5%

5VDIMM Linear
REGULATOR

VCC5_SB FET
REGULATOR

VCC3_WAKE Linear
REGULATOR

1.5V VDD SW
REGULATOR

1.1V VCCP SW
REGULATOR

VCC3_SB SW
REGULATOR

VCC5_SB

REGUALTOR

VDDA25 (S0, S1)

VCCP (S0, S1) / VCC_NB (S0, S1)

1.2V VDDR
REGULATOR

1.2V VDDP
REGULATOR

0.75V VTT_DDR
REGULATOR

CPU_VDDR (S0, S1)

CPU_VDDP (S0, S1)

VCC_DDR (S0, S1, S3)

DDRIII DIMM X4

VDD MEM
VTT_DDR

NB_VCC1P1 (S0, S1)

VCC3 (S0, S1)

VCC3_SB (S0, S1, S3, S5)

1.1V_SB Linear
REGULATOR

+1.1VDUAL(S0,S1,S3,S5)

15A
2 A

OPTION

0R

AMD FM1 CPU

VDDA

2.5V(1.8~2.7V)
VDDCORE

0.8-2V
VDDNBCORE

1.2V
CPU_VDDR

1.2V

CPU_VDDP

1.2V

DDR3 MEM I/F 1.5V
VCC_DDR

0.8~2.3V TBD A

HUDSON 2/3

VDDPL_11_DAC

VDDAN_11_ML

VDDCR_11

VDDAN_11_SATA

VDDAN_11_CLK

VDDAN_11_PCIE

VDDIO_33_PCIGP 3.3V
(S0, S1)
VDDPL_33_*_RUN

VDDPL_33_*_ALW

VDDIO_33_GBE_S

VDDAN_33_USB_S

VDDXL_33_S

VDDIO_33_S

VDDCR/AN_11_SUSB_S

VDDCR/AN_11_USB_S

VDDCR_11_GBE_S

VDDCR_11_S

100 mA
500 mA
700 mA
400 mA
900 mA

300 mA
320 mA

34 mA
1 mA
130 mA
6 mA
30 mA

500 mA
52 mA
100 mA

100 mA

0.5A
120A

20A

5A

5A

20 mA

B B

VCC3 (S0, S1)

+5VA Linear
REGULATOR

SVCC Linear
REGULATOR

SVCC(S0,S3)

+5VA (S0, S1)

AUDIO CODEC

3.3V CORE

5V ANALOG

0.1A

0.1A

SUPER I/O

+3.3V (S0, S1)

VCC3_WAKE (S0, S1, S3, S5)

+3.3VDUAL (S3)

0.01A

0.01A

VCC3_WAKE (S0, S1, S3, S5)

A A

5

COM Port

-12V

0.1A

X1 PCIE per

3.3V
12V

3.3Vaux

3.0A

0.5A

0.1A

4

X16 PCIE per

3.3V
12V

3.3VDual

3.0A

5.5A

0.3A

USB X6 FR

VDD
5VDual

3.8A

USB X4 RL 2XPS/2

5VDual

VDD

0.5A

5VDual

2.0A

3

ENTHENET

3.3V 1.05V

70mA

300mA

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

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Size Document Number Rev

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Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet of

MICRO-START INT'L CO.,LTD.

Power Deliver Chart

Power Deliver Chart

Power Deliver Chart

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

336Tuesday, November 22, 2011

336Tuesday, November 22, 2011

336Tuesday, November 22, 2011

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INTERNAL CLOCK MODE

D D

CH A CH B

DIMM1

DIMM2

DIMM3

DIMM4

AMD
HUDSON-D3/D2

MEM_MA_CLK_H0/L0

MEM_MA_CLK_H3/L3

MEM_MA_CLK_H2/L2

C C

MEM_MA_CLK_H1/L1

AMD

FM2 APU

B B

MEM_MB_CLK_H0/L0

MEM_MB_CLK_H3/L3

MEM_MB_CLK_H1/L1

MEM_MB_CLK_H2/L2

APU_CLKP/N

DISP_CLKP/N

FCH_APU_CLKP

FCH_DISP_CLKP
100MHZ (NO SPREAD)

USBCLK

14M_25M_48M_OSC

25M_X2

SATA_X1

25M_X1

25MHZ RTC CLOCK

FOR SATA DNI

25M Hz

32K_X1

SATA_X2

32.768K Hz

PCICLK0

PCICLK2

PCICLK2

PCICLK3

PCICLK4

LPCCLK0
LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

FCH_GFX_CLKP/N

FCH_GPP_CLK0P/N

FCH_GPP_CLK1P/N

FCH_GPP_CLK2P/N

FCH_GPP_CLK3P/N

FCH_GPP_CLK4P/N

32K_X2

PCICLK1

33MHZ

PCI_CLK4

PCI_CLK3PCI_CLK2

33MHZ

LPC_CLK0

LPCCLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

PE16_GXF_CLK/PE16_GXF_CLK#

100MHZ

PE1_GPP_CLK0/PE1_GPP_CLK0#

100MHZ

PE1_GPP_CLK1/PE1_GPP_CLK1#

100MHZ

PE1_GPP_CLK2/PE1_GPP_CLK2#

100MHZ

PE_LAN_CLK/PE_LAN_CLK#

100MHZ

SIO NCT6776F

STRAPS SETTING,

UNUSED CLOCKS

STRAPS SETTING,

RESERVE TP

HD AUDIO

SPI ROM & HEADER

PCIE GFX SLOT (FM1, 16 LANES)

PCIE GPP SLOT1 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT2 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT3(HUDSON-D3, 1 LANE)

PCIE LAN (FM1, 1 LANE)

reserve LAN_CLKREQ#

PCIEX16 SLOT

PCIE X1 SLOT

PCIE X1 SLOT

PCIE X1 SLOT

PCIE LAN

PCIE LAN RTL8111E

25M Hz

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

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Clock Distribution

Clock Distribution

Clock Distribution

Size Document Number Rev

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C

C

C

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MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

436Tuesday, November 22, 2011

436Tuesday, November 22, 2011

436Tuesday, November 22, 2011

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FM2

PWROK(Pin AG11)

4

PWRGD MAP

3

2

1

POWER ON SEQUENCE

HUDSON D3/D2

APU_PG(Pin E26)

D D

PWR_BTN#(Pin J4)

SLP_S3#(Pin T3)

SLP_S5#(Pin W2)

APU_PWRGD

FCH_PWRGDPWR_GD(Pin N7)

NCT 6776F

SLP_S5#

SLP_S5#(Pin 84)

SUSB#(Pin 64)SLP_S3#

PSOUT# (Pin 60)PSOUT#

ATX_POWER

U16

NCP1587

VRM U5

ISL6328CR

VDDPWRGD(Pin 34)

U32

NCP1587

U41

*

PS_ON#

FCH_PWRGD

CPU_VDD

VRM_PWRGD

U30

NCP102

Pin16

ATX_PWROK U23 (UP7501) 5VDIMM

Pin8

F_PANEL1PSIN#

VCC_DDR

CPU_VDDP
CPU_VDDR

NB_VCC1P1

*

U54 (UP7704) VDDA_25

MEANS OPTION

PSON# (Pin 63)

PSIN# (Pin 61)

C C

ATX_PWROK

SLP_S5#

ATX_PWROK
APU_FM1R1
VCC_DDR

VRM_PWRGD

B B

ATX_PWROK
NB_VCC1P1
FP_RST#
SLP_S3#

D41

CPU_VDDP_VDDR_EN

NBCORE_EN

D40

DDR_EN

VCORE_EN

APU_PWRGD

FCH_PWRGD_R

EN(Pin 25)

PWROK(Pin 35)

RESET MAP

FM2

RESET_L(Pin AJ13)

HUDSON D3/D2

CLK GEN

Reserve TP
Reserve TP

PCIE_RST#(Pin AE2)

A_RST#(Pin AD5)Super IO

PCIE_RST2#(Pin AB6)
PCIRST#(Pin AB5)

5

PCIE 16X slot
PCIE 1X slot 1
PCIE 1X slot 2
PCIE LAN

A A

LPC debug

ICS-9VRS4818

APU_RST#(Pin F26)

SYS_RESET#(Pin U4)

FP_RST#

APU_RST#

RESET#(Pin 12)RESET_IN#(Pin 70)

F_PANEL

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

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Custom

Custom

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MICRO-START INT'L CO.,LTD.

PWRGD/RESET MAP

PWRGD/RESET MAP

PWRGD/RESET MAP

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

536Tuesday, November 22, 2011

536Tuesday, November 22, 2011

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DDR DIMM Config.

SIO NCT6776F GPIO Config

D D

50 GP60 VSB

78 GP36 VSB SIO_VDUAL_EN

GPIO Power Rail Function descriptionPin

GP4638 VSB SIO_WAKE

YLW_LED/GP4539 VSB

GRN_LED/GP4440 VSB PWR_LED

GP6742 VSB

GP6544

GP6445 VSB

GP6347 VSB

GP6248 VSB

GP6149 VSB

VSB

SUS_LED

USB_EN

MB_ID0

MB_ID1

MB_ID2

COM_GPIO2

CHASSIS_ID1

CHASSIS_ID2

Comment

OD

GPI

GPI

GPI

GPI

GPI

GPI

reserved

reserved

reserved

reserved

reserved

reserved

DEVICE

DIMM 1

10100000B

CH-A

10100010B A4H

CH-A MEM_MA_CLK_H3/L3

DIMM 3

10100001B

CH-B

DIMM 4

10100011B A6H

CH-B

CLOCKADDRESS

MEM_MA_CLK_H1/L1

A0H

MEM_MA_CLK_H2/L2

MEM_MA_CLK_H0/L0DIMM 2

MEM_MB_CLK_H1/L1

A2H

MEM_MB_CLK_H2/L2

MEM_MB_CLK_H0/L0
MEM_MB_CLK_H3/L3

SMBus TABLE

FCH HUDSON D3/D2GPIO Config

Pin

AJ3

C C

B B

AD22 SATA_ACT#/GPIO67 SATA_LED#:SATA Channel Active

M6

V3 SPI_CLK/GPIO162 SPI Clock

V6 SPI_DI/GPIO164 SPI Data In

V5 SPI_DO/GPIO163 SPI Data Output

T6 SPI_CS1#/GPIO165 SPI Chip Select1#

Y6 SPI_HOLD#/GEVENT9# SPI HOLD#. Assert low to hold the SPI transaction.

J7 USB_OC1#/TDI/GEVENT13# OC#1:USB2.0 port 4,5

P5 USB_OC2#/TCK/GEVENT14#

P5 USB_OC3#/

P6 USB_OC4#/IR_RX0/

T1 OC#5:USB2.0 port 2,3

R8 OC#6:USB2.0 port 0,1

M7 OC#7:USB 3.0 port 2,USB 2.0 port12BLINK/USB_OC7#/

pin Name Function description

AD0/GPIO0 CLEAR_CMOS

IR_LED#/LLB#/GPIO184 MINI_PWRONJ2

TEMPIN3/TALERT#/
GPIO174

ROM_RST#/SPI_WP#/GPIO161V1 SPI write protect (active low)

USB_OC0#/SPI_TPM_CS#/
TRST#/GEVENT12#

AC_PRES/TDO/GEVENT15#

GEVENT16#
USB_OC5#/IR_TX0/
GEVENT17#
USB_OC6#/IR_TX1/
GEVENT6#

GEVENT18#

GPIO[171::173];GPIO[175::182];
GPIO[193::194]

FCH_TALERT#:Thermal Alert.
The FCH can be programmed to generate an
SMI, SCI, or IRQ13 through GPE, or generate an SMI
without GPE in response to the signal’s assertion.

OC#0:USB 3.0 port 3,USB 2.0 port 13T8

OC#2:USB2.0 port 8,9

OC#3:USB 3.0 port 0,USB 2.0 port 10

OC#4:USB 3.0 port 1,USB 2.0 port 11

Configure as one of the following:
10-kΩ 5% pull-up resistor to +3.3V_S5.
10-kΩ 5% pull-down resistor.

SOURCE

DP0_AUXP_C
/DP0_AUXN_C

APU

DP1_AUXP_C
/DP1_AUXN_C

SCLK0/SDATA0

FCH

SCLK1/SDATA1 LAN,PCIE SLOTs,MINI_PCIE

SCLK3/SDATA3 TP

RESET TABLE

SOURCE

PCIE_RST# PCIe 16X,1X,LAN,MINI_PCIE

FCH

FRONT
PANEL

A_RST# SIO,LPC debug
PCIE_RST2# RESERVE TP
LDT_RST# APU
AZ_RST# AZALIA CODEC
DDR3_RST# NC
FC_RST# DEBUG BUS
ROM_RST# NC
FP_RST# FCH,CLOCK GEN

LINKED DEVICESINGLE NAME

HDMI

Hudson D2/3
DP to VGA translator

DIMMs,CLOCK GEN
,SIO

LINKED DEVICESINGLE NAME

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

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C

C

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MICRO-START INT'L CO.,LTD.

GPIO/MSIC TABLE

GPIO/MSIC TABLE

GPIO/MSIC TABLE

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

636Tuesday, November 22, 2011

636Tuesday, November 22, 2011

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VID Override Circuit

R231KR23

R561KR56

1K

APU_SVC10
APU_SVD10

APU_SVT10

APU_PWRGD

,16

Note:
Remove R28, R29, R30, install R32

D D

set VID via SWITCH_VRM

SVC SVD

00
0

C C

1K

APU_PG:
from FCH to APU & UP1640
PU 330R to VCC_DDR

To override VID,

BOOT VOLTAGE

Pre_PWROK
Metal VID

1.1

1.0

1

0.9

01 1.0

0.8

11

VCCP

R20

R20

10R0402

10R0402

R22

R22

COREFB+10

0R0402

0R0402

R24 0R0402R24 0R0402

COREFB-10

R27

R27

NB_SENSE+10

NB_SENSE-10

CLOSE CHOKE8 CLOSE CHOKE10

VCCP

R75

R75
X_1KR0402

X_1KR0402

VRM_PWRGD_R

R76 X_10KR0402R76 X_10KR0402

B B

ATX_PWROK25,26,27,33,34
APU_FM2R110

VCORE_EN_R25,27

ATX_12V

ATX_12V

2

1

GND GND

GND GND

5

VCC5

R155

R155

X_0R0805

X_0R0805

R153 X_0R0805R153 X_0R0805

A A

C593

C593

X_C1u6.3X50402-HF

X_C1u6.3X50402-HF

VCC_DDRVCC_DDR

R34

R2551KR255
1K

R60 0RR60 0R
R230 0RR230 0R
R247 33RR247 33R
SP1SP1

R34

R35

R35

X_1K

X_1K

X_1K

X_1K

R259

R259

R199

R199

R226

R226

X_1K

X_1K

X_1K

X_1K

X_1K

X_1K

VRM_PWRGD27

V_FIX Mode

1.4

1.2

0.8

C123

C123

10R0402

10R0402

R41

R41

R43

R43

0R0402

0R0402

VSUM+ NB_VSUM+

2.61KR1%0402

2.61KR1%0402

RT1

RT1

10KRT1%

10KRT1%

D11 S-RB751V-40_SOD323-RHD11 S-RB751V-40_SOD323-RH
D72 S-RB751V-40_SOD323-RHD72 S-RB751V-40_SOD323-RH

VCORE_EN_R

4

12V

12V

3

12V

12V

PWR-2X2M_natural-RH

PWR-2X2M_natural-RH

R15 301R1%0402R15 301R1%0402

C14

C14

C1000p50X0402

C1000p50X0402

R19

R19

3.83KR1%0402

3.83KR1%0402

C330p16N0402-RH-1

C330p16N0402-RH-1

C21

C21

C330p16N0402-RH-1

C330p16N0402-RH-1

C130

C130

C1000p50X0402

C1000p50X0402

CPU_VDDNB

R104

R104

10R0402

10R0402

C108

C108

C330p16N0402-RH-1

C330p16N0402-RH-1

0R0402

0R0402

R106

R106

C109

C109

C1000p50X0402

C1000p50X0402

10R0402

10R0402

R107

R107

C38

C38

C41

C41

C0.33u6.3X50402-RH

C0.33u6.3X50402-RH

R52

R52

C0.22u50X_0805

C0.22u50X_0805

11KR0.5%0402-RH

11KR0.5%0402-RH

C118

C118

C0.1u16X0402

C0.1u16X0402

VCC5

R70

R70

DS

X_10KR0402

X_10KR0402

G

Q9

Q9

C

C

B

B

E

E

X_N-SST3904_SOT23

X_N-SST3904_SOT23

+12VIN

C107

C107

C0.1u16Y0402

C0.1u16Y0402

BOOT4 PH4

R135 X_0R0805R135 X_0R0805

U6

BOOT4

2

BOOT

7

FCCM

6

VCC

PWM4

3

PWM

4

GND

5

VRM_PWRGD_R
VRM_PWROK
VCORE_EN

R36

R36

VCC5

X_1K

X_1K

SVC
SVD
SVT

R97

R97

VRM_PWROK

VCC_DDR

C26

C26

C470p50X0402

C470p50X0402

R125

R125

X_100R0402

X_100R0402

G

X_ISL62081CRZU6X_ISL62081CRZ

1KR1%0805

1KR1%0805

X_1KR1%0805

X_1KR1%0805

R73

R73
X_220R

X_220R

R18 0R0402R18 0R0402

SVC
SVD
SVT

TP39TP39

C44 C100p50N0402C44 C100p50N0402

R14

R14

137KR1%0402

137KR1%0402

R17 41.2KR1%0402R17 41.2KR1%0402

R21

R21

3.83KR1%0402

3.83KR1%0402

R96

R96

499R1%0402

499R1%0402

R113

R113

5.6KR1%0402

5.6KR1%0402

C30

C30

C330p16N0402-RH-1

C330p16N0402-RH-1

C137 C0.33u6.3X50402-RHC137 C0.33u6.3X50402-RH

R53

R53

649R1%0402

649R1%0402

10KRT1%

10KRT1%

NB_VSUM-VSUM-

VRM_PWRGD

C90

C90

Q17

Q17

X_C0.1u16Y0402

X_C0.1u16Y0402

X_N-2N7002_SOT23

X_N-2N7002_SOT23

VCC5 +12VIN

R74

R74
10KR0402

10KR0402

DS

Q15

Q15
N-2N7002_SOT23

N-2N7002_SOT23

CHOKE7

CHOKE7

CH-1.2u15A1.7m-RH-2

CH-1.2u15A1.7m-RH-2

1 2

C163 X_C0.22u16XC163 X_C0.22u16X

UG4

R145 X_0R0805R145 X_0R0805

1

UGATE

PH4

8

PHASE

LG4

5

LGATE

GND_P

9

R91

R91

C16

C16

C110 C2200p50X0402C110 C2200p50X0402

R95

R95

RT2

RT2

X_10KR0402

X_10KR0402

C126 X_C0.1u16Y0402C126 X_C0.1u16Y0402
C125 X_C0.1u16Y0402C125 X_C0.1u16Y0402
C45 C2.2u6.3X50402C45 C2.2u6.3X50402

VCC5 VCC5

R92

R92

X_1KR1%0805

X_1KR1%0805

PG_NB

VRM_PWROK

C330p50N0402

C330p50N0402

C17 C10p25N0402-RH-2C17 C10p25N0402-RH-2

C139 C100p50N0402C139 C100p50N0402

143KR1%0402

143KR1%0402

R103

R103

R120

R120

5.6KR1%0402

5.6KR1%0402

2.61KR1%0402

2.61KR1%0402

R110

R110

11KR0.5%0402-RH

11KR0.5%0402-RH

C0.1u50X0805

C0.1u50X0805

R112

R112

C119

C119

Make sure +12VIN
connector plug in

R116

R116

10.7KR1%0402

10.7KR1%0402

DS

Q16

Q16

G

N-2N7002LT1G_SOT23-RH

N-2N7002LT1G_SOT23-RH

VIN

R123

R123

4
G

4
3
2
1

X_N-P0403BK_GEM-PAK8-RH

X_N-P0403BK_GEM-PAK8-RH

VCORE_EN

VRM_PWRGD_R

R88 X_0R0402R88 X_0R0402

C128

C128

X_C0.1u16X0402

X_C0.1u16X0402

R90

R90

X_24.9KR1%0402

X_24.9KR1%0402

C140

C140

C470p50X0402

C470p50X0402

X_32.4KR1%0402

X_32.4KR1%0402

C141 C2200p50X0402C141 C2200p50X0402

C40

C40

C42

C42

C0.33u25X0805

C0.33u25X0805

C0.1u16X0402

C0.1u16X0402

VIN

DS

1
2
3

Q93

Q93

X_N-P0903BD

X_N-P0903BD

5

Q92

Q92

X_N-P0403BK_GEM-PAK8-RH

X_N-P0403BK_GEM-PAK8-RH

R124 X_100R0402R124 X_100R0402

R115

R115

3.3KR0402

3.3KR0402

X_C1u16X5-RH

X_C1u16X5-RH

4
3
2
1

C132 C0.33u6.3X50402-RHC132 C0.33u6.3X50402-RH

4
G

4

C1u6.3X50402-HF

C1u6.3X50402-HF

23
42

10

22

20
21

18

19

43

44

45

16

17

47

46

R111 422R1%0402R111 422R1%0402

C92

C92
C2.2U6.3X0603

C2.2U6.3X0603

C365

C365

DS

1

X_C10u16X50805-HF

X_C10u16X50805-HF

2
3

Q94

Q94

X_N-P0903BD

X_N-P0903BD

5

Q80

Q80

VSUM+
ISEN4

VSUM-

4

9

ENABLE
PGOOD

PGOOD_NB
PWROK

4

SVC

6

SVD

8

SVT

5

VR_HOT_L

7

VDDIO

COMP

FB2
FB

VSEN

RTN

COMP_NB

FB_NB

VSEN_NB

ISUMP

ISUMN

ISUMP_NB

ISUMN_NB

ISL6277 HRZISL6277 HRZ

VCORE_EN

C352

C352

C144

C144

VCC5 VCC5

R1

0R0805R10R0805

C142

C142

C1u6.3X50402-HF

C1u6.3X50402-HF

29

VDD

R93

R93

X_2.2R1206

X_2.2R1206

C549

C549

X_C1000p50X0402

X_C1000p50X0402

R117X_3.65KR1%0402R117X_3.65KR1%0402

R114 X_10KR0402R114 X_10KR0402

C143

C143

X_C0.22u16X0402-HF

X_C0.22u16X0402-HF

R2

1R0805R21R0805

30

VDDP

PAD GND

49

1 2

12

CP23CP23

R144X_1R1%0402R144X_1R1%0402

+12VIN

R3

0R0805R30R0805

C18 C0.22u16XC18 C0.22u16X

R296

R296

35

xinhai@schmatic update(2011/10/07)

VIN

FCCM_NB

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

PWM_Y

BOOTX

UGATEX

PHASEX

LGATEX

PWM2_NB

ISNE1
ISNE2
ISEN3

ISNE1_NB
ISEN2_NB

NTC

NTC_NB

IMON

IMON_NB

C1000p50X0402

C1000p50X0402

C1u6.3X50402-HF

C1u6.3X50402-HF

CHOKE17

CHOKE17

X_CH-0.3u50A0.6m-HF

X_CH-0.3u50A0.6m-HF

12

CP25CP25

PWM4

X_0R0402

X_0R0402

41

R152

R152

24

0R0805

0R0805

25

26

27

R148

R148

34

0R0805

0R0805

33

32

31

PWMY

28

R142

R142

36

0R0805

0R0805

UG1_NB

37

PH1_NB

38

LG1_NB

39

PWM2_NB

40

ISEN1

15

ISEN2

14

ISEN3

13

NB_ISEN1

48

NB_ISEN2

1

12
2

11
3

R62

R62

130KR1%0402-RH

130KR1%0402-RH

C46

C46

C50

C50

C1000p50X0402

C1000p50X0402

130KR1%0402-RH

130KR1%0402-RH

C161

C161

R121 X_10KR0402/NCR121 X_10KR0402/NC

R109 X_10KR0402/NCR109 X_10KR0402/NC

R414 X_10KR0402/NCR414 X_10KR0402/NC

C22

C22

C0.22u16X

C0.22u16X

UG1

C24

C24

C0.22u16X

C0.22u16X

UG2

PH2

LG2

C29

C29

C0.22u16X

C0.22u16X

VCC5

R187

R187

X_0R0402

X_0R0402

R188

R188

X_0R0402

X_0R0402

R197 X_0R0402R197 X_0R0402

R309

R309

X_0R0402

X_0R0402

R297

R297

X_0R0402

X_0R0402

X_27.4KR1%0402-RH

X_27.4KR1%0402-RH

R66

R66

R67

R67

BOOT3 PH3

VCC5

R141

R141
0R0805

0R0805

R140 0R0805R140 0R0805

VCCP

ISEN1

ISEN2

ISEN3

R184 0R0805R184 0R0805

R7

X_41.2KR1%R7X_41.2KR1%

PH1

LG1

R166 0R0805R166 0R0805

R50

R50

10KR0402

10KR0402

R163 0R0805R163 0R0805

ISEN4

R326

R326

0R0402

0R0402

R58

R58

18.2KR1%0402-RH

18.2KR1%0402-RH

RT4

100KRT1%0402

RT4

100KRT1%0402

ERT-J0EV474J

CLOSE Q1 or Q13

R126

R126

BOOT3

PWMY

VCC5

R138

R138
0R0805

0R0805

C148

C148

C1u6.3X50402-HF

C1u6.3X50402-HF

3

R167

R167

R320

R320

0R0805

0R0805

3

10KR0402

10KR0402

X_0R0402

X_0R0402

2
7
6
3
4

R137 0R0805R137 0R0805

VIN

EC78

EC78

X_C10u16X50805-HF

X_C10u16X50805-HF

C1u16X5-RHC1C1u16X5-RH

R510KR0402 R510KR0402

DS

1

4

G

2
3

Q82

Q82

N-P0903BD

N-P0903BD

4
3
2
1

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

VIN

DS

1

4

G

2
3

Q84

Q84

N-P0903BD

N-P0903BD

4
3
2
1

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

VIN

DS

1

4

G

2
3

Q86

Q86

N-P0903BD

N-P0903BD

VCC5

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

C750

C750

C0.22u16X

C0.22u16X

ISL6208BCRZ_QFN8-HF

ISL6208BCRZ_QFN8-HF

U4

U4

BOOT

UGATE

FCCM

PHASE
VCC
PWM

LGATE

GND

GND_P

9

BOOT2_NB PH2_NB

R139

R139

BOOT2_NB

PWM2_NB

C35

C35

C1

4
G

5

Q42

Q42

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

4
G

5

Q45

Q45

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

4
G

5

Q78

Q78

4
3
2
1

R57

R57

18.2KR1%0402-RH

18.2KR1%0402-RH

R68

X_27.4KR1%0402-RH

R68

X_27.4KR1%0402-RH

100KRT1%0402

100KRT1%0402

ERT-J0EV474J

CLOSE Q7 or Q8

R133 0R0805R133 0R0805

1
8

LG3

5

C153

C153

0R0805

0R0805

ISL6208BCRZ_QFN8-HF

ISL6208BCRZ_QFN8-HF

U3

U3

2

BOOT

7

FCCM

6

VCC

3

PWM

4

GND

+

+

12

CD100u16SO-RH-1

CD100u16SO-RH-1

DS

1
2
3

Q81

Q81

N-P0903BD

N-P0903BD

4
3
2
1

DS

1
2
3

Q85

Q85

N-P0903BD

N-P0903BD

4
3
2
1

DS

1
2
3

Q87

Q87

N-P0903BD

N-P0903BD

4
3
2
1

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

RT3

RT3

R69

R69

10KR0402

10KR0402

UG3

PH3

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

C0.22u16X

C0.22u16X

1

UGATE

8

PHASE

5

LGATE

GND_P

9

2

+

+

12

+

+

12

EC84

EC84

EC88

EC88

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

C470u2.5SO-HF

C470u2.5SO-HF

R162

R162

5

Q41

Q41

2.2R1206

2.2R1206

C33

C33

C1000p50N

C1000p50N

VSUM+
ISEN1

C232

C232

C0.22u16X0402-HF

C0.22u16X0402-HF

VSUM-

EC22

EC22

+

+

12

C32

C32

C31

C31

CD100u16SO-RH-1

CD100u16SO-RH-1

X_C10u16X50805-HF

X_C10u16X50805-HF

R156

R156

2.2R1206

2.2R1206

C246

C246

C1000p50N

C1000p50N

VSUM+ ISEN3
ISEN2

C28

C28

C0.22u16X0402-HF

C0.22u16X0402-HF

VSUM-

EC77

EC77

+

+

12

CD100u16SO-RH-1

CD100u16SO-RH-1

R151

R151

2.2R1206

2.2R1206

C37

C37

C1000p50N

C1000p50N

NB_VSUM+

NB_ISEN1

NB_VSUM-

R419

R419

EC89

EC89

X_C470u2.5SO-HF

X_C470u2.5SO-HF

VIN

C1u16X5-RH

C1u16X5-RH

C48

C48

DS

1

4

R136 0R0805R136 0R0805

2
3

Q20

Q20

N-P0903BD

N-P0903BD

5

Q31

Q31

4
3
2
1

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

R71

R71

10KR0402

10KR0402

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

DS
4
G

Q21

Q21

N-P0903BD

N-P0903BD

5

Q26

Q26

4
G

4
3
2
1

5

Q44

Q44

C1u16X5-RH

C1u16X5-RH

5

X_10KR0402/NC

X_10KR0402/NC

4
3
2
1

UG2_NB
PH2_NB

LG2_NB

C1u16X5-RH

C1u16X5-RH

C62

C62

Q75

Q75

G

+

+

12

R10 3.65KR1%0402R10 3.65KR1%0402

R12 10KR0402R12 10KR0402

R13 1R1%0402R13 1R1%0402

R28 3.65KR1%0402R28 3.65KR1%0402

R31 10KR0402R31 10KR0402

R49 1R1%0402R49 1R1%0402

C57

C57

C0.22u16X0402-HF

C0.22u16X0402-HF

+

+

12

C47

C47

1

X_C10u16X50805-HF

X_C10u16X50805-HF

2
3

VSUM+
ISEN3

VSUM-

VIN

DS

1
2
3

Q22

Q22

N-P0903BD

N-P0903BD

5

Q37

Q37

N-P0403BK_GEM-PAK8-RH

N-P0403BK_GEM-PAK8-RH

2

+

+

12

EC85

EC85

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CP9CP912CP10CP10

CP11CP11

R54 3.65KR1%0402R54 3.65KR1%0402

R55 10KR0402R55 10KR0402

R72 1R1%0402R72 1R1%0402

+

+

12

CP17CP17

R89

R89

2.2R1206

2.2R1206

C56

C56

C1000p50X0402

C1000p50X0402

R81 3.65KR1%0402R81 3.65KR1%0402

R82 10KR0402R82 10KR0402

C59

C59

C0.22u16X0402-HF

C0.22u16X0402-HF

R1271R1%0402R1271R1%0402

C1u16X5-RH

C1u16X5-RH

C53

C53

DS
4
G

5

4
3
2
1

12

CP14CP14

EC74

EC74

X_C470u2.5SO-HF

X_C470u2.5SO-HF

Q38

Q38

N-P0903BD

N-P0903BD

Q32

Q32

+

+

12

EC86

EC86

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CHOKE14

CHOKE14

CH-0.3u50A0.6m-HF

CH-0.3u50A0.6m-HF

1 2

CHOKE15

CHOKE15

CH-0.3u50A0.6m-HF

CH-0.3u50A0.6m-HF

1 2

CP12CP12

CHOKE16

CHOKE16

CH-0.3u50A0.6m-HF

CH-0.3u50A0.6m-HF

1 2

12

+

+

12

CHOKE12

CHOKE12

CH-0.3u50A0.6m-HF

CH-0.3u50A0.6m-HF

1 2

12

CP18CP18

EC25

EC25

+

+

12

C52

C52

CD100u16SO-RH-1

CD100u16SO-RH-1

1
2

X_C10u16X50805-HF

X_C10u16X50805-HF

3

R131 3.65KR1%0402R131 3.65KR1%0402

NB_VSUM+
NB_ISEN2

R84 10KR0402R84 10KR0402

NB_VSUM-

12

EC87

EC87

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

12

R11 X_10KR0402/NCR11 X_10KR0402/NC

R6 X_10KR0402/NCR6 X_10KR0402/NC

R59 X_10KR0402/NCR59 X_10KR0402/NC

12

R32 X_10KR0402/NCR32 X_10KR0402/NC

R33 X_10KR0402/NCR33 X_10KR0402/NC

R44 X_10KR0402/NCR44 X_10KR0402/NC

12

CP13CP13

EC73

EC73

X_C470u2.5SO-HF

X_C470u2.5SO-HF

12

CP19CP19

R78

R78

2.2R1206

2.2R1206

C61

C61

C1000p50X0402

C1000p50X0402

C60

C60

C0.22u16X0402-HF

C0.22u16X0402-HF

R1291R1%0402R1291R1%0402

+

+

+

+

EC79

EC79

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

R51 X_10KR0402/NCR51 X_10KR0402/NC

+

+

12

R77 X_10KR0402/NCR77 X_10KR0402/NC

R80 X_10KR0402/NCR80 X_10KR0402/NC

R372 X_10KR0402/NCR372 X_10KR0402/NC

12

12

+

+

12

EC80

EC80

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

VCCP

EC26

EC26

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

ISEN2

ISEN4

CHOKE13

CHOKE13

CH-0.3u50A0.6m-HF

CH-0.3u50A0.6m-HF

1 2

CP20CP20

ISEN2

ISEN3

ISEN4

ISEN1

ISEN4

VCCP

ISEN1

12

+

+

12

EC81

EC81

EC82

EC82

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

C22u6.3X5-HF

C22u6.3X5-HF

C22u6.3X5-HF

C22u6.3X5-HF

C22u6.3X5-HF

C22u6.3X5-HF

C225

C225

C74

C74

VCCP

CPU_VDDNB

NB_ISEN2

+

+

12

+

+

12

EC60

EC60

EC27

EC27

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CPU_VDDNB

R134 X_10KR0402/NCR134 X_10KR0402/NC

NB_ISEN1

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 PCIE I/F

FM1 PCIE I/F

FM1 PCIE I/F

Custom

Custom

Custom

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

VCCP

C22u6.3X5-HF

C22u6.3X5-HF

C231

C231

R61

R61

X_10KR0402/NC

X_10KR0402/NC

1

VCCP

C85

C85

+

+

12

EC64

EC64

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

C22u6.3X5-HF

C22u6.3X5-HF

CPU_VDDNB

C22u6.3X5-HF

C22u6.3X5-HF

C106

C106

C105

C105

of

of

of

736Thursday, November 24, 2011

736Thursday, November 24, 2011

736Thursday, November 24, 2011

5

4

3

2

1

FM1 PCIE I/F

mach@CRB PCIE AC Capacitors:75nF to 200nF

D D

CPU1A

CPU1A

GFX_RX0P31
GFX_RX0N31
GFX_RX1P31
GFX_RX1N31
GFX_RX2P31
GFX_RX2N31
GFX_RX3P31
GFX_RX3N31
GFX_RX4P31
GFX_RX4N31
GFX_RX5P31
GFX_RX5N31
GFX_RX6P31
GFX_RX6N31
GFX_RX7P31
GFX_RX7N31
GFX_RX8P31
GFX_RX8N31

C C

B B

CPU_VDDP

GFX_RX9P31
GFX_RX9N31
GFX_RX10P31
GFX_RX10N31
GFX_RX11P31
GFX_RX11N31
GFX_RX12P31
GFX_RX12N31
GFX_RX13P31
GFX_RX13N31
GFX_RX14P31
GFX_RX14N31
GFX_RX15P31
GFX_RX15N31

LAN_RXC_P24
LAN_RXC_N24

UMI_RX0P16
UMI_RX0N16
UMI_RX1P16
UMI_RX1N16
UMI_RX2P16
UMI_RX2N16
UMI_RX3P16
UMI_RX3N16

R252 196R1%R252 196R1% R253 196R1%R253 196R1%

LAN_RXC_P
LAN_RXC_N

APU_P_ZVDDP

Layout:
Place within 1.5'' of APU

AD8

P_GFX_RXP0

AD9

P_GFX_RXN0

AC7

P_GFX_RXP1

AC8

P_GFX_RXN1

AB5

P_GFX_RXP2

AB6

P_GFX_RXN2

AB8

P_GFX_RXP3

AB9

P_GFX_RXN3

AA7

P_GFX_RXP4

AA8

P_GFX_RXN4

Y5

P_GFX_RXP5

Y6

P_GFX_RXN5

Y8

P_GFX_RXP6

Y9

P_GFX_RXN6

W7

P_GFX_RXP7

W8

P_GFX_RXN7

V5

P_GFX_RXP8

V6

P_GFX_RXN8

V8

P_GFX_RXP9

V9

P_GFX_RXN9

U7

P_GFX_RXP10

U8

P_GFX_RXN10

T5

P_GFX_RXP11

T6

P_GFX_RXN11

T8

P_GFX_RXP12

T9

P_GFX_RXN12

R7

P_GFX_RXP13

R8

P_GFX_RXN13

P5

P_GFX_RXP14

P6

P_GFX_RXN14

P8

P_GFX_RXP15

P9

P_GFX_RXN15

AF5

P_GPP_RXP0

AF6

P_GPP_RXN0

AF8

P_GPP_RXP1

AF9

P_GPP_RXN1

AE7

P_GPP_RXP2

AE8

P_GPP_RXN2

AD5

P_GPP_RXP3

AD6

P_GPP_RXN3

AJ8

P_UMI_RXP0

AJ7

P_UMI_RXN0

AH6

P_UMI_RXP1

AH5

P_UMI_RXN1

AH9

P_UMI_RXP2

AH8

P_UMI_RXN2

AG8

P_UMI_RXP3

AG7

P_UMI_RXN3

AJ2

P_ZVDDP

PZ90421-2M66-01H

PZ90421-2M66-01H

PCI EXPRESS

PCI EXPRESS

UMI GPP GRAPHICS

UMI GPP GRAPHICS

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9

P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

P_ZVSS

AC2
AC1
AC4
AC5
AB2
AB3
AA2
AA1
AA4
AA5
Y2
Y3
W2
W1
W4
W5
V2
V3
U2
U1
U4
U5
T2
T3
R2
R1
R4
R5
P2
P3
N2
N1

AF2
AF3
AE2
AE1
AE4
AE5
AD2
AD3

UMI_TX0P_APU

AJ5

UMI_TX0N_APU

AJ4

UMI_TX1P_APU

AH3

UMI_TX1N_APU

AH2

UMI_TX2P_APU

AG1

UMI_TX2N_APU

AG2

UMI_TX3P_APU

AG5

UMI_TX3N_APU

AG4

APU_P_ZVSS

AJ1

Layout: PLACE CAPS WITH APU < 1 INCH
ROUTE ALL PCIE AS 85OHM +/-10%

GFX_TXP0
GFX_TXN0
GFX_TXP1
GFX_TXN1
GFX_TXP2
GFX_TXN2
GFX_TXP3
GFX_TXN3
GFX_TXP4
GFX_TXN4
GFX_TXP5
GFX_TXN5
GFX_TXP6
GFX_TXN6
GFX_TXP7
GFX_TXN7
GFX_TXP8
GFX_TXN8
GFX_TXP9
GFX_TXN9
GFX_TXP10
GFX_TXN10
GFX_TXP11
GFX_TXN11
GFX_TXP12
GFX_TXN12
GFX_TXP13
GFX_TXN13
GFX_TXP14
GFX_TXN14
GFX_TXP15
GFX_TXN15

LAN_TXP
LAN_TXN

C423 C0.1u10X0402C423 C0.1u10X0402
C422 C0.1u10X0402C422 C0.1u10X0402
C420 C0.1u10X0402C420 C0.1u10X0402
C421 C0.1u10X0402C421 C0.1u10X0402
C418 C0.1u10X0402C418 C0.1u10X0402
C419 C0.1u10X0402C419 C0.1u10X0402
C417 C0.1u10X0402C417 C0.1u10X0402
C416 C0.1u10X0402C416 C0.1u10X0402
C414 C0.1u10X0402C414 C0.1u10X0402
C415 C0.1u10X0402C415 C0.1u10X0402
C412 C0.1u10X0402C412 C0.1u10X0402
C413 C0.1u10X0402C413 C0.1u10X0402
C411 C0.1u10X0402C411 C0.1u10X0402
C410 C0.1u10X0402C410 C0.1u10X0402
C409 C0.1u10X0402C409 C0.1u10X0402
C408 C0.1u10X0402C408 C0.1u10X0402
C406 C0.1u10X0402C406 C0.1u10X0402
C407 C0.1u10X0402C407 C0.1u10X0402
C405 C0.1u10X0402C405 C0.1u10X0402
C404 C0.1u10X0402C404 C0.1u10X0402
C402 C0.1u10X0402C402 C0.1u10X0402
C403 C0.1u10X0402C403 C0.1u10X0402
C400 C0.1u10X0402C400 C0.1u10X0402
C401 C0.1u10X0402C401 C0.1u10X0402
C399 C0.1u10X0402C399 C0.1u10X0402
C398 C0.1u10X0402C398 C0.1u10X0402
C396 C0.1u10X0402C396 C0.1u10X0402
C397 C0.1u10X0402C397 C0.1u10X0402
C394 C0.1u10X0402C394 C0.1u10X0402
C395 C0.1u10X0402C395 C0.1u10X0402
C393 C0.1u10X0402C393 C0.1u10X0402
C392 C0.1u10X0402C392 C0.1u10X0402

C799 C0.1u10X0402C799 C0.1u10X0402
C800 C0.1u10X0402C800 C0.1u10X0402

C318 C0.1u10X0402C318 C0.1u10X0402
C319 C0.1u10X0402C319 C0.1u10X0402
C304 C0.1u10X0402C304 C0.1u10X0402
C305 C0.1u10X0402C305 C0.1u10X0402
C302 C0.1u10X0402C302 C0.1u10X0402
C303 C0.1u10X0402C303 C0.1u10X0402
C316 C0.1u10X0402C316 C0.1u10X0402
C317 C0.1u10X0402C317 C0.1u10X0402

Layout:
Place within 1.5'' of APU

GFX_TXC_0P 31
GFX_TXC_0N 31
GFX_TXC_1P 31
GFX_TXC_1N 31
GFX_TXC_2P 31
GFX_TXC_2N 31
GFX_TXC_3P 31
GFX_TXC_3N 31
GFX_TXC_4P 31
GFX_TXC_4N 31
GFX_TXC_5P 31
GFX_TXC_5N 31
GFX_TXC_6P 31
GFX_TXC_6N 31
GFX_TXC_7P 31
GFX_TXC_7N 31
GFX_TXC_8P 31
GFX_TXC_8N 31
GFX_TXC_9P 31
GFX_TXC_9N 31
GFX_TXC_10P 31
GFX_TXC_10N 31
GFX_TXC_11P 31
GFX_TXC_11N 31
GFX_TXC_12P 31
GFX_TXC_12N 31
GFX_TXC_13P 31
GFX_TXC_13N 31
GFX_TXC_14P 31
GFX_TXC_14N 31
GFX_TXC_15P 31
GFX_TXC_15N 31

LAN_TXC_P 24
LAN_TXC_N 24

UMI_TX0P 16
UMI_TX0N 16
UMI_TX1P 16
UMI_TX1N 16
UMI_TX2P 16
UMI_TX2N 16
UMI_TX3P 16
UMI_TX3N 16

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

FM1 PCIE I/F

FM1 PCIE I/F

FM1 PCIE I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

of

of

of

836Tuesday, November 22, 2011

836Tuesday, November 22, 2011

836Tuesday, November 22, 2011

5

4

3

2

1

FM1DDR3 I/F

MEM_MA_DQS_L[7..0]12
MEM_MA_DQS_H[7..0]12

MEM_MA_DM[7..0]12

D D

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13

MEM_MA_ADD[15..0]12

MEM_MA_BANK012
MEM_MA_BANK112
MEM_MA_BANK212

C C

mach@CLOCK assignment can be changed

MEM_MA_CLK_H012
MEM_MA_CLK_L012
MEM_MA_CLK_H112
MEM_MA_CLK_L112
MEM_MA_CLK_H212
MEM_MA_CLK_L212
MEM_MA_CLK_H312
MEM_MA_CLK_L312

MEM_MA_CKE012
MEM_MA_CKE112

MEM_MA0_ODT012
MEM_MA0_ODT112
MEM_MA1_ODT012
MEM_MA1_ODT112

MEM_MA0_CS_L012
MEM_MA0_CS_L112
MEM_MA1_CS_L012

B B

MEM_MA1_CS_L112
MEM_MA_RAS_L12

MEM_MA_CAS_L12
MEM_MA_WE_L12

MEM_MA_RESET#12
MEM_MA_HOT#12

APU_M_VREF

VCC_DDR

MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7

MEM_MA_CLK_H0
MEM_MA_CLK_L0
MEM_MA_CLK_H1
MEM_MA_CLK_L1
MEM_MA_CLK_H2
MEM_MA_CLK_L2
MEM_MA_CLK_H3
MEM_MA_CLK_L3

MEM_MA_CKE0
MEM_MA_CKE1

MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA1_ODT0
MEM_MA1_ODT1

MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA1_CS_L0
MEM_MA1_CS_L1

MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA_WE_L

MEM_MA_RESET#
MEM_MA_HOT#

R254 39.2R1%0402R254 39.2R1%0402

Layout:
Place within 1.5'' of APU

APU_M_ZVDDIO

CPU1B

CPU1B

V27
P27
R25
P26
R24
P24
P23
N26
N23

M25

V24
N25

M24

Y23
L27
L24

W26

V25
L26

E17
H21
F25

G29
AF29
AE25

AG21

AF17

H17

G17

F21

E21

G26

G25

F30

E30
AE28
AE29

AG24
AG25

AF20
AF21
AE16
AD16

U27

U26

T23

U23

T25

T26

R27

R28

L23

K26
AA24

AC27
AA25
AC26

Y27
AB26

W23

AB25

W25

Y24

Y26

J25

U24

K22

J24

PZ90421-2M66-01H

PZ90421-2M66-01H

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MA_CKE0
MA_CKE1

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_RAS_L
MA_CAS_L
MA_WE_L

MA_RESET_L
MA_EVENT_L

M_VREF
M_ZVDDIO

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MEM_MA_DATA0

F16

MEM_MA_DATA1

G16

MEM_MA_DATA2

H18

MEM_MA_DATA3

F19

MEM_MA_DATA4

F15

MEM_MA_DATA5

H15

MEM_MA_DATA6

E18

MEM_MA_DATA7

F18

MEM_MA_DATA8

G20

MEM_MA_DATA9

H20

MEM_MA_DATA10

E23

MEM_MA_DATA11

G23

MEM_MA_DATA12

G19

MEM_MA_DATA13

E20

MEM_MA_DATA14

F22

MEM_MA_DATA15

G22

MEM_MA_DATA16

F24

MEM_MA_DATA17

H24

MEM_MA_DATA18

E27

MEM_MA_DATA19

F27

MEM_MA_DATA20

H23

MEM_MA_DATA21

E24

MEM_MA_DATA22

E26

MEM_MA_DATA23

H26

MEM_MA_DATA24

G28

MEM_MA_DATA25

E29

MEM_MA_DATA26

H29

MEM_MA_DATA27

H30

MEM_MA_DATA28

H27

MEM_MA_DATA29

F28

MEM_MA_DATA30

F31

MEM_MA_DATA31

G31

MEM_MA_DATA32

AD30

MEM_MA_DATA33

AF30

MEM_MA_DATA34

AG27

MEM_MA_DATA35

AF27

MEM_MA_DATA36

AD31

MEM_MA_DATA37

AE31

MEM_MA_DATA38

AG28

MEM_MA_DATA39

AD28

MEM_MA_DATA40

AF26

MEM_MA_DATA41

AD25

MEM_MA_DATA42

AF23

MEM_MA_DATA43

AE23

MEM_MA_DATA44

AD27

MEM_MA_DATA45

AE26

MEM_MA_DATA46

AF24

MEM_MA_DATA47

AD24

MEM_MA_DATA48

AG22

MEM_MA_DATA49

AD21

MEM_MA_DATA50

AE19

MEM_MA_DATA51

AG19

MEM_MA_DATA52

AD22

MEM_MA_DATA53

AE22

MEM_MA_DATA54

AE20

MEM_MA_DATA55

AD19

MEM_MA_DATA56

AG18

MEM_MA_DATA57

AE17

MEM_MA_DATA58

AF15

MEM_MA_DATA59

AG15

MEM_MA_DATA60

AD18

MEM_MA_DATA61

AF18

MEM_MA_DATA62

AG16

MEM_MA_DATA63

AD15

MEM_MA_DATA[63..0] 12

MEM_MB_ADD[15..0]13

MEM_MB_BANK013
MEM_MB_BANK113
MEM_MB_BANK213

MEM_MB_CLK_H013
MEM_MB_CLK_L013
MEM_MB_CLK_H113
MEM_MB_CLK_L113
MEM_MB_CLK_H213
MEM_MB_CLK_L213
MEM_MB_CLK_H313
MEM_MB_CLK_L313

MEM_MB_CKE013
MEM_MB_CKE113

MEM_MB0_ODT013
MEM_MB0_ODT113
MEM_MB1_ODT013
MEM_MB1_ODT113

MEM_MB0_CS_L013
MEM_MB0_CS_L113
MEM_MB1_CS_L013
MEM_MB1_CS_L113

MEM_MB_RAS_L13
MEM_MB_CAS_L13
MEM_MB_WE_L13

MEM_MB_RESET#13
MEM_MB_HOT#13

MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7

MEM_MB_CLK_H0
MEM_MB_CLK_L0
MEM_MB_CLK_H1
MEM_MB_CLK_L1
MEM_MB_CLK_H2
MEM_MB_CLK_L2
MEM_MB_CLK_H3
MEM_MB_CLK_L3

MEM_MB_CKE0
MEM_MB_CKE1

MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB1_ODT0
MEM_MB1_ODT1

MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB1_CS_L0
MEM_MB1_CS_L1

MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB_WE_L

MEM_MB_RESET#
MEM_MB_HOT#

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MEM_MB_DQS_L[7..0]13
MEM_MB_DQS_H[7..0]13

MEM_MB_DM[7..0]13

CPU1C

CPU1C

V31

N28

P29
N29
N31
M30
M31
M28
M27

L30
W31

L29

K28

AB28

K31

J31
W29

V30

K29
D16

B20

A25
D29

AL29
AH25
AK21
AJ17

A17

B17

B21
C21
D25
C25

B29

A29

AJ29
AH29
AK25
AL25
AJ20
AJ21
AL16
AL17

U30
U29

T29

T28
R31

T31

P30
R30

J30

J28

AA30
AC30
AA31
AC29

Y29

AB29

Y30

AB31

W28

AA27
AA28

J27

V28

PZ90421-2M66-01H

PZ90421-2M66-01H

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

MB_CKE0
MB_CKE1

MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB1_CS_L1

MB_RAS_L
MB_CAS_L
MB_WE_L

MB_RESET_L
MB_EVENT_L

MEMORY CHANNEL B

MEMORY CHANNEL B

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MEM_MB_DATA0

A16

MEM_MB_DATA1

C16

MEM_MB_DATA2

B18

MEM_MB_DATA3

A19

MEM_MB_DATA4

C15

MEM_MB_DATA5

B15

MEM_MB_DATA6

D17

MEM_MB_DATA7

C18

MEM_MB_DATA8

D20

MEM_MB_DATA9

A20

MEM_MB_DATA10

D22

MEM_MB_DATA11

D23

MEM_MB_DATA12

C19

MEM_MB_DATA13

D19

MEM_MB_DATA14

A22

MEM_MB_DATA15

C22

MEM_MB_DATA16

C24

MEM_MB_DATA17

B24

MEM_MB_DATA18

B26

MEM_MB_DATA19

C27

MEM_MB_DATA20

A23

MEM_MB_DATA21

B23

MEM_MB_DATA22

D26

MEM_MB_DATA23

A26

MEM_MB_DATA24

C28

MEM_MB_DATA25

D28

MEM_MB_DATA26

C31

MEM_MB_DATA27

D31

MEM_MB_DATA28

B27

MEM_MB_DATA29

A28

MEM_MB_DATA30

B30

MEM_MB_DATA31

C30

MEM_MB_DATA32

AJ30

MEM_MB_DATA33

AK30

MEM_MB_DATA34

AH28

MEM_MB_DATA35

AJ27

MEM_MB_DATA36

AG30

MEM_MB_DATA37

AH31

MEM_MB_DATA38

AK28

MEM_MB_DATA39

AL28

MEM_MB_DATA40

AJ26

MEM_MB_DATA41

AH26

MEM_MB_DATA42

AH23

MEM_MB_DATA43

AJ23

MEM_MB_DATA44

AK27

MEM_MB_DATA45

AL26

MEM_MB_DATA46

AJ24

MEM_MB_DATA47

AK24

MEM_MB_DATA48

AK22

MEM_MB_DATA49

AH22

MEM_MB_DATA50

AL19

MEM_MB_DATA51

AK19

MEM_MB_DATA52

AL23

MEM_MB_DATA53

AL22

MEM_MB_DATA54

AH20

MEM_MB_DATA55

AL20

MEM_MB_DATA56

AJ18

MEM_MB_DATA57

AH17

MEM_MB_DATA58

AJ15

MEM_MB_DATA59

AK15

MEM_MB_DATA60

AH19

MEM_MB_DATA61

AK18

MEM_MB_DATA62

AK16

MEM_MB_DATA63

AH16

MEM_MB_DATA[63..0] 13

VCC_DDR

R196

R196

1KR1%

1KR1%

A A

5

R201

R201

1KR1%

1KR1%

C170

C170

C1000P50X0402

C1000P50X0402

APU_M_VREF

C679

C679

C0.1u10X0402

C0.1u10X0402

C156

C156

Layout:
Place within 1.0'' of APU

C1000P50X0402

C1000P50X0402

4

VCC_DDR

R275 1KR0402R275 1KR0402
R274 1KR0402R274 1KR0402

3

MEM_MA_HOT#
MEM_MB_HOT#

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DDR3 I/F

FM1 DDR3 I/F

FM1 DDR3 I/F

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

936Tuesday, November 22, 2011

936Tuesday, November 22, 2011

936Tuesday, November 22, 2011

of

of

of

5

FM1 DISPLAY I/F

Note: Several vias on the DP0 interface violate the minimum distance rules
for via to via spacing between diff pairs. These violations have been reviewed and approved
on an individual basis, and pose no significant singal integrity issues for this implementation since
the route lengths are under the maximum allowed spec, and the via distance violations are not severe.

DP0_TX0P21

FCH_THERMTRIP# 17

FCH_TALERT# 18

FCH_PROCHOT# 16

DP0_TX0N21
DP0_TX1P21

DP0_TX1N21
DP0_TX2P21

DP0_TX2N21
DP0_TX3P21

DP0_TX3N21
DP1_TX0P18

DP1_TX0N18
DP1_TX1P18

DP1_TX1N18
DP1_TX2P18

DP1_TX2N18
DP1_TX3P18

DP1_TX3N18

APU_SIC

C337

C337

X_C10p50N0402

D D

APU_RST#
APU_PWRGD

APU_THERMTRIP#

C C

APU_ALERT#

APU_PROCHOT#

B B

X_C10p50N0402

mach@DP1 for CRT

Layout: Place within 1.5'' of APU

C335

C335

C299

C299

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

VCC_DDR VCC3_SB

R305

R305

2

10KR0402

10KR0402

61

Q49A

Q49A

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

VCC3_SBVCC_DDR

R303

R303

5

10KR0402

10KR0402

34

Q49B

Q49B

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

VCC3_SBVCC_DDR

R446

R446

5

10KR0402

10KR0402

34

Q132B

Q132B

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

R304

R304

R302

R302

10KR0402

10KR0402

10KR0402

10KR0402

R452

R452

10KR0402

10KR0402

APU_CLK16
APU_CLK#16

DISP_CLK16
DISP_CLK#16

APU_RST#16

APU_PWRGD7,16

APU_SIC25
APU_SID25

C230 C0.1u10X0402C230 C0.1u10X0402
C235 C0.1u10X0402C235 C0.1u10X0402

C226 C0.1u10X0402C226 C0.1u10X0402
C220 C0.1u10X0402C220 C0.1u10X0402

C213 C0.1u10X0402C213 C0.1u10X0402
C209 C0.1u10X0402C209 C0.1u10X0402

C210 C0.1u10X0402C210 C0.1u10X0402
C214 C0.1u10X0402C214 C0.1u10X0402

C255 C0.1u10X0402C255 C0.1u10X0402
C259 C0.1u10X0402C259 C0.1u10X0402

C248 C0.1u10X0402C248 C0.1u10X0402
C252 C0.1u10X0402C252 C0.1u10X0402

C244 C0.1u10X0402C244 C0.1u10X0402
C238 C0.1u10X0402C238 C0.1u10X0402

C240 C0.1u10X0402C240 C0.1u10X0402
C236 C0.1u10X0402C236 C0.1u10X0402

APU_SVC7
APU_SVD7
APU_SVT7

APU_SID

APU_RST#
APU_PWRGD

PULL UP

VCC_DDR

VCC5_SB

R307 1KR0402R307 1KR0402
R317 1KR0402R317 1KR0402

R288 300R0402R288 300R0402
R310 300R0402R310 300R0402

R289 1KR0402R289 1KR0402
R287 1KR0402R287 1KR0402
R290 1KR0402R290 1KR0402

R318 1KR0402R318 1KR0402

R301 10KR0402R301 10KR0402

APU_SIC_R
APU_SID

APU_RST#

APU_PWRGD

APU_PROCHOT#
APU_ALERT#
APU_THERMTRIP#

FCH_DMA_ACTIVE#

APU_FM2R1

R316 10R0402R316 10R0402

APU_PROCHOT#
APU_THERMTRIP#
APU_ALERT#

4

DP0_TX0P_APU
DP0_TX0N_APU

DP0_TX1P_APU
DP0_TX1N_APU

DP0_TX2P_APU
DP0_TX2N_APU

DP0_TX3P_APU
DP0_TX3N_APU

DP1_TX0P_APU
DP1_TX0N_APU

DP1_TX1P_APU
DP1_TX1N_APU

DP1_TX2P_APU
DP1_TX2N_APU

DP1_TX3P_APU
DP1_TX3N_APU

APU_SVC
APU_SVD
APU_SVT

APU_SIC_RAPU_SIC

CPU_TDI
CPU_TDO
CPU_TCK
CPU_TMS
CPU_TRST_L
CPU_DBRDY
CPU_DBREQ_L

ROUTE PCIE AS 85OHM +/-10%
PLACE CAPS WITH APU < 1 INCH

Trace length within 10"

CPU1D

CPU1D

ANALOG/DISPLAY/MISC

ANALOG/DISPLAY/MISC

N4

DP0_TXP0

N5

DP0_TXN0

M2

DP0_TXP1

M3

DP0_TXN1

L2

DP0_TXP2

L1

DP0_TXN2

L4

DP0_TXP3

L5

DP0_TXN3

K2

DP1_TXP0

K3

DP1_TXN0

J2

DP1_TXP1

J1

DP1_TXN1

J4

DP1_TXP2

J5

DP1_TXN2

H2

DP1_TXP3

H3

DP1_TXN3

L7

DP2_TXP0

L8

DP2_TXN0

K5

DP2_TXP1

K6

DP2_TXN1

K8

DP2_TXP2

K9

DP2_TXN2

J7

DP2_TXP3

J8

DP2_TXN3

N7

DP2_TXP4

N8

DP2_TXN4

M5

DP2_TXP5

M6

DP2_TXN5

M8

DP2_TXP6

M9

DP2_TXN6

AL12

CLKIN_H

AK12

CLKIN_L

AG12

DISP_CLKIN_H

AF12

DISP_CLKIN_L

C1

SVC

C2

SVD

D1

SVT

AK14

SIC

AL14

SID

AF10

RESET_L

AF14

PWROK

AE10

PROCHOT_L

AH14

THERMTRIP_L

AJ14

ALERT_L

G11

TDI

E10

TDO

E11

TCK

F11

TMS

F10

TRST_L

G10

DBRDY

E9

DBREQ_L

PZ90421-2M66-01H

PZ90421-2M66-01H

DISPLAY PORT 0

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY PORT 1

DISPLAY PORT 2 DISPLAY PORT 1

SER. CLK

SER. CLK

MISC

MISC

JTAG CTRL

JTAG CTRL

SENSE RSVD

SENSE RSVD

DP_AUX_ZVSS

DP_VARY_BL

DISPLAY PORT MISC.

DISPLAY PORT MISC.

TEST

TEST

DMAACTIVE_L

BP5/IDLEEXIT_L

VDDP_SENSE

VDDNB_SENSE

VDDIO_SENSE

VDDR_SENSE

DP_BLON

DP_DIGON

DP0_AUXP
DP0_AUXN

DP1_AUXP
DP1_AUXN

DP2_AUXP
DP2_AUXN

DP3_AUXP
DP3_AUXN

DP4_AUXP
DP4_AUXN

DP5_AUXP
DP5_AUXN

DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

FM2R1

LDTSTOP_L

CORETYPE

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

VDD_SENSE
VSS_SENSE

G9
F8

G8
E8

E1
E2

F1
F2

G1
G2

E5
E6

F5
F6

G5
G6

E3
F3
G3
E7
F7
G7

T21
U21
AD14
P21
R21
F12
E12
F13
E13
G13
G14
F14
E14
AJ11
AH11
H10
J10
T22
U22
AG31
V22
R22
AE14

AC10
AG14
AD10
G12
F9

AJ13
AH13
AD12
K23
K25
AB23
AC24
AG10

C3
A3
A4
B3
C4
B4

3

DP_AUX_ZVSS
APU_BLON

APU_DIGON
APU_BLPWM

DP0

DP1

DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

APU_TEST4
APU_TEST5
APU_TEST6
APU_TEST9
APU_TEST10
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24
APU_TEST25_H
APU_TEST25_L
APU_TEST28_H
APU_TEST28_L
APU_TEST30_H
APU_TEST30_L
APU_TEST31
APU_TEST32_H
APU_TEST32L
APU_TEST35

APU_FM2R1

FCH_DMA_ACTIVE#

VDDP_SENSE

VDDR_SENSE

R684 0R0402R684 0R0402

R680 0R0402R680 0R0402

Layout: Place within 1.5'' of APU

R207 150R1%0402R207 150R1%0402

DP0_AUXP_C 21
DP0_AUXN_C 21

MACH@??? DP2 to PCIE16X conn?

DP1_AUXP_C 18
DP1_AUXN_C 18

DP0_TX0,TX1,TX2 and TX3
DP0_AUX0 and DP0_HPD

DP1_TX0,TX1,TX2 and TX3
DP1_AUX0 and DP1_HPD

R266 100KR0402R266 100KR0402
R267 100KR0402R267 100KR0402
R262 100KR0402R262 100KR0402
R260 100KR0402R260 100KR0402

TP28TP28
TP45TP45
TP48TP48
TP49TP49
TP33TP33
TP20TP20
TP4TP4
TP21TP21
TP19TP19

R190 1KR0402R190 1KR0402
R189 1KR0402R189 1KR0402
R191 1KR0402R191 1KR0402
R193 1KR0402R193 1KR0402
R280 511R1%0402R280 511R1%0402

R319 511R1%0402R319 511R1%0402
TP26TP26
TP27TP27
TP30TP30
TP40TP40

R308 39.2R1%0402R308 39.2R1%0402

TP44TP44
TP43TP43

R204 X_300R0402R204 X_300R0402

R205 300R0402R205 300R0402

APU_FM2R1 7

FCH_DMA_ACTIVE# 16

LDTSTOP_L

LDTSTOP_L 16

FM_IDLEEXIT_L

LDTSTOP_L

R192 1KR0402R192 1KR0402

TP9TP9

NB_SENSE+ 7
VDDIOFB+ 27
COREFB+ 7

TP10TP10

COREFB- 7

NB_SENSE- 7

Sabine HDMI Design Guidance
HDMI enable strapping:
TEST35 PU TO VCC_DDR thru 300R

DP0_HPD_HDMI_C 21
DP1_HPD_VGA_C 18

CPU_VDDP

VCC_DDR

H:HDMI ENABLE

VCC_DDR

CPU_TRST_L

FM_IDLEEXIT_L

2

R203

R203
1KR0402

1KR0402

N-SST3904_SOT23

N-SST3904_SOT23

HDT+ Connector

VCC_DDR

J2

J2

1

CPU_VDDIO

3

GND

5

GND

7

R658 X_0R0402R658 X_0R0402
R659 X_10KR0402R659 X_10KR0402
R660 X_10KR0402R660 X_10KR0402
R661 X_10KR0402R661 X_10KR0402

Q83A

Q83A

X_NN-CMKT3904_SOT363-6-RH

X_NN-CMKT3904_SOT363-6-RH

VCC_DDR

B

Q74

Q74

GND
CPU_TRST_L9CPU_PWROK_BUF
CPU_DBRDY311CPU_RST_L_BUF
CPU_DBRDY213CPU_DBRDY0
CPU_DBRDY115CPU_DBREQ_L

17

GND
CPU_VDDIO19CPU_PLLTEST1

X_H2X10SM-1.27PITCH_BLUE-RH

X_H2X10SM-1.27PITCH_BLUE-RH

VCC3 VCC3

R9

R9

2

X_10KR0402

X_10KR0402

APU_PWROK_BUFAPU_PWRGD APU_LDT_RST_BUF

61

R583

R583

10KR0402

10KR0402

CE

FCH_IDLEEXIT_L 17

SCAN Conn,

APU_TEST18
APU_TEST19

APU_TEST24
APU_TEST20

WARM RESET

APU_RST#

GPU DEBUG

APU_BLON
APU_DIGON
APU_BLPWM
DP1_HPD_VGA_C

TP7TP7
TP32TP32

CPU_TCK

CPU_TMS

CPU_TDI

CPU_TDO

CPU_PLLTEST0

APU_RST#

VCC_DDR

1

CPU_TCK

2

CPU_TMS

4

CPU_TDI

6

CPU_TDO

8

APU_PWROK_BUF

10

APU_LDT_RST_BUF

12

CPU_DBRDY

14

CPU_DBREQ_L

16

APU_TEST19

18

APU_TEST18

20

R42

R42

5

X_10KR0402

R83

R83
X_0R0402

X_0R0402

VDDIOFB+
COREFB+

X_10KR0402

34

Q83B

Q83B

X_NN-CMKT3904_SOT363-6-RH

X_NN-CMKT3904_SOT363-6-RH

Layout: Place close to HDT header

R653 1KR0402R653 1KR0402
R651 1KR0402R651 1KR0402
R652 1KR0402R652 1KR0402
R657 1KR0402R657 1KR0402
R654 1KR0402R654 1KR0402

TP46TP46
TP64TP64

TP69TP69
TP70TP70

TP71TP71

TP76TP76
TP77TP77
TP78TP78
TP79TP79

CPU_TDI
CPU_TCK
CPU_TMS
CPU_TRST_L
CPU_DBREQ_L

A A

TEST2, TEST3, TEST6, TEST10, TEST23, TEST28_H TEST28_L, and any RSVD pins have no connections.
TEST4, TEST5, TEST[17:14], TEST25_H/L,TEST30_H/L, and TEST32_H/L have onboard test points.

5

4

mach@FM1R1 used to control VRM_EN(D66)???
FM1R1 = OPEN ON PKG. IF LOW, KEEP PWR OFF!

3

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DISPLAY/MSIC

FM1 DISPLAY/MSIC

FM1 DISPLAY/MSIC

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

1

10 36Tuesday, November 29, 2011

10 36Tuesday, November 29, 2011

10 36Tuesday, November 29, 2011

of

of

of

5

BOTTOM SIDE DECOUPLING

VCCP

C697,C700,C705,C710 change to ASM-5010

D D

C C

CPU_VDDNB

VCC_DDR

B B

CPU_VDDR

C697

C697

C700

C700

VCCP VCCP

C712

C712

VCCP

C715

C715

C796

C796

X_C47u6.3X1206

X_C47u6.3X1206

C695

C695

C22u6.3X1206

C22u6.3X1206

Layout: Place close to Pins
AH11,AJ11,AK11,AL11

C298

C298

C22u6.3X1206

C22u6.3X1206

C22u6.3X0805

C22u6.3X0805

C47u4X50805-RH

C47u4X50805-RH

C0.22U16X3

C0.22U16X3

C790

C790

X_C47u6.3X1206

X_C47u6.3X1206

C690

C690

C22u6.3X1206

C22u6.3X1206

C324

C324

C22u6.3X0805

C22u6.3X0805

C694

C694

C47u4X50805-RH

C47u4X50805-RH

C716

C716

C0.22U16X3

C0.22U16X3

C4.7u6.3X5

C4.7u6.3X5

C705

C705

C22u6.3X0805

C22u6.3X0805

C702

C702

C22u6.3X5-HF

C22u6.3X5-HF

C795

C795

X_C47u6.3X1206

X_C47u6.3X1206

C681

C681

C22u6.3X1206

C22u6.3X1206

C314

C314

C4.7u6.3X5

C4.7u6.3X5

C682

C682

C710

C710

C47u6.3X1206

C47u6.3X1206

C22u6.3X0805

C22u6.3X0805

C709

C689

C689

C789

C789

X_C47u6.3X1206

X_C47u6.3X1206

C685

C685

C22u6.3X1206

C22u6.3X1206

C332

C332

C0.22U16X3

C0.22U16X3

C709

C708

C708

C47u4X50805-RH

C47u4X50805-RH

C47u4X50805-RH

C47u4X50805-RH

C47u4X50805-RH

C47u4X50805-RH

VCCP VCCP

C711

C711

C0.01u25X0603

C0.01u25X0603

C792

C792

C794

C794

X_C47u6.3X1206

X_C47u6.3X1206

X_C47u6.3X1206

X_C47u6.3X1206

C223

C223

C698

C698

C4.7u6.3X5

C4.7u6.3X5

C10u6.3X50805

C10u6.3X50805

C330

C330

C189

C189

C0.22U16X3

C0.22U16X3

C10u6.3X50805

C10u6.3X50805

EMC Caps On Bottom side

A A

VCCP

C149

C149
C180p50N0402

C180p50N0402

5

C704

C704

C47u6.3X1206

C47u6.3X1206

C714

C714

C0.01u25X0603

C0.01u25X0603

C816

C816

C703

C703

C699

C699

C47u6.3X1206

C47u6.3X1206

C713

C713

C47u4X50805-RH

C47u4X50805-RH

C680

C680

C0.01u25X0603

C0.01u25X0603

X_C47u6.3X1206

X_C47u6.3X1206

C4.7u6.3X5

C4.7u6.3X5

C696

C696

C797

C797

C47u6.3X1206

C47u6.3X1206

C706

C706

C4.7u6.3X5

C4.7u6.3X5

C47u6.3X1206

C47u6.3X1206

C684

C684

C47u4X50805-RH

C47u4X50805-RH

C718

C718

C814

C814

C47u6.3X1206

C47u6.3X1206

C272

C272

C4.7u6.3X5

C4.7u6.3X5

C687

C687

C47u6.3X1206

C47u6.3X1206

C180p50N0402

C180p50N0402

C692

C692

C707

C707

C47u4X50805-RH

C47u4X50805-RH

C719

C719

C180p50N0402

C180p50N0402

C791

C791

X_C47u6.3X1206

X_C47u6.3X1206

C270

C270

C0.22U16X3

C0.22U16X3

C47u6.3X1206

C47u6.3X1206

C701

C701

C47u4X50805-RH

C47u4X50805-RH

C688

C688

C815

C815

X_C47u6.3X1206

X_C47u6.3X1206

C221

C221

C0.22U16X3

C0.22U16X3

C683

C683

C47u6.3X1206

C47u6.3X1206

C180p50N0402

C180p50N0402

C798

C798

X_C47u6.3X1206

X_C47u6.3X1206

C784

C784

C180p50N0402

C180p50N0402

4

VCCP VCCP

CPU1E

CPU1E

AA11

VDD_1

AB7

VDD_2

Y20

VDD_3

M10

VDD_4

P10

VDD_5

T20

VDD_6

W11

VDD_7

AA13

VDD_8

AA21

VDD_9

AA3

VDD_10

AA6

VDD_11

AB1

VDD_12

AB10

VDD_13

AB14

VDD_14

AB16

VDD_15

AB18

VDD_16

AB4

VDD_17

AC11

VDD_18

AC13

VDD_19

AC19

VDD_20

AC21

VDD_21

AD1

VDD_22

AE3

VDD_23

AF4

VDD_24

AF7

VDD_25

AG6

VDD_26

AH7

VDD_27

H12

VDD_28

H14

VDD_29

H8

VDD_30

J11

VDD_31

J13

VDD_32

J15

VDD_33

J17

VDD_34

J19

VDD_35

J21

VDD_36

J9

VDD_37

K10

VDD_38

K12

VDD_39

K14

VDD_40

U13

VDD_41

K16

VDD_42

AC17

VDD_43

Y18

VDD_44

K18

VDD_45

K20

VDD_46

K4

VDD_47

L3

VDD_48

L11

VDD_49

L15

VDD_50

PZ90421-2M66-01H

PZ90421-2M66-01H

CPU1F

CPU1F

K27

VDDIO_1

J29

VDDIO_2

U25

VDDIO_3

T30

VDDIO_4

V29

VDDIO_5

L28

VDDIO_6

L31

VDDIO_7

M22

VDDIO_8

M23

VDDIO_9

M26

VDDIO_10

N24

VDDIO_11

N27

VDDIO_12

N30

VDDIO_13

P22

VDDIO_14

U31

VDDIO_15

W24

VDDIO_16

V23

VDDIO_17

V26

VDDIO_18

U28

VDDIO_19

P25

VDDIO_20

P28

AB22
AB24
AB27
AB30
AC23
AC25
AC28
AC31

AA26

AA23

AA29
MEC1
MEC2
MEC3
MEC4

P31
R23
R26
R29
T24

W27

L25

W30

Y22
Y25
Y28
K24

K30
Y31

J26
M29
T27

VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38
VDDIO_39
VDDIO_40
VDDIO_41
VDDIO_42
VDDIO_43
VDDIO_44
VDDIO_45
VDDIO_46
VDDIO_47
VDDIO_48
VDDIO_49
MEC1
MEC2
MEC3
MEC4

PZ90421-2M66-01H

PZ90421-2M66-01H

C785

C785

C180p50N0402

C180p50N0402

4

VDD

VDD

VDDNB_CAP_1
VDDNB_CAP_2

VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99

VDDA_1
VDDA_2

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8

VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12
VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23
VDDNB_24
VDDNB_25
VDDNB_26
VDDNB_27
VDDNB_28
VDDNB_29
VDDNB_30

VDDR_1
VDDR_2
VDDR_3
VDDR_4
VDDR_5
VDDR_6

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDP_6
VDDP_7
VDDP_8
VDDP_9

L17
L21
M12
M16
M18
M20
N6
N11
N19
N3
P1
P12
P20
T1
P4
P7
R11
R13
R19
T10
T12
U11
V20
U3
U6
V1
V10
V12
V4
V7
W13
W19
J6
N21
U19
AE6
AC15
W21
Y1
Y10
Y12
Y14
AA15
AA17
AA19
Y16
AH1
AF1
K7

AE13
AD13

A7
A6
A5
A9
C6
A10
A11
A12
A13
A14
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C5
C14
C13
C12
C11
C10
C9
C8
C7
A8
M14
N13

AL10
AK8
AK9
AL8
AL9
AK10

AK4
AK5
AL5
AL3
AL4
AL6
AK3
AK6
AK2

CPU_VDDNB

C180p50N0402

C180p50N0402

C181

C181

3

TOTLE
POWER
PINS

430 2

VALUE/SIZE/
MATERIAL

22U/1206/X5R
10U/0805/X5R

4.7U/0805/X5R

0.22U/0603/X5R

0.1U/0603/X5R

0.01U/0603/X5R

3.3 nF/0603/X5R
1 nF/0603/X5R
1 nF/0603/X5R
180 pF/0603/X5R

VDDA25VCC_DDR

TP18TP18

CPU_VDDNB

VDDNB = 0.8V
(Variable)

Layout: Place close to Pins M14,M13
inside the backplate cavity openning

VDDNB_CAP

C686 C22u6.3X1206C686 C22u6.3X1206
C691 C22u6.3X1206C691 C22u6.3X1206

CPU_VDDR

CPU_VDDP

C180p50N0402

C180p50N0402

Layout: Place caps within 0.6'' of APU

VDDR = 1.2V
VDDPCIE = 1.2V
ONLY ONE SIDE OF VDDPCIE & VDDR MUST
CONNECTED ON THE PCB.CONNECTING BOTH SIDES
IS ACCEPTABLE BUT NOT REQUIRED. BOTH SIDES
MUST BE DECOUPLED.

CPU_VDDP CPU_VDDR

C204

C204

3

CPU_VDDP CPU_VDDR

C203

C203

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

FM2DECOUPLING CAPS

VSS

VDD

VDDNB

VDDNBCAP

99

232

/
/
/
/
/
/
/
/
/
/

Place across each VDDIO-GND plane seam

VCC_DDR

C281

C281

30

/

2
2

7

1

3
2

2

/

/
/

4
/

/

/

/

/

/

31

C357

C357

C758

C758

C0.22U16X3

C0.22U16X3

C0.22U16X3

C0.22U16X3

C306

C306

C312

C312

C4.7u6.3X5

C4.7u6.3X5

Layout: Place close to Pins
H1,H2,H3,H4

C308

C308

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

2+2

C371

C371

C0.22U16X3

C0.22U16X3

VDDIO

COMB

SPLIT

49

2

4

/
1
4

/
/
/
/
/
2+2

C180p50N0402

C180p50N0402

CPU_VDDP

C194

C194

1

2+1(B)

2

2+2

2

2+2
/

/

/

/

/

//

/
//

4

2

2+2

C757

C757

C180p50N0402

C180p50N0402

VDDA_25VDDA25

FB5

FB5

30L3A-40_0805-RH

30L3A-40_0805-RH

C717

C717

C3300p50X0402

C3300p50X0402

Layout: Place close to Pins
AH10,AJ10,AK10,AL10

C323

C47u4X50805-RH

C47u4X50805-RH

C310

C310

C10u6.3X50805

C10u6.3X50805

C321

C321

C180p50N0402

C180p50N0402

C323

C296

C296

2

VDDP

9

NEAR

//1

2
2
/
/
/
/
/
/

CPU_VDDNB

C4.7u6.3X5

C4.7u6.3X5

2

VDDR

SPLIT

6

FAR

/
/
2
2
/
/
/
/
/
/

C180

C180

C329

C329

C0.22U16X3

C0.22U16X3

C0.22U6.3X

C0.22U6.3X

VDDA

/
/
1
1
/
/
1

/
/

C164

C164

C0.22U6.3X

C0.22U6.3X

C326

C326

C1000P50X0402

C1000P50X0402

Mvref

1

/
/
/
/
/
1
/
1

/

C169

C169

C180p50N0402

C180p50N0402

C331

C331

C1000P50X0402

C1000P50X0402

1

CPU1H

CPU1H

AK29

VSS_115

R10

VSS_116

R12

VSS_117

R20

VSS_118

T4

VSS_119

T7

VSS_120

T11

VSS_121

T13

VSS_122

T19

VSS_123

U9

VSS_124

U10

VSS_125

U12

VSS_126

U20

VSS_127

V11

VSS_128

V13

VSS_129

V19

VSS_130

V21

VSS_131

W3

VSS_132

W6

VSS_133

W9

VSS_134

W10

VSS_135

W12

VSS_136

W20

VSS_137

W22

VSS_138

Y4

VSS_139

Y7

VSS_140

Y11

VSS_141

Y13

VSS_142

Y15

VSS_143

Y17

VSS_144

Y19

VSS_145

Y21

VSS_146

AA9

VSS_147

AA10

VSS_148

AA14

VSS_149

AA16

VSS_150

AA18

VSS_151

AA20

VSS_152

AA22

VSS_153

AB13

VSS_154

AB15

VSS_155

AB17

VSS_156

AB19

VSS_157

AB21

VSS_158

AC3

VSS_159

AC6

VSS_160

AC9

VSS_161

AC12

VSS_162

AC14

VSS_163

AC16

VSS_164

AC18

VSS_165

AC22

VSS_166

AD4

VSS_167

AD7

VSS_168

AD11

VSS_169

AK20

VSS_170

AK23

VSS_171

AF19

VSS_172

AK26

VSS_173

PZ90421-2M66-01H

PZ90421-2M66-01H

CPU1G

CPU1G

A18

VSS_1

A21

VSS_2

A24

VSS_3

A27

VSS_4

B16

VSS_5

B19

VSS_6

B22

VSS_7

N22

VSS_8

B25

VSS_9

B28

VSS_10

C17

VSS_11

C20

VSS_12

C23

VSS_13

C26

VSS_14

C29

VSS_15

D2

VSS_16

D3

VSS_17

D4

VSS_18

D5

VSS_19

D6

VSS_20

D7

VSS_21

D8

VSS_22

D9

VSS_23

D10

VSS_24

D11

VSS_25

D12

VSS_26

D13

VSS_27

D14

VSS_28

D15

VSS_29

D18

VSS_30

D21

VSS_31

D24

VSS_32

D27

VSS_33

D30

VSS_34

E4

VSS_35

E15

VSS_36

E16

VSS_37

E19

VSS_38

E22

VSS_39

E25

VSS_40

E28

VSS_41

E31

VSS_42

F4

VSS_43

F17

VSS_44

F20

VSS_45

F23

VSS_46

F26

VSS_47

F29

VSS_48

G15

VSS_49

G18

VSS_50

G21

VSS_51

G24

VSS_52

R6

VSS_53

AL21

VSS_54

AL24

VSS_55

AL18

VSS_56

P11

VSS_57

PZ90421-2M66-01H

PZ90421-2M66-01H

Title

Title

Title

FM1 POWER&DECOUPLING

FM1 POWER&DECOUPLING

FM1 POWER&DECOUPLING

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

K415-Virgo 0B

K415-Virgo 0B

K415-Virgo 0B

Date: Sheet

Date: Sheet

Date: Sheet

AF16

VSS_174

VSS

VSS

AF13

VSS_175

AF11

VSS_176

AF22

VSS_177

AF25

VSS_178

AF28

VSS_179

AF31

VSS_180

AG3

VSS_181

AG9

VSS_182

AG11

VSS_183

AG13

VSS_184

AG17

VSS_185

AG20

VSS_186

AG23

VSS_187

AG26

VSS_188

AG29

VSS_189

AH4

VSS_190

AH10

VSS_191

AH12

VSS_192

AH15

VSS_193

AH18

VSS_194

AH21

VSS_195

AH24

VSS_196

AH27

VSS_197

AH30

VSS_198

AJ3

VSS_199

AJ6

VSS_200

AJ9

VSS_201

AJ10

VSS_202

AJ12

VSS_203

AJ16

VSS_204

AJ19

VSS_205

AD17

VSS_206

AD20

VSS_207

AD23

VSS_208

AD26

VSS_209

AD29

VSS_210

AK7

VSS_211

AJ31

VSS_212

AJ28

VSS_213

AJ25

VSS_214

AJ22

VSS_215

AE9

VSS_216

AE11

VSS_217

AE12

VSS_218

AE15

VSS_219

AE18

VSS_220

AE21

VSS_221

AE24

VSS_222

AE27

VSS_223

AE30

VSS_224

AK11

VSS_225

AK13

VSS_226

K1

VSS_227

G4

VSS_228

M1

VSS_229

H1

VSS_230

J22

VSS_231

AB11

VSS_232

P13

VSS_58

VSS

VSS

P19

VSS_59

R3

VSS_60

M4

VSS_61

R9

VSS_62

G27

VSS_63

G30

VSS_64

H4

VSS_65

H5

VSS_66

H6

VSS_67

H7

VSS_68

H9

VSS_69

H11

VSS_70

H13

VSS_71

H16

VSS_72

H19

VSS_73

H22

VSS_74

H25

VSS_75

H28

VSS_76

H31

VSS_77

M7

VSS_78

M11

VSS_79

M15

VSS_80

M17

VSS_81

M21

VSS_82

N9

VSS_83

N10

VSS_84

N12

VSS_85

N20

VSS_86

J12

VSS_87

J14

VSS_88

J16

VSS_89

J18

VSS_90

J20

VSS_91

J23

VSS_92

K11

VSS_93

K13

VSS_94

K15

VSS_95

K17

VSS_96

K21

VSS_97

J3

VSS_98

L6

VSS_99

L9

VSS_100

L10

VSS_101

L12

VSS_102

L14

VSS_103

L16

VSS_104

L18

VSS_105

L20

VSS_106

L22

VSS_107

AL7

VSS_108

AL27

VSS_109

A15

VSS_110

AK17

VSS_111

AL11

VSS_112

AL15

VSS_113

AL13

VSS_114

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

11 36Tuesday, November 22, 2011

11 36Tuesday, November 22, 2011

11 36Tuesday, November 22, 2011

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of

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